adc_ctrl_sim_cfg.hjson

// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: adc_ctrl

  // Top level dut name (sv module).
  dut: adc_ctrl

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:adc_ctrl_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/ip/adc_ctrl/data/adc_ctrl_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/ip/adc_ctrl/data/adc_ctrl.hjson"

  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]

  // Add additional tops for simulation.
  sim_tops: ["adc_ctrl_bind", "adc_ctrl_cov_bind", "sec_cm_prim_onehot_check_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Add ADC_CTRL specific exclusion files.
  vcs_cov_excl_files: ["{proj_root}/hw/ip/adc_ctrl/dv/cov/adc_ctrl_cov_unr_excl.el"]

  // Default UVM test and seq class name.
  uvm_test: adc_ctrl_base_test
  uvm_test_seq: adc_ctrl_base_vseq

  // Enable cdc instrumentation.
  run_opts: ["+cdc_instrumentation_enabled=1"]

  // List of test specifications.
  tests: [
    {
      name: adc_ctrl_smoke
      uvm_test_seq: adc_ctrl_smoke_vseq
    }

    {
      name: adc_ctrl_filters_polled
      uvm_test_seq: adc_ctrl_filters_polled_vseq
    }

    {
      name: adc_ctrl_filters_polled_fixed
      uvm_test_seq: adc_ctrl_filters_polled_vseq
      run_opts: ["+filters_fixed=1"]
    }

    {
      name: adc_ctrl_filters_interrupt
      uvm_test_seq: adc_ctrl_filters_interrupt_vseq
    }

    {
      name: adc_ctrl_filters_interrupt_fixed
      uvm_test_seq: adc_ctrl_filters_interrupt_vseq
      run_opts: ["+filters_fixed=1"]
    }

    {
      name: adc_ctrl_filters_wakeup
      uvm_test_seq: adc_ctrl_filters_wakeup_vseq
      run_opts: ["+test_timeout_ns=2000000000"]
    }

    {
      name: adc_ctrl_filters_wakeup_fixed
      uvm_test_seq: adc_ctrl_filters_wakeup_vseq
      run_opts: ["+filters_fixed=1", "+test_timeout_ns=2000000000"]
    }

    {
      name: adc_ctrl_clock_gating
      uvm_test_seq: adc_ctrl_clock_gating_vseq
      run_opts: ["+test_timeout_ns=2000000000"]
    }

    {
      name: adc_ctrl_filters_both
      uvm_test_seq: adc_ctrl_filters_both_vseq
    }

    {
      name: adc_ctrl_poweron_counter
      uvm_test_seq: adc_ctrl_poweron_counter_vseq
    }

    {
      name: adc_ctrl_lowpower_counter
      uvm_test_seq: adc_ctrl_lowpower_counter_vseq
    }

    {
      name: adc_ctrl_fsm_reset
      uvm_test_seq: adc_ctrl_fsm_reset_vseq
    }

  ]

  // List of regressions.
  regressions: [
    {
      name: smoke
      tests: ["adc_ctrl_smoke"]
    }
  ]
}