From b44874c1003e34fee5809fb7fa80ea2c6b2ffd7d Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Tue, 31 Oct 2023 00:13:22 +0000 Subject: [PATCH 1/2] Add ST_NUCLEO144_F767ZI --- .github/PULL_REQUEST_TEMPLATE.md | 1 + CMakePresets.json | 1 + ChibiOS/ST_NUCLEO144_F767ZI/CMakeLists.txt | 51 + ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json | 58 + ChibiOS/ST_NUCLEO144_F767ZI/README.md | 11 + ChibiOS/ST_NUCLEO144_F767ZI/board.c | 270 +++ ChibiOS/ST_NUCLEO144_F767ZI/board.h | 1866 +++++++++++++++++ .../ST_NUCLEO144_F767ZI/common/CMakeLists.txt | 13 + .../common/Device_BlockStorage-DEBUG.c | 110 + .../common/Device_BlockStorage.c | 110 + .../ST_NUCLEO144_F767ZI/common/serialcfg.h | 18 + .../common/targetHAL_ConfigurationManager.cpp | 38 + ChibiOS/ST_NUCLEO144_F767ZI/launch.json | 107 + .../managed_helpers/README.md | 5 + .../ST_NUCLEO144_F767ZI.Adc.cs | 53 + .../managed_helpers/package.nuspec | 26 + ChibiOS/ST_NUCLEO144_F767ZI/mbedtls_config.h | 53 + .../nanoBooter/CMakeLists.txt | 10 + .../nanoBooter/STM32F76xx_booter-DEBUG.ld | 145 ++ .../nanoBooter/STM32F76xx_booter.ld | 145 ++ .../ST_NUCLEO144_F767ZI/nanoBooter/chconf.h | 834 ++++++++ .../ST_NUCLEO144_F767ZI/nanoBooter/halconf.h | 550 +++++ .../nanoBooter/halconf_nf.h | 17 + ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/main.c | 103 + .../ST_NUCLEO144_F767ZI/nanoBooter/mcuconf.h | 437 ++++ .../nanoBooter/mcuconf_nf.h | 9 + .../nanoBooter/target_board.h.in | 18 + .../nanoCLR/CMakeLists.txt | 11 + .../nanoCLR/STM32F76xx_CLR-DEBUG.ld | 144 ++ .../nanoCLR/STM32F76xx_CLR.ld | 144 ++ ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/chconf.h | 834 ++++++++ ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/halconf.h | 564 +++++ .../ST_NUCLEO144_F767ZI/nanoCLR/halconf_nf.h | 35 + ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/main.c | 82 + ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h | 440 ++++ .../ST_NUCLEO144_F767ZI/nanoCLR/mcuconf_nf.h | 28 + .../ST_NUCLEO144_F767ZI/nanoCLR/nanoHAL.cpp | 8 + .../nanoCLR/target_board.h.in | 18 + .../ST_NUCLEO144_F767ZI/stm32f7xx_hal_conf.h | 56 + .../ST_NUCLEO144_F767ZI/target_BlockStorage.c | 15 + .../ST_NUCLEO144_F767ZI/target_BlockStorage.h | 12 + ChibiOS/ST_NUCLEO144_F767ZI/target_common.c | 27 + .../ST_NUCLEO144_F767ZI/target_common.h.in | 47 + .../target_external_memory.c | 111 + .../target_lwip_sntp_opts.h | 8 + ChibiOS/ST_NUCLEO144_F767ZI/target_lwipopts.h | 8 + .../target_nf_dev_onewire_config.cpp | 29 + .../target_nf_dev_onewire_config.h | 17 + .../target_nf_device_can_config.cpp | 32 + .../target_nf_device_can_config.h | 24 + .../target_system_device_adc_config.cpp | 40 + .../target_system_device_dac_config.cpp | 14 + .../target_system_device_i2c_config.cpp | 44 + .../target_system_device_pwm_config.cpp | 9 + .../target_system_device_spi_config.cpp | 32 + .../target_system_io_ports_config.cpp | 79 + .../target_system_io_ports_config.h | 60 + README.md | 1 + azure-pipelines.yml | 54 + 59 files changed, 8086 insertions(+) create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/CMakeLists.txt create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/README.md create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/board.c create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/board.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/common/CMakeLists.txt create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage-DEBUG.c create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage.c create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/common/serialcfg.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/common/targetHAL_ConfigurationManager.cpp create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/launch.json create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/README.md create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/ST_NUCLEO144_F767ZI.Adc.cs create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/package.nuspec create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/mbedtls_config.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/CMakeLists.txt create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter-DEBUG.ld create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter.ld create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/chconf.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/halconf.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/halconf_nf.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/main.c create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/mcuconf.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/mcuconf_nf.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/target_board.h.in create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/CMakeLists.txt create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/chconf.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/halconf.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/halconf_nf.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/main.c create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf_nf.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/nanoHAL.cpp create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/target_board.h.in create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/stm32f7xx_hal_conf.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_BlockStorage.c create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_BlockStorage.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_common.c create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_common.h.in create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_external_memory.c create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_lwip_sntp_opts.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_lwipopts.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_nf_dev_onewire_config.cpp create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_nf_dev_onewire_config.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_nf_device_can_config.cpp create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_nf_device_can_config.h create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_adc_config.cpp create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_dac_config.cpp create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_i2c_config.cpp create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_pwm_config.cpp create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_spi_config.cpp create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.cpp create mode 100644 ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.h diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md index dc24e389..64bee362 100644 --- a/.github/PULL_REQUEST_TEMPLATE.md +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -21,6 +21,7 @@ - [ ] ST_STM32F411_DISCOVERY - [ ] ST_NUCLEO144_F412ZG_NF - [ ] ST_NUCLEO144_F746ZG +- [ ] ST_NUCLEO144_F767ZI - [ ] ST_STM32F4_DISCOVERY - [ ] ST_NUCLEO144_F439ZI - [ ] WEACT_F411CE diff --git a/CMakePresets.json b/CMakePresets.json index 4aed0ece..b3c8b7df 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -15,6 +15,7 @@ "ChibiOS/ST_NUCLEO144_F412ZG_NF/CMakePresets.json", "ChibiOS/ST_NUCLEO144_F439ZI/CMakePresets.json", "ChibiOS/ST_NUCLEO144_F746ZG/CMakePresets.json", + "ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json", "ChibiOS/ST_STM32F4_DISCOVERY/CMakePresets.json", "ChibiOS/ST_STM32F411_DISCOVERY/CMakePresets.json", "ChibiOS/WEACT_F411CE/CMakePresets.json", diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/CMakeLists.txt b/ChibiOS/ST_NUCLEO144_F767ZI/CMakeLists.txt new file mode 100644 index 00000000..f18cb001 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/CMakeLists.txt @@ -0,0 +1,51 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +include(binutils.common) +include(binutils.ChibiOS) + +nf_setup_target_build( + HAS_NANOBOOTER + + BOOTER_LINKER_FILE + STM32F76xx_booter + + CLR_LINKER_FILE + STM32F76xx_CLR + + CLR_EXTRA_SOURCE_FILES + # the next one is required is the target implements and it's using external memory + ${CMAKE_CURRENT_SOURCE_DIR}/target_external_memory.c + + BOOTER_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/ChibiOS/_common,--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x2000" + + CLR_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/ChibiOS/_common,--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x3B000" +) + +# generate bin file for deployment +if(SRECORD_TOOL_AVAILABLE) + + ############################################################################################################ + ## when changing the linker file make sure to update the addresses below with the offset of the CLR image ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + ############################################################################################################ + + if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + 10000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + else() + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + 10000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + endif() + +endif() diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json b/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json new file mode 100644 index 00000000..43465a08 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json @@ -0,0 +1,58 @@ +{ + "version": 4, + "include": [ + "../../../CMake/arm-gcc.json", + "../../../config/user-tools-repos.json", + "../../../config/user-prefs.json" + ], + "configurePresets": [ + { + "name": "ST_NUCLEO144_F767ZI", + "inherits": [ + "arm-gcc-cortex-preset", + "user-tools-repos", + "user-prefs" + ], + "hidden": false, + "cacheVariables": { + "TARGET_BOARD": "${presetName}", + "RTOS": "ChibiOS", + "TARGET_SERIES": "STM32F7xx", + "CHIBIOS_CONTRIB_REQUIRED": "OFF", + "STM32_CUBE_PACKAGE_REQUIRED": "OFF", + "SUPPORT_ANY_BASE_CONVERSION": "ON", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_HAS_SDCARD": "OFF", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "SWO_OUTPUT": "OFF", + "NF_BUILD_RTM": "OFF", + "API_System.Math": "ON", + "API_Hardware.Stm32": "ON", + "API_System.Device.Gpio": "ON", + "API_System.Device.Spi": "ON", + "API_System.Device.I2c": "ON", + "API_System.Device.Pwm": "ON", + "API_System.IO.Ports": "ON", + "API_System.Device.Adc": "ON", + "API_System.Device.Dac": "OFF", + "API_System.Net": "ON", + "API_nanoFramework.Device.OneWire": "OFF", + "API_nanoFramework.Device.Can": "ON", + "API_nanoFramework.ResourceManager": "ON", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON", + "API_Windows.Storage": "OFF", + "API_nanoFramework.Graphics": "OFF" + } + } + ], + "buildPresets": [ + { + "inherits": "base-user", + "name": "ST_NUCLEO144_F767ZI", + "displayName": "ST_NUCLEO144_F767ZI", + "configurePreset": "ST_NUCLEO144_F767ZI" + } + ] +} diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/README.md b/ChibiOS/ST_NUCLEO144_F767ZI/README.md new file mode 100644 index 00000000..a25cfca0 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/README.md @@ -0,0 +1,11 @@ +## Configuration of ChibiOS, HAL and MCU + +For a successful build the following changes are required: + +For memory maps, uuid etc. the reference document used was: http://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/96/8b/0d/ec/16/22/43/71/DM00224583/files/DM00224583.pdf/jcr:content/translations/en.DM00224583.pdf + +For port maps: +https://www.st.com/resource/en/user_manual/um1974-stm32-nucleo144-boards-mb1137-stmicroelectronics.pdf + +NOTE: this configuration was successfully tested in an ST_NUCLEO144_F767ZI board using the Serial port through the onboard ST Link USB connection. + diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/board.c b/ChibiOS/ST_NUCLEO144_F767ZI/board.c new file mode 100644 index 00000000..851aeb4c --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/board.c @@ -0,0 +1,270 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +// clang-format off + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* CHTODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* CHTODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* CHTODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* CHTODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @note You can add your board-specific code here. + */ +void boardInit(void) { + +} + +// clang-format on diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/board.h b/ChibiOS/ST_NUCLEO144_F767ZI/board.h new file mode 100644 index 00000000..9a2d748c --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/board.h @@ -0,0 +1,1866 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +// clang-format off + +#ifndef BOARD_H +#define BOARD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup for STMicroelectronics STM32 Nucleo144-F767ZI board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_NUCLEO144_F767ZI +#define BOARD_NAME "STMicroelectronics STM32 Nucleo144-F767ZI" + +/* + * Ethernet PHY type. + */ +#define BOARD_PHY_ID MII_LAN8742A_ID +#define BOARD_PHY_RMII + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#define STM32_LSEDRV (3U << 3U) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000U +#endif + +#define STM32_HSE_BYPASS + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F767xx + +/* + * IO pins assignments. + */ +#define GPIOA_ZIO_D32 0U +#define GPIOA_TIM2_CH1 0U +#define GPIOA_RMII_REF_CLK 1U +#define GPIOA_RMII_MDIO 2U +#define GPIOA_ARD_A0 3U +#define GPIOA_ADC123_IN3 3U +#define GPIOA_ZIO_D24 4U +#define GPIOA_SPI3_NSS 4U +#define GPIOA_ARD_D13 5U +#define GPIOA_SPI1_SCK 5U +#define GPIOA_ARD_D12 6U +#define GPIOA_SPI1_MISO 6U +#define GPIOA_ARD_D11 7U +#define GPIOA_SPI1_MOSI 7U +#define GPIOA_ZIO_D71 7U +#define GPIOA_RMII_RX_DV 7U +#define GPIOA_USB_SOF 8U +#define GPIOA_USB_VBUS 9U +#define GPIOA_USB_ID 10U +#define GPIOA_USB_DM 11U +#define GPIOA_USB_DP 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_ZIO_D20 15U +#define GPIOA_I2S3_WS 15U + +#define GPIOB_ZIO_D33 0U +#define GPIOB_TIM3_CH3 0U +#define GPIOB_LED1 0U +#define GPIOB_ZIO_A6 1U +#define GPIOB_ADC12_IN9 1U +#define GPIOB_ZIO_D27 2U +#define GPIOB_QSPI_CLK 2U +#define GPIOB_ZIO_D23 3U +#define GPIOB_I2S3_CK 3U +#define GPIOB_ZIO_D25 4U +#define GPIOB_SPI3_MISO 4U +#define GPIOB_ZIO_D22 5U +#define GPIOB_I2S3_SD 5U +#define GPIOB_ZIO_D26 6U +#define GPIOB_QSPI_BK1_NCS 6U +#define GPIOB_LED2 7U +#define GPIOB_ARD_D15 8U +#define GPIOB_I2C1_SCL 8U +#define GPIOB_ARD_D14 9U +#define GPIOB_I2C1_SDA 9U +#define GPIOB_ZIO_D36 10U +#define GPIOB_TIM2_CH3 10U +#define GPIOB_ZIO_D35 11U +#define GPIOB_TIM2_CH4 11U +#define GPIOB_ZIO_D19 12U +#define GPIOB_I2S2_WS 12U +#define GPIOB_ZIO_D18 13U +#define GPIOB_I2S2_CK 13U +#define GPIOB_RMII_TXD1 13U +#define GPIOB_LED3 14U +#define GPIOB_ZIO_D17 15U +#define GPIOB_I2S2_SD 15U + +#define GPIOC_ARD_A1 0U +#define GPIOC_ADC123_IN10 0U +#define GPIOC_RMII_MDC 1U +#define GPIOC_ZIO_A7 2U +#define GPIOC_ADC123_IN12 2U +#define GPIOC_ARD_A2 3U +#define GPIOC_ADC123_IN13 3U +#define GPIOC_RMII_RXD0 4U +#define GPIOC_RMII_RXD1 5U +#define GPIOC_ZIO_D16 6U +#define GPIOC_I2S2_MCK 6U +#define GPIOC_ZIO_D21 7U +#define GPIOC_I2S3_MCK 7U +#define GPIOC_ZIO_D43 8U +#define GPIOC_SDMMC_D0 8U +#define GPIOC_ZIO_D44 9U +#define GPIOC_SDMMC_D1 9U +#define GPIOC_ZIO_D45 10U +#define GPIOC_SDMMC_D2 10U +#define GPIOC_ZIO_D46 11U +#define GPIOC_SDMMC_D3 11U +#define GPIOC_ZIO_D47 12U +#define GPIOC_SDMMC_CK 12U +#define GPIOC_BUTTON 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_ZIO_D67 0U +#define GPIOD_CAN1_RX 0U +#define GPIOD_ZIO_D66 1U +#define GPIOD_CAN1_TX 1U +#define GPIOD_ZIO_D48 2U +#define GPIOD_SDMMC_CMD 2U +#define GPIOD_ZIO_D55 3U +#define GPIOD_USART2_CTS 3U +#define GPIOD_ZIO_D54 4U +#define GPIOD_USART2_RTS 4U +#define GPIOD_ZIO_D53 5U +#define GPIOD_USART2_TX 5U +#define GPIOD_ZIO_D52 6U +#define GPIOD_USART2_RX 6U +#define GPIOD_ZIO_D51 7U +#define GPIOD_USART2_SCLK 7U +#define GPIOD_USART3_RX 8U +#define GPIOD_STLK_RX 8U +#define GPIOD_USART3_TX 9U +#define GPIOD_STLK_TX 9U +#define GPIOD_PIN10 10U +#define GPIOD_ZIO_D30 11U +#define GPIOD_QSPI_BK1_IO0 11U +#define GPIOD_ZIO_D29 12U +#define GPIOD_QSPI_BK1_IO1 12U +#define GPIOD_ZIO_D28 13U +#define GPIOD_QSPI_BK1_IO3 13U +#define GPIOD_ARD_D10 14U +#define GPIOD_SPI1_NSS 14U +#define GPIOD_ARD_D9 15U +#define GPIOD_TIM4_CH4 15U + +#define GPIOE_ZIO_D34 0U +#define GPIOE_TIM4_ETR 0U +#define GPIOE_PIN1 1U +#define GPIOE_ZIO_D31 2U +#define GPIOE_ZIO_D56 2U +#define GPIOE_SAI1_MCLK_A 2U +#define GPIOE_ZIO_D60 3U +#define GPIOE_SAI1_SD_B 3U +#define GPIOE_ZIO_D57 4U +#define GPIOE_SAI1_FS_A 4U +#define GPIOE_ZIO_D58 5U +#define GPIOE_SAI1_SCK_A 5U +#define GPIOE_ZIO_D59 6U +#define GPIOE_SAI1_SD_A 6U +#define GPIOE_ZIO_D41 7U +#define GPIOE_TIM1_ETR 7U +#define GPIOE_ZIO_D42 8U +#define GPIOE_TIM1_CH1N 8U +#define GPIOE_ARD_D6 9U +#define GPIOE_TIM1_CH1 9U +#define GPIOE_ZIO_D40 10U +#define GPIOE_TIM1_CH2N 10U +#define GPIOE_ARD_D5 11U +#define GPIOE_TIM1_CH2 11U +#define GPIOE_ZIO_D39 12U +#define GPIOE_TIM1_CH3N 12U +#define GPIOE_ARD_D3 13U +#define GPIOE_TIM1_CH3 13U +#define GPIOE_ZIO_D38 14U +#define GPIOE_ZIO_D37 15U +#define GPIOE_TIM1_BKIN1 15U + +#define GPIOF_ZIO_D68 0U +#define GPIOF_I2C2_SDA 0U +#define GPIOF_ZIO_D69 1U +#define GPIOF_I2C2_SCL 1U +#define GPIOF_ZIO_D70 2U +#define GPIOF_I2C2_SMBA 2U +#define GPIOF_ARD_A3 3U +#define GPIOF_ADC3_IN9 3U +#define GPIOF_ZIO_A8 4U +#define GPIOF_ADC3_IN14 4U +#define GPIOF_ARD_A4 5U +#define GPIOF_ADC3_IN15 5U +#define GPIOF_PIN6 6U +#define GPIOF_ZIO_D62 7U +#define GPIOF_SAI1_MCLK_B 7U +#define GPIOF_ZIO_D61 8U +#define GPIOF_SAI1_SCK_B 8U +#define GPIOF_ZIO_D63 9U +#define GPIOF_SAI1_FS_B 9U +#define GPIOF_ARD_A5 10U +#define GPIOF_ADC3_IN8 10U +#define GPIOF_PIN11 11U +#define GPIOF_ARD_D8 12U +#define GPIOF_ARD_D7 13U +#define GPIOF_ARD_D4 14U +#define GPIOF_ARD_D2 15U + +#define GPIOG_ZIO_D65 0U +#define GPIOG_ZIO_D64 1U +#define GPIOG_ZIO_D49 2U +#define GPIOG_ZIO_D50 3U +#define GPIOG_PIN4 4U +#define GPIOG_PIN5 5U +#define GPIOG_USB_GPIO_OUT 6U +#define GPIOG_USB_GPIO_IN 7U +#define GPIOG_PIN8 8U +#define GPIOG_ARD_D0 9U +#define GPIOG_USART6_RX 9U +#define GPIOG_PIN10 10U +#define GPIOG_RMII_TX_EN 11U +#define GPIOG_PIN12 12U +#define GPIOG_RMII_TXD0 13U +#define GPIOG_ARD_D1 14U +#define GPIOG_USART6_TX 14U +#define GPIOG_PIN15 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +#define GPIOI_PIN0 0U +#define GPIOI_PIN1 1U +#define GPIOI_PIN2 2U +#define GPIOI_PIN3 3U +#define GPIOI_PIN4 4U +#define GPIOI_PIN5 5U +#define GPIOI_PIN6 6U +#define GPIOI_PIN7 7U +#define GPIOI_PIN8 8U +#define GPIOI_PIN9 9U +#define GPIOI_PIN10 10U +#define GPIOI_PIN11 11U +#define GPIOI_PIN12 12U +#define GPIOI_PIN13 13U +#define GPIOI_PIN14 14U +#define GPIOI_PIN15 15U + +#define GPIOJ_PIN0 0U +#define GPIOJ_PIN1 1U +#define GPIOJ_PIN2 2U +#define GPIOJ_PIN3 3U +#define GPIOJ_PIN4 4U +#define GPIOJ_PIN5 5U +#define GPIOJ_PIN6 6U +#define GPIOJ_PIN7 7U +#define GPIOJ_PIN8 8U +#define GPIOJ_PIN9 9U +#define GPIOJ_PIN10 10U +#define GPIOJ_PIN11 11U +#define GPIOJ_PIN12 12U +#define GPIOJ_PIN13 13U +#define GPIOJ_PIN14 14U +#define GPIOJ_PIN15 15U + +#define GPIOK_PIN0 0U +#define GPIOK_PIN1 1U +#define GPIOK_PIN2 2U +#define GPIOK_PIN3 3U +#define GPIOK_PIN4 4U +#define GPIOK_PIN5 5U +#define GPIOK_PIN6 6U +#define GPIOK_PIN7 7U +#define GPIOK_PIN8 8U +#define GPIOK_PIN9 9U +#define GPIOK_PIN10 10U +#define GPIOK_PIN11 11U +#define GPIOK_PIN12 12U +#define GPIOK_PIN13 13U +#define GPIOK_PIN14 14U +#define GPIOK_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_ZIO_D32 PAL_LINE(GPIOA, 0U) +#define LINE_TIM2_CH1 PAL_LINE(GPIOA, 0U) +#define LINE_RMII_REF_CLK PAL_LINE(GPIOA, 1U) +#define LINE_RMII_MDIO PAL_LINE(GPIOA, 2U) +#define LINE_ARD_A0 PAL_LINE(GPIOA, 3U) +#define LINE_ADC123_IN3 PAL_LINE(GPIOA, 3U) +#define LINE_ZIO_D24 PAL_LINE(GPIOA, 4U) +#define LINE_SPI3_NSS PAL_LINE(GPIOA, 4U) +#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U) +#define LINE_SPI1_SCK PAL_LINE(GPIOA, 5U) +#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U) +#define LINE_SPI1_MISO PAL_LINE(GPIOA, 6U) +#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U) +#define LINE_SPI1_MOSI PAL_LINE(GPIOA, 7U) +#define LINE_ZIO_D71 PAL_LINE(GPIOA, 7U) +#define LINE_RMII_RX_DV PAL_LINE(GPIOA, 7U) +#define LINE_USB_SOF PAL_LINE(GPIOA, 8U) +#define LINE_USB_VBUS PAL_LINE(GPIOA, 9U) +#define LINE_USB_ID PAL_LINE(GPIOA, 10U) +#define LINE_USB_DM PAL_LINE(GPIOA, 11U) +#define LINE_USB_DP PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_ZIO_D20 PAL_LINE(GPIOA, 15U) +#define LINE_I2S3_WS PAL_LINE(GPIOA, 15U) +#define LINE_ZIO_D33 PAL_LINE(GPIOB, 0U) +#define LINE_TIM3_CH3 PAL_LINE(GPIOB, 0U) +#define LINE_LED1 PAL_LINE(GPIOB, 0U) +#define LINE_ZIO_A6 PAL_LINE(GPIOB, 1U) +#define LINE_ADC12_IN9 PAL_LINE(GPIOB, 1U) +#define LINE_ZIO_D27 PAL_LINE(GPIOB, 2U) +#define LINE_QSPI_CLK PAL_LINE(GPIOB, 2U) +#define LINE_ZIO_D23 PAL_LINE(GPIOB, 3U) +#define LINE_I2S3_CK PAL_LINE(GPIOB, 3U) +#define LINE_ZIO_D25 PAL_LINE(GPIOB, 4U) +#define LINE_SPI3_MISO PAL_LINE(GPIOB, 4U) +#define LINE_ZIO_D22 PAL_LINE(GPIOB, 5U) +#define LINE_I2S3_SD PAL_LINE(GPIOB, 5U) +#define LINE_ZIO_D26 PAL_LINE(GPIOB, 6U) +#define LINE_QSPI_BK1_NCS PAL_LINE(GPIOB, 6U) +#define LINE_LED2 PAL_LINE(GPIOB, 7U) +#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U) +#define LINE_I2C1_SCL PAL_LINE(GPIOB, 8U) +#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U) +#define LINE_I2C1_SDA PAL_LINE(GPIOB, 9U) +#define LINE_ZIO_D36 PAL_LINE(GPIOB, 10U) +#define LINE_TIM2_CH3 PAL_LINE(GPIOB, 10U) +#define LINE_ZIO_D35 PAL_LINE(GPIOB, 11U) +#define LINE_TIM2_CH4 PAL_LINE(GPIOB, 11U) +#define LINE_ZIO_D19 PAL_LINE(GPIOB, 12U) +#define LINE_I2S2_WS PAL_LINE(GPIOB, 12U) +#define LINE_ZIO_D18 PAL_LINE(GPIOB, 13U) +#define LINE_I2S2_CK PAL_LINE(GPIOB, 13U) +#define LINE_RMII_TXD1 PAL_LINE(GPIOB, 13U) +#define LINE_LED3 PAL_LINE(GPIOB, 14U) +#define LINE_ZIO_D17 PAL_LINE(GPIOB, 15U) +#define LINE_I2S2_SD PAL_LINE(GPIOB, 15U) +#define LINE_ARD_A1 PAL_LINE(GPIOC, 0U) +#define LINE_ADC123_IN10 PAL_LINE(GPIOC, 0U) +#define LINE_RMII_MDC PAL_LINE(GPIOC, 1U) +#define LINE_ZIO_A7 PAL_LINE(GPIOC, 2U) +#define LINE_ADC123_IN12 PAL_LINE(GPIOC, 2U) +#define LINE_ARD_A2 PAL_LINE(GPIOC, 3U) +#define LINE_ADC123_IN13 PAL_LINE(GPIOC, 3U) +#define LINE_RMII_RXD0 PAL_LINE(GPIOC, 4U) +#define LINE_RMII_RXD1 PAL_LINE(GPIOC, 5U) +#define LINE_ZIO_D16 PAL_LINE(GPIOC, 6U) +#define LINE_I2S2_MCK PAL_LINE(GPIOC, 6U) +#define LINE_ZIO_D21 PAL_LINE(GPIOC, 7U) +#define LINE_I2S3_MCK PAL_LINE(GPIOC, 7U) +#define LINE_ZIO_D43 PAL_LINE(GPIOC, 8U) +#define LINE_SDMMC_D0 PAL_LINE(GPIOC, 8U) +#define LINE_ZIO_D44 PAL_LINE(GPIOC, 9U) +#define LINE_SDMMC_D1 PAL_LINE(GPIOC, 9U) +#define LINE_ZIO_D45 PAL_LINE(GPIOC, 10U) +#define LINE_SDMMC_D2 PAL_LINE(GPIOC, 10U) +#define LINE_ZIO_D46 PAL_LINE(GPIOC, 11U) +#define LINE_SDMMC_D3 PAL_LINE(GPIOC, 11U) +#define LINE_ZIO_D47 PAL_LINE(GPIOC, 12U) +#define LINE_SDMMC_CK PAL_LINE(GPIOC, 12U) +#define LINE_BUTTON PAL_LINE(GPIOC, 13U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) +#define LINE_ZIO_D67 PAL_LINE(GPIOD, 0U) +#define LINE_CAN1_RX PAL_LINE(GPIOD, 0U) +#define LINE_ZIO_D66 PAL_LINE(GPIOD, 1U) +#define LINE_CAN1_TX PAL_LINE(GPIOD, 1U) +#define LINE_ZIO_D48 PAL_LINE(GPIOD, 2U) +#define LINE_SDMMC_CMD PAL_LINE(GPIOD, 2U) +#define LINE_ZIO_D55 PAL_LINE(GPIOD, 3U) +#define LINE_USART2_CTS PAL_LINE(GPIOD, 3U) +#define LINE_ZIO_D54 PAL_LINE(GPIOD, 4U) +#define LINE_USART2_RTS PAL_LINE(GPIOD, 4U) +#define LINE_ZIO_D53 PAL_LINE(GPIOD, 5U) +#define LINE_USART2_TX PAL_LINE(GPIOD, 5U) +#define LINE_ZIO_D52 PAL_LINE(GPIOD, 6U) +#define LINE_USART2_RX PAL_LINE(GPIOD, 6U) +#define LINE_ZIO_D51 PAL_LINE(GPIOD, 7U) +#define LINE_USART2_SCLK PAL_LINE(GPIOD, 7U) +#define LINE_USART3_RX PAL_LINE(GPIOD, 8U) +#define LINE_STLK_RX PAL_LINE(GPIOD, 8U) +#define LINE_USART3_TX PAL_LINE(GPIOD, 9U) +#define LINE_STLK_TX PAL_LINE(GPIOD, 9U) +#define LINE_ZIO_D30 PAL_LINE(GPIOD, 11U) +#define LINE_QSPI_BK1_IO0 PAL_LINE(GPIOD, 11U) +#define LINE_ZIO_D29 PAL_LINE(GPIOD, 12U) +#define LINE_QSPI_BK1_IO1 PAL_LINE(GPIOD, 12U) +#define LINE_ZIO_D28 PAL_LINE(GPIOD, 13U) +#define LINE_QSPI_BK1_IO3 PAL_LINE(GPIOD, 13U) +#define LINE_ARD_D10 PAL_LINE(GPIOD, 14U) +#define LINE_SPI1_NSS PAL_LINE(GPIOD, 14U) +#define LINE_ARD_D9 PAL_LINE(GPIOD, 15U) +#define LINE_TIM4_CH4 PAL_LINE(GPIOD, 15U) +#define LINE_ZIO_D34 PAL_LINE(GPIOE, 0U) +#define LINE_TIM4_ETR PAL_LINE(GPIOE, 0U) +#define LINE_ZIO_D31 PAL_LINE(GPIOE, 2U) +#define LINE_ZIO_D56 PAL_LINE(GPIOE, 2U) +#define LINE_SAI1_MCLK_A PAL_LINE(GPIOE, 2U) +#define LINE_ZIO_D60 PAL_LINE(GPIOE, 3U) +#define LINE_SAI1_SD_B PAL_LINE(GPIOE, 3U) +#define LINE_ZIO_D57 PAL_LINE(GPIOE, 4U) +#define LINE_SAI1_FS_A PAL_LINE(GPIOE, 4U) +#define LINE_ZIO_D58 PAL_LINE(GPIOE, 5U) +#define LINE_SAI1_SCK_A PAL_LINE(GPIOE, 5U) +#define LINE_ZIO_D59 PAL_LINE(GPIOE, 6U) +#define LINE_SAI1_SD_A PAL_LINE(GPIOE, 6U) +#define LINE_ZIO_D41 PAL_LINE(GPIOE, 7U) +#define LINE_TIM1_ETR PAL_LINE(GPIOE, 7U) +#define LINE_ZIO_D42 PAL_LINE(GPIOE, 8U) +#define LINE_TIM1_CH1N PAL_LINE(GPIOE, 8U) +#define LINE_ARD_D6 PAL_LINE(GPIOE, 9U) +#define LINE_TIM1_CH1 PAL_LINE(GPIOE, 9U) +#define LINE_ZIO_D40 PAL_LINE(GPIOE, 10U) +#define LINE_TIM1_CH2N PAL_LINE(GPIOE, 10U) +#define LINE_ARD_D5 PAL_LINE(GPIOE, 11U) +#define LINE_TIM1_CH2 PAL_LINE(GPIOE, 11U) +#define LINE_ZIO_D39 PAL_LINE(GPIOE, 12U) +#define LINE_TIM1_CH3N PAL_LINE(GPIOE, 12U) +#define LINE_ARD_D3 PAL_LINE(GPIOE, 13U) +#define LINE_TIM1_CH3 PAL_LINE(GPIOE, 13U) +#define LINE_ZIO_D38 PAL_LINE(GPIOE, 14U) +#define LINE_ZIO_D37 PAL_LINE(GPIOE, 15U) +#define LINE_TIM1_BKIN1 PAL_LINE(GPIOE, 15U) +#define LINE_ZIO_D68 PAL_LINE(GPIOF, 0U) +#define LINE_I2C2_SDA PAL_LINE(GPIOF, 0U) +#define LINE_ZIO_D69 PAL_LINE(GPIOF, 1U) +#define LINE_I2C2_SCL PAL_LINE(GPIOF, 1U) +#define LINE_ZIO_D70 PAL_LINE(GPIOF, 2U) +#define LINE_I2C2_SMBA PAL_LINE(GPIOF, 2U) +#define LINE_ARD_A3 PAL_LINE(GPIOF, 3U) +#define LINE_ADC3_IN9 PAL_LINE(GPIOF, 3U) +#define LINE_ZIO_A8 PAL_LINE(GPIOF, 4U) +#define LINE_ADC3_IN14 PAL_LINE(GPIOF, 4U) +#define LINE_ARD_A4 PAL_LINE(GPIOF, 5U) +#define LINE_ADC3_IN15 PAL_LINE(GPIOF, 5U) +#define LINE_ZIO_D62 PAL_LINE(GPIOF, 7U) +#define LINE_SAI1_MCLK_B PAL_LINE(GPIOF, 7U) +#define LINE_ZIO_D61 PAL_LINE(GPIOF, 8U) +#define LINE_SAI1_SCK_B PAL_LINE(GPIOF, 8U) +#define LINE_ZIO_D63 PAL_LINE(GPIOF, 9U) +#define LINE_SAI1_FS_B PAL_LINE(GPIOF, 9U) +#define LINE_ARD_A5 PAL_LINE(GPIOF, 10U) +#define LINE_ADC3_IN8 PAL_LINE(GPIOF, 10U) +#define LINE_ARD_D8 PAL_LINE(GPIOF, 12U) +#define LINE_ARD_D7 PAL_LINE(GPIOF, 13U) +#define LINE_ARD_D4 PAL_LINE(GPIOF, 14U) +#define LINE_ARD_D2 PAL_LINE(GPIOF, 15U) +#define LINE_ZIO_D65 PAL_LINE(GPIOG, 0U) +#define LINE_ZIO_D64 PAL_LINE(GPIOG, 1U) +#define LINE_ZIO_D49 PAL_LINE(GPIOG, 2U) +#define LINE_ZIO_D50 PAL_LINE(GPIOG, 3U) +#define LINE_USB_GPIO_OUT PAL_LINE(GPIOG, 6U) +#define LINE_USB_GPIO_IN PAL_LINE(GPIOG, 7U) +#define LINE_ARD_D0 PAL_LINE(GPIOG, 9U) +#define LINE_USART6_RX PAL_LINE(GPIOG, 9U) +#define LINE_RMII_TX_EN PAL_LINE(GPIOG, 11U) +#define LINE_RMII_TXD0 PAL_LINE(GPIOG, 13U) +#define LINE_ARD_D1 PAL_LINE(GPIOG, 14U) +#define LINE_USART6_TX PAL_LINE(GPIOG, 14U) +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - ZIO_D32 TIM2_CH1 (input pullup). + * PA1 - RMII_REF_CLK (alternate 11). + * PA2 - RMII_MDIO (alternate 11). + * PA3 - ARD_A0 ADC123_IN3 (input pullup). + * PA4 - ZIO_D24 SPI3_NSS (input pullup). + * PA5 - ARD_D13 SPI1_SCK (input pullup). + * PA6 - ARD_D12 SPI1_MISO (input pullup). + * PA7 - ARD_D11 SPI1_MOSI ZIO_D71 RMII_RX_DV(alternate 11). + * PA8 - USB_SOF (alternate 10). + * PA9 - USB_VBUS (analog). + * PA10 - USB_ID (alternate 10). + * PA11 - USB_DM (alternate 10). + * PA12 - USB_DP (alternate 10). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - ZIO_D20 I2S3_WS (input pullup). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_ZIO_D32) | \ + PIN_MODE_ALTERNATE(GPIOA_RMII_REF_CLK) |\ + PIN_MODE_ALTERNATE(GPIOA_RMII_MDIO) | \ + PIN_MODE_INPUT(GPIOA_ARD_A0) | \ + PIN_MODE_INPUT(GPIOA_ZIO_D24) | \ + PIN_MODE_INPUT(GPIOA_ARD_D13) | \ + PIN_MODE_INPUT(GPIOA_ARD_D12) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D11) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_SOF) | \ + PIN_MODE_ANALOG(GPIOA_USB_VBUS) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_ID) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_ZIO_D20)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D32) | \ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_REF_CLK) |\ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_MDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D24) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_SOF) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_VBUS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D20)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ZIO_D32) | \ + PIN_OSPEED_HIGH(GPIOA_RMII_REF_CLK) | \ + PIN_OSPEED_HIGH(GPIOA_RMII_MDIO) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \ + PIN_OSPEED_HIGH(GPIOA_ZIO_D24) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D13) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \ + PIN_OSPEED_HIGH(GPIOA_USB_SOF) | \ + PIN_OSPEED_HIGH(GPIOA_USB_VBUS) | \ + PIN_OSPEED_HIGH(GPIOA_USB_ID) | \ + PIN_OSPEED_HIGH(GPIOA_USB_DM) | \ + PIN_OSPEED_HIGH(GPIOA_USB_DP) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_ZIO_D20)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_ZIO_D32) | \ + PIN_PUPDR_FLOATING(GPIOA_RMII_REF_CLK) |\ + PIN_PUPDR_PULLUP(GPIOA_RMII_MDIO) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | \ + PIN_PUPDR_PULLUP(GPIOA_ZIO_D24) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D13) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D12) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D11) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_SOF) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_VBUS) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_ID) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_ZIO_D20)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ZIO_D32) | \ + PIN_ODR_HIGH(GPIOA_RMII_REF_CLK) | \ + PIN_ODR_HIGH(GPIOA_RMII_MDIO) | \ + PIN_ODR_HIGH(GPIOA_ARD_A0) | \ + PIN_ODR_HIGH(GPIOA_ZIO_D24) | \ + PIN_ODR_HIGH(GPIOA_ARD_D13) | \ + PIN_ODR_HIGH(GPIOA_ARD_D12) | \ + PIN_ODR_HIGH(GPIOA_ARD_D11) | \ + PIN_ODR_HIGH(GPIOA_USB_SOF) | \ + PIN_ODR_HIGH(GPIOA_USB_VBUS) | \ + PIN_ODR_HIGH(GPIOA_USB_ID) | \ + PIN_ODR_HIGH(GPIOA_USB_DM) | \ + PIN_ODR_HIGH(GPIOA_USB_DP) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_ZIO_D20)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ZIO_D32, 0U) | \ + PIN_AFIO_AF(GPIOA_RMII_REF_CLK, 11U) | \ + PIN_AFIO_AF(GPIOA_RMII_MDIO, 11U) | \ + PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \ + PIN_AFIO_AF(GPIOA_ZIO_D24, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D13, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D11, 11U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_SOF, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_VBUS, 0U) | \ + PIN_AFIO_AF(GPIOA_USB_ID, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_DM, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_DP, 10U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_ZIO_D20, 0U)) + +/* + * GPIOB setup: + * + * PB0 - ZIO_D33 TIM3_CH3 LED1 (output pushpull maximum). + * PB1 - ZIO_A6 ADC12_IN9 (input pullup). + * PB2 - ZIO_D27 QSPI_CLK (input pullup). + * PB3 - ZIO_D23 I2S3_CK (input pullup). + * PB4 - ZIO_D25 SPI3_MISO (input pullup). + * PB5 - ZIO_D22 I2S3_SD (input pullup). + * PB6 - ZIO_D26 QSPI_BK1_NCS (input pullup). + * PB7 - LED2 (output pushpull maximum). + * PB8 - ARD_D15 I2C1_SCL (input pullup). + * PB9 - ARD_D14 I2C1_SDA (input pullup). + * PB10 - ZIO_D36 TIM2_CH3 (input pullup). + * PB11 - ZIO_D35 TIM2_CH4 (input pullup). + * PB12 - ZIO_D19 I2S2_WS (input pullup). + * PB13 - ZIO_D18 I2S2_CK RMII_TXD1 (alternate 11). + * PB14 - LED3 (output pushpull maximum). + * PB15 - ZIO_D17 I2S2_SD (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_ZIO_D33) | \ + PIN_MODE_INPUT(GPIOB_ZIO_A6) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D27) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D23) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D25) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D22) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D26) | \ + PIN_MODE_OUTPUT(GPIOB_LED2) | \ + PIN_MODE_INPUT(GPIOB_ARD_D15) | \ + PIN_MODE_INPUT(GPIOB_ARD_D14) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D36) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D35) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D19) | \ + PIN_MODE_ALTERNATE(GPIOB_ZIO_D18) | \ + PIN_MODE_OUTPUT(GPIOB_LED3) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D17)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D33) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_A6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D27) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D23) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D25) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D22) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D26) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LED2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D15) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D36) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D35) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D19) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D18) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LED3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D17)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ZIO_D33) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_A6) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D27) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D23) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D25) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D22) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D26) | \ + PIN_OSPEED_HIGH(GPIOB_LED2) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D15) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D14) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D36) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D35) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D19) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D18) | \ + PIN_OSPEED_HIGH(GPIOB_LED3) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D17)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_ZIO_D33) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_A6) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D27) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D23) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D25) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D22) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D26) | \ + PIN_PUPDR_FLOATING(GPIOB_LED2) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D15) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D14) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D36) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D35) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D19) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D18) | \ + PIN_PUPDR_FLOATING(GPIOB_LED3) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D17)) +#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_ZIO_D33) | \ + PIN_ODR_HIGH(GPIOB_ZIO_A6) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D27) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D23) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D25) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D22) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D26) | \ + PIN_ODR_LOW(GPIOB_LED2) | \ + PIN_ODR_HIGH(GPIOB_ARD_D15) | \ + PIN_ODR_HIGH(GPIOB_ARD_D14) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D36) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D35) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D19) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D18) | \ + PIN_ODR_LOW(GPIOB_LED3) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D17)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ZIO_D33, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_A6, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D27, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D23, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D25, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D22, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D26, 0U) | \ + PIN_AFIO_AF(GPIOB_LED2, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D14, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D36, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D35, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D19, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D18, 11U) | \ + PIN_AFIO_AF(GPIOB_LED3, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D17, 0U)) + +/* + * GPIOC setup: + * + * PC0 - ARD_A1 ADC123_IN10 (input pullup). + * PC1 - RMII_MDC (alternate 11). + * PC2 - ZIO_A7 ADC123_IN12 (input pullup). + * PC3 - ARD_A2 ADC123_IN13 (input pullup). + * PC4 - RMII_RXD0 (alternate 11). + * PC5 - RMII_RXD1 (alternate 11). + * PC6 - ZIO_D16 I2S2_MCK (input pullup). + * PC7 - ZIO_D21 I2S3_MCK (input pullup). + * PC8 - ZIO_D43 SDMMC_D0 (input pullup). + * PC9 - ZIO_D44 SDMMC_D1 (input pullup). + * PC10 - ZIO_D45 SDMMC_D2 (input pullup). + * PC11 - ZIO_D46 SDMMC_D3 (input pullup). + * PC12 - ZIO_D47 SDMMC_CK (input pullup). + * PC13 - BUTTON (input floating). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_ARD_A1) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_MDC) | \ + PIN_MODE_INPUT(GPIOC_ZIO_A7) | \ + PIN_MODE_INPUT(GPIOC_ARD_A2) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_RXD0) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_RXD1) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D16) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D21) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D43) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D44) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D45) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D46) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D47) | \ + PIN_MODE_INPUT(GPIOC_BUTTON) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_MDC) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_A7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D16) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D21) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D43) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D44) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D45) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D46) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D47) | \ + PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A1) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_MDC) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_A7) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_A2) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_RXD0) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_RXD1) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D16) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D21) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D43) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D44) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D45) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D46) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D47) | \ + PIN_OSPEED_HIGH(GPIOC_BUTTON) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_ARD_A1) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_MDC) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_A7) | \ + PIN_PUPDR_PULLUP(GPIOC_ARD_A2) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_RXD0) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_RXD1) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D16) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D21) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D43) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D44) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D45) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D46) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D47) | \ + PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A1) | \ + PIN_ODR_HIGH(GPIOC_RMII_MDC) | \ + PIN_ODR_HIGH(GPIOC_ZIO_A7) | \ + PIN_ODR_HIGH(GPIOC_ARD_A2) | \ + PIN_ODR_HIGH(GPIOC_RMII_RXD0) | \ + PIN_ODR_HIGH(GPIOC_RMII_RXD1) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D16) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D21) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D43) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D44) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D45) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D46) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D47) | \ + PIN_ODR_HIGH(GPIOC_BUTTON) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A1, 0U) | \ + PIN_AFIO_AF(GPIOC_RMII_MDC, 11U) | \ + PIN_AFIO_AF(GPIOC_ZIO_A7, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_A2, 0U) | \ + PIN_AFIO_AF(GPIOC_RMII_RXD0, 11U) | \ + PIN_AFIO_AF(GPIOC_RMII_RXD1, 11U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D16, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D21, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_ZIO_D43, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D44, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D45, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D46, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D47, 0U) | \ + PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + +/* + * GPIOD setup: + * + * PD0 - ZIO_D67 CAN1_RX (input pullup). + * PD1 - ZIO_D66 CAN1_TX (input pullup). + * PD2 - ZIO_D48 SDMMC_CMD (input pullup). + * PD3 - ZIO_D55 USART2_CTS (input pullup). + * PD4 - ZIO_D54 USART2_RTS (input pullup). + * PD5 - ZIO_D53 USART2_TX (input pullup). + * PD6 - ZIO_D52 USART2_RX (input pullup). + * PD7 - ZIO_D51 USART2_SCLK (input pullup). + * PD8 - USART3_RX STLK_RX (alternate 7). + * PD9 - USART3_TX STLK_TX (alternate 7). + * PD10 - PIN10 (input pullup). + * PD11 - ZIO_D30 QSPI_BK1_IO0 (input pullup). + * PD12 - ZIO_D29 QSPI_BK1_IO1 (input pullup). + * PD13 - ZIO_D28 QSPI_BK1_IO3 (input pullup). + * PD14 - ARD_D10 SPI1_NSS (input pullup). + * PD15 - ARD_D9 TIM4_CH4 (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_ZIO_D67) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D66) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D48) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D55) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D54) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D53) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D52) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D51) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D30) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D29) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D28) | \ + PIN_MODE_INPUT(GPIOD_ARD_D10) | \ + PIN_MODE_INPUT(GPIOD_ARD_D9)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D67) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D66) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D48) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D55) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D54) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D53) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D52) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D51) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D30) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D29) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D28) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ARD_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ARD_D9)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_ZIO_D67) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D66) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D48) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D55) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D54) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D53) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D52) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D51) | \ + PIN_OSPEED_HIGH(GPIOD_USART3_RX) | \ + PIN_OSPEED_HIGH(GPIOD_USART3_TX) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN10) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D30) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D29) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D28) | \ + PIN_OSPEED_HIGH(GPIOD_ARD_D10) | \ + PIN_OSPEED_HIGH(GPIOD_ARD_D9)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_ZIO_D67) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D66) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D48) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D55) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D54) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D53) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D52) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D51) | \ + PIN_PUPDR_FLOATING(GPIOD_USART3_RX) | \ + PIN_PUPDR_FLOATING(GPIOD_USART3_TX) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D30) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D29) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D28) | \ + PIN_PUPDR_PULLUP(GPIOD_ARD_D10) | \ + PIN_PUPDR_PULLUP(GPIOD_ARD_D9)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_ZIO_D67) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D66) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D48) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D55) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D54) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D53) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D52) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D51) | \ + PIN_ODR_HIGH(GPIOD_USART3_RX) | \ + PIN_ODR_HIGH(GPIOD_USART3_TX) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D30) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D29) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D28) | \ + PIN_ODR_HIGH(GPIOD_ARD_D10) | \ + PIN_ODR_HIGH(GPIOD_ARD_D9)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_ZIO_D67, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D66, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D48, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D55, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D54, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D53, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D52, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D51, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_RX, 7U) | \ + PIN_AFIO_AF(GPIOD_USART3_TX, 7U) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D30, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D29, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D28, 0U) | \ + PIN_AFIO_AF(GPIOD_ARD_D10, 0U) | \ + PIN_AFIO_AF(GPIOD_ARD_D9, 0U)) + +/* + * GPIOE setup: + * + * PE0 - ZIO_D34 TIM4_ETR (input pullup). + * PE1 - PIN1 (input pullup). + * PE2 - ZIO_D31 ZIO_D56 SAI1_MCLK_A(input pullup). + * PE3 - ZIO_D60 SAI1_SD_B (input pullup). + * PE4 - ZIO_D57 SAI1_FS_A (input pullup). + * PE5 - ZIO_D58 SAI1_SCK_A (input pullup). + * PE6 - ZIO_D59 SAI1_SD_A (input pullup). + * PE7 - ZIO_D41 TIM1_ETR (input pullup). + * PE8 - ZIO_D42 TIM1_CH1N (input pullup). + * PE9 - ARD_D6 TIM1_CH1 (input pullup). + * PE10 - ZIO_D40 TIM1_CH2N (input pullup). + * PE11 - ARD_D5 TIM1_CH2 (input pullup). + * PE12 - ZIO_D39 TIM1_CH3N (input pullup). + * PE13 - ARD_D3 TIM1_CH3 (input pullup). + * PE14 - ZIO_D38 (input pullup). + * PE15 - ZIO_D37 TIM1_BKIN1 (input pullup). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_ZIO_D34) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D31) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D60) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D57) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D58) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D59) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D41) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D42) | \ + PIN_MODE_INPUT(GPIOE_ARD_D6) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D40) | \ + PIN_MODE_INPUT(GPIOE_ARD_D5) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D39) | \ + PIN_MODE_INPUT(GPIOE_ARD_D3) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D38) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D37)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D34) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D31) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D60) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D57) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D58) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D59) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D41) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D42) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ARD_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D40) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ARD_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D39) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ARD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D38) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D37)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_ZIO_D34) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN1) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D31) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D60) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D57) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D58) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D59) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D41) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D42) | \ + PIN_OSPEED_HIGH(GPIOE_ARD_D6) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D40) | \ + PIN_OSPEED_HIGH(GPIOE_ARD_D5) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D39) | \ + PIN_OSPEED_HIGH(GPIOE_ARD_D3) | \ + PIN_OSPEED_VERYLOW(GPIOE_ZIO_D38) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D37)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_ZIO_D34) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D31) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D60) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D57) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D58) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D59) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D41) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D42) | \ + PIN_PUPDR_PULLUP(GPIOE_ARD_D6) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D40) | \ + PIN_PUPDR_PULLUP(GPIOE_ARD_D5) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D39) | \ + PIN_PUPDR_PULLUP(GPIOE_ARD_D3) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D38) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D37)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_ZIO_D34) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D31) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D60) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D57) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D58) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D59) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D41) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D42) | \ + PIN_ODR_HIGH(GPIOE_ARD_D6) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D40) | \ + PIN_ODR_HIGH(GPIOE_ARD_D5) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D39) | \ + PIN_ODR_HIGH(GPIOE_ARD_D3) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D38) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D37)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_ZIO_D34, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D31, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D60, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D57, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D58, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D59, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D41, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_ZIO_D42, 0U) | \ + PIN_AFIO_AF(GPIOE_ARD_D6, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D40, 0U) | \ + PIN_AFIO_AF(GPIOE_ARD_D5, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D39, 0U) | \ + PIN_AFIO_AF(GPIOE_ARD_D3, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D38, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D37, 0U)) + +/* + * GPIOF setup: + * + * PF0 - ZIO_D68 I2C2_SDA (input pullup). + * PF1 - ZIO_D69 I2C2_SCL (input pullup). + * PF2 - ZIO_D70 I2C2_SMBA (input pullup). + * PF3 - ARD_A3 ADC3_IN9 (input pullup). + * PF4 - ZIO_A8 ADC3_IN14 (input pullup). + * PF5 - ARD_A4 ADC3_IN15 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - ZIO_D62 SAI1_MCLK_B (input pullup). + * PF8 - ZIO_D61 SAI1_SCK_B (input pullup). + * PF9 - ZIO_D63 SAI1_FS_B (input pullup). + * PF10 - ARD_A5 ADC3_IN8 (input pullup). + * PF11 - PIN11 (input pullup). + * PF12 - ARD_D8 (input pullup). + * PF13 - ARD_D7 (input pullup). + * PF14 - ARD_D4 (input pullup). + * PF15 - ARD_D2 (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_ZIO_D68) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D69) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D70) | \ + PIN_MODE_INPUT(GPIOF_ARD_A3) | \ + PIN_MODE_INPUT(GPIOF_ZIO_A8) | \ + PIN_MODE_INPUT(GPIOF_ARD_A4) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D62) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D61) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D63) | \ + PIN_MODE_INPUT(GPIOF_ARD_A5) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_ARD_D8) | \ + PIN_MODE_INPUT(GPIOF_ARD_D7) | \ + PIN_MODE_INPUT(GPIOF_ARD_D4) | \ + PIN_MODE_INPUT(GPIOF_ARD_D2)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D68) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D69) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D70) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_A8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D62) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D61) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D63) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D2)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_ZIO_D68) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D69) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D70) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A3) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_A8) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A4) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D62) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D61) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D63) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A5) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D8) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D7) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D4) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D2)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_ZIO_D68) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D69) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D70) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A3) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_A8) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A4) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D62) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D61) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D63) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D8) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D7) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D4) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D2)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_ZIO_D68) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D69) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D70) | \ + PIN_ODR_HIGH(GPIOF_ARD_A3) | \ + PIN_ODR_HIGH(GPIOF_ZIO_A8) | \ + PIN_ODR_HIGH(GPIOF_ARD_A4) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D62) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D61) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D63) | \ + PIN_ODR_HIGH(GPIOF_ARD_A5) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_ARD_D8) | \ + PIN_ODR_HIGH(GPIOF_ARD_D7) | \ + PIN_ODR_HIGH(GPIOF_ARD_D4) | \ + PIN_ODR_HIGH(GPIOF_ARD_D2)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_ZIO_D68, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_D69, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_D70, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_A3, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_A8, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_A4, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_D62, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_ZIO_D61, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_D63, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_A5, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D8, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D7, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D4, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D2, 0U)) + +/* + * GPIOG setup: + * + * PG0 - ZIO_D65 (input pullup). + * PG1 - ZIO_D64 (input pullup). + * PG2 - ZIO_D49 (input pullup). + * PG3 - ZIO_D50 (input pullup). + * PG4 - PIN4 (input pullup). + * PG5 - PIN5 (input pullup). + * PG6 - USB_GPIO_OUT (input pullup). + * PG7 - USB_GPIO_IN (input pullup). + * PG8 - PIN8 (input pullup). + * PG9 - ARD_D0 USART6_RX (input pullup). + * PG10 - PIN10 (input pullup). + * PG11 - RMII_TX_EN (alternate 11). + * PG12 - PIN12 (input pullup). + * PG13 - RMII_TXD0 (alternate 11). + * PG14 - ARD_D1 USART6_TX (input pullup). + * PG15 - PIN15 (input pullup). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_ZIO_D65) | \ + PIN_MODE_INPUT(GPIOG_ZIO_D64) | \ + PIN_MODE_INPUT(GPIOG_ZIO_D49) | \ + PIN_MODE_INPUT(GPIOG_ZIO_D50) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_INPUT(GPIOG_USB_GPIO_OUT) | \ + PIN_MODE_INPUT(GPIOG_USB_GPIO_IN) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_INPUT(GPIOG_ARD_D0) | \ + PIN_MODE_INPUT(GPIOG_PIN10) | \ + PIN_MODE_ALTERNATE(GPIOG_RMII_TX_EN) | \ + PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOG_RMII_TXD0) | \ + PIN_MODE_INPUT(GPIOG_ARD_D1) | \ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D65) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D64) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D49) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D50) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_USB_GPIO_OUT) |\ + PIN_OTYPE_PUSHPULL(GPIOG_USB_GPIO_IN) |\ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ARD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RMII_TX_EN) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ARD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_ZIO_D65) | \ + PIN_OSPEED_VERYLOW(GPIOG_ZIO_D64) | \ + PIN_OSPEED_VERYLOW(GPIOG_ZIO_D49) | \ + PIN_OSPEED_VERYLOW(GPIOG_ZIO_D50) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \ + PIN_OSPEED_HIGH(GPIOG_USB_GPIO_OUT) | \ + PIN_OSPEED_HIGH(GPIOG_USB_GPIO_IN) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \ + PIN_OSPEED_HIGH(GPIOG_ARD_D0) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \ + PIN_OSPEED_HIGH(GPIOG_RMII_TX_EN) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \ + PIN_OSPEED_HIGH(GPIOG_RMII_TXD0) | \ + PIN_OSPEED_HIGH(GPIOG_ARD_D1) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_ZIO_D65) | \ + PIN_PUPDR_PULLUP(GPIOG_ZIO_D64) | \ + PIN_PUPDR_PULLUP(GPIOG_ZIO_D49) | \ + PIN_PUPDR_PULLUP(GPIOG_ZIO_D50) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOG_USB_GPIO_OUT) | \ + PIN_PUPDR_PULLUP(GPIOG_USB_GPIO_IN) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOG_ARD_D0) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOG_RMII_TX_EN) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOG_RMII_TXD0) | \ + PIN_PUPDR_PULLUP(GPIOG_ARD_D1) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_ZIO_D65) | \ + PIN_ODR_HIGH(GPIOG_ZIO_D64) | \ + PIN_ODR_HIGH(GPIOG_ZIO_D49) | \ + PIN_ODR_HIGH(GPIOG_ZIO_D50) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_USB_GPIO_OUT) | \ + PIN_ODR_HIGH(GPIOG_USB_GPIO_IN) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_ARD_D0) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_RMII_TX_EN) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_RMII_TXD0) | \ + PIN_ODR_HIGH(GPIOG_ARD_D1) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_ZIO_D65, 0U) | \ + PIN_AFIO_AF(GPIOG_ZIO_D64, 0U) | \ + PIN_AFIO_AF(GPIOG_ZIO_D49, 0U) | \ + PIN_AFIO_AF(GPIOG_ZIO_D50, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOG_USB_GPIO_OUT, 0U) | \ + PIN_AFIO_AF(GPIOG_USB_GPIO_IN, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOG_ARD_D0, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOG_RMII_TX_EN, 11U) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOG_RMII_TXD0, 11U) | \ + PIN_AFIO_AF(GPIOG_ARD_D1, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0U)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - PIN4 (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input pullup). + * PI1 - PIN1 (input pullup). + * PI2 - PIN2 (input pullup). + * PI3 - PIN3 (input pullup). + * PI4 - PIN4 (input pullup). + * PI5 - PIN5 (input pullup). + * PI6 - PIN6 (input pullup). + * PI7 - PIN7 (input pullup). + * PI8 - PIN8 (input pullup). + * PI9 - PIN9 (input pullup). + * PI10 - PIN10 (input pullup). + * PI11 - PIN11 (input pullup). + * PI12 - PIN12 (input pullup). + * PI13 - PIN13 (input pullup). + * PI14 - PIN14 (input pullup). + * PI15 - PIN15 (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0U)) + +/* + * GPIOJ setup: + * + * PJ0 - PIN0 (input pullup). + * PJ1 - PIN1 (input pullup). + * PJ2 - PIN2 (input pullup). + * PJ3 - PIN3 (input pullup). + * PJ4 - PIN4 (input pullup). + * PJ5 - PIN5 (input pullup). + * PJ6 - PIN6 (input pullup). + * PJ7 - PIN7 (input pullup). + * PJ8 - PIN8 (input pullup). + * PJ9 - PIN9 (input pullup). + * PJ10 - PIN10 (input pullup). + * PJ11 - PIN11 (input pullup). + * PJ12 - PIN12 (input pullup). + * PJ13 - PIN13 (input pullup). + * PJ14 - PIN14 (input pullup). + * PJ15 - PIN15 (input pullup). + */ +#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_PIN0) | \ + PIN_MODE_INPUT(GPIOJ_PIN1) | \ + PIN_MODE_INPUT(GPIOJ_PIN2) | \ + PIN_MODE_INPUT(GPIOJ_PIN3) | \ + PIN_MODE_INPUT(GPIOJ_PIN4) | \ + PIN_MODE_INPUT(GPIOJ_PIN5) | \ + PIN_MODE_INPUT(GPIOJ_PIN6) | \ + PIN_MODE_INPUT(GPIOJ_PIN7) | \ + PIN_MODE_INPUT(GPIOJ_PIN8) | \ + PIN_MODE_INPUT(GPIOJ_PIN9) | \ + PIN_MODE_INPUT(GPIOJ_PIN10) | \ + PIN_MODE_INPUT(GPIOJ_PIN11) | \ + PIN_MODE_INPUT(GPIOJ_PIN12) | \ + PIN_MODE_INPUT(GPIOJ_PIN13) | \ + PIN_MODE_INPUT(GPIOJ_PIN14) | \ + PIN_MODE_INPUT(GPIOJ_PIN15)) +#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN15)) +#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOJ_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN15)) +#define VAL_GPIOJ_PUPDR (PIN_PUPDR_PULLUP(GPIOJ_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN15)) +#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_PIN0) | \ + PIN_ODR_HIGH(GPIOJ_PIN1) | \ + PIN_ODR_HIGH(GPIOJ_PIN2) | \ + PIN_ODR_HIGH(GPIOJ_PIN3) | \ + PIN_ODR_HIGH(GPIOJ_PIN4) | \ + PIN_ODR_HIGH(GPIOJ_PIN5) | \ + PIN_ODR_HIGH(GPIOJ_PIN6) | \ + PIN_ODR_HIGH(GPIOJ_PIN7) | \ + PIN_ODR_HIGH(GPIOJ_PIN8) | \ + PIN_ODR_HIGH(GPIOJ_PIN9) | \ + PIN_ODR_HIGH(GPIOJ_PIN10) | \ + PIN_ODR_HIGH(GPIOJ_PIN11) | \ + PIN_ODR_HIGH(GPIOJ_PIN12) | \ + PIN_ODR_HIGH(GPIOJ_PIN13) | \ + PIN_ODR_HIGH(GPIOJ_PIN14) | \ + PIN_ODR_HIGH(GPIOJ_PIN15)) +#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN7, 0U)) +#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN15, 0U)) + +/* + * GPIOK setup: + * + * PK0 - PIN0 (input pullup). + * PK1 - PIN1 (input pullup). + * PK2 - PIN2 (input pullup). + * PK3 - PIN3 (input pullup). + * PK4 - PIN4 (input pullup). + * PK5 - PIN5 (input pullup). + * PK6 - PIN6 (input pullup). + * PK7 - PIN7 (input pullup). + * PK8 - PIN8 (input pullup). + * PK9 - PIN9 (input pullup). + * PK10 - PIN10 (input pullup). + * PK11 - PIN11 (input pullup). + * PK12 - PIN12 (input pullup). + * PK13 - PIN13 (input pullup). + * PK14 - PIN14 (input pullup). + * PK15 - PIN15 (input pullup). + */ +#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \ + PIN_MODE_INPUT(GPIOK_PIN1) | \ + PIN_MODE_INPUT(GPIOK_PIN2) | \ + PIN_MODE_INPUT(GPIOK_PIN3) | \ + PIN_MODE_INPUT(GPIOK_PIN4) | \ + PIN_MODE_INPUT(GPIOK_PIN5) | \ + PIN_MODE_INPUT(GPIOK_PIN6) | \ + PIN_MODE_INPUT(GPIOK_PIN7) | \ + PIN_MODE_INPUT(GPIOK_PIN8) | \ + PIN_MODE_INPUT(GPIOK_PIN9) | \ + PIN_MODE_INPUT(GPIOK_PIN10) | \ + PIN_MODE_INPUT(GPIOK_PIN11) | \ + PIN_MODE_INPUT(GPIOK_PIN12) | \ + PIN_MODE_INPUT(GPIOK_PIN13) | \ + PIN_MODE_INPUT(GPIOK_PIN14) | \ + PIN_MODE_INPUT(GPIOK_PIN15)) +#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN15)) +#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOK_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN15)) +#define VAL_GPIOK_PUPDR (PIN_PUPDR_PULLUP(GPIOK_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN15)) +#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \ + PIN_ODR_HIGH(GPIOK_PIN1) | \ + PIN_ODR_HIGH(GPIOK_PIN2) | \ + PIN_ODR_HIGH(GPIOK_PIN3) | \ + PIN_ODR_HIGH(GPIOK_PIN4) | \ + PIN_ODR_HIGH(GPIOK_PIN5) | \ + PIN_ODR_HIGH(GPIOK_PIN6) | \ + PIN_ODR_HIGH(GPIOK_PIN7) | \ + PIN_ODR_HIGH(GPIOK_PIN8) | \ + PIN_ODR_HIGH(GPIOK_PIN9) | \ + PIN_ODR_HIGH(GPIOK_PIN10) | \ + PIN_ODR_HIGH(GPIOK_PIN11) | \ + PIN_ODR_HIGH(GPIOK_PIN12) | \ + PIN_ODR_HIGH(GPIOK_PIN13) | \ + PIN_ODR_HIGH(GPIOK_PIN14) | \ + PIN_ODR_HIGH(GPIOK_PIN15)) +#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN7, 0U)) +#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN15, 0U)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ + +// clang-format on diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/common/CMakeLists.txt b/ChibiOS/ST_NUCLEO144_F767ZI/common/CMakeLists.txt new file mode 100644 index 00000000..190dc7f5 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/common/CMakeLists.txt @@ -0,0 +1,13 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_ConfigurationManager.cpp") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") + +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage-DEBUG.c b/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 00000000..9ff4bb4d --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,110 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// clang-format off + +#include +#include + +// 32kB blocks +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 08000000 nanoBooter + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + { BlockRange_BLOCKTYPE_CONFIG , 1, 1 }, // 08008000 configuration block + /////////////////////////////////////////////////////////////////////////////////////// + + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 08010000 nanoCLR +}; + +//128kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08020000 nanoCLR +}; + +// 256kB blocks +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 2 }, // 08040000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 3, 6 } // 08100000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x8000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 1, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08040000, // start address for block region + 7, // total number of blocks in this region + 0x40000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), // STM32 flash memory is XIP + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; + +// clang-format on diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage.c b/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage.c new file mode 100644 index 00000000..9ff4bb4d --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage.c @@ -0,0 +1,110 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// clang-format off + +#include +#include + +// 32kB blocks +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 08000000 nanoBooter + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + { BlockRange_BLOCKTYPE_CONFIG , 1, 1 }, // 08008000 configuration block + /////////////////////////////////////////////////////////////////////////////////////// + + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 08010000 nanoCLR +}; + +//128kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08020000 nanoCLR +}; + +// 256kB blocks +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 2 }, // 08040000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 3, 6 } // 08100000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x8000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 1, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08040000, // start address for block region + 7, // total number of blocks in this region + 0x40000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), // STM32 flash memory is XIP + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; + +// clang-format on diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/common/serialcfg.h b/ChibiOS/ST_NUCLEO144_F767ZI/common/serialcfg.h new file mode 100644 index 00000000..d862be85 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/common/serialcfg.h @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// clang-format off + +#ifndef SERIALCFG_H +#define SERIALCFG_H + +// define which serial driver the Wire Protocol will be using +#define SERIAL_DRIVER SD3 + +#endif /* SERIALCFG_H */ + +/** @} */ + +// clang-format on diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/common/targetHAL_ConfigurationManager.cpp b/ChibiOS/ST_NUCLEO144_F767ZI/common/targetHAL_ConfigurationManager.cpp new file mode 100644 index 00000000..06dc9238 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/common/targetHAL_ConfigurationManager.cpp @@ -0,0 +1,38 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +// Default initialisation for Network interface config blocks +// strong implementation replacing ChibiOS 'weak' one +bool InitialiseNetworkDefaultConfig(HAL_Configuration_NetworkInterface *pconfig, uint32_t configurationIndex) +{ + (void)configurationIndex; + + // zero memory + memset(pconfig, 0, sizeof(HAL_Configuration_NetworkInterface)); + + // make sure the config block marker is set + memcpy(pconfig->Marker, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); + + pconfig->InterfaceType = NetworkInterfaceType_Ethernet; + pconfig->StartupAddressMode = AddressMode_DHCP; + pconfig->AutomaticDNS = 1; + pconfig->SpecificConfigId = UINT32_MAX; + + // set MAC address with ST provided MAC for development boards + // 00:80:E1:01:35:D1 + pconfig->MacAddress[0] = 0x00; + pconfig->MacAddress[1] = 0x80; + pconfig->MacAddress[2] = 0xE1; + pconfig->MacAddress[3] = 0x01; + pconfig->MacAddress[4] = 0x35; + pconfig->MacAddress[5] = 0xD1; + + return true; +} diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/launch.json b/ChibiOS/ST_NUCLEO144_F767ZI/launch.json new file mode 100644 index 00000000..ef75fa3e --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/launch.json @@ -0,0 +1,107 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "ST_NUCLEO144_F767ZI nanoBooter", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "MIMode": "gdb", + "miDebuggerArgs": "", + "program": "${workspaceRoot}/build/nanoBooter.elf", + "setupCommands": [ + { + "text": "target extended-remote localhost:3333" + }, + { + "text": "monitor reset_config none separate" + }, + { + "text": "monitor reset halt" + }, + { + "text": "monitor flash write_image erase \"/build/nanoBooter.hex\" " + }, + { + "text": "file /build/nanoBooter.elf" + }, + { + "text": "set output-radix 16", + "description": "set the default numeric base to 16", + "ignoreFailures": true + } + ], + "logging": { + "moduleLoad": false, + "trace": false, + "engineLogging": false, + "programOutput": true, + "exceptions": true + }, + "launchCompleteCommand": "exec-continue", + "debugServerPath": "/bin/openocd.exe", + "debugServerArgs": "-s \"/scripts/\" -f board/stm32f769i-disco.cfg", + "serverStarted": "Listening on port .* for gdb connections", + "filterStderr": true, + "stopAtConnect": false, + "stopAtEntry": false, + "externalConsole": false, + "cwd": "${cwd}", + "hardwareBreakpoints": { + "require": true, + "limit": 6 + } + }, + { + "name": "ST_NUCLEO144_F767ZI nanoCLR", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "MIMode": "gdb", + "miDebuggerArgs": "", + "program": "${workspaceRoot}/build/nanoCLR.elf", + "setupCommands": [ + { + "text": "target extended-remote localhost:3333" + }, + { + "text": "monitor reset_config none separate" + }, + { + "text": "monitor reset halt" + }, + { + "text": "monitor flash write_image erase \"/build/nanoCLR.hex\" " + }, + { + "text": "file /build/nanoCLR.elf" + }, + { + "text": "set output-radix 16", + "description": "set the default numeric base to 16", + "ignoreFailures": true + } + ], + "logging": { + "moduleLoad": false, + "trace": false, + "engineLogging": false, + "programOutput": true, + "exceptions": true + }, + "launchCompleteCommand": "exec-continue", + "debugServerPath": "/bin/openocd.exe", + "debugServerArgs": "-s \"/scripts/\" -f board/stm32f769i-disco.cfg", + "serverStarted": "Listening on port .* for gdb connections", + "filterStderr": true, + "stopAtConnect": false, + "stopAtEntry": false, + "externalConsole": false, + "cwd": "${cwd}", + "hardwareBreakpoints": { + "require": true, + "limit": 6 + } + } + ] +} diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/README.md b/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/README.md new file mode 100644 index 00000000..77f99610 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/README.md @@ -0,0 +1,5 @@ +## Managed code helpers + +This folder contains helper classes to make developers life easier when coding for this target board. + +* [Adc](STM32F767ZI_NUCLEO.Adc.cs) diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/ST_NUCLEO144_F767ZI.Adc.cs b/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/ST_NUCLEO144_F767ZI.Adc.cs new file mode 100644 index 00000000..00e9efe5 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/ST_NUCLEO144_F767ZI.Adc.cs @@ -0,0 +1,53 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.ST_NUCLEO144_F767ZI +{ + /// + /// Enumeration of ADC channels available for ST_NUCLEO144_F767ZI + /// + public static class AdcChannels + { + // /// + // /// Channel 0, exposed on A0, connected to PA6 (ADC1 - IN6) + // /// + // public const int Channel_0 = 0; + + // /// + // /// Channel 1, exposed on A1, connected to PA4 (ADC1 - IN4) + // /// + // public const int Channel_1 = 1; + + // /// + // /// Channel 2, exposed on A2, connected to PC2 (ADC1 - IN12) + // /// + // public const int Channel_2 = 2; + + // /// + // /// Channel 3, exposed on A3, connected to PF10 (ADC3 - IN8) + // /// + // public const int Channel_3 = 3; + + // /// + // /// Channel 4, exposed on A4, connected to PF8 (ADC3 - IN6) + // /// + // public const int Channel_4 = 4; + + // /// + // /// Channel 5, internal temperature sensor, connected to ADC1 + // /// + // public const int Channel_TemperatureSensor = 5; + + // /// + // /// Channel 6, internal voltage reference, connected to ADC1 + // /// + // public const int Channel_VrefIn = 6; + + // /// + // /// Channel 7, connected to VBatt pin, ADC1 + // /// + // public const int Channel_Vbatt = 7; + } +} diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/package.nuspec b/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/package.nuspec new file mode 100644 index 00000000..81af53f3 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/package.nuspec @@ -0,0 +1,26 @@ + + + + nanoFramework.Targets.ST_NUCLEO144_F767ZI + nanoFramework.Targets.ST_NUCLEO144_F767ZI + 1.0.0 + nanoframework + false + + Helper classes to use ST_NUCLEO144_F767ZI target in C# applications. + + + + https://github.com/nanoframework + images\nf-logo.png + LICENSE.md + Copyright (c) .NET Foundation and Contributors + + nanoFramework, nano Framework, NETNF, NETMF, Micro Framework, STM32, .net, STM32F769I + + + + + + + diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/mbedtls_config.h b/ChibiOS/ST_NUCLEO144_F767ZI/mbedtls_config.h new file mode 100644 index 00000000..e2c2fff6 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/mbedtls_config.h @@ -0,0 +1,53 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006-2015, ARM Limited, All Rights Reserved +// See LICENSE file in the project root for full license information. +// + +#ifndef MBEDTLS_CONFIG_H +#define MBEDTLS_CONFIG_H + +/* For test certificates */ +// #define MBEDTLS_CERTS_C +// #define MBEDTLS_PEM_PARSE_C + +// #define SSL_DEBUG_BUF MBEDTLS_SSL_DEBUG_BUF +// #define SSL_DEBUG_CRT MBEDTLS_SSL_DEBUG_CRT +// #define SSL_DEBUG_ECP MBEDTLS_SSL_DEBUG_ECP +// #define SSL_DEBUG_MPI MBEDTLS_SSL_DEBUG_MPI +// #define SSL_DEBUG_MSG MBEDTLS_SSL_DEBUG_MSG +// #define SSL_DEBUG_RET MBEDTLS_SSL_DEBUG_RET + +// #define MBEDTLS_SSL_ALL_ALERT_MESSAGES +// #define MBEDTLS_VERSION_FEATURES +// #define MBEDTLS_CERTS_C +// #define MBEDTLS_ERROR_C +// #define MBEDTLS_VERSION_C + +// uncomment the defines below to enable static memory allocation feature +#if 0 +#define MBEDTLS_MEMORY_BUFFER_ALLOC_C +#define MBEDTLS_PLATFORM_MEMORY +#endif + +#ifdef USE_LCD +#include "lcd_log.h" +#define MBEDTLS_PLATFORM_PRINTF_MACRO LCD_UsrLog +#endif + +// uncomment the defines bellow to generate debug output +// set below the threshold level for debug messages +// check Mbed TLS mbedtls/debug.h header for details. +// Debug levels: +// 0 No debug +// 1 Error +// 2 State change +// 3 Informational +// 4 Verbose + +// #define MBEDTLS_DEBUG_C +// #define MBEDTLS_SSL_DEBUG_ALL +// #define MBEDTLS_SSL_ALL_ALERT_MESSAGES +// #define MBEDTLS_DEBUG_THRESHOLD 2 + +#endif // MBEDTLS_CONFIG_H diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/CMakeLists.txt b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/CMakeLists.txt new file mode 100644 index 00000000..73b5927c --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# # append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter-DEBUG.ld b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter-DEBUG.ld new file mode 100644 index 00000000..7ce269e0 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter-DEBUG.ld @@ -0,0 +1,145 @@ +/* +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F76xxI generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + /* for flash0 and flash1 regions + * they are the same flash but accessed through different addresses + * taking into account: + * only the booter region to use the first 32k + * the config region is already using 32k + * the application deployment region needs to use 1024k + */ + flash0 (rx) : org = 0x08000000, len = 32k /* Flash region as AXIM (writable) */ + flash1 (rx) : org = 0x00200000, len = 32k /* Flash region as ITCM */ + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ + ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */ + ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */ + ram3 (wx) : org = 0x20000030, len = 128k-48 /* DTCM-RAM */ + ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 + + config (rw) : org = 0x08008000, len = 32k /* address space reserved for configuration block */ + deployment (rx) : org = 0x08100000, len = 1024k /* address space reserved for application deployment */ + ramvt (wx) : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table (should use chibios) */ + bootclpbrd (wx) : org = 0x20000000, len = 48 /* boot clipboard area */ +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash1); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash1); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash1); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash1); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Stack rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* Memory rules inclusion.*/ +INCLUDE rules_memory.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter.ld b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter.ld new file mode 100644 index 00000000..415aee15 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter.ld @@ -0,0 +1,145 @@ +/* +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F76xxI generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + /* for flash0 and flash1 regions + * they are the same flash but accessed through different addresses + * taking into account: + * only the booter region to use the first 32k + * the config region is already using 32k + * the application deployment region needs to use 1024k + */ + flash0 (rx) : org = 0x08000000, len = 32k /* Flash region as AXIM (writable) */ + flash1 (rx) : org = 0x00200000, len = 32k /* Flash region as ITCM */ + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ + ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */ + ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */ + ram3 (wx) : org = 0x20000030, len = 128k-48 /* DTCM-RAM */ + ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 + + config (rw) : org = 0x08008000, len = 32k /* address space reserved for configuration block */ + deployment (rx) : org = 0x08100000, len = 1024k /* address space reserved for application deployment */ + ramvt (wx) : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table (should use chibios) */ + bootclpbrd (wx) : org = 0x20000000, len = 48 /* boot clipboard area */ +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash1); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash1); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash1); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash1); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Stack rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* Memory rules inclusion.*/ +INCLUDE rules_memory.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/chconf.h b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/chconf.h new file mode 100644 index 00000000..1902e347 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/chconf.h @@ -0,0 +1,834 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// clang-format off + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ + +// clang-format on diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/halconf.h b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/halconf.h new file mode 100644 index 00000000..410839a6 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/halconf.h @@ -0,0 +1,550 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// clang-format off + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 64 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_NONE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" +#endif /* HALCONF_H */ + +/** @} */ + +// clang-format on diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/halconf_nf.h b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/halconf_nf.h new file mode 100644 index 00000000..b71505cc --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/halconf_nf.h @@ -0,0 +1,17 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef HALCONF_NF_H +#define HALCONF_NF_H + +// enables STM32 Flash driver +#if !defined(HAL_NF_USE_STM32_FLASH) +#define HAL_NF_USE_STM32_FLASH TRUE +#endif + +// enable USB MSD (from ChibiOS Contrib) +#define HAL_USBH_USE_MSD FALSE + +#endif // HALCONF_NF_H diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/main.c b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/main.c new file mode 100644 index 00000000..71171354 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/main.c @@ -0,0 +1,103 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); + +// Application entry point. +int main(void) +{ + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init boot clipboard + InitBootClipboard(); + +// init SWO as soon as possible to make it available to output ASAP +#if (SWO_OUTPUT == TRUE) + SwoInit(); +#endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + osDelay(20); // Let init stabilize + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // check if there is a request to remain on nanoBooter + if (!IsToRemainInBooter()) + { + // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter + // the user button in this board has a pull-up resistor so the check has to be inverted + if (!palReadLine(LINE_BUTTON)) + { + // check for valid CLR image + // we are checking for a valid image right after the configuration block + if (CheckValidCLRImage((uint32_t)&__nanoConfig_end__)) + { + // there seems to be a valid CLR image + // launch nanoCLR + LaunchCLR((uint32_t)&__nanoConfig_end__); + } + } + } + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + +#if (HAL_NF_USE_STM32_CRC == TRUE) + // startup crc + crcStart(NULL); +#endif + + // starts the serial driver + sdStart(&SERIAL_DRIVER, NULL); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + ConfigurationManager_Initialize(); + + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); + + // Normal main() thread + while (true) + { + palSetLine(LINE_LED1); + osDelay(500); + palClearLine(LINE_LED1); + osDelay(500); + } +} diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/mcuconf.h b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/mcuconf.h new file mode 100644 index 00000000..d1ece457 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/mcuconf.h @@ -0,0 +1,437 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +// clang-format off + +/* + * STM32F7xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F7xx_MCUCONF +#define STM32F767_MCUCONF + +/* + * General settings. + */ +#define STM32_NO_INIT FALSE + +/* + * Memory attributes settings. + */ +#define STM32_NOCACHE_ENABLE TRUE +#define STM32_NOCACHE_MPU_REGION MPU_REGION_6 +#define STM32_NOCACHE_RBAR 0x2004C000U +#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K + +/* + * HAL driver system settings. + */ +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 432 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 25 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE +#define STM32_I2SSRC STM32_I2SSRC_OFF +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SP_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLI2SDIVQ_VALUE 2 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 4 +#define STM32_PLLSAIQ_VALUE 4 +#define STM32_PLLSAIR_VALUE 4 +#define STM32_PLLSAIDIVQ_VALUE 2 +#define STM32_PLLSAIDIVR_VALUE 2 +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_LCDTFT_REQUIRED FALSE +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK +#define STM32_SDMMC2SEL STM32_SDMMC2SEL_PLL48CLK + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 6 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 6 +#define STM32_IRQ_EXTI22_PRIORITY 6 +#define STM32_IRQ_EXTI23_PRIORITY 6 + +#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7 +#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7 +#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 +#define STM32_IRQ_TIM7_PRIORITY 7 +#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7 +#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7 +#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7 +#define STM32_IRQ_TIM8_CC_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART3_PRIORITY 12 +#define STM32_IRQ_UART4_PRIORITY 12 +#define STM32_IRQ_UART5_PRIORITY 12 +#define STM32_IRQ_USART6_PRIORITY 12 +#define STM32_IRQ_UART7_PRIORITY 12 +#define STM32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_USE_CAN3 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 +#define STM32_CAN_CAN3_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM10 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM13 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_USE_TIM15 FALSE +#define STM32_GPT_USE_TIM16 FALSE +#define STM32_GPT_USE_TIM17 FALSE + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_USE_TIM10 FALSE +#define STM32_ICU_USE_TIM11 FALSE +#define STM32_ICU_USE_TIM12 FALSE +#define STM32_ICU_USE_TIM13 FALSE +#define STM32_ICU_USE_TIM14 FALSE +#define STM32_ICU_USE_TIM15 FALSE +#define STM32_ICU_USE_TIM16 FALSE +#define STM32_ICU_USE_TIM17 FALSE + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_USE_TIM10 FALSE +#define STM32_PWM_USE_TIM11 FALSE +#define STM32_PWM_USE_TIM12 FALSE +#define STM32_PWM_USE_TIM13 FALSE +#define STM32_PWM_USE_TIM14 FALSE +#define STM32_PWM_USE_TIM15 FALSE +#define STM32_PWM_USE_TIM16 FALSE +#define STM32_PWM_USE_TIM17 FALSE + +/* + * RTC driver system settings. + */ +#define STM32_RTC_PRESA_VALUE 32 +#define STM32_RTC_PRESS_VALUE 1024 +#define STM32_RTC_CR_INIT 0 +#define STM32_RTC_TAMPCR_INIT 0 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_USE_SDMMC2 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 10000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 10000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDMMC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC2_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 +#define STM32_SDC_SDMMC2_IRQ_PRIORITY 9 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_USART2 FALSE +#define STM32_SIO_USE_USART3 FALSE +#define STM32_SIO_USE_UART4 FALSE +#define STM32_SIO_USE_UART5 FALSE +#define STM32_SIO_USE_USART6 FALSE +#define STM32_SIO_USE_UART7 FALSE +#define STM32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * TRNG driver system settings. + */ +#define STM32_TRNG_USE_RNG1 FALSE + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +/* + * WSPI driver system settings. + */ +#define STM32_WSPI_USE_QUADSPI1 FALSE +#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1 + +// clang-format on + +#endif /* MCUCONF_H */ diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/mcuconf_nf.h b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/mcuconf_nf.h new file mode 100644 index 00000000..35e74e10 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/mcuconf_nf.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_NF_H +#define MCUCONF_NF_H + +#endif // MCUCONF_NF_H diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/target_board.h.in b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/target_board.h.in new file mode 100644 index 00000000..ac85c850 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef TARGET_BOARD_NANOBOOTER_H +#define TARGET_BOARD_NANOBOOTER_H + +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_NAME@" + +#endif // TARGET_BOARD_NANOBOOTER_H diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/CMakeLists.txt b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..f5fab759 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld new file mode 100644 index 00000000..27afcecc --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld @@ -0,0 +1,144 @@ +/* +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F76xxI generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + /* for flash0 and flash1 regions + * they are the same flash but accessed through different addresses + * taking into account: + * the booter region is already using the first 32k + * the config region is already using 32k + * the application deployment region needs to use 1024k + */ + flash0 (rx) : org = 0x08010000, len = 2M - 32k - 32k - 1024k /* Flash region as AXIM (writable) */ + flash1 (rx) : org = 0x00210000, len = 2M - 32k - 32k - 1024k /* Flash region as ITCM */ + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ + ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */ + ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */ + ram3 (wx) : org = 0x20000030, len = 128k-48 /* DTCM-RAM */ + ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 + + config (rw) : org = 0x08008000, len = 32k /* address space reserved for configuration block */ + deployment (rx) : org = 0x08100000, len = 1024k /* address space reserved for application deployment */ + ramvt (wx) : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table (should use chibios) */ +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash1); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash1); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash1); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash1); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +/* Stack rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* Memory rules inclusion.*/ +INCLUDE rules_memory.ld + +/* nanoCLR rules inclusion.*/ +INCLUDE rules_clr.ld diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld new file mode 100644 index 00000000..27afcecc --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld @@ -0,0 +1,144 @@ +/* +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F76xxI generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + /* for flash0 and flash1 regions + * they are the same flash but accessed through different addresses + * taking into account: + * the booter region is already using the first 32k + * the config region is already using 32k + * the application deployment region needs to use 1024k + */ + flash0 (rx) : org = 0x08010000, len = 2M - 32k - 32k - 1024k /* Flash region as AXIM (writable) */ + flash1 (rx) : org = 0x00210000, len = 2M - 32k - 32k - 1024k /* Flash region as ITCM */ + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ + ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */ + ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */ + ram3 (wx) : org = 0x20000030, len = 128k-48 /* DTCM-RAM */ + ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 + + config (rw) : org = 0x08008000, len = 32k /* address space reserved for configuration block */ + deployment (rx) : org = 0x08100000, len = 1024k /* address space reserved for application deployment */ + ramvt (wx) : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table (should use chibios) */ +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash1); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash1); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash1); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash1); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +/* Stack rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* Memory rules inclusion.*/ +INCLUDE rules_memory.ld + +/* nanoCLR rules inclusion.*/ +INCLUDE rules_clr.ld diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/chconf.h b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/chconf.h new file mode 100644 index 00000000..1902e347 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/chconf.h @@ -0,0 +1,834 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// clang-format off + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ + +// clang-format on diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/halconf.h b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/halconf.h new file mode 100644 index 00000000..a129779b --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/halconf.h @@ -0,0 +1,564 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// clang-format off + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +// #define HAL_USE_ADC FALSE +// #endif + +/** + * @brief Enables the CAN subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +// #define HAL_USE_DAC FALSE +// #endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ + // this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +// #define HAL_USE_I2C FALSE +// #endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +// #define HAL_USE_MAC FALSE +// #endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +// #define HAL_USE_PWM FALSE +// #endif + +/** + * @brief Enables the RTC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +// #define HAL_USE_RTC FALSE +// #endif + +/** + * @brief Enables the SDC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +// #define HAL_USE_SDC FALSE +// #endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +// #define HAL_USE_SPI FALSE +// #endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +// #define HAL_USE_UART FALSE +// #endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +// #define HAL_USE_WDG FALSE +// #endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 64 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_NONE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + + +#endif /* HALCONF_H */ + +/** @} */ + +// clang-format on diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/halconf_nf.h b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/halconf_nf.h new file mode 100644 index 00000000..a5696a1b --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/halconf_nf.h @@ -0,0 +1,35 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef HALCONF_NF_H +#define HALCONF_NF_H + +// enables STM32 Flash driver +#if !defined(HAL_NF_USE_STM32_FLASH) +#define HAL_NF_USE_STM32_FLASH TRUE +#endif + +// Enables the FSMC subsystem. +#if !defined(HAL_NF_USE_FSMC) +#define HAL_NF_USE_FSMC TRUE +#endif + +// enables STM32 QSPI driver +#if !defined(HAL_NF_USE_STM32_QSPI) +#define HAL_NF_USE_STM32_QSPI FALSE +#endif + +// // enable STM32 graphics +// #if !defined(HAL_DSI_MODULE_ENABLED) +// #define HAL_DSI_MODULE_ENABLED TRUE +// #endif + +#if !defined(HAL_LTDC_MODULE_ENABLED) +#define HAL_LTDC_MODULE_ENABLED TRUE +#endif + + + +#endif // HALCONF_NF_H diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/main.c b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/main.c new file mode 100644 index 00000000..8451ba48 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/main.c @@ -0,0 +1,82 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); +// declare CLRStartup thread here +osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread"); + +// Application entry point. +int main(void) +{ + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init boot clipboard + InitBootClipboard(); + +// init SWO as soon as possible to make it available to output ASAP +#if (SWO_OUTPUT == TRUE) + SwoInit(); +#endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // start watchdog + Watchdog_Init(); + +#if (HAL_NF_USE_STM32_CRC == TRUE) + // startup crc + crcStart(NULL); +#endif + + // config and init external memory + // this has to be called after osKernelInitialize, otherwise an hard fault will occur + Target_ExternalMemoryInit(); + + // starts the serial driver + sdStart(&SERIAL_DRIVER, NULL); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // create the CLR Startup thread + osThreadCreate(osThread(CLRStartupThread), &clrSettings); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + while (true) + { + osDelay(100); + } +} diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h new file mode 100644 index 00000000..61de24ec --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h @@ -0,0 +1,440 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +// clang-format off + +/* + * STM32F7xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F7xx_MCUCONF +#define STM32F767_MCUCONF + +/* + * General settings. + */ +#define STM32_NO_INIT FALSE + +/* + * Memory attributes settings. + */ +#define STM32_NOCACHE_ENABLE TRUE +#define STM32_NOCACHE_MPU_REGION MPU_REGION_6 +#define STM32_NOCACHE_RBAR 0x2004C000U +#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K + +/* + * HAL driver system settings. + */ +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 432 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 25 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE +#define STM32_I2SSRC STM32_I2SSRC_OFF +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SP_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLI2SDIVQ_VALUE 2 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 4 +#define STM32_PLLSAIQ_VALUE 4 +#define STM32_PLLSAIR_VALUE 4 +#define STM32_PLLSAIDIVQ_VALUE 2 +#define STM32_PLLSAIDIVR_VALUE 2 +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_LCDTFT_REQUIRED FALSE +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK +#define STM32_SDMMC2SEL STM32_SDMMC2SEL_PLL48CLK + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 6 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 6 +#define STM32_IRQ_EXTI22_PRIORITY 6 +#define STM32_IRQ_EXTI23_PRIORITY 6 + +#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7 +#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7 +#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 +#define STM32_IRQ_TIM7_PRIORITY 7 +#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7 +#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7 +#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7 +#define STM32_IRQ_TIM8_CC_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART3_PRIORITY 12 +#define STM32_IRQ_UART4_PRIORITY 12 +#define STM32_IRQ_UART5_PRIORITY 12 +#define STM32_IRQ_USART6_PRIORITY 12 +#define STM32_IRQ_UART7_PRIORITY 12 +#define STM32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_USE_CAN3 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 +#define STM32_CAN_CAN3_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM10 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM13 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_USE_TIM15 FALSE +#define STM32_GPT_USE_TIM16 FALSE +#define STM32_GPT_USE_TIM17 FALSE + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 TRUE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_USE_TIM10 FALSE +#define STM32_ICU_USE_TIM11 FALSE +#define STM32_ICU_USE_TIM12 FALSE +#define STM32_ICU_USE_TIM13 FALSE +#define STM32_ICU_USE_TIM14 FALSE +#define STM32_ICU_USE_TIM15 FALSE +#define STM32_ICU_USE_TIM16 FALSE +#define STM32_ICU_USE_TIM17 FALSE + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_USE_TIM10 FALSE +#define STM32_PWM_USE_TIM11 FALSE +#define STM32_PWM_USE_TIM12 FALSE +#define STM32_PWM_USE_TIM13 FALSE +#define STM32_PWM_USE_TIM14 TRUE +#define STM32_PWM_USE_TIM15 FALSE +#define STM32_PWM_USE_TIM16 FALSE +#define STM32_PWM_USE_TIM17 FALSE + +/* + * RTC driver system settings. + */ +#define STM32_RTC_PRESA_VALUE 32 +#define STM32_RTC_PRESS_VALUE 1024 +#define STM32_RTC_CR_INIT 0 +#define STM32_RTC_TAMPCR_INIT 0 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_USE_SDMMC2 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 10000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 10000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDMMC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC2_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 +#define STM32_SDC_SDMMC2_IRQ_PRIORITY 9 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_USART2 FALSE +#define STM32_SIO_USE_USART3 FALSE +#define STM32_SIO_USE_UART4 FALSE +#define STM32_SIO_USE_UART5 FALSE +#define STM32_SIO_USE_USART6 FALSE +#define STM32_SIO_USE_UART7 FALSE +#define STM32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * TRNG driver system settings. + */ +#define STM32_TRNG_USE_RNG1 FALSE + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 TRUE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG TRUE + +/* + * WSPI driver system settings. + */ +#define STM32_WSPI_USE_QUADSPI1 FALSE +#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1 + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ + +// clang-format on diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf_nf.h b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf_nf.h new file mode 100644 index 00000000..f3e7d185 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf_nf.h @@ -0,0 +1,28 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_NF_H +#define MCUCONF_NF_H +/* + * FSMC driver system settings. + */ +#define STM32_FSMC_USE_FSMC1 TRUE +#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 +#define STM32_FSMC_DMA_CHN 0x03010201 + +/* + * FSMC SDRAM driver system settings. + */ +#define STM32_USE_FSMC_SDRAM TRUE +#define STM32_SDRAM_USE_FSMC_SDRAM1 TRUE +#define STM32_SDRAM_USE_FSMC_SDRAM2 FALSE + +/* + * PWM driver system settings. + */ + #define STM32_PWM_USE_ADVANCED TRUE + + +#endif // MCUCONF_NF_H diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/nanoHAL.cpp b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/nanoHAL.cpp new file mode 100644 index 00000000..e754dd5f --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/nanoHAL.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/target_board.h.in b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/target_board.h.in new file mode 100644 index 00000000..53a87fce --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef TARGET_BOARD_NANOCLR_H +#define TARGET_BOARD_NANOCLR_H + +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_NAME@" + +#endif // TARGET_BOARD_NANOCLR_H diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/stm32f7xx_hal_conf.h b/ChibiOS/ST_NUCLEO144_F767ZI/stm32f7xx_hal_conf.h new file mode 100644 index 00000000..997ab810 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/stm32f7xx_hal_conf.h @@ -0,0 +1,56 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2016 STMicroelectronics. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef STM32F7xx_HAL_CONF_H +#define STM32F7xx_HAL_CONF_H + +#define STM32F767xx + +#ifdef __cplusplus + extern "C" { +#endif + +#define HAL_DMA_MODULE_ENABLED +#define HAL_QSPI_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED + +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + + +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) + void assert_failed(uint8_t *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + + +#ifdef __cplusplus +} +#endif + +#endif // __STM32F7xx_HAL_CONF_H diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_BlockStorage.c b/ChibiOS/ST_NUCLEO144_F767ZI/target_BlockStorage.c new file mode 100644 index 00000000..db45d1a4 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &STM32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_BlockStorage.h b/ChibiOS/ST_NUCLEO144_F767ZI/target_BlockStorage.h new file mode 100644 index 00000000..eac9e104 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef TARGETPAL_BLOCKSTORAGE_H +#define TARGETPAL_BLOCKSTORAGE_H + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //TARGETPAL_BLOCKSTORAGE_H diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_common.c b/ChibiOS/ST_NUCLEO144_F767ZI/target_common.c new file mode 100644 index 00000000..413b264b --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_common.c @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = { + {true}, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, // ConvertCOM_DebugHandle(1), + 0, // ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + {RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size}, + {FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target can use JTAG for updates +inline GET_TARGET_CAPABILITIES(TargetCapabilities_JtagUpdate); +inline TARGET_HAS_PROPRIETARY_BOOTER(false); diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_common.h.in b/ChibiOS/ST_NUCLEO144_F767ZI/target_common.h.in new file mode 100644 index 00000000..dd32c876 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_common.h.in @@ -0,0 +1,47 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef TARGET_COMMON_H +#define TARGET_COMMON_H + +// #include +#include +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0xC0000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x01000000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00200000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@TARGET_NAME@" +#define PLATFORMNAMESTRING "STM32F7" +////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT palToggleLine(LINE_LED2) +///////////////////////////////////// + +#endif // TARGET_COMMON_H diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_external_memory.c b/ChibiOS/ST_NUCLEO144_F767ZI/target_external_memory.c new file mode 100644 index 00000000..ac5a917b --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_external_memory.c @@ -0,0 +1,111 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "hal.h" +#include "fsmc_sdram_lld.h" + + +// SDRAM Mode definition register defines +#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001) +#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002) +#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004) +#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020) +#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030) +#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +// FMC_ReadPipe_Delay +#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) +#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) +#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) +#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000) + +// FMC_Read_Burst +#define FMC_Read_Burst_Disable ((uint32_t)0x00000000) +#define FMC_Read_Burst_Enable ((uint32_t)0x00001000) +#define FMC_Read_Burst_Mask ((uint32_t)0x00001000) + +// FMC_SDClock_Period +#define FMC_SDClock_Disable ((uint32_t)0x00000000) +#define FMC_SDClock_Period_2 ((uint32_t)0x00000800) +#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) +#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00) + +// FMC_ColumnBits_Number +#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) +#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) +#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) +#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003) + +// FMC_RowBits_Number +#define FMC_RowBits_Number_11b ((uint32_t)0x00000000) +#define FMC_RowBits_Number_12b ((uint32_t)0x00000004) +#define FMC_RowBits_Number_13b ((uint32_t)0x00000008) + +// FMC_SDMemory_Data_Width +#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) +#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) +#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) + +// FMC_InternalBank_Number +#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) +#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) + +// FMC_CAS_Latency +#define FMC_CAS_Latency_1 ((uint32_t)0x00000080) +#define FMC_CAS_Latency_2 ((uint32_t)0x00000100) +#define FMC_CAS_Latency_3 ((uint32_t)0x00000180) + +// FMC_Write_Protection +#define FMC_Write_Protection_Disable ((uint32_t)0x00000000) +#define FMC_Write_Protection_Enable ((uint32_t)0x00000200) + +#define SDRAM_SIZE (16 * 1024 * 1024) +#define SDRAM_START ((void *)FSMC_Bank5_MAP_BASE) + + +// SDRAM driver configuration structure. +static const SDRAMConfig sdram_cfg = { + .sdcr = (uint32_t) FMC_ColumnBits_Number_8b | + FMC_RowBits_Number_12b | + FMC_SDMemory_Width_32b | + FMC_InternalBank_Number_4 | + FMC_CAS_Latency_3 | + FMC_Write_Protection_Disable | + FMC_SDClock_Period_2 | + FMC_Read_Burst_Enable | + FMC_ReadPipe_Delay_0, + .sdtr = (uint32_t) (2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles) + (7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns)) + (4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns)) + (7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns)) + (3 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns)) + (2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns) + (2 << 24), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns) + // NRFS = 4-1 + .sdcmr = (3 << 5) | (FMC_SDCMR_MRD_BURST_LENGTH_2 | + FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL | + FMC_SDCMR_MRD_CAS_LATENCY_3 | + FMC_SDCMR_MRD_OPERATING_MODE_STANDARD | + FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9, + + .sdrtr = (uint32_t)(683 << 1), +}; + +void Target_ExternalMemoryInit() +{ + fsmcSdramInit(); + + // FIXME + // this swaps SDRAM address to 0x60000000 and makes it L1 cacheable + //SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0; + + fsmcSdramStart(&SDRAMD, &sdram_cfg); +} diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_lwip_sntp_opts.h b/ChibiOS/ST_NUCLEO144_F767ZI/target_lwip_sntp_opts.h new file mode 100644 index 00000000..c4d09f1f --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_lwip_sntp_opts.h @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T OVERRIDE ANY lwIP SNTP OPTIONS // +////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_lwipopts.h b/ChibiOS/ST_NUCLEO144_F767ZI/target_lwipopts.h new file mode 100644 index 00000000..ca1a0b44 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_lwipopts.h @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +///////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T OVERRIDE ANY lwIP OPTIONS // +///////////////////////////////////////////////////////////////////////////////////////// diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_dev_onewire_config.cpp b/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_dev_onewire_config.cpp new file mode 100644 index 00000000..af91e060 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_dev_onewire_config.cpp @@ -0,0 +1,29 @@ +// // +// // Copyright (c) .NET Foundation and Contributors +// // See LICENSE file in the project root for full license information. +// // + +// #include "target_nf_dev_onewire_config.h" +// #include + +// /////////// +// // UART4 // +// /////////// + +// // pin configuration for UART4 +// // port for TX pin is: GPIOC +// // TX pin: is GPIOC_10 +// // GPIO alternate pin function is 8 +// UART_CONFIG_PINS(4, GPIOC, 10, 8) + +// // buffers +// // buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// // because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +// #if defined(__GNUC__) +// __attribute__((aligned(32))) +// #endif +// uint8_t Uart4_TxBuffer[UART4_TX_SIZE]; +// #if defined(__GNUC__) +// __attribute__((aligned(32))) +// #endif +// uint8_t Uart4_RxBuffer[UART4_RX_SIZE]; diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_dev_onewire_config.h b/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_dev_onewire_config.h new file mode 100644 index 00000000..e75c4211 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_dev_onewire_config.h @@ -0,0 +1,17 @@ +// // +// // Copyright (c) .NET Foundation and Contributors +// // See LICENSE file in the project root for full license information. +// // + +// /////////// +// // UART4 // +// /////////// + +// // enable USART4 +// #define NF_ONEWIRE_STM32_UART_USE_USART4 TRUE + +// // buffers size +// // tx buffer size: 32 bytes +// #define UART4_TX_SIZE 32 +// // rx buffer size: 32 bytes +// #define UART4_RX_SIZE 32 \ No newline at end of file diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_device_can_config.cpp b/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_device_can_config.cpp new file mode 100644 index 00000000..32280e6d --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_device_can_config.cpp @@ -0,0 +1,32 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_nf_device_can_config.h" +#include + +/////////// +// CAN1 // +/////////// + +// pin configuration for CAN1 +// port for TX pin is: GPIOD +// TX pin: is GPIOD_01 +// port for RX pin is: GPIOD +// RX pin: is GPIOD_00 +// GPIO alternate pin function is 9 (see alternate function mapping table in device datasheet) +CAN_CONFIG_PINS(1, GPIOD, GPIOD, 1, 0, 9) + +// buffer +CANRxFrame Can1_MsgBuffer[CAN1_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(1, CAN1_RX_BUFFER_SIZE) + +/////////// +// CAN2 // +/////////// + +// NOT AVAILABLE diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_device_can_config.h b/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_device_can_config.h new file mode 100644 index 00000000..88af94ef --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_device_can_config.h @@ -0,0 +1,24 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////// +// CAN1 // +////////// + +// enable CAN1 +#define NF_CAN_STM32_CAN_USE_CAN1 TRUE + +// buffers size +#define CAN1_RX_BUFFER_SIZE 16 + +////////// +// CAN2 // +////////// + +// // enable CAN2 +// #define NF_CAN_STM32_CAN_USE_CAN2 TRUE + +// // buffers size +// #define CAN2_RX_BUFFER_SIZE 16 diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_adc_config.cpp b/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_adc_config.cpp new file mode 100644 index 00000000..7291c3e0 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_adc_config.cpp @@ -0,0 +1,40 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC1 + {1, GPIOA, 3, ADC_CHANNEL_IN3}, + {1, GPIOB, 1, ADC_CHANNEL_IN9}, + {1, GPIOC, 0, ADC_CHANNEL_IN10}, + {1, GPIOC, 2, ADC_CHANNEL_IN12}, + {1, GPIOC, 3, ADC_CHANNEL_IN13}, + + // ADC 2 + {2, GPIOA, 3, ADC_CHANNEL_IN3}, + {2, GPIOB, 1, ADC_CHANNEL_IN9}, + {2, GPIOC, 0, ADC_CHANNEL_IN10}, + {2, GPIOC, 2, ADC_CHANNEL_IN12}, + {2, GPIOC, 3, ADC_CHANNEL_IN13}, + + // ADC3 + {3, GPIOA, 3, ADC_CHANNEL_IN3}, + {3, GPIOF, 10, ADC_CHANNEL_IN8}, + {3, GPIOF, 3, ADC_CHANNEL_IN9}, + {3, GPIOC, 0, ADC_CHANNEL_IN10}, + {3, GPIOC, 2, ADC_CHANNEL_IN12}, + {3, GPIOC, 3, ADC_CHANNEL_IN13}, + {3, GPIOF, 4, ADC_CHANNEL_IN14}, + {3, GPIOF, 5, ADC_CHANNEL_IN15}, + + // these are the internal sources, available only at ADC1 + {1, NULL, 0, ADC_CHANNEL_SENSOR}, + {1, NULL, 0, ADC_CHANNEL_VREFINT}, + {1, NULL, 0, ADC_CHANNEL_VBAT}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_dac_config.cpp b/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_dac_config.cpp new file mode 100644 index 00000000..c85ba3f3 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_dac_config.cpp @@ -0,0 +1,14 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[] = { + +// // DAC1, channel 1, GPIO port A, pin 4 +// {1, 1, GPIOA, 4}, +// }; + +// const int DacChannelCount = ARRAYSIZE(DacPortPinConfig); diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_i2c_config.cpp b/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_i2c_config.cpp new file mode 100644 index 00000000..1e6b2594 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_i2c_config.cpp @@ -0,0 +1,44 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_8 +// SDA pin: is GPIOB_9 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) + + +////////// +// I2C2 // +////////// + +// pin configuration for I2C2 +// port for SCL pin is: GPIOF +// port for SDA pin is: GPIOF +// SCL pin: is GPIOF_1 +// SDA pin: is GPIOB_0 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(2, GPIOB, GPIOB, 1, 0, 4) + + +////////// +// I2C3 // +////////// + +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_8 +// SDA pin: is GPIOB_9 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +// I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_pwm_config.cpp b/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_pwm_config.cpp new file mode 100644 index 00000000..73cc6666 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_pwm_config.cpp @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_spi_config.cpp b/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_spi_config.cpp new file mode 100644 index 00000000..7a61d4fb --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_spi_config.cpp @@ -0,0 +1,32 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// SPI1 // +////////// + +// pin configuration for SPI1 +// port for SCK pin is: PA5 (D13) +// port for MISO pin is: PA6 (D12) +// port for MOSI pin is: PA7 (D11) +// AF 5 + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(1, GPIOA, 5, GPIOA, 6, GPIOA, 7, 5) + +////////// +// SPI3 // +////////// + +// pin configuration for SPI3 +// port for SCK pin is: PB3 (D23) +// port for MISO pin is: PB4 (D25) +// port for MOSI pin is: PB5 (D22) +// AF 6 + +// GPIO alternate pin function is 6 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(3, GPIOB, 3, GPIOB, 4, GPIOB, 5, 6) diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.cpp b/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.cpp new file mode 100644 index 00000000..49a10c74 --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.cpp @@ -0,0 +1,79 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_system_io_ports_config.h" +#include + +/////////// +// UART1 // +/////////// + +// NOT AVAILABLE + +/////////// +// UART2 // +/////////// + +// pin configuration for UART2 +// port for TX pin is: GPIOD +// port for RX pin is: GPIOD +// TX pin: is GPIOD_5 +// RX pin: is GPIOC_6 +// GPIO alternate pin function is 7 (see alternate function mapping table in device datasheet) +UART_CONFIG_PINS(2, GPIOD, GPIOD, 5, 6, 7) + +// initialization for UART2 +UART_INIT(2) + +// un-initialization for UART2 +UART_UNINIT(2) + +/////////// +// UART3 // +/////////// + +// Used for STLINK. + +// /////////// +// // UART4 // +// /////////// + +// NOT AVAILABLE + +/////////// +// UART5 // +/////////// + +// NOT AVAILABLE + +/////////// +// UART6 // +/////////// + +// pin configuration for UART6 +// port for TX pin is: GPIOG +// port for RX pin is: GPIOG +// TX pin: is GPIOC_14 +// RX pin: is GPIOC_9 +// GPIO alternate pin function is 8 (see alternate function mapping table in device datasheet) +UART_CONFIG_PINS(6, GPIOG, GPIOG, 14, 9, 8) + +// initialization for UART6 +UART_INIT(6) + +// un-initialization for UART6 +UART_UNINIT(6) + +/////////// +// UART7 // +/////////// + +// NOT AVAILABLE + +/////////// +// UART8 // +/////////// + +// NOT AVAILABLE diff --git a/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.h b/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.h new file mode 100644 index 00000000..bf538a8c --- /dev/null +++ b/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.h @@ -0,0 +1,60 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// /////////// +// // UART1 // +// /////////// + +// enable UART1 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART1 TRUE + +/////////// +// UART2 // +/////////// + +// enable UART2 +#define NF_SERIAL_COMM_STM32_UART_USE_USART2 TRUE + +// /////////// +// // UART3 // +// /////////// + +// // enable UART3 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART3 TRUE + +// /////////// +// // UART4 // +// /////////// + +// // enable UART4 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART4 TRUE + +/////////// +// UART5 // +/////////// + +// enable UART5 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART5 TRUE + +/////////// +// UART6 // +/////////// + +// enable USART6 +#define NF_SERIAL_COMM_STM32_UART_USE_USART6 TRUE + +// /////////// +// // UART7 // +// /////////// + +// // enable UART7 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART7 TRUE + +// /////////// +// // UART8 // +// /////////// + +// // enable UART8 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART8 TRUE diff --git a/README.md b/README.md index 4af44eff..314a9f19 100644 --- a/README.md +++ b/README.md @@ -26,6 +26,7 @@ The provided boards are **NOT** supported by the .NET **nanoFramework** team and | [ST_STM32F411_DISCOVERY](ChibiOS/ST_STM32F411_DISCOVERY) | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images-community-targets/raw/ST_STM32F411_DISCOVERY/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images-community-targets/packages/detail/raw/ST_STM32F411_DISCOVERY/latest/) | STM32F411VE | 100MHz | 512kB | 128kB | | [ST Nucleo144 F412ZG](ChibiOS/ST_NUCLEO144_F412ZG_NF) | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images-community-targets/raw/ST_NUCLEO144_F412ZG_NF/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images-community-targets/packages/detail/raw/ST_NUCLEO144_F412ZG_NF/latest/) | STM32F412ZG | 100 MHz | 1024 kB | 256 kB | | [ST Nucleo144 F746ZG](ChibiOS/ST_NUCLEO144_F746ZG) | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images-community-targets/raw/ST_NUCLEO144_F746ZG/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images-community-targets/packages/detail/raw/ST_NUCLEO144_F746ZG/latest/) | STM32F746ZG | 216 MHz | 1024 kB | 320 kB | +| [ST Nucleo144 F746ZG](ChibiOS/ST_NUCLEO144_F767ZI) | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images-community-targets/raw/ST_NUCLEO144_F767ZI/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images-community-targets/packages/detail/raw/ST_NUCLEO144_F767ZI/latest/) | STM32F767ZI | 216 MHz | 1024 kB | 320 kB | | [ST STM32F4DISCO](ChibiOS/ST_STM32F4_DISCOVERY) | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images-community-targets/raw/ST_STM32F4_DISCOVERY/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images-community-targets/packages/detail/raw/ST_STM32F4_DISCOVERY/latest/) | STM32F407VGT6 | 168 MHz | 1024 kB | 192 kB | | [ST Nucleo144 F439ZI](ChibiOS/ST_NUCLEO144_F439ZI) | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images-community-targets/raw/ST_NUCLEO144_F439ZI/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images-community-targets/packages/detail/raw/ST_NUCLEO144_F439ZI/latest/) | STM32F439ZI | 180 MHz | 2048 kB | 256 kB | | [TI_CC1352P1_LAUNCHXL_868](TI_SimpleLink/TI_CC1352P1_LAUNCHXL) | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images-community-targets/raw/TI_CC1352P1_LAUNCHXL_868/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images-community-targets/packages/detail/raw/TI_CC1352P1_LAUNCHXL_868/latest/) | TI CC1352 | 48MHz | 352kB | 80kB | diff --git a/azure-pipelines.yml b/azure-pipelines.yml index 4a082ce1..d0e51d5f 100644 --- a/azure-pipelines.yml +++ b/azure-pipelines.yml @@ -908,6 +908,60 @@ jobs: buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build - template: azure-pipelines-templates/publish-cloudsmith.yml@templatesBuild +############################## +- job: Build_ST_NUCLEO144_F767ZI + condition: >- + or( + contains(dependencies.Get_Commit_Message.outputs['GetCommitDetails.COMMIT_MESSAGE'], '[x] ST_NUCLEO144_F767ZI'), + contains(dependencies.Get_Commit_Message.outputs['GetCommitDetails.COMMIT_MESSAGE'], '[x] BUILD ALL'), + contains(dependencies.Check_Build_Options.outputs['BuildOptions.COMMIT_MESSAGE_FROMPR'], '[x] ST_NUCLEO144_F767ZI'), + contains(dependencies.Check_Build_Options.outputs['BuildOptions.COMMIT_MESSAGE_FROMPR'], '[x] BUILD ALL'), + eq(variables['BUILD_ALL'], 'true'), + eq(variables['BUILD_ST_NUCLEO144_F767ZI'], 'true'), + eq(dependencies.Check_Build_Options.outputs['BuildOptions.GO'], 'True') + ) + + dependsOn: + - Check_Code_Style + + pool: + vmImage: 'windows-latest' + + variables: + TargetBoard: ST_NUCLEO144_F767ZI + TargetPlatform: 'stm32' + BuildOptions: + # creates a counter and assigns it to the revision variable + REVISION: $[counter('ST_NUCLEO144_F767ZI_versioncounter_1_8_1', 0)] + GccArm_Version: + NeedsDFU: true + NeedsSRECORD: false + CMakePreset: ST_NUCLEO144_F767ZI + + steps: + - checkout: self + fetchDepth: 1 + - checkout: templatesBuild + fetchDepth: 1 + + - template: azure-pipelines-templates/clone-nf-interpreter-repo.yml + - template: azure-pipelines-templates/build-preparations.yml@templatesBuild + parameters: + repoDirectory: '$(Build.SourcesDirectory)\nf-interpreter' + - template: azure-pipelines-templates/nb-gitversioning.yml@templatesBuild + parameters: + repoDirectory: '$(Build.SourcesDirectory)\nf-interpreter' + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml@templatesBuild + - template: azure-pipelines-templates/download-install-ninja.yml@templatesBuild + - template: azure-pipelines-templates/download-hexdfu.yml@templatesBuild + - template: azure-pipelines-templates/build-chibios-stm32-targets.yml@templatesBuild + parameters: + repoDirectory: $(Build.SourcesDirectory)\nf-interpreter + - template: azure-pipelines-templates/pack-publish-artifacts.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + - template: azure-pipelines-templates/publish-cloudsmith.yml@templatesBuild + ############################## - job: Build_ST_STM32F4_DISCOVERY condition: >- From ec6744f21c495fe0848a12baa5ff230c498b3309 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 1 Nov 2023 14:42:37 +0000 Subject: [PATCH 2/2] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 314a9f19..49d73e70 100644 --- a/README.md +++ b/README.md @@ -26,7 +26,7 @@ The provided boards are **NOT** supported by the .NET **nanoFramework** team and | [ST_STM32F411_DISCOVERY](ChibiOS/ST_STM32F411_DISCOVERY) | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images-community-targets/raw/ST_STM32F411_DISCOVERY/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images-community-targets/packages/detail/raw/ST_STM32F411_DISCOVERY/latest/) | STM32F411VE | 100MHz | 512kB | 128kB | | [ST Nucleo144 F412ZG](ChibiOS/ST_NUCLEO144_F412ZG_NF) | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images-community-targets/raw/ST_NUCLEO144_F412ZG_NF/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images-community-targets/packages/detail/raw/ST_NUCLEO144_F412ZG_NF/latest/) | STM32F412ZG | 100 MHz | 1024 kB | 256 kB | | [ST Nucleo144 F746ZG](ChibiOS/ST_NUCLEO144_F746ZG) | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images-community-targets/raw/ST_NUCLEO144_F746ZG/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images-community-targets/packages/detail/raw/ST_NUCLEO144_F746ZG/latest/) | STM32F746ZG | 216 MHz | 1024 kB | 320 kB | -| [ST Nucleo144 F746ZG](ChibiOS/ST_NUCLEO144_F767ZI) | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images-community-targets/raw/ST_NUCLEO144_F767ZI/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images-community-targets/packages/detail/raw/ST_NUCLEO144_F767ZI/latest/) | STM32F767ZI | 216 MHz | 1024 kB | 320 kB | +| [ST Nucleo144 F767ZG](ChibiOS/ST_NUCLEO144_F767ZI) | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images-community-targets/raw/ST_NUCLEO144_F767ZI/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images-community-targets/packages/detail/raw/ST_NUCLEO144_F767ZI/latest/) | STM32F767ZI | 216 MHz | 1024 kB | 320 kB | | [ST STM32F4DISCO](ChibiOS/ST_STM32F4_DISCOVERY) | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images-community-targets/raw/ST_STM32F4_DISCOVERY/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images-community-targets/packages/detail/raw/ST_STM32F4_DISCOVERY/latest/) | STM32F407VGT6 | 168 MHz | 1024 kB | 192 kB | | [ST Nucleo144 F439ZI](ChibiOS/ST_NUCLEO144_F439ZI) | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images-community-targets/raw/ST_NUCLEO144_F439ZI/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images-community-targets/packages/detail/raw/ST_NUCLEO144_F439ZI/latest/) | STM32F439ZI | 180 MHz | 2048 kB | 256 kB | | [TI_CC1352P1_LAUNCHXL_868](TI_SimpleLink/TI_CC1352P1_LAUNCHXL) | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images-community-targets/raw/TI_CC1352P1_LAUNCHXL_868/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images-community-targets/packages/detail/raw/TI_CC1352P1_LAUNCHXL_868/latest/) | TI CC1352 | 48MHz | 352kB | 80kB |