DE10_NANO_SoC_GHRD.sv

//=======================================================
//  This code *was, at some time, * generated by Terasic System Builder
//=======================================================

module DE10_NANO_SoC_GHRD(

    //////////// CLOCK //////////
    input logic              FPGA_CLK1_50,
    input logic              FPGA_CLK2_50,
    input logic              FPGA_CLK3_50,

    //////////// HPS //////////
    output logic  [14: 0]    HPS_DDR3_ADDR,
    output logic  [ 2: 0]    HPS_DDR3_BA,
    output logic             HPS_DDR3_CAS_N,
    output logic             HPS_DDR3_CK_N,
    output logic             HPS_DDR3_CK_P,
    output logic             HPS_DDR3_CKE,
    output logic             HPS_DDR3_CS_N,
    output logic  [ 3: 0]    HPS_DDR3_DM,
    inout  logic  [31: 0]    HPS_DDR3_DQ,
    inout  logic  [ 3: 0]    HPS_DDR3_DQS_N,
    inout  logic  [ 3: 0]    HPS_DDR3_DQS_P,
    output logic             HPS_DDR3_ODT,
    output logic             HPS_DDR3_RAS_N,
    output logic             HPS_DDR3_RESET_N,
    input  logic             HPS_DDR3_RZQ,
    output logic             HPS_DDR3_WE_N,

    //////////// GPIO //////////
    inout  logic  [35:0]     GPIO_D,

    //////////// LED //////////
    output logic  [ 7: 0]    LED,

    //////////// SWITCHES //////////
    input  logic  [ 3: 0]    SW,
     
    //////////// SWITCHES //////////
    input  logic  [ 1: 0]    KEY
);

//=======================================================
//  reg/wire declarations
//=======================================================
logic hps_fpga_reset_n;
logic fpga_clk_50;

//=======================================================
//  RAM variables
//=======================================================
logic [21:0] address = 16'd0;
logic read = 1'b0;
logic write = 1'b0;
logic acknowledge;
logic [31:0] read_data = 32'd0;
logic [31:0] write_data = 32'd0;
logic [3:0] byte_enable = 4'b1111;

//=======================================================
//  UART variables
//=======================================================
logic [7:0] uart_wdata;
logic uart_write;
logic uart_in_error;
logic uart_in_ready;

logic [7:0] uart_rdata;
logic uart_out_ready;
logic uart_out_error;
logic uart_out_valid;
logic [31:0] GPIOS;

// connection of internal logics
assign fpga_clk_50 = FPGA_CLK1_50;
assign GPIO_D[34:3] = GPIOS;

//=======================================================
//  Structural coding
//=======================================================
soc_system u_u0(
    //Clock&Resetread_data[6:0]
    .clk_clk(FPGA_CLK1_50),                                      //                            clk.clk
    .reset_reset_n(hps_fpga_reset_n),                            //                          reset.reset_n
    //HPS ddr3
    .memory_mem_a(HPS_DDR3_ADDR),                                //                         memory.mem_a
    .memory_mem_ba(HPS_DDR3_BA),                                 //                               .mem_ba
    .memory_mem_ck(HPS_DDR3_CK_P),                               //                               .mem_ck
    .memory_mem_ck_n(HPS_DDR3_CK_N),                             //                               .mem_ck_n
    .memory_mem_cke(HPS_DDR3_CKE),                               //                               .mem_cke
    .memory_mem_cs_n(HPS_DDR3_CS_N),                             //                               .mem_cs_n
    .memory_mem_ras_n(HPS_DDR3_RAS_N),                           //                               .mem_ras_n
    .memory_mem_cas_n(HPS_DDR3_CAS_N),                           //                               .mem_cas_n
    .memory_mem_we_n(HPS_DDR3_WE_N),                             //                               .mem_we_n
    .memory_mem_reset_n(HPS_DDR3_RESET_N),                       //                               .mem_reset_n
    .memory_mem_dq(HPS_DDR3_DQ),                                 //                               .mem_dq
    .memory_mem_dqs(HPS_DDR3_DQS_P),                             //                               .mem_dqs
    .memory_mem_dqs_n(HPS_DDR3_DQS_N),                           //                               .mem_dqs_n
    .memory_mem_odt(HPS_DDR3_ODT),                               //                               .mem_odt
    .memory_mem_dm(HPS_DDR3_DM),                                 //                               .mem_dm
    .memory_oct_rzqin(HPS_DDR3_RZQ),                             //                               .oct_rzqin

    .hps_0_h2f_reset_reset_n(hps_fpga_reset_n),                  //                hps_0_h2f_reset.reset_n
    .sdram_address(address),
    .sdram_byte_enable(byte_enable),                             //                .byte_enable
    .sdram_read(read),              //                .read
    .sdram_write(write),             //                .write
    .sdram_write_data(write_data),        //                .write_data
    .sdram_acknowledge(acknowledge),       //                .acknowledge
    .sdram_read_data(read_data),

    .uart_RXD(GPIO_D[0]), // uart_0_external_connection.rxd
    .uart_TXD(GPIO_D[1]), //                           .txd

    .uart_in_data(uart_wdata),
    .uart_in_error(uart_in_error),
    .uart_in_valid(uart_write),
    .uart_in_ready(uart_in_ready),

    .uart_out_ready(uart_out_ready),
    .uart_out_data(uart_rdata),
    .uart_out_error(uart_out_error),
    .uart_out_valid(uart_out_valid)
);

//=======================================================
//  Memory read/write finite automata
//=======================================================

enum int unsigned {
    MEM_STATE_INIT = 1,
    MEM_STATE_READ_PENDING = 2,
    MEM_STATE_WRITE_PENDING = 3
} cur_mem_state, next_mem_state;

logic read_req  = 0;
logic write_req = 0;

// State switch logic
always_comb begin
    next_mem_state = cur_mem_state;
    case (cur_mem_state)
        MEM_STATE_INIT: begin
            if (read_req) next_mem_state = MEM_STATE_READ_PENDING;
            else if (write_req) next_mem_state = MEM_STATE_WRITE_PENDING;
        end

        MEM_STATE_READ_PENDING: begin
            if (acknowledge) next_mem_state = MEM_STATE_INIT;
        end

        MEM_STATE_WRITE_PENDING: begin
            if (acknowledge) next_mem_state = MEM_STATE_INIT;
        end

        default: begin
            next_mem_state = MEM_STATE_INIT;
        end
    endcase
end

always_comb begin
    read = 0;
    write = 0;

    case (cur_mem_state)
        MEM_STATE_READ_PENDING: begin
            read = 1;
        end

        MEM_STATE_WRITE_PENDING: begin
            write = 1;
        end

        default: begin
        end
    endcase
end

//=======================================================
//  CPU state enum and regs / wires
//=======================================================
enum int unsigned {
    CPU_STATE_INSTR_FETCH              = 1,
    CPU_STATE_INSTR_FETCH_1            = 2,
    CPU_STATE_INSTR_DECODE             = 3,
    CPU_STATE_INSTR_DECODE_1           = 4,
    CPU_STATE_INSTR_IMM_FETCH          = 5,
    CPU_STATE_INSTR_OPERAND_FETCH      = 6,
    CPU_STATE_INSTR_EXEC               = 7,
    CPU_STATE_INSTR_WRITEBACK          = 8
} cur_cpu_state;

//=======================================================
//  CPU single-step button setup.
//=======================================================

// Cpu single-step clock setup
// If a SW[3] is set to 1,
// then the cpu cycles by pressing KEY[1]
logic [1:0] debounced_keys = 2'd0;
debounce #(2, "LOW", 50000, 16) debouncer(
    .clk(fpga_clk_50),
    .reset_n(hps_fpga_reset_n),
    .data_in(KEY),
    .data_out(debounced_keys)
);

reg   is_halted    = 0;
reg   cycle_done   = 1;
reg   prev_pressed = 0;

//=======================================================
//  CPU instruction decoder / registers
//=======================================================

parameter MEM_STACK_BASE = 16'h4000;

reg [23:0] cur_instruction = 24'd0;
reg [15:0] PC = 16'd0;
reg [15:0] IMM_ADDR = 16'd0;
reg [15:0] FR = 16'd0;
reg [15:0] SP  = MEM_STACK_BASE;

reg [15:0] ACC = 0;
reg [15:0] IR1 = 0;
reg [15:0] IR2 = 0;

// CPU variables
reg [31:0] data = 32'd0;
reg [15:0] tmp_address = 16'd0;
reg [15:0] tmp_word = 16'd0;
reg [15:0] cur_imm = 16'd0;
reg [15:0] snd_imm = 16'd0;
assign LED[7: 0] = PC[7:0];

//=======================================================
//  UART I/O variables and logic
//=======================================================
logic uart_write_req = 0;
logic uart_read_req = 0;
logic [7:0] uart_data = 0;

always_ff @(posedge fpga_clk_50 or negedge hps_fpga_reset_n) begin
if (~hps_fpga_reset_n) begin


cur_mem_state <= MEM_STATE_INIT;
cur_cpu_state <= CPU_STATE_INSTR_FETCH;
cycle_done <= 1;

read_req <= '0;
write_req <= '0;
prev_pressed <= debounced_keys[1];

cur_instruction <= 6'd0;
PC <= '0;
FR <= 16'd0;
SP <= MEM_STACK_BASE;
uart_out_ready <= '1;
uart_write <= '0;


end else begin


if (uart_out_valid) begin
    uart_data <= uart_rdata;
    uart_read_req <= 0;
    uart_out_ready <= 0;
    uart_write <= 0;
end

if (uart_write) begin
    uart_write_req <= 0;
    uart_out_ready <= 0;
    uart_write <= 0;
end

if (uart_write_req & uart_in_ready & ~uart_out_valid & ~uart_write) begin
    uart_out_ready <= 0;
    uart_write <= 1;
end else if (uart_read_req & ~uart_out_valid) begin
    uart_out_ready <= 1;
    uart_write <= 0;
end 

// Lotsa logic, sorry
cur_mem_state <= next_mem_state;

if (~debounced_keys[0]) is_halted <= 0;
if (~debounced_keys[0] & SW[1]) begin
    SP <= MEM_STACK_BASE;
    PC <= '0;
end

prev_pressed <= debounced_keys[1];
case (cur_mem_state)
    MEM_STATE_INIT: begin
    end

    MEM_STATE_READ_PENDING: begin
        if (acknowledge) data <= read_data;
        read_req <= 0;
        write_req <= 0;
    end

    MEM_STATE_WRITE_PENDING: begin
        read_req <= 0;
        write_req <= 0;
    end

    default: begin
        read_req <= 0;
        write_req <= 0;
    end
endcase

//=======================================================
//  The instruction decoder itself. Finally )
//=======================================================
if (
    ~SW[1] & // If SW[1] is on, we wait for button 0 to set PC to 0
    cur_mem_state == MEM_STATE_INIT & ~is_halted & // Only do cpu stuff when memory is not read/written to
    ~read_req & ~write_req & // Same as line one
    ~uart_write_req &  ~uart_read_req &// Can't do UART either (
    (~SW[3] | (prev_pressed & ~debounced_keys[1] & cycle_done) | ~cycle_done) // Button checker
    ) begin
    cycle_done <= cur_cpu_state == CPU_STATE_INSTR_WRITEBACK;

    case (cur_cpu_state)
        CPU_STATE_INSTR_FETCH: begin
            cur_cpu_state <= CPU_STATE_INSTR_FETCH_1;
        end

        CPU_STATE_INSTR_FETCH_1: begin
            cur_cpu_state <= CPU_STATE_INSTR_DECODE;
        end

        CPU_STATE_INSTR_DECODE: begin
            cur_cpu_state <= CPU_STATE_INSTR_DECODE_1;
        end

        CPU_STATE_INSTR_DECODE_1: begin
            cur_cpu_state <= CPU_STATE_INSTR_IMM_FETCH;
        end

        CPU_STATE_INSTR_IMM_FETCH: begin
            cur_cpu_state <= CPU_STATE_INSTR_OPERAND_FETCH;
        end

        CPU_STATE_INSTR_OPERAND_FETCH: begin
            cur_cpu_state <= CPU_STATE_INSTR_EXEC;
        end

        CPU_STATE_INSTR_EXEC: begin
            cur_cpu_state <= CPU_STATE_INSTR_WRITEBACK;
        end

        CPU_STATE_INSTR_WRITEBACK: begin
            cur_cpu_state <= CPU_STATE_INSTR_FETCH;
        end

        default: begin
            cur_cpu_state <= CPU_STATE_INSTR_FETCH;
        end
    endcase

    if (cur_cpu_state == CPU_STATE_INSTR_FETCH) begin
        address <= {PC[15:2], 2'b00};
        byte_enable <= 4'b1111;
        read_req <= 1;
    end else if (cur_cpu_state == CPU_STATE_INSTR_FETCH_1) begin
        case (PC[1:0])
            2'b00: cur_instruction <= data[23:0];
            2'b01: cur_instruction <= data[31:8];
            2'b10: begin
                cur_instruction[15:0] <= data[31:16];
                address <= {PC[15:2], 2'b00} + 16'd4;
                read_req <= 1;
                byte_enable <= 4'b1111;
            end

            2'b11: begin
                cur_instruction[7:0] <= data[31:24];
                address <= {PC[15:2], 2'b00} + 16'd4;
                read_req <= 1;
                byte_enable <= 4'b1111;
            end
            default: begin
            end
        endcase
    end else if (cur_cpu_state == CPU_STATE_INSTR_DECODE) begin
        case (PC[1:0])
            2'b10: cur_instruction[23:16] <= data[7:0];
            2'b11: cur_instruction[23:8] <= data[15:0];
            default: begin
            end
        endcase
    end else if (cur_cpu_state == CPU_STATE_INSTR_DECODE_1) begin
        if (cur_instruction[7]) PC <= PC + 16'd3;
        else PC <= PC + 16'd1;
    end else begin
        case (cur_instruction[7:0])
            // NOP
            default: begin
                if (cur_cpu_state == CPU_STATE_INSTR_WRITEBACK) PC <= PC + 1;
            end

            // HALT
            8'b00000000: begin
                if (cur_cpu_state == CPU_STATE_INSTR_WRITEBACK) is_halted <= 1;
            end

            // LOAD
            8'b00000001: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        address <= {ACC[15:2], 2'b00}; 
                        tmp_address <= ACC;
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (ACC[1:0])
                            2'b00: ACC <= data[15:0];
                            2'b01: ACC <= data[23:8];
                            2'b10: ACC <= data[31:16];
                            2'b11: begin
                                ACC[7:0] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) ACC[15:8] <= data[7:0];
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        ACC <= {ACC[7:0], ACC[15:8]};
                    end

                    default: begin
                    end
                endcase
            end

            // LOAD $IMM
            8'b10010000: begin
                if (cur_cpu_state == CPU_STATE_INSTR_EXEC) ACC <= cur_instruction[23:8];
                else if (cur_cpu_state == CPU_STATE_INSTR_WRITEBACK) ACC <= {ACC[7:0], ACC[15:8]};
            end

            // LOADF
            8'b00000010: begin
                if (cur_cpu_state == CPU_STATE_INSTR_EXEC) ACC <= FR;
            end

            // LOAD1
            8'b01000001: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        address <= {IR1[15:2], 2'b00}; 
                        tmp_address <= IR1;
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (IR1[1:0])
                            2'b00: ACC <= data[15:0];
                            2'b01: ACC <= data[23:8];
                            2'b10: ACC <= data[31:16];
                            2'b11: begin
                                ACC[7:0] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) ACC[15:8] <= data[7:0];
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        ACC <= {ACC[7:0], ACC[15:8]};
                    end

                    default: begin
                    end
                endcase
            end

            // LOAD2
            8'b01000010: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        address <= {IR2[15:2], 2'b00}; 
                        tmp_address <= IR2;
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (IR2[1:0])
                            2'b00: ACC <= data[15:0];
                            2'b01: ACC <= data[23:8];
                            2'b10: ACC <= data[31:16];
                            2'b11: begin
                                ACC[7:0] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) ACC[15:8] <= data[7:0];
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        ACC <= {ACC[7:0], ACC[15:8]};
                    end

                    default: begin
                    end
                endcase
            end

            // LOADI1
            8'b00011111: begin
                if (cur_cpu_state == CPU_STATE_INSTR_EXEC) ACC <= IR1;
            end

            // LOADI2
            8'b00100000: begin
                if (cur_cpu_state == CPU_STATE_INSTR_EXEC) ACC <= IR2;
            end

            // STORE1
            8'b00000011: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        ACC <= {ACC[7:0], ACC[15:8]};
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        write_req <= 1;
                        address <= {IR1[15:2], 2'b00};
                        case (IR1[1:0])
                            2'b00: begin
                                byte_enable <= 4'b0011;
                                write_data <= {2{ACC[7:0], ACC[15:8]}};
                            end

                            2'b10: begin
                                byte_enable <= 4'b1100;
                                write_data <= {2{ACC[7:0], ACC[15:8]}};
                            end

                            2'b01: begin
                                byte_enable <= 4'b0010;
                                write_data <= {4{ACC[7:0]}};
                            end

                            2'b11: begin
                                byte_enable <= 4'b1000;
                                write_data <= {4{ACC[7:0]}};
                            end

                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        case (IR1[1:0])
                            2'b01: begin
                                write_req <= 1;
                                address <= {IR1[15:2], 2'b00};
                                byte_enable <= 4'b0100;
                                write_data <= {4{ACC[15:8]}};
                            end

                            2'b11: begin
                                write_req <= 1;
                                address <= {IR1[15:2], 2'b00} + 16'd4;
                                byte_enable <= 4'b0001;
                                write_data <= {4{ACC[15:8]}};
                            end

                            default: begin
                            end
                        endcase

                    end

                    default: begin
                    end
                endcase
            end

            // STORE1 $IMM
            8'b10010001: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        write_req <= 1;
                        address <= {IR1[15:2], 2'b00};
                        case (IR1[1:0])
                            2'b00: begin
                                byte_enable <= 4'b0011;
                                write_data <= {2{cur_instruction[23:8]}};
                            end

                            2'b10: begin
                                byte_enable <= 4'b1100;
                                write_data <= {2{cur_instruction[23:8]}};
                            end

                            2'b01: begin
                                byte_enable <= 4'b0010;
                                write_data <= {4{cur_instruction[15:8]}};
                            end

                            2'b11: begin
                                byte_enable <= 4'b1000;
                                write_data <= {4{cur_instruction[15:8]}};
                            end

                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (IR1[1:0])
                            2'b01: begin
                                write_req <= 1;
                                address <= {IR1[15:2], 2'b00};
                                byte_enable <= 4'b0100;
                                write_data <= {4{cur_instruction[23:16]}};
                            end

                            2'b11: begin
                                write_req <= 1;
                                address <= {IR1[15:2], 2'b00} + 16'd4;
                                byte_enable <= 4'b0001;
                                write_data <= {4{cur_instruction[23:16]}};
                            end

                            default: begin
                            end
                        endcase

                    end

                    default: begin
                    end
                endcase
            end

            // STORE2
            8'b00100011: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        ACC <= {ACC[7:0], ACC[15:8]};
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        write_req <= 1;
                        address <= {IR2[15:2], 2'b00};
                        case (IR2[1:0])
                            2'b00: begin
                                byte_enable <= 4'b0011;
                                write_data <= {2{ACC[7:0], ACC[15:8]}};
                            end

                            2'b10: begin
                                byte_enable <= 4'b1100;
                                write_data <= {2{ACC[7:0], ACC[15:8]}};
                            end

                            2'b01: begin
                                byte_enable <= 4'b0010;
                                write_data <= {4{ACC[7:0]}};
                            end

                            2'b11: begin
                                byte_enable <= 4'b1000;
                                write_data <= {4{ACC[7:0]}};
                            end

                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        case (IR2[1:0])
                            2'b01: begin
                                write_req <= 1;
                                address <= {IR2[15:2], 2'b00};
                                byte_enable <= 4'b0100;
                                write_data <= {4{ACC[15:8]}};
                            end

                            2'b11: begin
                                write_req <= 1;
                                address <= {IR2[15:2], 2'b00} + 16'd4;
                                byte_enable <= 4'b0001;
                                write_data <= {4{ACC[15:8]}};
                            end

                            default: begin
                            end
                        endcase

                    end

                    default: begin
                    end
                endcase
            end

            // STORE2 $IMM
            8'b11110010: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        write_req <= 1;
                        address <= {IR2[15:2], 2'b00};
                        case (IR2[1:0])
                            2'b00: begin
                                byte_enable <= 4'b0011;
                                write_data <= {2{cur_instruction[23:8]}};
                            end

                            2'b10: begin
                                byte_enable <= 4'b1100;
                                write_data <= {2{cur_instruction[23:8]}};
                            end

                            2'b01: begin
                                byte_enable <= 4'b0010;
                                write_data <= {4{cur_instruction[15:8]}};
                            end

                            2'b11: begin
                                byte_enable <= 4'b1000;
                                write_data <= {4{cur_instruction[15:8]}};
                            end

                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (IR2[1:0])
                            2'b01: begin
                                write_req <= 1;
                                address <= {IR2[15:2], 2'b00};
                                byte_enable <= 4'b0100;
                                write_data <= {4{cur_instruction[23:16]}};
                            end

                            2'b11: begin
                                write_req <= 1;
                                address <= {IR2[15:2], 2'b00} + 16'd4;
                                byte_enable <= 4'b0001;
                                write_data <= {4{cur_instruction[23:16]}};
                            end

                            default: begin
                            end
                        endcase

                    end

                    default: begin
                    end
                endcase
            end

            // STOREF
            8'b00000100: begin
                if (cur_cpu_state == CPU_STATE_INSTR_EXEC) FR <= ACC;
            end

            // STOREI1
            8'b00100001: begin
                if (cur_cpu_state == CPU_STATE_INSTR_EXEC) IR1 <= ACC;
            end

            // STOREI2
            8'b00100010: begin
                if (cur_cpu_state == CPU_STATE_INSTR_EXEC) IR2 <= ACC;
            end

            // TI12
            8'b00111111: begin
                if (cur_cpu_state == CPU_STATE_INSTR_EXEC) IR2 <= IR1;
            end

            // TI21
            8'b01000000: begin
                if (cur_cpu_state == CPU_STATE_INSTR_EXEC) IR1 <= IR2;
            end

            // MOV $IMM
            8'b10000000: begin
                if (cur_cpu_state == CPU_STATE_INSTR_EXEC) ACC <= {cur_instruction[15:8], cur_instruction[23:16]};
            end

            // PUSH
            8'b00000101: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        SP <= SP - 16'd2;
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        write_req <= 1;
                        write_data <= {2{ACC[7:0], ACC[15:8]}};
                        address <= {SP[15:2], 2'b00};
                        if (SP[1]) byte_enable <= 4'b1100;
                        else byte_enable <= 4'b0011;
                    end

                    default: begin
                    end
                endcase
            end

            // POP
            8'b00000111: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        SP <= SP + 16'd2;
                        address <= {SP[15:2], 2'b00};
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        if (SP[1]) ACC <= {data[23:16], data[31:24]};
                        else ACC <= {data[7:0], data[15:8]};
                    end

                    default: begin
                    end
                endcase
            end

            // PUSHF
            8'b00000110: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        SP <= SP - 16'd2;
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        write_req <= 1;
                        write_data <= {2{FR[7:0], FR[15:8]}};
                        address <= {SP[15:2], 2'b00};
                        if (SP[1]) byte_enable <= 4'b1100;
                        else byte_enable <= 4'b0011;
                    end

                    default: begin
                    end
                endcase
            end

            // POPF
            8'b00001000: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        SP <= SP + 16'd2;
                        address <= {SP[15:2], 2'b00};
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        if (SP[1]) FR <= {data[23:16], data[31:24]};
                        else FR <= {data[7:0], data[15:8]};
                    end

                    default: begin
                    end
                endcase
            end

            // PUSHI1
            8'b00111101: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        SP <= SP - 16'd2;
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        write_req <= 1;
                        write_data <= {2{IR1[7:0], IR1[15:8]}};
                        address <= {SP[15:2], 2'b00};
                        if (SP[1]) byte_enable <= 4'b1100;
                        else byte_enable <= 4'b0011;
                    end

                    default: begin
                    end
                endcase
            end

            // POPI1
            8'b00001001: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        SP <= SP + 16'd2;
                        address <= {SP[15:2], 2'b00};
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        if (SP[1]) IR1 <= {data[23:16], data[31:24]};
                        else IR1 <= {data[7:0], data[15:8]};
                    end

                    default: begin
                    end
                endcase
            end

            // PUSHI2
            8'b00100100: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        SP <= SP - 16'd2;
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        write_req <= 1;
                        write_data <= {2{IR2[7:0], IR2[15:8]}};
                        address <= {SP[15:2], 2'b00};
                        if (SP[1]) byte_enable <= 4'b1100;
                        else byte_enable <= 4'b0011;
                    end

                    default: begin
                    end
                endcase
            end

            // POPI2
            8'b00100101: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        SP <= SP + 16'd2;
                        address <= {SP[15:2], 2'b00};
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        if (SP[1]) IR2 <= {data[23:16], data[31:24]};
                        else IR2 <= {data[7:0], data[15:8]};
                    end

                    default: begin
                    end
                endcase
            end

            // ADD [$MEM]
            8'b00001010: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= {cur_instruction[15:8], cur_instruction[23:16]};
                        address <= {cur_instruction[15:8], cur_instruction[23:16], 2'b00}; 
                        PC <= PC + 16'd2;
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC + {tmp_word[15:8], data[7:0]};
                        end else begin
                            ACC <= ACC + {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC < tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // ADDI1
            8'b00100110: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR1;
                        address <= {IR1[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC + {tmp_word[15:8], data[7:0]};
                        end else begin
                            ACC <= ACC + {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC < tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // ADDI2
            8'b00100111: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR2;
                        address <= {IR2[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC + {tmp_word[15:8], data[7:0]};
                        end else begin
                            ACC <= ACC + {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC < tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // SUB [$MEM]
            8'b00001011: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= {cur_instruction[15:8], cur_instruction[23:16]};
                        address <= {cur_instruction[15:8], cur_instruction[23:16], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC - {tmp_word[15:8], data[7:0]};
                        end else begin
                            ACC <= ACC - {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC > tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // SUBI1
            8'b00101000: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR1;
                        address <= {IR1[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC - {tmp_word[15:8], data[7:0]};
                        end else begin
                            ACC <= ACC - {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC > tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // SUBI2
            8'b00101001: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR2;
                        address <= {IR2[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC - {tmp_word[15:8], data[7:0]};
                        end else begin
                            ACC <= ACC - {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC > tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // MUL [$MEM]
            8'b00001110: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= {cur_instruction[15:8], cur_instruction[23:16]};
                        address <= {cur_instruction[15:8], cur_instruction[23:16], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC * {tmp_word[15:8], data[7:0]};
                        end else begin
                            ACC <= ACC * {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC > tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= tmp_word == 0 | cur_imm == 0;
                    end

                    default: begin
                    end
                endcase
            end

            // MULI1
            8'b00101010: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR1;
                        address <= {IR1[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC * {tmp_word[15:8], data[7:0]};
                        end else begin
                            ACC <= ACC * {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC > tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= tmp_word == 0 | cur_imm == 0;
                    end

                    default: begin
                    end
                endcase
            end

            // MULI2
            8'b00101011: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR2;
                        address <= {IR2[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC * {tmp_word[15:8], data[7:0]};
                        end else begin
                            ACC <= ACC * {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC > tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= tmp_word == 0 | cur_imm == 0;
                    end

                    default: begin
                    end
                endcase
            end

            // DIV [$MEM]
            8'b00001111: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= {cur_instruction[15:8], cur_instruction[23:16]};
                        address <= {cur_instruction[15:8], cur_instruction[23:16], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            if (|{tmp_word[15:8], data[7:0]}) ACC <= ACC / {tmp_word[15:8], data[7:0]};
                            else ACC <= 0;
                        end else begin
                            if (|{tmp_word[7:0], tmp_word[15:8]}) ACC <= ACC / {tmp_word[7:0], tmp_word[15:8]};
                            else ACC <= 0;
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC > tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ACC == 0;
                        FR[4] <= tmp_word == 0;
                    end

                    default: begin
                    end
                endcase
            end

            // DIVI1
            8'b00101100: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR1;
                        address <= {IR1[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            if (|{tmp_word[15:8], data[7:0]}) ACC <= ACC / {tmp_word[15:8], data[7:0]};
                            else ACC <= 0;
                        end else begin
                            if (|{tmp_word[7:0], tmp_word[15:8]}) ACC <= ACC / {tmp_word[7:0], tmp_word[15:8]};
                            else ACC <= 0;
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC > tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ACC == 0;
                        FR[4] <= tmp_word == 0;
                    end

                    default: begin
                    end
                endcase
            end

            // DIVI2
            8'b00101101: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR2;
                        address <= {IR2[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            if (|{tmp_word[15:8], data[7:0]}) ACC <= ACC / {tmp_word[15:8], data[7:0]};
                            else ACC <= 0;
                        end else begin
                            if (|{tmp_word[7:0], tmp_word[15:8]}) ACC <= ACC / {tmp_word[7:0], tmp_word[15:8]};
                            else ACC <= 0;
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC > tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ACC == 0;
                        FR[4] <= tmp_word == 0;
                    end

                    default: begin
                    end
                endcase
            end

            // INC
            8'b00001100: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        tmp_word <= 16'd1;
                        cur_imm <= ACC;
                        ACC <= ACC + 16'd1;
                        FR <= 16'd0;
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        FR[0] <= ACC < tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // IN1
            8'b00101110: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        tmp_word <= 16'd1;
                        cur_imm <= IR1;
                        IR1 <= IR1 + 16'd1;
                        FR <= 16'd0;
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        FR[0] <= IR1 < tmp_word;
                        FR[1] <= (
                            (~IR1[15] & tmp_word[15] & cur_imm[15]) |
                            (IR1[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= IR1[15];
                        FR[3] <= ~(|IR1);
                    end

                    default: begin
                    end
                endcase
            end

            // IN2
            8'b00101111: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        tmp_word <= 16'd1;
                        cur_imm <= IR2;
                        IR2 <= IR2 + 16'd1;
                        FR <= 16'd0;
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        FR[0] <= IR2 < tmp_word;
                        FR[1] <= (
                            (~IR2[15] & tmp_word[15] & cur_imm[15]) |
                            (IR2[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= IR2[15];
                        FR[3] <= ~(|IR2);
                    end

                    default: begin
                    end
                endcase
            end

            // DEC
            8'b00001101: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        tmp_word <= 16'd1;
                        cur_imm <= ACC;
                        ACC <= ACC - 16'd1;
                        FR <= 16'd0;
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        FR[0] <= ACC > tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // DE1
            8'b00110000: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        tmp_word <= 16'd1;
                        cur_imm <= IR1;
                        IR1 <= IR1 - 16'd1;
                        FR <= 16'd0;
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        FR[0] <= IR1 > tmp_word;
                        FR[1] <= (
                            (~IR1[15] & tmp_word[15] & cur_imm[15]) |
                            (IR1[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= IR1[15];
                        FR[3] <= ~(|IR1);
                    end

                    default: begin
                    end
                endcase
            end

            // DE2
            8'b00110001: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        tmp_word <= 16'd1;
                        cur_imm <= IR2;
                        IR2 <= IR2 + 16'd1;
                        FR <= 16'd0;
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        FR[0] <= IR2 > tmp_word;
                        FR[1] <= (
                            (~IR2[15] & tmp_word[15] & cur_imm[15]) |
                            (IR2[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= IR2[15];
                        FR[3] <= ~(|IR2);
                    end

                    default: begin
                    end
                endcase
            end

            // AND [$MEM]
            8'b00010000: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= {cur_instruction[15:8], cur_instruction[23:16]};
                        address <= {cur_instruction[15:8], cur_instruction[23:16], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC & {tmp_word[15:8], data[7:0]};
                        end else  begin
                            ACC <= ACC & {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC < tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // ANDI1
            8'b00110010: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR1;
                        address <= {IR1[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC & {tmp_word[15:8], data[7:0]};
                        end else  begin
                            ACC <= ACC & {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC < tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // ANDI2
            8'b00110011: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR2;
                        address <= {IR2[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC & {tmp_word[15:8], data[7:0]};
                        end else  begin
                            ACC <= ACC & {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC < tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // OR [$MEM]
            8'b00010001: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= {cur_instruction[15:8], cur_instruction[23:16]};
                        address <= {cur_instruction[15:8], cur_instruction[23:16], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC | {data[7:0], tmp_word[7:0]};
                        end else begin
                            ACC <= ACC | {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC < tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // ORI1
            8'b00110100: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR1;
                        address <= {IR1[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC | {data[7:0], tmp_word[7:0]};
                        end else begin
                            ACC <= ACC | {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC < tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // ORI2
            8'b00110101: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR2;
                        address <= {IR2[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC | {data[7:0], tmp_word[7:0]};
                        end else begin
                            ACC <= ACC | {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC < tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // XOR [$MEM]
            8'b00010010: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= {cur_instruction[15:8], cur_instruction[23:16]};
                        address <= {cur_instruction[15:8], cur_instruction[23:16], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC ^ {data[7:0], tmp_word[7:0]};
                        end else begin
                            ACC <= ACC ^ {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC < tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // XORI1
            8'b00110110: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR1;
                        address <= {IR1[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC ^ {data[7:0], tmp_word[7:0]};
                        end else begin
                            ACC <= ACC ^ {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC < tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // XORI2
            8'b00110111: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR2;
                        address <= {IR2[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            ACC <= ACC ^ {data[7:0], tmp_word[7:0]};
                        end else begin
                            ACC <= ACC ^ {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC < tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // NOT
            8'b00010011: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        ACC <= ~ACC;
                    end
                    default: begin
                    end
                endcase
            end

            // NOTI1
            8'b00111000: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR1;
                        address <= {IR1[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[7:0] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[15:8] <= data[7:0];
                            ACC <= ~{data[7:0], tmp_word[7:0]};
                        end else ACC <= ~tmp_word;
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC < tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // NOTI2
            8'b00111110: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR2;
                        address <= {IR2[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[7:0] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[15:8] <= data[7:0];
                            ACC <= ~{data[7:0], tmp_word[7:0]};
                        end else ACC <= ~tmp_word;
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= ACC < tmp_word;
                        FR[1] <= (
                            (~ACC[15] & tmp_word[15] & cur_imm[15]) |
                            (ACC[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // LSH $NUM
            8'b10000001: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_EXEC: begin
                        ACC <= ACC << {cur_instruction[15:8], cur_instruction[7:0]};
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= cur_imm[15];
                        FR[1] <= ACC[15] ^ cur_imm[15];
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // RSH $NUM
            8'b10000010: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_EXEC: begin
                        ACC <= ACC >> {cur_instruction[15:8], cur_instruction[7:0]};
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= cur_imm[15];
                        FR[1] <= ACC[15] ^ cur_imm[15];
                        FR[2] <= ACC[15];
                        FR[3] <= ~(ACC != 0);
                    end

                    default: begin
                    end
                endcase
            end

            // CALL label
            8'b10000100: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        SP <= SP - 16'd2;
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (SP[1]) byte_enable <= 4'b1100;
                        else byte_enable <= 4'b0011;
                        write_data <= {2{PC[7:0], PC[15:8]}};
                        write_req <= 1;
                        PC <= cur_instruction[23:8];

                    end

                    default: begin
                    end
                endcase
            end

            // CALL
            8'b00010100: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        SP <= SP - 16'd2;
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (SP[1]) byte_enable <= 4'b1100;
                        else byte_enable <= 4'b0011;
                        write_data <= {2{PC[7:0], PC[15:8]}};
                        write_req <= 1;
                        PC <= ACC;

                    end

                    default: begin
                    end
                endcase
            end

            // RET
            8'b00010101: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        SP <= SP + 16'd2;
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (SP[1]) PC <= {data[7:0], data[15:8]};
                        else PC <= {data[23:16], data[31:24]};
                    end

                    default: begin
                    end
                endcase
            end

            // CMP [$MEM]
            8'b00010110: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= {cur_instruction[15:8], cur_instruction[23:16]};
                        address <= {cur_instruction[15:8], cur_instruction[23:16], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            snd_imm <= ACC - {tmp_word[15:8], data[7:0]};
                        end else begin
                            snd_imm <= ACC - {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= snd_imm > tmp_word;
                        FR[1] <= (
                            (~snd_imm[15] & tmp_word[15] & cur_imm[15]) |
                            (snd_imm[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= snd_imm[15];
                        FR[3] <= ~(|snd_imm);
                    end

                    default: begin
                    end
                endcase
            end

            // CMPI1
            8'b00111001: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR1;
                        address <= {IR1[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            snd_imm <= ACC - {tmp_word[15:8], data[7:0]};
                        end else begin
                            snd_imm <= ACC - {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= snd_imm > tmp_word;
                        FR[1] <= (
                            (~snd_imm[15] & tmp_word[15] & cur_imm[15]) |
                            (snd_imm[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= snd_imm[15];
                        FR[3] <= ~(|snd_imm);
                    end

                    default: begin
                    end
                endcase
            end

            // CMPI2
            8'b00111010: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR2;
                        address <= {IR2[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            snd_imm <= ACC - {tmp_word[15:8], data[7:0]};
                        end else begin
                            snd_imm <= ACC - {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= snd_imm > tmp_word;
                        FR[1] <= (
                            (~snd_imm[15] & tmp_word[15] & cur_imm[15]) |
                            (snd_imm[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= snd_imm[15];
                        FR[3] <= ~(|snd_imm);
                    end

                    default: begin
                    end
                endcase
            end

            // CMP $IMM
            8'b10000101: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        tmp_word <= {cur_instruction[15:8], cur_instruction[23:16]};
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        snd_imm <= ACC - tmp_word;
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= snd_imm > tmp_word;
                        FR[1] <= (
                            (~snd_imm[15] & tmp_word[15] & cur_imm[15]) |
                            (snd_imm[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= snd_imm[15];
                        FR[3] <= ~(|snd_imm);
                    end

                    default: begin
                    end
                endcase
            end

            // TEST $IMM
            8'b10000110: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        tmp_word <= {cur_instruction[15:8], cur_instruction[23:16]};;
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        snd_imm <= ACC & tmp_word;
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= snd_imm > tmp_word;
                        FR[1] <= (
                            (~snd_imm[15] & tmp_word[15] & cur_imm[15]) |
                            (snd_imm[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= snd_imm[15];
                        FR[3] <= ~(|snd_imm);
                    end

                    default: begin
                    end
                endcase
            end

            // TEST [$MEM]
            8'b10001111: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= {cur_instruction[15:8], cur_instruction[23:16]};
                        address <= {cur_instruction[15:8], cur_instruction[23:16], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            snd_imm <= ACC & {tmp_word[15:8], data[7:0]};
                        end else begin
                            snd_imm <= ACC & {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= snd_imm > tmp_word;
                        FR[1] <= (
                            (~snd_imm[15] & tmp_word[15] & cur_imm[15]) |
                            (snd_imm[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= snd_imm[15];
                        FR[3] <= ~(|snd_imm);
                    end

                    default: begin
                    end
                endcase
            end

            // TESTI1
            8'b00111011: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR1;
                        address <= {IR1[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            snd_imm <= ACC & {tmp_word[15:8], data[7:0]};
                        end else begin
                            snd_imm <= ACC & {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= snd_imm < tmp_word;
                        FR[1] <= (
                            (~snd_imm[15] & tmp_word[15] & cur_imm[15]) |
                            (snd_imm[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= snd_imm[15];
                        FR[3] <= ~(|snd_imm);
                    end

                    default: begin
                    end
                endcase
            end

            // TESTI2
            8'b00111100: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_IMM_FETCH: begin
                        read_req <= 1;
                        byte_enable <= 4'b1111;
                        tmp_address <= IR2;
                        address <= {IR2[15:2], 2'b00}; 
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        case (tmp_address[1:0])
                            2'b00: tmp_word <= data[15:0];
                            2'b01: tmp_word <= data[23:8];
                            2'b10: tmp_word <= data[31:16];
                            2'b11: begin
                                tmp_word[15:8] <= data[31:24];
                                read_req <= 1;
                                byte_enable <= 4'b1111;
                                address <= {tmp_address[15:2], 2'b00} + 16'd4;
                            end
                            default: begin
                            end
                        endcase
                    end

                    CPU_STATE_INSTR_EXEC: begin
                        if (tmp_address[1:0] == 2'b11) begin
                            tmp_word[7:0] <= data[7:0];
                            snd_imm <= ACC & {tmp_word[15:8], data[7:0]};
                        end else begin
                            snd_imm <= ACC & {tmp_word[7:0], tmp_word[15:8]};
                            tmp_word <= {tmp_word[7:0], tmp_word[15:8]};
                        end
                        FR <= 16'd0;
                        cur_imm <= ACC;
                    end

                    CPU_STATE_INSTR_WRITEBACK: begin
                        FR[0] <= snd_imm < tmp_word;
                        FR[1] <= (
                            (~snd_imm[15] & tmp_word[15] & cur_imm[15]) |
                            (snd_imm[15] & ~tmp_word[15] & ~cur_imm[15])
                        );
                        FR[2] <= snd_imm[15];
                        FR[3] <= ~(|snd_imm);
                    end

                    default: begin
                    end
                endcase
            end

            // JMP $NUM
            8'b10000111: begin
                if (cur_cpu_state == CPU_STATE_INSTR_EXEC) PC <= {cur_instruction[15:8], cur_instruction[23:16]};
            end

            // JMP
            8'b00010111: begin
                if (cur_cpu_state == CPU_STATE_INSTR_EXEC) PC <= ACC;
            end

            // JE $NUM
            8'b10001000: begin
                if (FR[3] & cur_cpu_state == CPU_STATE_INSTR_EXEC) PC <= {cur_instruction[15:8], cur_instruction[23:16]};
            end

            // JE
            8'b00011000: begin
                if (FR[3]& cur_cpu_state == CPU_STATE_INSTR_EXEC) PC <= ACC;
            end

            // JNE $NUM
            8'b10001001: begin
                if (~FR[3] & cur_cpu_state == CPU_STATE_INSTR_EXEC) PC <= {cur_instruction[15:8], cur_instruction[23:16]};
            end

            // JNE
            8'b00011001: begin
                if (~FR[3]& cur_cpu_state == CPU_STATE_INSTR_EXEC) PC <= ACC;
            end

            // JG $NUM
            8'b10001010: begin
                if (FR[3] & FR[2] & cur_cpu_state == CPU_STATE_INSTR_EXEC) PC <= {cur_instruction[15:8], cur_instruction[23:16]};
            end

            // JG
            8'b00011010: begin
                if (FR[3] & FR[2] & cur_cpu_state == CPU_STATE_INSTR_EXEC) PC <= ACC;
            end

            // JGE $NUM
            8'b10001011: begin
                if (FR[0] & cur_cpu_state == CPU_STATE_INSTR_EXEC) PC <= {cur_instruction[15:8], cur_instruction[23:16]};
            end

            // JGE
            8'b00011011: begin
                if (FR[0] & cur_cpu_state == CPU_STATE_INSTR_EXEC) PC <= ACC;
            end

            // JL $NUM
            8'b10001100: begin
                if ((FR[1] ^ FR[2]) & cur_cpu_state == CPU_STATE_INSTR_EXEC) PC <= {cur_instruction[15:8], cur_instruction[23:16]};
            end

            // JL
            8'b00011100: begin
                if ((FR[1] ^ FR[2]) & cur_cpu_state == CPU_STATE_INSTR_EXEC) PC <= ACC;
            end

            // JLE $NUM
            8'b10001101: begin
                if ((FR[0] | FR[3]) & cur_cpu_state == CPU_STATE_INSTR_EXEC) PC <= {cur_instruction[15:8], cur_instruction[23:16]};
            end

            // JLE
            8'b00011101: begin
                if ((FR[0] | FR[3]) & cur_cpu_state == CPU_STATE_INSTR_EXEC) PC <= ACC;
            end

            // IN $IMM
            8'b10001110: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_EXEC: begin
                        uart_read_req <= 1;
                    end

                    CPU_STATE_INSTR_OPERAND_FETCH: begin
                        ACC <= {8'b0, uart_data};
                    end

                    default: begin
                    end
                endcase
            end

            // OUT $IMM
            8'b10011000: begin
                case (cur_cpu_state)
                    CPU_STATE_INSTR_EXEC: begin
                        if (cur_instruction[23:8] == 0) begin
                            uart_write_req <= 1;
                            uart_wdata <= ACC[7:0];
                        end else GPIOS[cur_imm[5:0]] <= ACC[0];
                    end

                    default: begin
                    end
                endcase
            end

        endcase
    end

    end
end
end

endmodule