Have to manually change the file path for program file

[hadirkhan10]

Right now we have to manually provide the path of program file that is to be loaded in the instruction memory. Since we are working on multiple platforms (Linux, Mac) each user has to provide the location of the file manually. Let's make a functionality of dynamic path loading of program file, which finds the correct path of the program file itself from the user's environment.

[alishairkhan7385]

In which module (scala file) we have to add path of program file manually? cant find it. Also there is no Instruction_memory.scala.

[hadirkhan10]

Sorry @alishairkhan7385 the README is pretty behind in terms of updates. Currently, Buraq-mini standalone cannot work unless it is integrated inside an SoC. We have an SoC named "Shaheen" (https://github.com/merledu/Shaheen) where Buraq-mini is integrated.

[hadirkhan10]

You can find the line here where the path to the program file needs to be provided.

[alishairkhan7385]

I see, Well, I'm upto a comparison between single cycle and pipelined Architecture, pros and cons etc, BTW great work aka MERL. And thanks for the response, peace.

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On Mon, 26 Apr 2021, 4:12 PM Muhammad Hadir Khan, ***@***.***> wrote: You can find the line here <https://github.com/merledu/Shaheen/blob/master/src/test/scala/shaheen_soc/ShaheenTest.scala#L68> where the path to the program file needs to be provided. — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub <https://github.com/merledu/Buraq-mini/issues/17#issuecomment-826750107>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AKEZ5CQAJLES737WH3YTKKLTKVDBLANCNFSM4LXZGC4A> .

[alishairkhan7385]

Aoa, Hello sir hope you are doing well, I'm currently working on pipeline architecture of Risc v, what I want to ask is there any way to change the time period of clock in chisel3?

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On Mon, 26 Apr 2021, 4:20 PM Shair Khan, ***@***.***> wrote: I see, Well, I'm upto a comparison between single cycle and pipelined Architecture, pros and cons etc, BTW great work aka MERL. And thanks for the response, peace. On Mon, 26 Apr 2021, 4:12 PM Muhammad Hadir Khan, < ***@***.***> wrote: > You can find the line here > <https://github.com/merledu/Shaheen/blob/master/src/test/scala/shaheen_soc/ShaheenTest.scala#L68> > where the path to the program file needs to be provided. > > — > You are receiving this because you were mentioned. > Reply to this email directly, view it on GitHub > <https://github.com/merledu/Buraq-mini/issues/17#issuecomment-826750107>, > or unsubscribe > <https://github.com/notifications/unsubscribe-auth/AKEZ5CQAJLES737WH3YTKKLTKVDBLANCNFSM4LXZGC4A> > . >

[hadirkhan10]

Hi @alishairkhan7385 I am not aware of why you want to do that? You can change the frequency by providing the clock of a certain frequency range through a PLL. If you are talking about changing the the simulation time period then that I guess cannot be done with Scala based testbenches. You can emit verilog and write a testbench in verilog for that purpose. You can ask this question on the Chisel3 Gitter channel here: https://gitter.im/freechipsproject/chisel3

[alishairkhan7385]

Well thank you Sir, I really need chisel3 community to talk about stuff, I'm not around people's who take interest in architectures etc. Thank you

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On Sun, 6 Jun 2021, 4:19 PM Muhammad Hadir Khan, ***@***.***> wrote: Hi @alishairkhan7385 <https://github.com/alishairkhan7385> I am not aware of why you want to do that? You can change the frequency by providing the clock of a certain frequency range through a PLL. If you are talking about changing the the simulation time period then that I guess cannot be done with Scala based testbenches. You can emit verilog and write a testbench in verilog for that purpose. You can ask this question on the Chisel3 Gitter channel here: https://gitter.im/freechipsproject/chisel3 — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub <#17 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AKEZ5CXIDIO6EBHCIPLJGS3TRNKVRANCNFSM4LXZGC4A> .