From eb1a3934c41dcce3cf5bad0602842bb9fef23a02 Mon Sep 17 00:00:00 2001 From: Dustin Richmond Date: Thu, 11 Aug 2016 13:54:54 -0700 Subject: [PATCH] Fixing/updating makefiles for new xilinx clock test projects --- fpga/xilinx/vc709/Makefile | 2 +- fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/Makefile | 2 +- fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/Makefile | 2 +- fpga/xilinx/vc709/board.mk | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/fpga/xilinx/vc709/Makefile b/fpga/xilinx/vc709/Makefile index c1fc1b0..67d2d09 100644 --- a/fpga/xilinx/vc709/Makefile +++ b/fpga/xilinx/vc709/Makefile @@ -40,7 +40,7 @@ # Author: Dustin Richmond (@darichmond) #----------------------------------------------------------------------- BOARD:=vc709 -BOARD_PROJECTS:=VC709_Gen1x8If64 VC709_Gen2x8If128 VC709_Gen3x4If128 +BOARD_PROJECTS:=VC709_Gen1x8If64 VC709_Gen2x8If128 VC709_Gen3x4If128 VC709_Gen1x8If64_CLK VC709_Gen2x8If128_CLK BOARD_TYPE:=ultrascale VENDOR:=xilinx include ../vendor.mk diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/Makefile b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/Makefile index 795546b..6acd252 100644 --- a/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/Makefile +++ b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/Makefile @@ -59,4 +59,4 @@ endif include $(RIFFA_HDL_PATH)/riffa.mk include $(BOARD_PATH)/board.mk -PROJECT_IP+=ip/PCIeGen1x8If64.xci +PROJECT_IP+=ip/PCIeGen1x8If64.xci ip/clk_250MIn_2/clk_250MIn_2.xci ip/clk_250MIn_1/clk_250MIn_1.xci diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/Makefile b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/Makefile index d760cff..d44aa05 100644 --- a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/Makefile +++ b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/Makefile @@ -59,4 +59,4 @@ endif include $(RIFFA_HDL_PATH)/riffa.mk include $(BOARD_PATH)/board.mk -PROJECT_IP+=ip/PCIeGen2x8If128.xci +PROJECT_IP+=ip/PCIeGen2x8If128.xci ip/clk_250MIn_2/clk_250MIn_2.xci ip/clk_250MIn_1/clk_250MIn_1.xci diff --git a/fpga/xilinx/vc709/board.mk b/fpga/xilinx/vc709/board.mk index 0d6b7bf..cb78bd0 100644 --- a/fpga/xilinx/vc709/board.mk +++ b/fpga/xilinx/vc709/board.mk @@ -78,7 +78,7 @@ all $(TYPE) $(VENDOR) $(BOARD):$(PROJECT) clean: echo "reset_run impl_1; reset_run synth_1;" | vivado -mode tcl prj/$(PROJECT).xpr rm -rf *.log *.jou *~ .Xil - rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~ + rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~ ip/*.txt ip/clk_250MIn_2 ip/clk_250MIn_1 rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~ clobber: