diff --git a/fpga/xilinx/NetFPGA/board.mk b/fpga/xilinx/NetFPGA/board.mk
index be164fb..989c98b 100644
--- a/fpga/xilinx/NetFPGA/board.mk
+++ b/fpga/xilinx/NetFPGA/board.mk
@@ -64,6 +64,7 @@ prj/$(PROJECT).runs/impl_1: $($(PROJECT)_FILES)
 
 all $(TYPE) $(VENDOR) $(BOARD):$(PROJECT)
 clean:
+	echo "reset_run impl_1; reset_run synth_1;" | vivado -mode tcl prj/$(PROJECT).xpr
 	rm -rf *.log *.jou *~ .Xil 
 	rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~
 	rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~
diff --git a/fpga/xilinx/ac701/board.mk b/fpga/xilinx/ac701/board.mk
index be164fb..989c98b 100644
--- a/fpga/xilinx/ac701/board.mk
+++ b/fpga/xilinx/ac701/board.mk
@@ -64,6 +64,7 @@ prj/$(PROJECT).runs/impl_1: $($(PROJECT)_FILES)
 
 all $(TYPE) $(VENDOR) $(BOARD):$(PROJECT)
 clean:
+	echo "reset_run impl_1; reset_run synth_1;" | vivado -mode tcl prj/$(PROJECT).xpr
 	rm -rf *.log *.jou *~ .Xil 
 	rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~
 	rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~
diff --git a/fpga/xilinx/adm7V3/board.mk b/fpga/xilinx/adm7V3/board.mk
index be164fb..989c98b 100644
--- a/fpga/xilinx/adm7V3/board.mk
+++ b/fpga/xilinx/adm7V3/board.mk
@@ -64,6 +64,7 @@ prj/$(PROJECT).runs/impl_1: $($(PROJECT)_FILES)
 
 all $(TYPE) $(VENDOR) $(BOARD):$(PROJECT)
 clean:
+	echo "reset_run impl_1; reset_run synth_1;" | vivado -mode tcl prj/$(PROJECT).xpr
 	rm -rf *.log *.jou *~ .Xil 
 	rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~
 	rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~
diff --git a/fpga/xilinx/kc705/board.mk b/fpga/xilinx/kc705/board.mk
index be164fb..989c98b 100644
--- a/fpga/xilinx/kc705/board.mk
+++ b/fpga/xilinx/kc705/board.mk
@@ -64,6 +64,7 @@ prj/$(PROJECT).runs/impl_1: $($(PROJECT)_FILES)
 
 all $(TYPE) $(VENDOR) $(BOARD):$(PROJECT)
 clean:
+	echo "reset_run impl_1; reset_run synth_1;" | vivado -mode tcl prj/$(PROJECT).xpr
 	rm -rf *.log *.jou *~ .Xil 
 	rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~
 	rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~
diff --git a/fpga/xilinx/kcu105/board.mk b/fpga/xilinx/kcu105/board.mk
index be164fb..989c98b 100644
--- a/fpga/xilinx/kcu105/board.mk
+++ b/fpga/xilinx/kcu105/board.mk
@@ -64,6 +64,7 @@ prj/$(PROJECT).runs/impl_1: $($(PROJECT)_FILES)
 
 all $(TYPE) $(VENDOR) $(BOARD):$(PROJECT)
 clean:
+	echo "reset_run impl_1; reset_run synth_1;" | vivado -mode tcl prj/$(PROJECT).xpr
 	rm -rf *.log *.jou *~ .Xil 
 	rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~
 	rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~
diff --git a/fpga/xilinx/vc707/board.mk b/fpga/xilinx/vc707/board.mk
index be164fb..989c98b 100644
--- a/fpga/xilinx/vc707/board.mk
+++ b/fpga/xilinx/vc707/board.mk
@@ -64,6 +64,7 @@ prj/$(PROJECT).runs/impl_1: $($(PROJECT)_FILES)
 
 all $(TYPE) $(VENDOR) $(BOARD):$(PROJECT)
 clean:
+	echo "reset_run impl_1; reset_run synth_1;" | vivado -mode tcl prj/$(PROJECT).xpr
 	rm -rf *.log *.jou *~ .Xil 
 	rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~
 	rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~
diff --git a/fpga/xilinx/vc709/board.mk b/fpga/xilinx/vc709/board.mk
index d8f92b6..989c98b 100644
--- a/fpga/xilinx/vc709/board.mk
+++ b/fpga/xilinx/vc709/board.mk
@@ -64,9 +64,10 @@ prj/$(PROJECT).runs/impl_1: $($(PROJECT)_FILES)
 
 all $(TYPE) $(VENDOR) $(BOARD):$(PROJECT)
 clean:
+	echo "reset_run impl_1; reset_run synth_1;" | vivado -mode tcl prj/$(PROJECT).xpr
 	rm -rf *.log *.jou *~ .Xil 
 	rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~
 	rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~
 
 clobber:
-	rm -rf bit/*.sof
+	rm -rf bit/*.bit
diff --git a/fpga/xilinx/vcu108/board.mk b/fpga/xilinx/vcu108/board.mk
index be164fb..989c98b 100644
--- a/fpga/xilinx/vcu108/board.mk
+++ b/fpga/xilinx/vcu108/board.mk
@@ -64,6 +64,7 @@ prj/$(PROJECT).runs/impl_1: $($(PROJECT)_FILES)
 
 all $(TYPE) $(VENDOR) $(BOARD):$(PROJECT)
 clean:
+	echo "reset_run impl_1; reset_run synth_1;" | vivado -mode tcl prj/$(PROJECT).xpr
 	rm -rf *.log *.jou *~ .Xil 
 	rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~
 	rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~
diff --git a/fpga/xilinx/zc706/board.mk b/fpga/xilinx/zc706/board.mk
index be164fb..989c98b 100644
--- a/fpga/xilinx/zc706/board.mk
+++ b/fpga/xilinx/zc706/board.mk
@@ -64,6 +64,7 @@ prj/$(PROJECT).runs/impl_1: $($(PROJECT)_FILES)
 
 all $(TYPE) $(VENDOR) $(BOARD):$(PROJECT)
 clean:
+	echo "reset_run impl_1; reset_run synth_1;" | vivado -mode tcl prj/$(PROJECT).xpr
 	rm -rf *.log *.jou *~ .Xil 
 	rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~
 	rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~