From a115b94971453c5a11a04578da3cd5faae0be683 Mon Sep 17 00:00:00 2001 From: Emmanuel Blot Date: Mon, 3 Jun 2024 19:07:53 +0200 Subject: [PATCH 01/14] [ot] hw/riscv: ibex_common: ignore MemMapEntry.size value Signed-off-by: Emmanuel Blot --- hw/riscv/ibex_common.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/riscv/ibex_common.c b/hw/riscv/ibex_common.c index 8eb8e5c7d689..49e8c90b31c1 100644 --- a/hw/riscv/ibex_common.c +++ b/hw/riscv/ibex_common.c @@ -636,8 +636,6 @@ void ibex_unimp_configure(DeviceState *dev, const IbexDeviceDef *def, qdev_prop_set_string(dev, "name", def->name); } g_assert(def->memmap != NULL); - g_assert(def->memmap->size != 0); - qdev_prop_set_uint64(dev, "size", def->memmap->size); } uint32_t ibex_load_kernel(CPUState *cpu) From 7bb4beca067e1878a3817e3ad2e6b459ac5a4832 Mon Sep 17 00:00:00 2001 From: Emmanuel Blot Date: Mon, 3 Jun 2024 19:06:15 +0200 Subject: [PATCH 02/14] [ot] hw/riscv: ibexdemo: do not define MemMapEntry.size This .size field is not used, but error prone since changing its value does nothing. Signed-off-by: Emmanuel Blot --- hw/riscv/ibexdemo.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/hw/riscv/ibexdemo.c b/hw/riscv/ibexdemo.c index eba20dafe468..b3d2caa089d4 100644 --- a/hw/riscv/ibexdemo.c +++ b/hw/riscv/ibexdemo.c @@ -63,9 +63,6 @@ static void ibexdemo_soc_uart_configure( /* Constants */ /* ------------------------------------------------------------------------ */ -static const MemMapEntry ibexdemo_ram = { .base = 0x00100000u, - .size = 0x10000u }; - static const uint32_t IBEXDEMO_BOOT[] = { /* Exception vectors */ 0x0840006fu, 0x0800006fu, 0x07c0006fu, 0x0780006fu, 0x0740006fu, @@ -111,7 +108,9 @@ enum IbexDemoBoardDevice { */ #define IBEXDEMO_TAP_IDCODE IBEX_JTAG_IDCODE(256, 1, 0) -#define PULP_DM_BASE 0x00010000u +#define PULP_DM_BASE 0x00010000u +#define SRAM_MAIN_BASE 0x100000u +#define SRAM_MAIN_SIZE 0x10000u #define IBEXDEMO_DM_CONNECTION(_dst_dev_, _num_) \ { \ @@ -186,7 +185,7 @@ static const IbexDeviceDef ibexdemo_soc_devices[] = { [IBEXDEMO_SOC_DEV_RV_DM] = { .type = TYPE_PULP_RV_DM, .memmap = MEMMAPENTRIES( - { .base = 0x00000000u, .size = 0x1000u } + { .base = 0x00000000u } ), .gpio = IBEXGPIOCONNDEFS( IBEXDEMO_DM_CONNECTION(IBEXDEMO_SOC_DEV_DM, 0), @@ -198,21 +197,21 @@ static const IbexDeviceDef ibexdemo_soc_devices[] = { [IBEXDEMO_SOC_DEV_SIM_CTRL] = { .type = TYPE_IBEXDEMO_SIMCTRL, .memmap = MEMMAPENTRIES( - { .base = 0x00020000u, .size = 0x0400u } + { .base = 0x00020000u } ), }, [IBEXDEMO_SOC_DEV_GPIO] = { .type = TYPE_IBEXDEMO_GPIO, .cfg = &ibexdemo_soc_gpio_configure, .memmap = MEMMAPENTRIES( - { .base = 0x80000000u, .size = 0x1000u } + { .base = 0x80000000u } ), }, [IBEXDEMO_SOC_DEV_UART] = { .type = TYPE_IBEXDEMO_UART, .cfg = &ibexdemo_soc_uart_configure, .memmap = MEMMAPENTRIES( - { .base = 0x80001000u, .size = 0x1000u } + { .base = 0x80001000u } ), .gpio = IBEXGPIOCONNDEFS( IBEX_GPIO_SYSBUS_IRQ(0, IBEXDEMO_SOC_DEV_HART, 16) @@ -221,7 +220,7 @@ static const IbexDeviceDef ibexdemo_soc_devices[] = { [IBEXDEMO_SOC_DEV_TIMER] = { .type = TYPE_IBEXDEMO_TIMER, .memmap = MEMMAPENTRIES( - { .base = 0x80002000u, .size = 0x1000u } + { .base = 0x80002000u } ), .gpio = IBEXGPIOCONNDEFS( IBEX_GPIO_SYSBUS_IRQ(0, IBEXDEMO_SOC_DEV_HART, IRQ_M_TIMER) @@ -232,13 +231,13 @@ static const IbexDeviceDef ibexdemo_soc_devices[] = { .name = "ibexdemo-pwm", .cfg = &ibex_unimp_configure, .memmap = MEMMAPENTRIES( - { .base = 0x80003000u, .size = 0x1000u } + { .base = 0x80003000u } ), }, [IBEXDEMO_SOC_DEV_SPI] = { .type = TYPE_IBEXDEMO_SPI, .memmap = MEMMAPENTRIES( - { .base = 0x80004000u, .size = 0x0400u } + { .base = 0x80004000u } ), }, /* clang-format on */ @@ -359,7 +358,7 @@ static void ibexdemo_soc_realize(DeviceState *dev, Error **errp) MachineState *ms = MACHINE(qdev_get_machine()); MemoryRegion *sys_mem = get_system_memory(); - memory_region_add_subregion(sys_mem, ibexdemo_ram.base, ms->ram); + memory_region_add_subregion(sys_mem, SRAM_MAIN_BASE, ms->ram); ibex_link_devices(s->devices, ibexdemo_soc_devices, ARRAY_SIZE(ibexdemo_soc_devices)); @@ -507,7 +506,7 @@ static void ibexdemo_machine_class_init(ObjectClass *oc, void *data) mc->max_cpus = 1u; mc->default_cpu_type = ibexdemo_soc_devices[IBEXDEMO_SOC_DEV_HART].type; mc->default_ram_id = "ibexdemo.ram"; - mc->default_ram_size = ibexdemo_ram.size; + mc->default_ram_size = SRAM_MAIN_SIZE; } static const TypeInfo ibexdemo_machine_type_info = { From c80fdaa840644d339c6660bc8a649e1e1a48c64b Mon Sep 17 00:00:00 2001 From: Emmanuel Blot Date: Mon, 3 Jun 2024 16:01:30 +0200 Subject: [PATCH 03/14] [ot] hw/riscv: ot_darjeeling, ot_earlgrey: do not define MemMapEntry.size This .size field is not used, but error prone since changing its value does nothing. Signed-off-by: Emmanuel Blot --- hw/riscv/ot_darjeeling.c | 94 ++++++++++++++------------- hw/riscv/ot_earlgrey.c | 136 +++++++++++++++++++++++---------------- 2 files changed, 130 insertions(+), 100 deletions(-) diff --git a/hw/riscv/ot_darjeeling.c b/hw/riscv/ot_darjeeling.c index a2374b413557..d17b4129b554 100644 --- a/hw/riscv/ot_darjeeling.c +++ b/hw/riscv/ot_darjeeling.c @@ -405,7 +405,7 @@ static const uint32_t ot_dj_pmp_addrs[] = { #define OT_DJ_SOC_DEV_MBX(_ix_, _addr_, _asname_, _irq_, _alert_) \ .type = TYPE_OT_MBX, .instance = (_ix_), \ - .memmap = MEMMAPENTRIES({ (_addr_), OT_MBX_HOST_APERTURE }), \ + .memmap = MEMMAPENTRIES({ .base = (_addr_) }), \ .gpio = IBEXGPIOCONNDEFS(OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, (_irq_)), \ OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, (_irq_) + 1u), \ OT_DJ_SOC_GPIO_SYSBUS_IRQ(2, PLIC, (_irq_) + 2u), \ @@ -417,8 +417,7 @@ static const uint32_t ot_dj_pmp_addrs[] = { #define OT_DJ_SOC_DEV_MBX_DUAL(_ix_, _addr_, _asname_, _irq_, _alert_, \ _xaddr_) \ .type = TYPE_OT_MBX, .instance = (_ix_), \ - .memmap = MEMMAPENTRIES({ (_addr_), OT_MBX_HOST_APERTURE }, \ - { (_xaddr_), OT_MBX_SYS_APERTURE }), \ + .memmap = MEMMAPENTRIES({ .base = (_addr_) }, { .base = (_xaddr_) }), \ .gpio = IBEXGPIOCONNDEFS(OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, (_irq_)), \ OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, (_irq_) + 1u), \ OT_DJ_SOC_GPIO_SYSBUS_IRQ(2, PLIC, (_irq_) + 2u), \ @@ -569,7 +568,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_AES] = { .type = TYPE_OT_AES, .memmap = MEMMAPENTRIES( - { 0x21100000u, 0x1000u } + { .base = 0x21100000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_CLKMGR_HINT(OT_CLKMGR_HINT_AES), @@ -586,7 +585,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_HMAC] = { .type = TYPE_OT_HMAC, .memmap = MEMMAPENTRIES( - { 0x21110000u, 0x1000u } + { .base = 0x21110000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 115), @@ -599,7 +598,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_KMAC] = { .type = TYPE_OT_KMAC, .memmap = MEMMAPENTRIES( - { 0x21120000u, 0x1000u } + { .base = 0x21120000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 118), @@ -619,7 +618,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_OTBN] = { .type = TYPE_OT_OTBN, .memmap = MEMMAPENTRIES( - { 0x21130000u, 0x10000u } + { .base = 0x21130000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 121), @@ -641,13 +640,16 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { .name = "ot-keymgr_dpe", .cfg = &ibex_unimp_configure, .memmap = MEMMAPENTRIES( - { 0x21140000u, 0x100u } + { .base = 0x21140000u } + ), + .prop = IBEXDEVICEPROPDEFS( + IBEX_DEV_UINT_PROP("size", 0x100u) ), }, [OT_DJ_SOC_DEV_CSRNG] = { .type = TYPE_OT_CSRNG, .memmap = MEMMAPENTRIES( - { 0x21150000u, 0x80u } + { .base = 0x21150000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 123), @@ -666,7 +668,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { .type = TYPE_OT_EDN, .instance = 0, .memmap = MEMMAPENTRIES( - { 0x21170000u, 0x80u } + { .base = 0x21170000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 127), @@ -685,7 +687,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { .type = TYPE_OT_EDN, .instance = 1, .memmap = MEMMAPENTRIES( - { 0x21180000u, 0x80u } + { .base = 0x21180000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 129), @@ -704,8 +706,8 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { .type = TYPE_OT_SRAM_CTRL, .instance = 0, .memmap = MEMMAPENTRIES( - { 0x211c0000u, 0x20u }, - { 0x10000000, 0x10000u } + { .base = 0x211c0000u }, + { 0x10000000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_ALERT(0, 70) @@ -722,8 +724,8 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { .type = TYPE_OT_SRAM_CTRL, .instance = 1, .memmap = MEMMAPENTRIES( - { 0x211d0000u, 0x20u }, - { 0x11000000u, 0x1000u } + { .base = 0x211d0000u }, + { 0x11000000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_ALERT(0, 71) @@ -740,8 +742,8 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { .type = TYPE_OT_ROM_CTRL, .instance = 0, .memmap = MEMMAPENTRIES( - { 0x211e0000u, 0x80u }, - { 0x00008000u, 0x8000u } + { .base = 0x211e0000u }, + { 0x00008000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_ALERT(0, 72), @@ -763,8 +765,8 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { .type = TYPE_OT_ROM_CTRL, .instance = 1, .memmap = MEMMAPENTRIES( - { 0x211e1000u, 0x80u }, - { 0x00020000u, 0x10000u } + { .base = 0x211e1000u }, + { 0x00020000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_ALERT(0, 73), @@ -785,7 +787,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_IBEX_WRAPPER] = { .type = TYPE_OT_IBEX_WRAPPER_DJ, .memmap = MEMMAPENTRIES( - { 0x211f0000u, 0x800u } + { .base = 0x211f0000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_ALERT(0, 95), @@ -803,8 +805,8 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_RV_DM] = { .type = TYPE_PULP_RV_DM, .memmap = MEMMAPENTRIES( - { PULP_DM_BASE, 0x1000u }, - { 0x21200000u, 0x1000u } + { .base = PULP_DM_BASE }, + { .base = 0x21200000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_DM_CONNECTION(OT_DJ_SOC_DEV_DM, 0), @@ -842,7 +844,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_DMA] = { .type = TYPE_OT_DMA, .memmap = MEMMAPENTRIES( - { 0x22010000u, 0x200u } + { .base = 0x22010000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 131), @@ -859,7 +861,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_SOC_PROXY] = { .type = TYPE_OT_SOC_PROXY, .memmap = MEMMAPENTRIES( - { 0x22030000u, 0x10u } + { .base = 0x22030000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 83), @@ -937,7 +939,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_PLIC] = { .type = TYPE_SIFIVE_PLIC, .memmap = MEMMAPENTRIES( - { 0x28000000u, 0x4000000u } + { .base = 0x28000000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO(1, HART, IRQ_M_EXT) @@ -960,7 +962,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_PLIC_EXT] = { .type = TYPE_OT_PLIC_EXT, .memmap = MEMMAPENTRIES( - { 0x2c000000u, 0x10u } + { .base = 0x2c000000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO(0, HART, IRQ_M_SOFT), @@ -970,7 +972,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_GPIO] = { .type = TYPE_OT_GPIO_DJ, .memmap = MEMMAPENTRIES( - { 0x30000000u, 0x80u } + { .base = 0x30000000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 9), @@ -1013,7 +1015,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { .cfg = &ot_dj_soc_uart_configure, .instance = 0, .memmap = MEMMAPENTRIES( - { 0x30010000u, 0x40u } + { .base = 0x30010000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 1), @@ -1033,7 +1035,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_SENSOR_CTRL] = { .type = TYPE_OT_SENSOR, .memmap = MEMMAPENTRIES( - { 0x30020000u, 0x40u } + { .base = 0x30020000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 81), @@ -1044,7 +1046,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { .type = TYPE_OT_I2C_DJ, .instance = 0, .memmap = MEMMAPENTRIES( - { 0x30080000u, 0x80u } + { .base = 0x30080000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 53), @@ -1071,7 +1073,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_TIMER] = { .type = TYPE_OT_TIMER, .memmap = MEMMAPENTRIES( - { 0x30100000u, 0x200u } + { .base = 0x30100000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO(0, HART, IRQ_M_TIMER), @@ -1086,8 +1088,8 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { .type = TYPE_OT_OTP_DJ, .cfg = &ot_dj_soc_otp_ctrl_configure, .memmap = MEMMAPENTRIES( - { 0x30130000u, 0x8000u }, - { 0x30138000u, 0x80u } + { .base = 0x30130000u }, + { .base = 0x30138000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 69), @@ -1109,8 +1111,8 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_LC_CTRL] = { .type = TYPE_OT_LC_CTRL, .memmap = MEMMAPENTRIES( - { 0x30140000u, 0x100u }, - { DEBUG_MEMORY(OT_DJ_DEBUG_LC_CTRL_ADDR), OT_DJ_DEBUG_LC_CTRL_SIZE } + { .base = 0x30140000u }, + { .base = DEBUG_MEMORY(OT_DJ_DEBUG_LC_CTRL_ADDR) } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_ALERT(0, 10), @@ -1153,7 +1155,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_ALERT_HANDLER] = { .type = TYPE_OT_ALERT, .memmap = MEMMAPENTRIES( - { 0x30150000u, 0x800u } + { .base = 0x30150000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 71), @@ -1180,7 +1182,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { .type = TYPE_OT_SPI_HOST, .instance = 0, .memmap = MEMMAPENTRIES( - { 0x30300000u, 0x40u } + { .base = 0x30300000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 76), @@ -1194,7 +1196,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_SPI_DEVICE] = { .type = TYPE_OT_SPI_DEVICE, .memmap = MEMMAPENTRIES( - { 0x30310000u, 0x2000u } + { .base = 0x30310000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 41), @@ -1215,7 +1217,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_PWRMGR] = { .type = TYPE_OT_PWRMGR, .memmap = MEMMAPENTRIES( - { 0x30400000u, 0x80u } + { .base = 0x30400000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 78), @@ -1238,7 +1240,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_RSTMGR] = { .type = TYPE_OT_RSTMGR, .memmap = MEMMAPENTRIES( - { 0x30410000u, 0x80u } + { .base = 0x30410000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_ALERT(0, 15), @@ -1250,7 +1252,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_CLKMGR] = { .type = TYPE_OT_CLKMGR, .memmap = MEMMAPENTRIES( - { 0x30420000u, 0x80u } + { .base = 0x30420000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_ALERT(0, 17), @@ -1260,7 +1262,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_PINMUX] = { .type = TYPE_OT_PINMUX_DJ, .memmap = MEMMAPENTRIES( - { 0x30460000u, 0x1000u } + { .base = 0x30460000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO0, GPIO, 0), @@ -1301,7 +1303,7 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_AON_TIMER] = { .type = TYPE_OT_AON_TIMER, .memmap = MEMMAPENTRIES( - { 0x30470000u, 0x40u } + { .base = 0x30470000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 79), @@ -1319,15 +1321,15 @@ static const IbexDeviceDef ot_dj_soc_devices[] = { [OT_DJ_SOC_DEV_AST] = { .type = TYPE_OT_AST_DJ, .memmap = MEMMAPENTRIES( - { 0x30480000u, 0x400u } + { .base = 0x30480000u } ), }, [OT_DJ_SOC_DEV_SRAM_RET] = { .type = TYPE_OT_SRAM_CTRL, .instance = 2, .memmap = MEMMAPENTRIES( - { 0x30500000u, 0x20u }, - { 0x30600000u, 0x1000u } + { .base = 0x30500000u }, + { .base = 0x30600000u } ), .gpio = IBEXGPIOCONNDEFS( OT_DJ_SOC_GPIO_ALERT(0, 52) diff --git a/hw/riscv/ot_earlgrey.c b/hw/riscv/ot_earlgrey.c index db6f3bfa8045..6e97a795c59e 100644 --- a/hw/riscv/ot_earlgrey.c +++ b/hw/riscv/ot_earlgrey.c @@ -250,7 +250,8 @@ static const uint32_t ot_eg_pmp_addrs[] = { /* Earlgrey M2.5.2-RC0 RV DM */ #define EG_TAP_IDCODE IBEX_JTAG_IDCODE(0, 1, 0) -#define PULP_DM_BASE 0x00010000u +#define PULP_DM_BASE 0x00010000u +#define SRAM_MAIN_SIZE 0x20000u /* * MMIO/interrupt mapping as per: @@ -322,7 +323,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .cfg = &ot_eg_soc_uart_configure, .instance = 0, .memmap = MEMMAPENTRIES( - { 0x40000000u, 0x40u } + { .base = 0x40000000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 1), @@ -343,7 +344,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .cfg = &ot_eg_soc_uart_configure, .instance = 1, .memmap = MEMMAPENTRIES( - { 0x40010000u, 0x40u } + { .base = 0x40010000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 9), @@ -364,7 +365,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .cfg = &ot_eg_soc_uart_configure, .instance = 2, .memmap = MEMMAPENTRIES( - { 0x40020000u, 0x40u } + { .base = 0x40020000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 17), @@ -385,7 +386,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .cfg = &ot_eg_soc_uart_configure, .instance = 3, .memmap = MEMMAPENTRIES( - { 0x40030000u, 0x1000u } + { .base = 0x40030000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 25), @@ -404,7 +405,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { [OT_EG_SOC_DEV_GPIO] = { .type = TYPE_OT_GPIO_EG, .memmap = MEMMAPENTRIES( - { 0x40040000u, 0x40u } + { .base = 0x40040000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 33), @@ -444,7 +445,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { [OT_EG_SOC_DEV_SPI_DEVICE] = { .type = TYPE_OT_SPI_DEVICE, .memmap = MEMMAPENTRIES( - { 0x40050000u, 0x2000u } + { .base = 0x40050000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 65), @@ -470,8 +471,11 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .cfg = &ibex_unimp_configure, .instance = 0, .memmap = MEMMAPENTRIES( - { 0x40080000u, 0x80u } + { .base = 0x40080000u } ), + .prop = IBEXDEVICEPROPDEFS( + IBEX_DEV_UINT_PROP("size", 0x80u) + ) }, [OT_EG_SOC_DEV_I2C1] = { .type = TYPE_UNIMPLEMENTED_DEVICE, @@ -479,8 +483,11 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .cfg = &ibex_unimp_configure, .instance = 1, .memmap = MEMMAPENTRIES( - { 0x40090000u, 0x80u } + { .base = 0x40090000u } ), + .prop = IBEXDEVICEPROPDEFS( + IBEX_DEV_UINT_PROP("size", 0x80u) + ) }, [OT_EG_SOC_DEV_I2C2] = { .type = TYPE_UNIMPLEMENTED_DEVICE, @@ -488,21 +495,27 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .cfg = &ibex_unimp_configure, .instance = 2, .memmap = MEMMAPENTRIES( - { 0x400a0000u, 0x80u } + { .base = 0x400a0000u } ), + .prop = IBEXDEVICEPROPDEFS( + IBEX_DEV_UINT_PROP("size", 0x80u) + ) }, [OT_EG_SOC_DEV_PATTGEN] = { .type = TYPE_UNIMPLEMENTED_DEVICE, .name = "ot-pattgen", .cfg = &ibex_unimp_configure, .memmap = MEMMAPENTRIES( - { 0x400e0000u, 0x40u } + { .base = 0x400e0000u } ), + .prop = IBEXDEVICEPROPDEFS( + IBEX_DEV_UINT_PROP("size", 0x80u) + ) }, [OT_EG_SOC_DEV_TIMER] = { .type = TYPE_OT_TIMER, .memmap = MEMMAPENTRIES( - { 0x40100000u, 0x200u } + { .base = 0x40100000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO(0, HART, IRQ_M_TIMER), @@ -516,8 +529,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .type = TYPE_OT_OTP_EG, .cfg = &ot_eg_soc_otp_ctrl_configure, .memmap = MEMMAPENTRIES( - { 0x40130000u, 0x2000u }, - { 0x40132000u, 0x1000u } + { .base = 0x40130000u }, + { .base = 0x40132000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 125), @@ -533,7 +546,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { [OT_EG_SOC_DEV_LC_CTRL] = { .type = TYPE_OT_LC_CTRL, .memmap = MEMMAPENTRIES( - { 0x40140000u, 0x100u } + { .base = 0x40140000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_RSP(OT_PWRMGR_LC, PWRMGR) @@ -556,7 +569,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { [OT_EG_SOC_DEV_ALERT_HANDLER] = { .type = TYPE_OT_ALERT, .memmap = MEMMAPENTRIES( - { 0x40150000u, 0x800u } + { .base = 0x40150000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 127), @@ -579,7 +592,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .type = TYPE_OT_SPI_HOST, .instance = 0, .memmap = MEMMAPENTRIES( - { 0x40300000u, 0x40u } + { .base = 0x40300000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 131), @@ -593,7 +606,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .type = TYPE_OT_SPI_HOST, .instance = 1, .memmap = MEMMAPENTRIES( - { 0x40310000u, 0x40u } + { .base = 0x40310000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 133), @@ -608,13 +621,16 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .name = "ot-usbdev", .cfg = &ibex_unimp_configure, .memmap = MEMMAPENTRIES( - { 0x40320000u, 0x1000u } + { .base = 0x40320000u } ), + .prop = IBEXDEVICEPROPDEFS( + IBEX_DEV_UINT_PROP("size", 0x1000u) + ) }, [OT_EG_SOC_DEV_PWRMGR] = { .type = TYPE_OT_PWRMGR, .memmap = MEMMAPENTRIES( - { 0x40400000u, 0x80u } + { .base = 0x40400000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 152), @@ -637,7 +653,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { [OT_EG_SOC_DEV_RSTMGR] = { .type = TYPE_OT_RSTMGR, .memmap = MEMMAPENTRIES( - { 0x40410000u, 0x80u } + { .base = 0x40410000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_SIGNAL(OT_RSTMGR_SW_RST, 0, PWRMGR, \ @@ -647,7 +663,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { [OT_EG_SOC_DEV_CLKMGR] = { .type = TYPE_OT_CLKMGR, .memmap = MEMMAPENTRIES( - { 0x40420000u, 0x80u } + { .base = 0x40420000u } ), }, [OT_EG_SOC_DEV_SYSRST_CTRL] = { @@ -655,35 +671,44 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .name = "ot-sysrst_ctrl", .cfg = &ibex_unimp_configure, .memmap = MEMMAPENTRIES( - { 0x40430000u, 0x100u } + { .base = 0x40430000u } ), + .prop = IBEXDEVICEPROPDEFS( + IBEX_DEV_UINT_PROP("size", 0x100u) + ) }, [OT_EG_SOC_DEV_ADC_CTRL] = { .type = TYPE_UNIMPLEMENTED_DEVICE, .name = "ot-adc_ctrl", .cfg = &ibex_unimp_configure, .memmap = MEMMAPENTRIES( - { 0x40440000u, 0x80u } + { .base = 0x40440000u } ), + .prop = IBEXDEVICEPROPDEFS( + IBEX_DEV_UINT_PROP("size", 0x80u) + ) }, [OT_EG_SOC_DEV_PWM] = { .type = TYPE_UNIMPLEMENTED_DEVICE, .name = "ot-pwm", .cfg = &ibex_unimp_configure, .memmap = MEMMAPENTRIES( - { 0x40450000u, 0x80u } + { .base = 0x40450000u } ), + .prop = IBEXDEVICEPROPDEFS( + IBEX_DEV_UINT_PROP("size", 0x80u) + ) }, [OT_EG_SOC_DEV_PINMUX] = { .type = TYPE_OT_PINMUX_EG, .memmap = MEMMAPENTRIES( - { 0x40460000u, 0x1000u } + { .base = 0x40460000u } ), }, [OT_EG_SOC_DEV_AON_TIMER] = { .type = TYPE_OT_AON_TIMER, .memmap = MEMMAPENTRIES( - { 0x40470000u, 0x40u } + { .base = 0x40470000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 155), @@ -700,21 +725,21 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { [OT_EG_SOC_DEV_AST] = { .type = TYPE_OT_AST_EG, .memmap = MEMMAPENTRIES( - { 0x40480000u, 0x400u } + { .base = 0x40480000u } ), }, [OT_EG_SOC_DEV_SENSOR_CTRL] = { .type = TYPE_OT_SENSOR, .memmap = MEMMAPENTRIES( - { 0x40490000u, 0x40u } + { .base = 0x40490000u } ), }, [OT_EG_SOC_DEV_SRAM_RET_CTRL] = { .type = TYPE_OT_SRAM_CTRL, .instance = 0, .memmap = MEMMAPENTRIES( - { 0x40500000u, 0x20u }, - { 0x40600000u, 0x1000u } + { .base = 0x40500000u }, + { .base = 0x40600000u } ), .link = IBEXDEVICELINKDEFS( OT_EG_SOC_DEVLINK("otp_ctrl", OTP_CTRL) @@ -728,9 +753,9 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .type = TYPE_OT_FLASH, .cfg = &ot_eg_soc_flash_ctrl_configure, .memmap = MEMMAPENTRIES( - { 0x41000000u, 0x1000u }, - { 0x41008000u, 0x1000u }, - { 0x20000000u, 0x100000u } + { .base = 0x41000000u }, + { .base = 0x41008000u }, + { .base = 0x20000000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 159), @@ -744,7 +769,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { [OT_EG_SOC_DEV_AES] = { .type = TYPE_OT_AES, .memmap = MEMMAPENTRIES( - { 0x41100000u, 0x100u } + { .base = 0x41100000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_CLKMGR_HINT(OT_CLKMGR_HINT_AES) @@ -759,7 +784,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { [OT_EG_SOC_DEV_HMAC] = { .type = TYPE_OT_HMAC, .memmap = MEMMAPENTRIES( - { 0x41110000u, 0x1000u } + { .base = 0x41110000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 165), @@ -771,7 +796,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { [OT_EG_SOC_DEV_KMAC] = { .type = TYPE_OT_KMAC, .memmap = MEMMAPENTRIES( - { 0x41120000u, 0x1000u } + { .base = 0x41120000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 168), @@ -789,7 +814,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { [OT_EG_SOC_DEV_OTBN] = { .type = TYPE_OT_OTBN, .memmap = MEMMAPENTRIES( - { 0x41130000u, 0x10000u } + { .base = 0x41130000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 171), @@ -809,13 +834,16 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .name = "ot-keymgr", .cfg = &ibex_unimp_configure, .memmap = MEMMAPENTRIES( - { 0x41140000u, 0x100u } + { .base = 0x41140000u } ), + .prop = IBEXDEVICEPROPDEFS( + IBEX_DEV_UINT_PROP("size", 0x100u) + ) }, [OT_EG_SOC_DEV_CSRNG] = { .type = TYPE_OT_CSRNG, .memmap = MEMMAPENTRIES( - { 0x41150000u, 0x80u } + { .base = 0x41150000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 173), @@ -831,7 +859,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { [OT_EG_SOC_DEV_ENTROPY_SRC] = { .type = TYPE_OT_ENTROPY_SRC, .memmap = MEMMAPENTRIES( - { 0x41160000u, 0x100u } + { .base = 0x41160000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 177), @@ -848,7 +876,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .type = TYPE_OT_EDN, .instance = 0, .memmap = MEMMAPENTRIES( - { 0x41170000u, 0x80u } + { .base = 0x41170000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 181), @@ -865,7 +893,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .type = TYPE_OT_EDN, .instance = 1, .memmap = MEMMAPENTRIES( - { 0x41180000u, 0x80u } + { .base = 0x41180000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 183), @@ -882,14 +910,14 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .type = TYPE_OT_SRAM_CTRL, .instance = 1, .memmap = MEMMAPENTRIES( - { 0x411c0000u, 0x20u }, - { 0x10000000u, 0x20000u } + { .base = 0x411c0000u }, + { .base = 0x10000000u } ), .link = IBEXDEVICELINKDEFS( OT_EG_SOC_DEVLINK("otp_ctrl", OTP_CTRL) ), .prop = IBEXDEVICEPROPDEFS( - IBEX_DEV_UINT_PROP("size", 0x20000u), + IBEX_DEV_UINT_PROP("size", SRAM_MAIN_SIZE), IBEX_DEV_STRING_PROP("ot_id", "ram") ), }, @@ -897,8 +925,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { .type = TYPE_OT_ROM_CTRL, .name = "ot-rom_ctrl", .memmap = MEMMAPENTRIES( - { 0x411e0000u, 0x80u }, - { 0x00008000u, 0x8000u } + { .base = 0x411e0000u }, + { .base = 0x00008000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_SIGNAL(OT_ROM_CTRL_GOOD, 0, PWRMGR, \ @@ -918,7 +946,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { [OT_EG_SOC_DEV_IBEX_WRAPPER] = { .type = TYPE_OT_IBEX_WRAPPER_EG, .memmap = MEMMAPENTRIES( - { 0x411f0000u, 0x100u } + { .base = 0x411f0000u } ), .link = IBEXDEVICELINKDEFS( OT_EG_SOC_DEVLINK("edn", EDN0) @@ -930,8 +958,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { [OT_EG_SOC_DEV_RV_DM] = { .type = TYPE_PULP_RV_DM, .memmap = MEMMAPENTRIES( - { PULP_DM_BASE, 0x1000u }, - { 0x41200000u, 0x1000u } + { .base = PULP_DM_BASE }, + { .base = 0x41200000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_DM_CONNECTION(OT_EG_SOC_DEV_DM, 0), @@ -943,7 +971,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { [OT_EG_SOC_DEV_PLIC] = { .type = TYPE_SIFIVE_PLIC, .memmap = MEMMAPENTRIES( - { 0x48000000u, 0x4000000u } + { .base = 0x48000000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO(1, HART, IRQ_M_EXT) @@ -966,7 +994,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = { [OT_EG_SOC_DEV_PLIC_EXT] = { .type = TYPE_OT_PLIC_EXT, .memmap = MEMMAPENTRIES( - { 0x2c000000u, 0x10u } + { .base = 0x2c000000u } ), .gpio = IBEXGPIOCONNDEFS( OT_EG_SOC_GPIO(0, HART, IRQ_M_SOFT) @@ -1341,7 +1369,7 @@ static void ot_eg_machine_class_init(ObjectClass *oc, void *data) const IbexDeviceDef *sram = &ot_eg_soc_devices[OT_EG_SOC_DEV_SRAM_MAIN_CTRL]; mc->default_ram_id = sram->type; - mc->default_ram_size = sram->memmap[1].size; + mc->default_ram_size = SRAM_MAIN_SIZE; } static const TypeInfo ot_eg_machine_type_info = { From cac2f74800ba22f6b59254ab2133bd525a12bcb0 Mon Sep 17 00:00:00 2001 From: Emmanuel Blot Date: Mon, 3 Jun 2024 19:07:08 +0200 Subject: [PATCH 04/14] [ot] hw/riscv: ibex_common: replace MemMapEntry with IbexMemMapEntry .size field is not required, and error prone Signed-off-by: Emmanuel Blot --- hw/riscv/ibex_common.c | 10 +++++----- include/hw/riscv/ibex_common.h | 18 ++++++++++++------ 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/hw/riscv/ibex_common.c b/hw/riscv/ibex_common.c index 49e8c90b31c1..490025353fa2 100644 --- a/hw/riscv/ibex_common.c +++ b/hw/riscv/ibex_common.c @@ -242,9 +242,9 @@ void ibex_map_devices_mask(DeviceState **devices, MemoryRegion **mrs, (SysBusDevice *)object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE); if (busdev) { - const MemMapEntry *memmap = def->memmap; + const IbexMemMapEntry *memmap = def->memmap; unsigned mem = 0; - while (memmap->size) { + while (!IBEX_MEMMAP_IS_LAST(memmap)) { unsigned region = IBEX_MEMMAP_GET_REGIDX(memmap->base); if (region_mask & (1u << region)) { MemoryRegion *mr = mrs[region]; @@ -278,10 +278,10 @@ void ibex_map_devices_ext_mask(DeviceState *dev, MemoryRegion **mrs, sdev = OBJECT_CHECK(SysBusDevice, child, TYPE_SYS_BUS_DEVICE); g_free(name); - const MemMapEntry *memmap = def->memmap; + const IbexMemMapEntry *memmap = def->memmap; unsigned mem = 0; - while (memmap->size) { - if (!SKIP_MEMMAP(memmap)) { + while (!IBEX_MEMMAP_IS_LAST(memmap)) { + if (!IBEX_MEMMAP_IGNORE(memmap)) { unsigned region = IBEX_MEMMAP_GET_REGIDX(memmap->base); if (region_mask & (1u << region)) { MemoryRegion *mr = mrs[region]; diff --git a/include/hw/riscv/ibex_common.h b/include/hw/riscv/ibex_common.h index aa7e81da98ab..1e441f9139ce 100644 --- a/include/hw/riscv/ibex_common.h +++ b/include/hw/riscv/ibex_common.h @@ -155,6 +155,10 @@ typedef struct { }; } IbexDevicePropDef; +typedef struct IbexMemMapEntry { + hwaddr base; +} IbexMemMapEntry; + /* Device definition */ struct IbexDeviceDef { /** Registered type of the device */ @@ -166,7 +170,7 @@ struct IbexDeviceDef { /** Optional configuration function */ ibex_dev_cfg_fn cfg; /** Array of memory map */ - const MemMapEntry *memmap; + const IbexMemMapEntry *memmap; /** Array of GPIO connections */ const IbexGpioConnDef *gpio; /** Array of linked devices */ @@ -184,7 +188,7 @@ typedef struct { /** Instance number, default to 0 */ int instance; /** Array of memory map */ - const MemMapEntry *memmap; + const IbexMemMapEntry *memmap; } IbexDeviceMapDef; /* @@ -226,18 +230,20 @@ typedef struct { (((_par_) << IBEX_DEVLINK_RMT_SHIFT) | ((_ix_) & IBEX_DEVLINK_IDX_MASK)) /* MemMapEntry that should be ignored (i.e. skipped, not mapped) */ -#define MEMMAPSKIP { .base = HWADDR_MAX, .size = HWADDR_MAX } -#define SKIP_MEMMAP(_mmap_) ((_mmap_)->size == HWADDR_MAX) +#define IBEX_MEMMAP_LAST ((hwaddr)0ull) +#define IBEX_MEMMAP_SKIP { .base = HWADDR_MAX } +#define IBEX_MEMMAP_IS_LAST(_mmap_) ((_mmap_)->base == IBEX_MEMMAP_LAST) +#define IBEX_MEMMAP_IGNORE(_mmap_) ((_mmap_)->base == HWADDR_MAX) /** * Create memory map entries, each arg is MemMapEntry definition */ #define MEMMAPENTRIES(...) \ - (const MemMapEntry[]) \ + (const IbexMemMapEntry[]) \ { \ __VA_ARGS__, \ { \ - .size = 0u \ + .base = IBEX_MEMMAP_LAST \ } \ } From 37e20b908006f0ecba90bed8561a5608bea63863 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Tue, 4 Jun 2024 09:04:11 +0200 Subject: [PATCH 05/14] [ot] hw/opentitan: ot_aon_timer: fix BITE trigger MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes an issue where BITE would not trigger while BARK is active. Signed-off-by: Loïc Lefort --- hw/opentitan/ot_aon_timer.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/opentitan/ot_aon_timer.c b/hw/opentitan/ot_aon_timer.c index c4ba28e82c75..5fe93f12815f 100644 --- a/hw/opentitan/ot_aon_timer.c +++ b/hw/opentitan/ot_aon_timer.c @@ -256,21 +256,26 @@ static void ot_aon_timer_rearm_wdog(OtAonTimerState *s, bool reset_origin) uint32_t count = ot_aon_timer_get_wdog_count(s, now); uint32_t bark_threshold = s->regs[R_WDOG_BARK_THOLD]; uint32_t bite_threshold = s->regs[R_WDOG_BITE_THOLD]; - uint32_t threshold = 0; + uint32_t threshold; + bool pending; if (count >= bark_threshold) { s->regs[R_INTR_STATE] |= INTR_WDOG_TIMER_BARK_MASK; + threshold = UINT32_MAX; + pending = false; } else { threshold = bark_threshold; + pending = true; } if (count >= bite_threshold) { s->wdog_bite = true; - } else if (bite_threshold < threshold) { - threshold = bite_threshold; + } else { + threshold = MIN(threshold, bite_threshold); + pending = true; } - if (count >= threshold) { + if (!pending) { timer_del(s->wdog_timer); } else { int64_t delta = ot_aon_timer_ticks_to_ns(s, 0u, threshold - count); From 27b81b98744857e5057e0c3de1050edab772f035 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Tue, 4 Jun 2024 09:58:07 +0200 Subject: [PATCH 06/14] [ot] hw/opentitan: ot_pwrmgr: fix reported RESET_STATUS value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit RESET_STATUS should only report HW reset channels. Signed-off-by: Loïc Lefort --- hw/opentitan/ot_pwrmgr.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/hw/opentitan/ot_pwrmgr.c b/hw/opentitan/ot_pwrmgr.c index b07ed72b43d8..af301eda60a0 100644 --- a/hw/opentitan/ot_pwrmgr.c +++ b/hw/opentitan/ot_pwrmgr.c @@ -82,8 +82,6 @@ REG32(WAKE_STATUS, 0x24u) REG32(RESET_EN_REGWEN, 0x28u) FIELD(RESET_EN_REGWEN, EN, 0u, 1u) REG32(RESET_EN, 0x2cu) - SHARED_FIELD(RESET_CHANNEL_0, 0u, 1u) - SHARED_FIELD(RESET_CHANNEL_1, 1u, 1u) REG32(RESET_STATUS, 0x30u) REG32(ESCALATE_RESET_STATUS, 0x34u) FIELD(ESCALATE_RESET_STATUS, VAL, 0u, 1u) @@ -106,7 +104,6 @@ REG32(FAULT_STATUS, 0x40u) #define WAKEUP_MASK \ (WAKEUP_CHANNEL_0_MASK | WAKEUP_CHANNEL_1_MASK | WAKEUP_CHANNEL_2_MASK | \ WAKEUP_CHANNEL_3_MASK | WAKEUP_CHANNEL_4_MASK | WAKEUP_CHANNEL_5_MASK) -#define RESET_MASK (RESET_CHANNEL_0_MASK | RESET_CHANNEL_1_MASK) #define WAKE_INFO_MASK \ (R_WAKE_INFO_REASONS_MASK | R_WAKE_INFO_FALL_THROUGH_MASK | \ R_WAKE_INFO_ABORT_MASK) @@ -114,7 +111,6 @@ REG32(FAULT_STATUS, 0x40u) #define CDC_SYNC_PULSE_DURATION_NS 100000u /* 100us */ #define PWRMGR_WAKEUP_MAX 6u -#define PWRMGR_RESET_MAX 3u /* special exit error code to report escalation panic */ #define EXIT_ESCALATION_PANIC 39 @@ -123,8 +119,7 @@ REG32(FAULT_STATUS, 0x40u) #define NUM_SW_RST_REQ 1u #define HW_RESET_WIDTH \ (PARAM_NUM_RST_REQS + PARAM_NUM_INT_RST_REQS + PARAM_NUM_DEBUG_RST_REQS) -#define TOTAL_RESET_WIDTH (HW_RESET_WIDTH + NUM_SW_RST_REQ) -#define RESET_SW_REQ_IDX (TOTAL_RESET_WIDTH - 1u) +#define RESET_SW_REQ_IDX (HW_RESET_WIDTH) #define R32_OFF(_r_) ((_r_) / sizeof(uint32_t)) @@ -336,16 +331,14 @@ static const OtPwrMgrConfig PWRMGR_CONFIG[OT_PWMGR_VERSION_COUNT] = { }, }; -static int PWRMGR_RESET_DISPATCH[OT_PWMGR_VERSION_COUNT][PWRMGR_RESET_MAX] = { +static int PWRMGR_RESET_DISPATCH[OT_PWMGR_VERSION_COUNT][PARAM_NUM_RST_REQS] = { [OT_PWMGR_VERSION_EG] = { [0] = OT_RSTMGR_RESET_SYSCTRL, [1] = OT_RSTMGR_RESET_AON_TIMER, - [2] = -1 }, [OT_PWMGR_VERSION_DJ] = { [0] = OT_RSTMGR_RESET_AON_TIMER, [1] = OT_RSTMGR_RESET_SOC_PROXY, - [2] = -1, }, }; @@ -369,11 +362,10 @@ PWRMGR_WAKEUP_NAMES[OT_PWMGR_VERSION_COUNT][PWRMGR_WAKEUP_MAX] = { }, }; -static const char *PWRMGR_RST_NAMES[OT_PWMGR_VERSION_COUNT][PWRMGR_RESET_MAX] = { +static const char *PWRMGR_RST_NAMES[OT_PWMGR_VERSION_COUNT][PARAM_NUM_RST_REQS] = { [OT_PWMGR_VERSION_EG] = { [0] = "SYSRST", [1] = "AON_TIMER", - [2] = "SENSOR", }, [OT_PWMGR_VERSION_DJ] = { [0] = "AON_TIMER", @@ -533,7 +525,7 @@ static void ot_pwrmgr_sw_rst_req(void *opaque, int irq, int level) unsigned src = (unsigned)irq; g_assert(src < NUM_SW_RST_REQ); - uint32_t rstbit = 1u << (NUM_SW_RST_REQ + src); + uint32_t rstbit = 1u << (RESET_SW_REQ_IDX + src); if (level) { trace_ot_pwrmgr_rst_req(s->ot_id, "SW", src); @@ -754,7 +746,6 @@ static uint64_t ot_pwrmgr_regs_read(void *opaque, hwaddr addr, unsigned size) case R_WAKE_STATUS: case R_RESET_EN_REGWEN: case R_RESET_EN: - case R_RESET_STATUS: case R_ESCALATE_RESET_STATUS: case R_WAKE_INFO_CAPTURE_DIS: case R_WAKE_INFO: @@ -768,6 +759,9 @@ static uint64_t ot_pwrmgr_regs_read(void *opaque, hwaddr addr, unsigned size) __func__, s->ot_id, addr, REG_NAME(reg)); val32 = 0; break; + case R_RESET_STATUS: + val32 = s->regs[reg] & PWRMGR_CONFIG[s->version].reset_mask; + break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, @@ -848,7 +842,7 @@ static void ot_pwrmgr_regs_write(void *opaque, hwaddr addr, uint64_t val64, break; case R_RESET_EN: if (s->regs[R_RESET_EN_REGWEN] & R_RESET_EN_REGWEN_EN_MASK) { - val32 &= RESET_MASK; + val32 &= PWRMGR_CONFIG[s->version].reset_mask; s->regs[reg] = val32; } else { qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: %s protected w/ REGWEN\n", @@ -906,6 +900,12 @@ static void ot_pwrmgr_reset_enter(Object *obj, ResetType type) g_assert(s->version < OT_PWMGR_VERSION_COUNT); + /* sanity checks for platform reset count and mask */ + g_assert(PWRMGR_CONFIG[s->version].reset_count <= PARAM_NUM_RST_REQS); + g_assert(ctpop32(PWRMGR_CONFIG[s->version].reset_mask + 1u) == 1); + g_assert(PWRMGR_CONFIG[s->version].reset_mask < + (1u << PWRMGR_CONFIG[s->version].reset_count)); + if (!s->ot_id) { s->ot_id = g_strdup(object_get_canonical_path_component(OBJECT(s)->parent)); @@ -997,7 +997,7 @@ static void ot_pwrmgr_init(Object *obj) qdev_init_gpio_in_named(DEVICE(obj), &ot_pwrmgr_wkup, OT_PWRMGR_WKUP, PWRMGR_WAKEUP_MAX); qdev_init_gpio_in_named(DEVICE(obj), &ot_pwrmgr_rst_req, OT_PWRMGR_RST, - PWRMGR_RESET_MAX); + PARAM_NUM_RST_REQS); qdev_init_gpio_in_named(DEVICE(obj), &ot_pwrmgr_sw_rst_req, OT_PWRMGR_SW_RST, NUM_SW_RST_REQ); qdev_init_gpio_in_named(DEVICE(obj), &ot_pwrmgr_pwr_lc_rsp, From f3fd1478356ec46d3f0ba86d8bdac3a529bc43f4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Tue, 4 Jun 2024 11:57:03 +0200 Subject: [PATCH 07/14] [ot] .gitlab-ci.d: update baremetal tests MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Loïc Lefort --- .gitlab-ci.d/opentitan/qemu-ot.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.d/opentitan/qemu-ot.yml b/.gitlab-ci.d/opentitan/qemu-ot.yml index 1950cf41c23e..553081af3243 100644 --- a/.gitlab-ci.d/opentitan/qemu-ot.yml +++ b/.gitlab-ci.d/opentitan/qemu-ot.yml @@ -1,5 +1,5 @@ variables: - BAREMETAL_REF: "240531-1" + BAREMETAL_REF: "240604-2" QEMU_BUILD_OPTS: "" include: From bd6a4b9e3ccfb14edc24c4c4d72cb193e7bc2319 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Tue, 4 Jun 2024 15:33:47 +0200 Subject: [PATCH 08/14] [ot] hw/riscv: ibexdemo: add missing size property to UNIMP PWM device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Loïc Lefort --- hw/riscv/ibexdemo.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/riscv/ibexdemo.c b/hw/riscv/ibexdemo.c index b3d2caa089d4..69371844af72 100644 --- a/hw/riscv/ibexdemo.c +++ b/hw/riscv/ibexdemo.c @@ -112,6 +112,9 @@ enum IbexDemoBoardDevice { #define SRAM_MAIN_BASE 0x100000u #define SRAM_MAIN_SIZE 0x10000u +#define NUM_PWM_MODULES 12u +#define PWM_SIZE (NUM_PWM_MODULES * 8u) + #define IBEXDEMO_DM_CONNECTION(_dst_dev_, _num_) \ { \ .out = { \ @@ -233,6 +236,9 @@ static const IbexDeviceDef ibexdemo_soc_devices[] = { .memmap = MEMMAPENTRIES( { .base = 0x80003000u } ), + .prop = IBEXDEVICEPROPDEFS( + IBEX_DEV_UINT_PROP("size", PWM_SIZE) + ), }, [IBEXDEMO_SOC_DEV_SPI] = { .type = TYPE_IBEXDEMO_SPI, From 33e4ce4401f3a15bd54ed89c9c483a603ecceabf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Tue, 4 Jun 2024 16:43:04 +0200 Subject: [PATCH 09/14] [ot] scripts/opentitan: swexit: make SoC type mandatory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In preparation for adding ibexdemo support, make SoC type mandatory. Address can still be overridden if provided on command line. Signed-off-by: Loïc Lefort --- scripts/opentitan/swexit.py | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/scripts/opentitan/swexit.py b/scripts/opentitan/swexit.py index efbd236120b4..1022f3a64208 100755 --- a/scripts/opentitan/swexit.py +++ b/scripts/opentitan/swexit.py @@ -33,11 +33,10 @@ def main(): try: desc = modules[__name__].__doc__.split('.', 1)[0].strip() argparser = ArgumentParser(description=f'{desc}') - grp = argparser.add_mutually_exclusive_group(required=True) - grp.add_argument('-a', '--address', type=to_int, - help='Ibex wrapper base address') - grp.add_argument('-t', '--opentitan', choices=list(BASE_ADDRESS), - help='Ibex wrapper base address') + argparser.add_argument('-a', '--address', type=to_int, + help='Base address for swexit device (default: depends on SoC)') + argparser.add_argument('-t', '--soc', choices=list(BASE_ADDRESS), + help='SoC type', required=True) argparser.add_argument('-o', '--output', type=FileType('wb'), help='output file, default to stdout') argparser.add_argument('-d', '--debug', action='store_true', @@ -45,7 +44,7 @@ def main(): args = argparser.parse_args() debug = args.debug - addr = BASE_ADDRESS[args.opentitan] if args.opentitan else args.address + addr = args.address if args.address else BASE_ADDRESS[args.soc] addr &= ~LUI_MASK lui = addr | 0x537 bincode = spack(' Date: Tue, 4 Jun 2024 16:44:20 +0200 Subject: [PATCH 10/14] [ot] scripts/opentitan: swexit: add support for ibexdemo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Loïc Lefort --- scripts/opentitan/swexit.py | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/scripts/opentitan/swexit.py b/scripts/opentitan/swexit.py index 1022f3a64208..8d12e0e0e16d 100755 --- a/scripts/opentitan/swexit.py +++ b/scripts/opentitan/swexit.py @@ -19,6 +19,7 @@ BASE_ADDRESS = { 'earlgrey': 0x411f0000, 'darjeeling': 0x211f0000, + 'ibexdemo': 0x20000, } LUI_MASK = (1 << 12) - 1 @@ -28,6 +29,26 @@ def to_int(value: str) -> int: return int(value.strip(), value.startswith('0x') and 16 or 10) +def opentitan_code(addr: int) -> bytes: + addr &= ~LUI_MASK + lui = addr | 0x537 + return spack(' bytes: + addr &= ~LUI_MASK + lui = addr | 0x537 + return spack(' Date: Tue, 4 Jun 2024 16:45:01 +0200 Subject: [PATCH 11/14] [ot] hw/ibexdemo: ibexdemo_simctrl: use QEMU shutdown API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Loïc Lefort --- hw/ibexdemo/ibexdemo_simctrl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/ibexdemo/ibexdemo_simctrl.c b/hw/ibexdemo/ibexdemo_simctrl.c index f8acdd743bcb..f88c0230cfb5 100644 --- a/hw/ibexdemo/ibexdemo_simctrl.c +++ b/hw/ibexdemo/ibexdemo_simctrl.c @@ -31,6 +31,7 @@ #include "hw/qdev-properties.h" #include "hw/registerfields.h" #include "hw/sysbus.h" +#include "sysemu/runstate.h" #include "trace.h" /* clang-format off */ @@ -74,7 +75,8 @@ static void ibexdemo_simctrl_write(void *opaque, hwaddr addr, uint64_t val64, break; case R_CTRL: /* would be nicer to receive a value with the code for exiting... */ - exit(100); + qemu_system_shutdown_request_with_code(SHUTDOWN_CAUSE_GUEST_SHUTDOWN, + 100); break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", From 1f8296b763115754b966067a53756ad02b1d4a2b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Tue, 4 Jun 2024 16:47:35 +0200 Subject: [PATCH 12/14] [ot] .gitlab-ci.d: add ibexdemo smoketest MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Loïc Lefort --- .gitlab-ci.d/opentitan/build.yml | 1 + .gitlab-ci.d/opentitan/ot-smoke.yml | 3 +++ 2 files changed, 4 insertions(+) diff --git a/.gitlab-ci.d/opentitan/build.yml b/.gitlab-ci.d/opentitan/build.yml index b5ebeaf4ce8a..8345fce6c992 100644 --- a/.gitlab-ci.d/opentitan/build.yml +++ b/.gitlab-ci.d/opentitan/build.yml @@ -26,6 +26,7 @@ build-clang: - strip qemu-system-riscv32 qemu-img - QEMU_DIR="$(cd .. && pwd -P)"; cat compile_commands.json | sed -E 's,'"$QEMU_DIR"',@QEMU_DIR@,g' > compile_commands.json.tpl + - ../scripts/opentitan/swexit.py -t ibexdemo -o exit_id.bin - ../scripts/opentitan/swexit.py -t earlgrey -o exit_eg.bin - ../scripts/opentitan/swexit.py -t darjeeling -o exit_dj.bin artifacts: diff --git a/.gitlab-ci.d/opentitan/ot-smoke.yml b/.gitlab-ci.d/opentitan/ot-smoke.yml index a597c5ef850b..27888416f422 100644 --- a/.gitlab-ci.d/opentitan/ot-smoke.yml +++ b/.gitlab-ci.d/opentitan/ot-smoke.yml @@ -4,8 +4,11 @@ smoke-tests-ot: stage: test needs: ["build-clang"] script: + - build/qemu-system-riscv32 -M help | grep ibexdemo - build/qemu-system-riscv32 -M help | grep ot-earlgrey - build/qemu-system-riscv32 -M help | grep ot-darjeeling + - timeout -s KILL 4 build/qemu-system-riscv32 -M ibexdemo -nographic + -device loader,addr=0x100080,file=build/exit_id.bin -d in_asm,int - timeout -s KILL 4 build/qemu-system-riscv32 -M ot-earlgrey,no_epmp_cfg=true -nographic -object ot-rom-img,id=rom,file=build/exit_eg.bin,digest=fake,addr=0x8080 -d in_asm,int - timeout -s KILL 4 build/qemu-system-riscv32 -M ot-darjeeling,no_epmp_cfg=true -nographic From 30b833a8bbe53165eb130135b45ae85bd832cbac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Tue, 4 Jun 2024 17:04:46 +0200 Subject: [PATCH 13/14] [ot] hw/ibexdemo: ibexdemo_simctrl: add possibility to provide exit code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Loïc Lefort --- hw/ibexdemo/ibexdemo_simctrl.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/ibexdemo/ibexdemo_simctrl.c b/hw/ibexdemo/ibexdemo_simctrl.c index f88c0230cfb5..788e8d63a7b5 100644 --- a/hw/ibexdemo/ibexdemo_simctrl.c +++ b/hw/ibexdemo/ibexdemo_simctrl.c @@ -74,9 +74,11 @@ static void ibexdemo_simctrl_write(void *opaque, hwaddr addr, uint64_t val64, putc((int)(uint8_t)val64, stderr); break; case R_CTRL: - /* would be nicer to receive a value with the code for exiting... */ - qemu_system_shutdown_request_with_code(SHUTDOWN_CAUSE_GUEST_SHUTDOWN, - 100); + if (val64 & 1u) { + /* as a QEMU extension, bits [7:1] are used as exit code */ + qemu_system_shutdown_request_with_code( + SHUTDOWN_CAUSE_GUEST_SHUTDOWN, (val64 >> 1u) & 0x7fu); + } break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", From d52f5966bb05597aeaaaef03d943e7dc935e751b Mon Sep 17 00:00:00 2001 From: Emmanuel Blot Date: Fri, 7 Jun 2024 11:08:43 +0200 Subject: [PATCH 14/14] [ot] .github: add ibexdemo smoketest Signed-off-by: Emmanuel Blot --- .github/workflows/build_test.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/.github/workflows/build_test.yaml b/.github/workflows/build_test.yaml index 8d8d9b96af50..1440739a9b7d 100644 --- a/.github/workflows/build_test.yaml +++ b/.github/workflows/build_test.yaml @@ -36,6 +36,7 @@ jobs: strip build-clang/qemu-system-riscv32 - name: Create minimal test binaries run: | + scripts/opentitan/swexit.py -t ibexdemo -o build-clang/exit_id.bin scripts/opentitan/swexit.py -t earlgrey -o build-clang/exit_eg.bin scripts/opentitan/swexit.py -t darjeeling -o build-clang/exit_dj.bin - name: Upload QEMU binary artifacts @@ -118,8 +119,13 @@ jobs: - name: Check machine availability run: | chmod +x ./qemu-system-riscv32 && + ./qemu-system-riscv32 -M help | grep ibexdemo && ./qemu-system-riscv32 -M help | grep ot-earlgrey && ./qemu-system-riscv32 -M help | grep ot-darjeeling + - name: Check IbexDemo VM execution + run: | + timeout -s KILL 4 ./qemu-system-riscv32 -M ibexdemo -nographic \ + -device loader,addr=0x100080,file=exit_id.bin -d in_asm,int - name: Check EarlGrey VM execution run: | timeout -s KILL 4 ./qemu-system-riscv32 -M ot-earlgrey,no_epmp_cfg=true -nographic \