diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 529effe369b3..d8a777a80bf3 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -31,6 +31,7 @@
 #include "migration/vmstate.h"
 #include "hw/irq.h"
 #include "sysemu/kvm.h"
+#include "trace.h"
 
 static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
 {
@@ -64,12 +65,20 @@ static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value)
 
 static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level)
 {
-    atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level);
+    uint32_t old;
+    old = atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -level);
+    if ((old >> (irq & 31)) ^ level) {
+        trace_sifive_plic_set_pending(irq, level);
+    }
 }
 
 static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level)
 {
-    atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level);
+    uint32_t old;
+    old = atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -level);
+    if ((old >> (irq & 31)) ^ level) {
+        trace_sifive_plic_set_claimed(irq, level);
+    }
 }
 
 static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid)
@@ -124,9 +133,11 @@ static void sifive_plic_update(SiFivePLICState *plic)
 
         switch (mode) {
         case PLICMode_M:
+            trace_sifive_plic_update(hartid, 'M', level);
             qemu_set_irq(plic->m_external_irqs[hartid - plic->hartid_base], level);
             break;
         case PLICMode_S:
+            trace_sifive_plic_update(hartid, 'S', level);
             qemu_set_irq(plic->s_external_irqs[hartid - plic->hartid_base], level);
             break;
         default:
@@ -197,9 +208,11 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
              * out the access to unsupported priority bits.
              */
             plic->source_priority[irq] = value % (plic->num_priorities + 1);
+            trace_sifive_plic_set_priority(irq, plic->source_priority[irq]);
             sifive_plic_update(plic);
         } else if (value <= plic->num_priorities) {
             plic->source_priority[irq] = value;
+            trace_sifive_plic_set_priority(irq, plic->source_priority[irq]);
             sifive_plic_update(plic);
         }
     } else if (addr_between(addr, plic->pending_base,
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 50cadfb996ed..8483b5cd9267 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -309,3 +309,10 @@ loongarch_msi_set_irq(int irq_num) "set msi irq %d"
 loongarch_extioi_setirq(int irq, int level) "set extirq irq %d level %d"
 loongarch_extioi_readw(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
 loongarch_extioi_writew(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
+
+# sifive_plic.c
+
+sifive_plic_set_claimed(int irq, bool level) "irq %d: %u"
+sifive_plic_set_priority(uint32_t irq, uint32_t prio) "irq %u: %u"
+sifive_plic_set_pending(int irq, bool level) "irq %d: %u"
+sifive_plic_update(uint32_t hartid, int mode, bool level) "hart %u %c: %u"