From adda5da21585f2353eec179714ac8045e5f68536 Mon Sep 17 00:00:00 2001 From: Pascal Nasahl Date: Mon, 25 Mar 2024 13:10:59 +0000 Subject: [PATCH] [fi] Add register file cmd handler This commit adds the command handlers for the following FI tests: - ibex.char.register_file_read - ibex.char.register_file The device code is located in lowRISC/opentitan#21359 Signed-off-by: Pascal Nasahl --- ...obal_fi.ibex.char.register_file.cw310.yaml | 39 +++++++++++++++++++ ...fi.ibex.char.register_file_read.cw310.yaml | 39 +++++++++++++++++++ target/communication/fi_ibex_commands.py | 18 +++++++++ 3 files changed, 96 insertions(+) create mode 100644 fault_injection/configs/pen.global_fi.ibex.char.register_file.cw310.yaml create mode 100644 fault_injection/configs/pen.global_fi.ibex.char.register_file_read.cw310.yaml diff --git a/fault_injection/configs/pen.global_fi.ibex.char.register_file.cw310.yaml b/fault_injection/configs/pen.global_fi.ibex.char.register_file.cw310.yaml new file mode 100644 index 00000000..c1e2dff3 --- /dev/null +++ b/fault_injection/configs/pen.global_fi.ibex.char.register_file.cw310.yaml @@ -0,0 +1,39 @@ +target: + target_type: cw310 + fpga_bitstream: "../objs/lowrisc_systems_chip_earlgrey_cw310_0.1.bit" + force_program_bitstream: False + fw_bin: "../objs/sca_ujson_fpga_cw310.bin" + output_len_bytes: 16 + target_clk_mult: 0.24 + target_freq: 24000000 + baudrate: 115200 + protocol: "ujson" + port: "/dev/ttyACM4" +fisetup: + fi_gear: "husky" + fi_type: "voltage_glitch" + parameter_generation: "random" + # Voltage glitch width in cycles. + glitch_width_min: 5 + glitch_width_max: 150 + glitch_width_step: 3 + # Range for trigger delay in cycles. + trigger_delay_min: 0 + trigger_delay_max: 500 + trigger_step: 10 + # Number of iterations for the parameter sweep. + num_iterations: 100 +fiproject: + # Project database type and memory threshold. + project_db: "ot_fi_project" + project_mem_threshold: 10000 + # Store FI plot. + show_plot: True + num_plots: 10 + plot_x_axis: "trigger_delay" + plot_x_axis_legend: "[cycles]" + plot_y_axis: "glitch_width" + plot_y_axis_legend: "[cycles]" +test: + which_test: "ibex_char_register_file" + expected_result: '{"result":0,"err_status":0}' diff --git a/fault_injection/configs/pen.global_fi.ibex.char.register_file_read.cw310.yaml b/fault_injection/configs/pen.global_fi.ibex.char.register_file_read.cw310.yaml new file mode 100644 index 00000000..b03bd43e --- /dev/null +++ b/fault_injection/configs/pen.global_fi.ibex.char.register_file_read.cw310.yaml @@ -0,0 +1,39 @@ +target: + target_type: cw310 + fpga_bitstream: "../objs/lowrisc_systems_chip_earlgrey_cw310_0.1.bit" + force_program_bitstream: False + fw_bin: "../objs/sca_ujson_fpga_cw310.bin" + output_len_bytes: 16 + target_clk_mult: 0.24 + target_freq: 24000000 + baudrate: 115200 + protocol: "ujson" + port: "/dev/ttyACM4" +fisetup: + fi_gear: "husky" + fi_type: "voltage_glitch" + parameter_generation: "random" + # Voltage glitch width in cycles. + glitch_width_min: 5 + glitch_width_max: 150 + glitch_width_step: 3 + # Range for trigger delay in cycles. + trigger_delay_min: 0 + trigger_delay_max: 500 + trigger_step: 10 + # Number of iterations for the parameter sweep. + num_iterations: 100 +fiproject: + # Project database type and memory threshold. + project_db: "ot_fi_project" + project_mem_threshold: 10000 + # Store FI plot. + show_plot: True + num_plots: 10 + plot_x_axis: "trigger_delay" + plot_x_axis_legend: "[cycles]" + plot_y_axis: "glitch_width" + plot_y_axis_legend: "[cycles]" +test: + which_test: "ibex_char_register_file_read" + expected_result: '{"result":0,"err_status":0}' diff --git a/target/communication/fi_ibex_commands.py b/target/communication/fi_ibex_commands.py index 28e5f6e3..000d665d 100644 --- a/target/communication/fi_ibex_commands.py +++ b/target/communication/fi_ibex_commands.py @@ -108,6 +108,24 @@ def ibex_char_conditional_branch(self) -> None: time.sleep(0.01) self.target.write(json.dumps("CharCondBranch").encode("ascii")) + def ibex_char_register_file(self) -> None: + """ Starts the ibex.char.register_file test. + """ + # IbexFi command. + self._ujson_ibex_fi_cmd() + # CharRegisterFile command. + time.sleep(0.01) + self.target.write(json.dumps("CharRegisterFile").encode("ascii")) + + def ibex_char_register_file_read(self) -> None: + """ Starts the ibex.char.register_file_read test. + """ + # IbexFi command. + self._ujson_ibex_fi_cmd() + # CharRegisterFileRead command. + time.sleep(0.01) + self.target.write(json.dumps("CharRegisterFileRead").encode("ascii")) + def init_trigger(self) -> None: """ Initialize the FI trigger on the chip.