diff --git a/fault_injection/configs/pen.global_fi.ibex.address_translation.cw310.yaml b/fault_injection/configs/pen.global_fi.ibex.address_translation.cw310.yaml
new file mode 100644
index 000000000..5f606ad56
--- /dev/null
+++ b/fault_injection/configs/pen.global_fi.ibex.address_translation.cw310.yaml
@@ -0,0 +1,39 @@
+target:
+  target_type: cw310
+  fpga_bitstream: "../objs/lowrisc_systems_chip_earlgrey_cw310_0.1.bit"
+  force_program_bitstream: False
+  fw_bin: "../objs/sca_ujson_fpga_cw310.bin"
+  output_len_bytes: 16
+  target_clk_mult: 0.24
+  target_freq: 24000000
+  baudrate: 115200
+  protocol: "ujson"
+  port: "/dev/ttyACM4"
+fisetup:
+  fi_gear: "husky"
+  fi_type: "voltage_glitch"
+  parameter_generation: "random"
+  # Voltage glitch width in cycles.
+  glitch_width_min: 5
+  glitch_width_max: 150
+  glitch_width_step: 3
+  # Range for trigger delay in cycles.
+  trigger_delay_min: 0
+  trigger_delay_max: 500
+  trigger_step: 10
+  # Number of iterations for the parameter sweep.
+  num_iterations: 100
+fiproject:
+  # Project database type and memory threshold.
+  project_db: "ot_fi_project"
+  project_mem_threshold: 10000
+  # Store FI plot.
+  show_plot: True
+  num_plots: 10
+  plot_x_axis: "trigger_delay"
+  plot_x_axis_legend: "[cycles]"
+  plot_y_axis: "glitch_width"
+  plot_y_axis_legend: "[cycles]"
+test:
+  which_test: "ibex_address_translation"
+  expected_result: '{"result":0,"err_status":0}'
diff --git a/fault_injection/configs/pen.global_fi.ibex.address_translation_config.cw310.yaml b/fault_injection/configs/pen.global_fi.ibex.address_translation_config.cw310.yaml
new file mode 100644
index 000000000..cb1df0a3d
--- /dev/null
+++ b/fault_injection/configs/pen.global_fi.ibex.address_translation_config.cw310.yaml
@@ -0,0 +1,39 @@
+target:
+  target_type: cw310
+  fpga_bitstream: "../objs/lowrisc_systems_chip_earlgrey_cw310_0.1.bit"
+  force_program_bitstream: False
+  fw_bin: "../objs/sca_ujson_fpga_cw310.bin"
+  output_len_bytes: 16
+  target_clk_mult: 0.24
+  target_freq: 24000000
+  baudrate: 115200
+  protocol: "ujson"
+  port: "/dev/ttyACM4"
+fisetup:
+  fi_gear: "husky"
+  fi_type: "voltage_glitch"
+  parameter_generation: "random"
+  # Voltage glitch width in cycles.
+  glitch_width_min: 5
+  glitch_width_max: 150
+  glitch_width_step: 3
+  # Range for trigger delay in cycles.
+  trigger_delay_min: 0
+  trigger_delay_max: 500
+  trigger_step: 10
+  # Number of iterations for the parameter sweep.
+  num_iterations: 100
+fiproject:
+  # Project database type and memory threshold.
+  project_db: "ot_fi_project"
+  project_mem_threshold: 10000
+  # Store FI plot.
+  show_plot: True
+  num_plots: 10
+  plot_x_axis: "trigger_delay"
+  plot_x_axis_legend: "[cycles]"
+  plot_y_axis: "glitch_width"
+  plot_y_axis_legend: "[cycles]"
+test:
+  which_test: "ibex_address_translation_config"
+  expected_result: '{"result":0,"err_status":0}'
diff --git a/fault_injection/configs/pen.global_fi.ibex.char.csr_read.cw310.yaml b/fault_injection/configs/pen.global_fi.ibex.char.csr_read.cw310.yaml
new file mode 100644
index 000000000..66b8c7856
--- /dev/null
+++ b/fault_injection/configs/pen.global_fi.ibex.char.csr_read.cw310.yaml
@@ -0,0 +1,39 @@
+target:
+  target_type: cw310
+  fpga_bitstream: "../objs/lowrisc_systems_chip_earlgrey_cw310_0.1.bit"
+  force_program_bitstream: False
+  fw_bin: "../objs/sca_ujson_fpga_cw310.bin"
+  output_len_bytes: 16
+  target_clk_mult: 0.24
+  target_freq: 24000000
+  baudrate: 115200
+  protocol: "ujson"
+  port: "/dev/ttyACM4"
+fisetup:
+  fi_gear: "husky"
+  fi_type: "voltage_glitch"
+  parameter_generation: "random"
+  # Voltage glitch width in cycles.
+  glitch_width_min: 5
+  glitch_width_max: 150
+  glitch_width_step: 3
+  # Range for trigger delay in cycles.
+  trigger_delay_min: 0
+  trigger_delay_max: 500
+  trigger_step: 10
+  # Number of iterations for the parameter sweep.
+  num_iterations: 100
+fiproject:
+  # Project database type and memory threshold.
+  project_db: "ot_fi_project"
+  project_mem_threshold: 10000
+  # Store FI plot.
+  show_plot: True
+  num_plots: 10
+  plot_x_axis: "trigger_delay"
+  plot_x_axis_legend: "[cycles]"
+  plot_y_axis: "glitch_width"
+  plot_y_axis_legend: "[cycles]"
+test:
+  which_test: "ibex_char_csr_read"
+  expected_result: '{"result":0,"err_status":0}'
diff --git a/fault_injection/configs/pen.global_fi.ibex.char.csr_write.cw310.yaml b/fault_injection/configs/pen.global_fi.ibex.char.csr_write.cw310.yaml
new file mode 100644
index 000000000..b7cb1abd1
--- /dev/null
+++ b/fault_injection/configs/pen.global_fi.ibex.char.csr_write.cw310.yaml
@@ -0,0 +1,39 @@
+target:
+  target_type: cw310
+  fpga_bitstream: "../objs/lowrisc_systems_chip_earlgrey_cw310_0.1.bit"
+  force_program_bitstream: False
+  fw_bin: "../objs/sca_ujson_fpga_cw310.bin"
+  output_len_bytes: 16
+  target_clk_mult: 0.24
+  target_freq: 24000000
+  baudrate: 115200
+  protocol: "ujson"
+  port: "/dev/ttyACM4"
+fisetup:
+  fi_gear: "husky"
+  fi_type: "voltage_glitch"
+  parameter_generation: "random"
+  # Voltage glitch width in cycles.
+  glitch_width_min: 5
+  glitch_width_max: 150
+  glitch_width_step: 3
+  # Range for trigger delay in cycles.
+  trigger_delay_min: 0
+  trigger_delay_max: 500
+  trigger_step: 10
+  # Number of iterations for the parameter sweep.
+  num_iterations: 100
+fiproject:
+  # Project database type and memory threshold.
+  project_db: "ot_fi_project"
+  project_mem_threshold: 10000
+  # Store FI plot.
+  show_plot: True
+  num_plots: 10
+  plot_x_axis: "trigger_delay"
+  plot_x_axis_legend: "[cycles]"
+  plot_y_axis: "glitch_width"
+  plot_y_axis_legend: "[cycles]"
+test:
+  which_test: "ibex_char_csr_write"
+  expected_result: '{"result":0,"err_status":0}'
diff --git a/objs/sca_ujson_fpga_cw310.bin b/objs/sca_ujson_fpga_cw310.bin
index 7fb91096d..670bd996b 100644
--- a/objs/sca_ujson_fpga_cw310.bin
+++ b/objs/sca_ujson_fpga_cw310.bin
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:b79fa7125b748b00bc231ecb563e266edf4213eb27ef2318b35315d5c32169b1
-size 304188
+oid sha256:7dfc74e72d83d90377ffc113455f6ac638a553a916f3d94a18e35c4f68b5b7c9
+size 314716
diff --git a/target/communication/fi_ibex_commands.py b/target/communication/fi_ibex_commands.py
index 28e5f6e30..d8a452eb5 100644
--- a/target/communication/fi_ibex_commands.py
+++ b/target/communication/fi_ibex_commands.py
@@ -132,6 +132,42 @@ def start_test(self, cfg: dict) -> None:
         test_function = getattr(self, cfg["test"]["which_test"])
         test_function()
 
+    def ibex_char_csr_write(self) -> None:
+        """ Starts the ibex.fi.char.csr_write test.
+        """
+        # IbexFi command.
+        self._ujson_ibex_fi_cmd()
+        # CharCsrWrite command.
+        time.sleep(0.01)
+        self.target.write(json.dumps("CharCsrWrite").encode("ascii"))
+
+    def ibex_char_csr_read(self) -> None:
+        """ Starts the ibex.fi.char.csr_read test.
+        """
+        # IbexFi command.
+        self._ujson_ibex_fi_cmd()
+        # CharCsrRead command.
+        time.sleep(0.01)
+        self.target.write(json.dumps("CharCsrRead").encode("ascii"))
+    
+    def ibex_address_translation_config(self) -> None:
+        """ Starts the ibex.fi.address_translation_config test.
+        """
+        # IbexFi command.
+        self._ujson_ibex_fi_cmd()
+        # AddressTranslationCfg command.
+        time.sleep(0.01)
+        self.target.write(json.dumps("AddressTranslationCfg").encode("ascii"))
+
+    def ibex_address_translation(self) -> None:
+        """ Starts the ibex.fi.address_translation test.
+        """
+        # IbexFi command.
+        self._ujson_ibex_fi_cmd()
+        # AddressTranslation command.
+        time.sleep(0.01)
+        self.target.write(json.dumps("AddressTranslation").encode("ascii"))
+
     def read_response(self, max_tries: Optional[int] = 1) -> str:
         """ Read response from Ibex FI framework.
         Args: