From f049f9679db7c1715b447407993e599fc7857ff7 Mon Sep 17 00:00:00 2001 From: Hugo McNally Date: Tue, 26 Nov 2024 11:53:05 +0000 Subject: [PATCH 01/24] [python] Enforce minimum python version on dependencies `uv pip compile` currently doesn't appear to adhere to the minimum python version set in `pyproject.toml` even when set with to `=3.8`, so the `--python-version` argument was used. Signed-off-by: Hugo McNally --- util/sh/scripts/gen-python-requirements.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/util/sh/scripts/gen-python-requirements.sh b/util/sh/scripts/gen-python-requirements.sh index 7ec432d0aced2..c5271a4ac358b 100755 --- a/util/sh/scripts/gen-python-requirements.sh +++ b/util/sh/scripts/gen-python-requirements.sh @@ -16,6 +16,7 @@ uv pip compile \ --generate-hashes \ --no-annotate \ --no-header \ + --python-version 3.8.2 \ "$PYTHON_REQS_IN_FILE" \ -o "$PYTHON_REQS_OUT_FILE" echo -e "\n$(cat "$PYTHON_REQS_OUT_FILE")" > "$PYTHON_REQS_OUT_FILE" From 65b091cd20585aad5c3d81cc5e13a684a3c0b03f Mon Sep 17 00:00:00 2001 From: Hugo McNally Date: Mon, 25 Nov 2024 17:26:32 +0000 Subject: [PATCH 02/24] [ralgen] Specified position ralgen files should be inserted. Co-authored-by: Alexander Williams Signed-off-by: Hugo McNally --- hw/ip/adc_ctrl/dv/env/adc_ctrl_env.core | 1 + hw/ip/aes/dv/env/aes_env.core | 1 + hw/ip/aon_timer/dv/env/aon_timer_env.core | 1 + hw/ip/csrng/dv/env/csrng_env.core | 1 + hw/ip/edn/dv/env/edn_env.core | 1 + hw/ip/entropy_src/dv/env/entropy_src_env.core | 1 + hw/ip/gpio/dv/env/gpio_env.core | 1 + hw/ip/hmac/dv/env/hmac_env.core | 1 + hw/ip/i2c/dv/env/i2c_env.core | 1 + hw/ip/keymgr/dv/env/keymgr_env.core | 1 + hw/ip/kmac/dv/env/kmac_env.core | 1 + hw/ip/lc_ctrl/dv/env/lc_ctrl_env.core | 1 + hw/ip/otbn/dv/uvm/env/otbn_env.core | 1 + hw/ip/otp_ctrl/dv/env/otp_ctrl_env.core | 1 + hw/ip/pattgen/dv/env/pattgen_env.core | 1 + hw/ip/pwm/dv/env/pwm_env.core | 1 + hw/ip/rom_ctrl/dv/env/rom_ctrl_env.core | 1 + hw/ip/rv_dm/dv/env/rv_dm_env.core | 1 + hw/ip/rv_timer/dv/env/rv_timer_env.core | 1 + hw/ip/spi_device/dv/env/spi_device_env.core | 1 + hw/ip/spi_host/dv/env/spi_host_env.core | 1 + hw/ip/sram_ctrl/dv/env/sram_ctrl_env.core | 1 + hw/ip/sysrst_ctrl/dv/env/sysrst_ctrl_env.core | 1 + hw/ip/uart/dv/env/uart_env.core | 1 + hw/ip/usbdev/dv/env/usbdev_env.core | 1 + hw/ip_templates/clkmgr/dv/env/clkmgr_env.core | 1 + hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env.core | 1 + hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core | 1 + hw/ip_templates/rstmgr/dv/env/rstmgr_env.core | 1 + hw/top_earlgrey/dv/env/chip_env.core | 1 + hw/top_earlgrey/ip_autogen/clkmgr/dv/env/clkmgr_env.core | 1 + hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env.core | 1 + hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core | 1 + hw/top_earlgrey/ip_autogen/rstmgr/dv/env/rstmgr_env.core | 1 + 34 files changed, 34 insertions(+) diff --git a/hw/ip/adc_ctrl/dv/env/adc_ctrl_env.core b/hw/ip/adc_ctrl/dv/env/adc_ctrl_env.core index d0ffea07751d0..42b9294cc2daf 100644 --- a/hw/ip/adc_ctrl/dv/env/adc_ctrl_env.core +++ b/hw/ip/adc_ctrl/dv/env/adc_ctrl_env.core @@ -40,6 +40,7 @@ generate: parameters: name: adc_ctrl ip_hjson: ../../data/adc_ctrl.hjson + position: prepend targets: default: diff --git a/hw/ip/aes/dv/env/aes_env.core b/hw/ip/aes/dv/env/aes_env.core index d3c9c2af8b85a..76a797d22392a 100644 --- a/hw/ip/aes/dv/env/aes_env.core +++ b/hw/ip/aes/dv/env/aes_env.core @@ -52,6 +52,7 @@ generate: parameters: name: aes ip_hjson: ../../data/aes.hjson + position: prepend targets: default: diff --git a/hw/ip/aon_timer/dv/env/aon_timer_env.core b/hw/ip/aon_timer/dv/env/aon_timer_env.core index 84b2fe4219cef..d3642c74a73b2 100644 --- a/hw/ip/aon_timer/dv/env/aon_timer_env.core +++ b/hw/ip/aon_timer/dv/env/aon_timer_env.core @@ -31,6 +31,7 @@ generate: parameters: name: aon_timer ip_hjson: ../../data/aon_timer.hjson + position: prepend targets: default: diff --git a/hw/ip/csrng/dv/env/csrng_env.core b/hw/ip/csrng/dv/env/csrng_env.core index 0cc2fa7045ee6..13a9ad4192919 100644 --- a/hw/ip/csrng/dv/env/csrng_env.core +++ b/hw/ip/csrng/dv/env/csrng_env.core @@ -43,6 +43,7 @@ generate: parameters: name: csrng ip_hjson: ../../data/csrng.hjson + position: prepend targets: default: diff --git a/hw/ip/edn/dv/env/edn_env.core b/hw/ip/edn/dv/env/edn_env.core index 633db36e2de9c..a82c69f77a12b 100644 --- a/hw/ip/edn/dv/env/edn_env.core +++ b/hw/ip/edn/dv/env/edn_env.core @@ -38,6 +38,7 @@ generate: parameters: name: edn ip_hjson: ../../data/edn.hjson + position: prepend targets: default: diff --git a/hw/ip/entropy_src/dv/env/entropy_src_env.core b/hw/ip/entropy_src/dv/env/entropy_src_env.core index 0cb2db904b05e..15504c85358b4 100644 --- a/hw/ip/entropy_src/dv/env/entropy_src_env.core +++ b/hw/ip/entropy_src/dv/env/entropy_src_env.core @@ -46,6 +46,7 @@ generate: parameters: name: entropy_src ip_hjson: ../../data/entropy_src.hjson + position: prepend targets: default: diff --git a/hw/ip/gpio/dv/env/gpio_env.core b/hw/ip/gpio/dv/env/gpio_env.core index da4d4389683e1..bfae129a8cee4 100644 --- a/hw/ip/gpio/dv/env/gpio_env.core +++ b/hw/ip/gpio/dv/env/gpio_env.core @@ -36,6 +36,7 @@ generate: parameters: name: gpio ip_hjson: ../../data/gpio.hjson + position: prepend targets: default: diff --git a/hw/ip/hmac/dv/env/hmac_env.core b/hw/ip/hmac/dv/env/hmac_env.core index 0c15ec668078d..7046d1e05fd60 100644 --- a/hw/ip/hmac/dv/env/hmac_env.core +++ b/hw/ip/hmac/dv/env/hmac_env.core @@ -43,6 +43,7 @@ generate: parameters: name: hmac ip_hjson: ../../data/hmac.hjson + position: prepend targets: default: diff --git a/hw/ip/i2c/dv/env/i2c_env.core b/hw/ip/i2c/dv/env/i2c_env.core index 8ecee38f1bef4..02ee982b7ae89 100644 --- a/hw/ip/i2c/dv/env/i2c_env.core +++ b/hw/ip/i2c/dv/env/i2c_env.core @@ -70,6 +70,7 @@ generate: parameters: name: i2c ip_hjson: ../../data/i2c.hjson + position: prepend targets: default: diff --git a/hw/ip/keymgr/dv/env/keymgr_env.core b/hw/ip/keymgr/dv/env/keymgr_env.core index 879368c22ea38..605e44ab2f5a4 100644 --- a/hw/ip/keymgr/dv/env/keymgr_env.core +++ b/hw/ip/keymgr/dv/env/keymgr_env.core @@ -45,6 +45,7 @@ generate: parameters: name: keymgr ip_hjson: ../../data/keymgr.hjson + position: prepend targets: default: diff --git a/hw/ip/kmac/dv/env/kmac_env.core b/hw/ip/kmac/dv/env/kmac_env.core index bfce898ab189c..659a4a557221c 100644 --- a/hw/ip/kmac/dv/env/kmac_env.core +++ b/hw/ip/kmac/dv/env/kmac_env.core @@ -56,6 +56,7 @@ generate: parameters: name: kmac ip_hjson: ../../data/kmac.hjson + position: prepend targets: default: diff --git a/hw/ip/lc_ctrl/dv/env/lc_ctrl_env.core b/hw/ip/lc_ctrl/dv/env/lc_ctrl_env.core index 2091b977f3cd7..297b771c51a64 100644 --- a/hw/ip/lc_ctrl/dv/env/lc_ctrl_env.core +++ b/hw/ip/lc_ctrl/dv/env/lc_ctrl_env.core @@ -48,6 +48,7 @@ generate: parameters: name: lc_ctrl ip_hjson: ../../data/lc_ctrl.hjson + position: prepend targets: default: diff --git a/hw/ip/otbn/dv/uvm/env/otbn_env.core b/hw/ip/otbn/dv/uvm/env/otbn_env.core index 01efc6c928873..ed52705b0b691 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_env.core +++ b/hw/ip/otbn/dv/uvm/env/otbn_env.core @@ -73,6 +73,7 @@ generate: parameters: name: otbn ip_hjson: ../../../data/otbn.hjson + position: prepend targets: default: diff --git a/hw/ip/otp_ctrl/dv/env/otp_ctrl_env.core b/hw/ip/otp_ctrl/dv/env/otp_ctrl_env.core index 4b35e4c2118ab..74dce56d8f465 100644 --- a/hw/ip/otp_ctrl/dv/env/otp_ctrl_env.core +++ b/hw/ip/otp_ctrl/dv/env/otp_ctrl_env.core @@ -50,6 +50,7 @@ generate: parameters: name: otp_ctrl ip_hjson: ../../data/otp_ctrl.hjson + position: prepend targets: default: diff --git a/hw/ip/pattgen/dv/env/pattgen_env.core b/hw/ip/pattgen/dv/env/pattgen_env.core index 847c57ec34550..3b3a944ae7deb 100644 --- a/hw/ip/pattgen/dv/env/pattgen_env.core +++ b/hw/ip/pattgen/dv/env/pattgen_env.core @@ -37,6 +37,7 @@ generate: parameters: name: pattgen ip_hjson: ../../data/pattgen.hjson + position: prepend targets: default: diff --git a/hw/ip/pwm/dv/env/pwm_env.core b/hw/ip/pwm/dv/env/pwm_env.core index 0a2f937f90de6..87a4264221979 100644 --- a/hw/ip/pwm/dv/env/pwm_env.core +++ b/hw/ip/pwm/dv/env/pwm_env.core @@ -35,6 +35,7 @@ generate: parameters: name: pwm ip_hjson: ../../data/pwm.hjson + position: prepend targets: default: diff --git a/hw/ip/rom_ctrl/dv/env/rom_ctrl_env.core b/hw/ip/rom_ctrl/dv/env/rom_ctrl_env.core index 6dd4f8cf95eb4..f2a49f6a58b76 100644 --- a/hw/ip/rom_ctrl/dv/env/rom_ctrl_env.core +++ b/hw/ip/rom_ctrl/dv/env/rom_ctrl_env.core @@ -39,6 +39,7 @@ generate: parameters: name: rom_ctrl ip_hjson: ../../data/rom_ctrl.hjson + position: prepend targets: default: diff --git a/hw/ip/rv_dm/dv/env/rv_dm_env.core b/hw/ip/rv_dm/dv/env/rv_dm_env.core index ae0bb804389ef..14ac7e5a89d5f 100644 --- a/hw/ip/rv_dm/dv/env/rv_dm_env.core +++ b/hw/ip/rv_dm/dv/env/rv_dm_env.core @@ -63,6 +63,7 @@ generate: parameters: name: rv_dm ip_hjson: ../../data/rv_dm.hjson + position: prepend targets: default: diff --git a/hw/ip/rv_timer/dv/env/rv_timer_env.core b/hw/ip/rv_timer/dv/env/rv_timer_env.core index b1efb02f9e98e..4f829eb60c913 100644 --- a/hw/ip/rv_timer/dv/env/rv_timer_env.core +++ b/hw/ip/rv_timer/dv/env/rv_timer_env.core @@ -31,6 +31,7 @@ generate: parameters: name: rv_timer ip_hjson: ../../data/rv_timer.hjson + position: prepend targets: default: diff --git a/hw/ip/spi_device/dv/env/spi_device_env.core b/hw/ip/spi_device/dv/env/spi_device_env.core index fbd826cb24334..1413fe26ed447 100644 --- a/hw/ip/spi_device/dv/env/spi_device_env.core +++ b/hw/ip/spi_device/dv/env/spi_device_env.core @@ -51,6 +51,7 @@ generate: parameters: name: spi_device ip_hjson: ../../data/spi_device.hjson + position: prepend targets: default: diff --git a/hw/ip/spi_host/dv/env/spi_host_env.core b/hw/ip/spi_host/dv/env/spi_host_env.core index 6c757abf4793b..616f24e93670c 100644 --- a/hw/ip/spi_host/dv/env/spi_host_env.core +++ b/hw/ip/spi_host/dv/env/spi_host_env.core @@ -47,6 +47,7 @@ generate: parameters: name: spi_host ip_hjson: ../../data/spi_host.hjson + position: prepend targets: default: diff --git a/hw/ip/sram_ctrl/dv/env/sram_ctrl_env.core b/hw/ip/sram_ctrl/dv/env/sram_ctrl_env.core index e29523e7e1644..ff82e715fe8a9 100644 --- a/hw/ip/sram_ctrl/dv/env/sram_ctrl_env.core +++ b/hw/ip/sram_ctrl/dv/env/sram_ctrl_env.core @@ -46,6 +46,7 @@ generate: parameters: name: sram_ctrl ip_hjson: ../../data/sram_ctrl.hjson + position: prepend targets: default: diff --git a/hw/ip/sysrst_ctrl/dv/env/sysrst_ctrl_env.core b/hw/ip/sysrst_ctrl/dv/env/sysrst_ctrl_env.core index ebfde1c162026..ffeb56ed0f398 100644 --- a/hw/ip/sysrst_ctrl/dv/env/sysrst_ctrl_env.core +++ b/hw/ip/sysrst_ctrl/dv/env/sysrst_ctrl_env.core @@ -43,6 +43,7 @@ generate: parameters: name: sysrst_ctrl ip_hjson: ../../data/sysrst_ctrl.hjson + position: prepend targets: default: diff --git a/hw/ip/uart/dv/env/uart_env.core b/hw/ip/uart/dv/env/uart_env.core index b91373709f0b8..64e4a78590814 100644 --- a/hw/ip/uart/dv/env/uart_env.core +++ b/hw/ip/uart/dv/env/uart_env.core @@ -45,6 +45,7 @@ generate: parameters: name: uart ip_hjson: ../../data/uart.hjson + position: prepend targets: default: diff --git a/hw/ip/usbdev/dv/env/usbdev_env.core b/hw/ip/usbdev/dv/env/usbdev_env.core index b515d17eb611d..fd2dbc976c0f3 100644 --- a/hw/ip/usbdev/dv/env/usbdev_env.core +++ b/hw/ip/usbdev/dv/env/usbdev_env.core @@ -102,6 +102,7 @@ generate: parameters: name: usbdev ip_hjson: ../../data/usbdev.hjson + position: prepend targets: default: diff --git a/hw/ip_templates/clkmgr/dv/env/clkmgr_env.core b/hw/ip_templates/clkmgr/dv/env/clkmgr_env.core index 2fa8234336d2c..34fd79715f99b 100644 --- a/hw/ip_templates/clkmgr/dv/env/clkmgr_env.core +++ b/hw/ip_templates/clkmgr/dv/env/clkmgr_env.core @@ -40,6 +40,7 @@ generate: parameters: name: clkmgr ip_hjson: ../../data/clkmgr.hjson + position: prepend targets: default: diff --git a/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env.core b/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env.core index 735c3fb1f3aba..f339e44e1f82c 100644 --- a/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env.core +++ b/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env.core @@ -104,6 +104,7 @@ generate: parameters: name: flash_ctrl ip_hjson: ../../data/flash_ctrl.hjson + position: prepend targets: default: diff --git a/hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core b/hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core index 731e28063b434..90c6919414578 100644 --- a/hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core +++ b/hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core @@ -46,6 +46,7 @@ generate: parameters: name: pwrmgr ip_hjson: ../../data/pwrmgr.hjson + position: prepend targets: default: diff --git a/hw/ip_templates/rstmgr/dv/env/rstmgr_env.core b/hw/ip_templates/rstmgr/dv/env/rstmgr_env.core index a8d54568b804e..25504659e8c81 100644 --- a/hw/ip_templates/rstmgr/dv/env/rstmgr_env.core +++ b/hw/ip_templates/rstmgr/dv/env/rstmgr_env.core @@ -43,6 +43,7 @@ generate: parameters: name: rstmgr ip_hjson: ../../data/rstmgr.hjson + position: prepend targets: default: diff --git a/hw/top_earlgrey/dv/env/chip_env.core b/hw/top_earlgrey/dv/env/chip_env.core index 2700ff84fb9d8..41c95a48c069d 100644 --- a/hw/top_earlgrey/dv/env/chip_env.core +++ b/hw/top_earlgrey/dv/env/chip_env.core @@ -168,6 +168,7 @@ generate: parameters: name: chip top_hjson: ../../data/top_earlgrey.hjson + position: prepend targets: default: diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/dv/env/clkmgr_env.core b/hw/top_earlgrey/ip_autogen/clkmgr/dv/env/clkmgr_env.core index 2fa8234336d2c..34fd79715f99b 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/dv/env/clkmgr_env.core +++ b/hw/top_earlgrey/ip_autogen/clkmgr/dv/env/clkmgr_env.core @@ -40,6 +40,7 @@ generate: parameters: name: clkmgr ip_hjson: ../../data/clkmgr.hjson + position: prepend targets: default: diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env.core index 735c3fb1f3aba..f339e44e1f82c 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env.core +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env.core @@ -104,6 +104,7 @@ generate: parameters: name: flash_ctrl ip_hjson: ../../data/flash_ctrl.hjson + position: prepend targets: default: diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core index 731e28063b434..90c6919414578 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core @@ -46,6 +46,7 @@ generate: parameters: name: pwrmgr ip_hjson: ../../data/pwrmgr.hjson + position: prepend targets: default: diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/dv/env/rstmgr_env.core b/hw/top_earlgrey/ip_autogen/rstmgr/dv/env/rstmgr_env.core index a8d54568b804e..25504659e8c81 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/dv/env/rstmgr_env.core +++ b/hw/top_earlgrey/ip_autogen/rstmgr/dv/env/rstmgr_env.core @@ -43,6 +43,7 @@ generate: parameters: name: rstmgr ip_hjson: ../../data/rstmgr.hjson + position: prepend targets: default: From 5dc93937524ab150b899c7555562b47bc440d85c Mon Sep 17 00:00:00 2001 From: Hugo McNally Date: Fri, 22 Nov 2024 20:50:07 +0000 Subject: [PATCH 03/24] [prim] Replaced primgen with virtual prim cores In addition to changing to virtual prim cores, quite a few paths had to be updated for FuseSoC's new build directory layout. Note, prim_pkg still exists as prim_pkg_legacy because some RTL beyond the old primitive wrappers depends on the implementation enum. prim_pkg_legacy has been labelled as legacy. Co-authored-by: Alexander Williams Signed-off-by: Hugo McNally --- hw/bitstream/vivado/BUILD | 4 +- hw/dv/dpi/dpi_sim_cfg.hjson | 4 +- hw/dv/tools/dvsim/fusesoc.hjson | 4 +- hw/dv/tools/dvsim/xcelium.hjson | 2 +- .../verilator/cpp/scrambled_ecc32_mem_area.cc | 6 +- .../memutil_dpi_scrambled_opts.hjson | 26 +- hw/ip/aes/model/aes_model_sim_opts.hjson | 4 +- .../entropy_src/dv/env/entropy_src_env_cfg.sv | 2 +- hw/ip/hmac/dv/hmac_sim_cfg.hjson | 12 +- hw/ip/kmac/dv/kmac_base_sim_cfg.hjson | 20 +- ...rl_volatile_unlock_disabled_unr_exclude.el | 2 +- ...trl_volatile_unlock_enabled_unr_exclude.el | 2 +- .../dv/memutil/otbn_memutil_sim_opts.hjson | 6 +- .../otbn/dv/tracer/otbn_tracer_sim_opts.hjson | 2 +- hw/ip/otbn/dv/uvm/tb.sv | 4 +- hw/ip/otbn/dv/verilator/otbn_top_sim.cc | 4 +- hw/ip/otbn/dv/verilator/otbn_top_sim.core | 1 + hw/ip/otp_ctrl/data/otp_ctrl.hjson | 2 +- hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl | 2 +- hw/ip/otp_ctrl/data/otp_ctrl_if.sv.tpl | 2 +- .../otp_ctrl/dv/cov/otp_ctrl_cov_unr_excl.el | 106 ++-- hw/ip/otp_ctrl/dv/env/otp_ctrl_if.sv | 2 +- hw/ip/otp_ctrl/dv/tb.sv | 4 +- hw/ip/otp_ctrl/otp_ctrl.core | 2 + hw/ip/otp_ctrl/rtl/otp_ctrl.sv | 4 +- .../crypto_dpi_prince_sim_opts.hjson | 4 +- hw/ip/prim/prim.core | 1 - hw/ip/prim/prim_and2.core | 48 -- hw/ip/prim/prim_buf.core | 48 -- hw/ip/prim/prim_clock_buf.core | 47 -- hw/ip/prim/prim_clock_div.core | 46 -- hw/ip/prim/prim_clock_gating.core | 47 -- hw/ip/prim/prim_clock_inv.core | 47 -- hw/ip/prim/prim_clock_mux2.core | 47 -- hw/ip/prim/prim_flash.core | 52 -- hw/ip/prim/prim_flop.core | 48 -- hw/ip/prim/prim_flop_2sync.core | 47 -- hw/ip/prim/prim_flop_en.core | 47 -- ...prim_pkg.core.tpl => prim_legacy_pkg.core} | 9 +- hw/ip/prim/prim_onehot_check.core | 2 - hw/ip/prim/prim_otp.core | 50 -- hw/ip/prim/prim_pad_attr.core | 48 -- hw/ip/prim/prim_pad_wrapper.core | 49 -- hw/ip/prim/prim_pkg.core | 23 - hw/ip/prim/prim_ram_1p.core | 48 -- hw/ip/prim/prim_ram_1r1w.core | 48 -- hw/ip/prim/prim_ram_2p.core | 48 -- hw/ip/prim/prim_rom.core | 48 -- hw/ip/prim/prim_rst_sync.core | 4 +- hw/ip/prim/prim_usb_diff_rx.core | 48 -- hw/ip/prim/prim_xnor2.core | 48 -- hw/ip/prim/prim_xor2.core | 48 -- hw/ip/prim/primgen.core | 10 - .../prim_legacy_pkg.sv} | 15 +- hw/ip/prim/util/primgen.py | 497 ------------------ hw/ip/prim/util/primgen/abstract_prim.sv.tpl | 33 -- hw/ip/prim_generic/prim_generic.core | 37 ++ hw/ip/prim_generic/prim_generic_and2.core | 3 + hw/ip/prim_generic/prim_generic_buf.core | 3 + .../prim_generic/prim_generic_clock_buf.core | 3 + .../prim_generic/prim_generic_clock_div.core | 5 +- .../prim_generic_clock_gating.core | 3 + .../prim_generic/prim_generic_clock_inv.core | 3 + .../prim_generic/prim_generic_clock_mux2.core | 3 + hw/ip/prim_generic/prim_generic_flash.core | 3 + hw/ip/prim_generic/prim_generic_flop.core | 3 + .../prim_generic/prim_generic_flop_2sync.core | 3 + hw/ip/prim_generic/prim_generic_flop_en.core | 3 + hw/ip/prim_generic/prim_generic_otp.core | 3 + hw/ip/prim_generic/prim_generic_pad_attr.core | 3 + .../prim_generic_pad_wrapper.core | 3 + hw/ip/prim_generic/prim_generic_ram_1p.core | 3 + hw/ip/prim_generic/prim_generic_ram_1r1w.core | 3 + hw/ip/prim_generic/prim_generic_ram_2p.core | 3 + hw/ip/prim_generic/prim_generic_rom.core | 3 + .../prim_generic_usb_diff_rx.core | 3 + hw/ip/prim_generic/prim_generic_xnor2.core | 3 + hw/ip/prim_generic/prim_generic_xor2.core | 3 + hw/ip/prim_generic/rtl/prim_generic_and2.sv | 2 +- hw/ip/prim_generic/rtl/prim_generic_buf.sv | 2 +- .../rtl/prim_generic_clock_buf.sv | 4 +- .../rtl/prim_generic_clock_div.sv | 2 +- .../rtl/prim_generic_clock_gating.sv | 2 +- .../rtl/prim_generic_clock_inv.sv | 4 +- .../rtl/prim_generic_clock_mux2.sv | 4 +- hw/ip/prim_generic/rtl/prim_generic_flash.sv | 4 +- .../rtl/prim_generic_flash_bank.sv | 2 +- hw/ip/prim_generic/rtl/prim_generic_flop.sv | 2 +- .../rtl/prim_generic_flop_2sync.sv | 4 +- .../prim_generic/rtl/prim_generic_flop_en.sv | 2 +- hw/ip/prim_generic/rtl/prim_generic_otp.sv | 4 +- .../prim_generic/rtl/prim_generic_pad_attr.sv | 4 +- .../rtl/prim_generic_pad_wrapper.sv | 4 +- hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv | 2 +- .../prim_generic/rtl/prim_generic_ram_1r1w.sv | 2 +- hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv | 2 +- hw/ip/prim_generic/rtl/prim_generic_rom.sv | 2 +- .../rtl/prim_generic_usb_diff_rx.sv | 4 +- hw/ip/prim_generic/rtl/prim_generic_xnor2.sv | 2 +- hw/ip/prim_generic/rtl/prim_generic_xor2.sv | 2 +- hw/ip/prim_xilinx/prim_xilinx.core | 36 ++ hw/ip/prim_xilinx/prim_xilinx_and2.core | 3 + hw/ip/prim_xilinx/prim_xilinx_buf.core | 3 + hw/ip/prim_xilinx/prim_xilinx_clock_buf.core | 3 + .../prim_xilinx/prim_xilinx_clock_gating.core | 3 + hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core | 3 + hw/ip/prim_xilinx/prim_xilinx_flop.core | 3 + hw/ip/prim_xilinx/prim_xilinx_flop_en.core | 3 + hw/ip/prim_xilinx/prim_xilinx_pad_attr.core | 3 + .../prim_xilinx/prim_xilinx_pad_wrapper.core | 3 + hw/ip/prim_xilinx/prim_xilinx_xor2.core | 3 + hw/ip/prim_xilinx/rtl/prim_xilinx_and2.sv | 2 +- hw/ip/prim_xilinx/rtl/prim_xilinx_buf.sv | 2 +- .../prim_xilinx/rtl/prim_xilinx_clock_buf.sv | 2 +- .../rtl/prim_xilinx_clock_gating.sv | 2 +- .../prim_xilinx/rtl/prim_xilinx_clock_mux2.sv | 4 +- hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv | 2 +- hw/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv | 2 +- hw/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv | 4 +- .../rtl/prim_xilinx_pad_wrapper.sv | 4 +- hw/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv | 2 +- .../prim_xilinx_ultrascale.core | 36 ++ .../prim_xilinx_ultrascale_and2.core | 3 + .../prim_xilinx_ultrascale_buf.core | 3 + .../prim_xilinx_ultrascale_clock_buf.core | 3 + .../prim_xilinx_ultrascale_clock_div.core | 5 +- .../prim_xilinx_ultrascale_clock_gating.core | 3 + .../prim_xilinx_ultrascale_clock_inv.core | 3 + .../prim_xilinx_ultrascale_clock_mux2.core | 3 + .../prim_xilinx_ultrascale_flop.core | 3 + .../prim_xilinx_ultrascale_flop_en.core | 3 + .../prim_xilinx_ultrascale_pad_attr.core | 3 + .../prim_xilinx_ultrascale_pad_wrapper.core | 3 + .../prim_xilinx_ultrascale_xor2.core | 3 + .../rtl/prim_xilinx_ultrascale_and2.sv | 2 +- .../rtl/prim_xilinx_ultrascale_buf.sv | 2 +- .../rtl/prim_xilinx_ultrascale_clock_buf.sv | 2 +- .../rtl/prim_xilinx_ultrascale_clock_div.sv | 2 +- .../prim_xilinx_ultrascale_clock_gating.sv | 2 +- .../rtl/prim_xilinx_ultrascale_clock_inv.sv | 2 +- .../rtl/prim_xilinx_ultrascale_clock_mux2.sv | 4 +- .../rtl/prim_xilinx_ultrascale_flop.sv | 2 +- .../rtl/prim_xilinx_ultrascale_flop_en.sv | 2 +- .../rtl/prim_xilinx_ultrascale_pad_attr.sv | 4 +- .../rtl/prim_xilinx_ultrascale_pad_wrapper.sv | 4 +- .../rtl/prim_xilinx_ultrascale_xor2.sv | 2 +- hw/ip/rom_ctrl/dv/tb.sv | 2 +- .../env/seq_lib/spi_device_mem_parity_vseq.sv | 2 +- .../dv/env/seq_lib/sram_ctrl_ram_cfg_vseq.sv | 2 +- hw/ip/sram_ctrl/dv/tb.sv | 2 +- .../dv/env/seq_lib/uart_noise_filter_vseq.sv | 2 +- hw/ip/usbdev/dv/tb/tb.sv | 2 +- .../dv/alert_handler_sim.core.tpl | 12 +- ...er_env.core => alert_handler_env.core.tpl} | 13 +- ...dler_tb.core => alert_handler_tb.core.tpl} | 4 +- ..._test.core => alert_handler_test.core.tpl} | 4 +- .../flash_ctrl/data/flash_ctrl.hjson.tpl | 2 +- .../flash_ctrl/dv/env/flash_ctrl_env.core | 2 + .../flash_ctrl/dv/env/flash_ctrl_seq_cfg.sv | 2 +- hw/ip_templates/flash_ctrl/dv/tb/tb.sv | 17 +- .../flash_ctrl/flash_ctrl.core.tpl | 2 + .../flash_ctrl/rtl/flash_ctrl.sv.tpl | 2 +- hw/top_earlgrey/cdc/cdc_waivers.data.tcl | 12 +- hw/top_earlgrey/cdc/cdc_waivers.misc.tcl | 52 +- .../cdc/cdc_waivers.multclk_crossings.tcl | 50 +- hw/top_earlgrey/cdc/cdc_waivers.rst_sync.tcl | 20 +- .../cdc/cdc_waivers.spi_device.tcl | 12 +- .../cdc/cdc_waivers.synch_rst_crossing.tcl | 2 +- hw/top_earlgrey/cdc/cdc_waivers.tcl | 18 +- .../cdc/cdc_waivers.w_async_rst_flops.tcl | 6 +- hw/top_earlgrey/cdc/cdc_waivers.w_data.tcl | 30 +- hw/top_earlgrey/cdc/cdc_waivers.w_fanout.tcl | 22 +- .../cdc/cdc_waivers.w_g_clk_glitch.tcl | 18 +- .../cdc/cdc_waivers.w_interface.tcl | 50 +- hw/top_earlgrey/cdc/cdc_waivers.w_masync.tcl | 52 +- .../cdc/cdc_waivers.w_net_no_wave.tcl | 2 +- hw/top_earlgrey/cdc/cdc_waivers.w_recon.tcl | 60 +-- hw/top_earlgrey/chip_earlgrey_asic.core | 2 + hw/top_earlgrey/chip_earlgrey_cw310.core | 2 + .../chip_earlgrey_cw310_hyperdebug.core | 2 + hw/top_earlgrey/chip_earlgrey_cw340.core | 2 + hw/top_earlgrey/chip_earlgrey_verilator.core | 2 + hw/top_earlgrey/data/clocks.xdc | 46 +- hw/top_earlgrey/data/clocks_cw341.xdc | 48 +- hw/top_earlgrey/data/placement.xdc | 10 +- hw/top_earlgrey/dv/tb/chip_hier_macros.svh | 6 +- hw/top_earlgrey/dv/verilator/chip_sim_tb.cc | 31 +- hw/top_earlgrey/ip/ast/ast.core | 4 +- .../alert_handler/dv/alert_handler_sim.core | 12 +- .../dv/env/alert_handler_env.core | 13 +- .../alert_handler/dv/tb/alert_handler_tb.core | 4 +- .../dv/tests/alert_handler_test.core | 4 +- .../flash_ctrl/data/flash_ctrl.hjson | 2 +- .../flash_ctrl/dv/env/flash_ctrl_env.core | 2 + .../flash_ctrl/dv/env/flash_ctrl_seq_cfg.sv | 2 +- .../ip_autogen/flash_ctrl/dv/tb/tb.sv | 17 +- .../ip_autogen/flash_ctrl/flash_ctrl.core | 2 + .../ip_autogen/flash_ctrl/rtl/flash_ctrl.sv | 2 +- .../rdc/chip_earlgrey_asic_scenario.tcl | 2 +- hw/top_earlgrey/rdc/rdc_waivers.tcl | 4 +- .../chip_englishbreakfast_cw305.core | 2 + .../chip_englishbreakfast_verilator.cc | 16 +- .../chip_englishbreakfast_verilator.core | 2 + hw/top_englishbreakfast/data/clocks.xdc | 22 +- 204 files changed, 811 insertions(+), 2124 deletions(-) delete mode 100644 hw/ip/prim/prim_and2.core delete mode 100644 hw/ip/prim/prim_buf.core delete mode 100644 hw/ip/prim/prim_clock_buf.core delete mode 100644 hw/ip/prim/prim_clock_div.core delete mode 100644 hw/ip/prim/prim_clock_gating.core delete mode 100644 hw/ip/prim/prim_clock_inv.core delete mode 100644 hw/ip/prim/prim_clock_mux2.core delete mode 100644 hw/ip/prim/prim_flash.core delete mode 100644 hw/ip/prim/prim_flop.core delete mode 100644 hw/ip/prim/prim_flop_2sync.core delete mode 100644 hw/ip/prim/prim_flop_en.core rename hw/ip/prim/{util/primgen/prim_pkg.core.tpl => prim_legacy_pkg.core} (65%) delete mode 100644 hw/ip/prim/prim_otp.core delete mode 100644 hw/ip/prim/prim_pad_attr.core delete mode 100644 hw/ip/prim/prim_pad_wrapper.core delete mode 100644 hw/ip/prim/prim_pkg.core delete mode 100644 hw/ip/prim/prim_ram_1p.core delete mode 100644 hw/ip/prim/prim_ram_1r1w.core delete mode 100644 hw/ip/prim/prim_ram_2p.core delete mode 100644 hw/ip/prim/prim_rom.core delete mode 100644 hw/ip/prim/prim_usb_diff_rx.core delete mode 100644 hw/ip/prim/prim_xnor2.core delete mode 100644 hw/ip/prim/prim_xor2.core delete mode 100644 hw/ip/prim/primgen.core rename hw/ip/prim/{util/primgen/prim_pkg.sv.tpl => rtl/prim_legacy_pkg.sv} (53%) delete mode 100755 hw/ip/prim/util/primgen.py delete mode 100644 hw/ip/prim/util/primgen/abstract_prim.sv.tpl create mode 100644 hw/ip/prim_generic/prim_generic.core create mode 100644 hw/ip/prim_xilinx/prim_xilinx.core create mode 100644 hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale.core rename hw/ip_templates/alert_handler/dv/env/{alert_handler_env.core => alert_handler_env.core.tpl} (88%) rename hw/ip_templates/alert_handler/dv/tb/{alert_handler_tb.core => alert_handler_tb.core.tpl} (75%) rename hw/ip_templates/alert_handler/dv/tests/{alert_handler_test.core => alert_handler_test.core.tpl} (79%) diff --git a/hw/bitstream/vivado/BUILD b/hw/bitstream/vivado/BUILD index bfe1e6e804af6..6bc8ba0558cd7 100644 --- a/hw/bitstream/vivado/BUILD +++ b/hw/bitstream/vivado/BUILD @@ -13,12 +13,12 @@ load("//rules:bitstreams.bzl", "bitstream_manifest_fragment") package(default_visibility = ["//visibility:public"]) # The readmem directives in the fusesoc-ized build tree will be in the subdir -# ${build_root}/src/lowrisc_prim_util_memload_0/rtl/prim_util_memload.svh, +# ${build_root}/${core}/${target}-${tool}/src/lowrisc_prim_util_memload_0/rtl/prim_util_memload.svh, # and ${build_root} will be a subdirectory called `build.fpga_cw310` inside of # bazel-out/k8-{configname}/bin/hw/bitstream/vivado. # Therefore, the relative path between prim_util_memload.svh and the project-root # relative $(location ...) resolved labels is up 10 subdirectories. -_PREFIX = "../../../../../../../../../.." +_PREFIX = "../../../../../../../../../../.." _CW310_TESTROM = "//sw/device/lib/testing/test_rom:test_rom_fpga_cw310_scr_vmem" diff --git a/hw/dv/dpi/dpi_sim_cfg.hjson b/hw/dv/dpi/dpi_sim_cfg.hjson index 4a2a4e1aa187a..b7d95710885e4 100644 --- a/hw/dv/dpi/dpi_sim_cfg.hjson +++ b/hw/dv/dpi/dpi_sim_cfg.hjson @@ -10,12 +10,12 @@ build_modes: [ { name: vcs_dpi_build_opts - build_opts: ["-CFLAGS -I{build_dir}/src/{dpi_common_dir}", "-lutil"] + build_opts: ["-CFLAGS -I{build_dir}/fusesoc-work/src/{dpi_common_dir}", "-lutil"] } { name: xcelium_dpi_build_opts - build_opts: ["-I{build_dir}/src/{dpi_common_dir}", "-lutil"] + build_opts: ["-I{build_dir}/fusesoc-work/src/{dpi_common_dir}", "-lutil"] } ] } diff --git a/hw/dv/tools/dvsim/fusesoc.hjson b/hw/dv/tools/dvsim/fusesoc.hjson index 1e441668883fb..eef40638e5270 100644 --- a/hw/dv/tools/dvsim/fusesoc.hjson +++ b/hw/dv/tools/dvsim/fusesoc.hjson @@ -8,10 +8,10 @@ "run", "{sv_flist_gen_flags}", "--target=sim", - "--build-root={build_dir}", + "--work-root={build_dir}/fusesoc-work", "--setup {fusesoc_core}"] fusesoc_cores_root_dirs: ["--cores-root {proj_root}"] - sv_flist_gen_dir: "{build_dir}/sim-vcs" + sv_flist_gen_dir: "{build_dir}/fusesoc-work" sv_flist: "{sv_flist_gen_dir}/{fusesoc_core_}.scr" sv_flist_gen_flags: ["--flag=fileset_{design_level}"] } diff --git a/hw/dv/tools/dvsim/xcelium.hjson b/hw/dv/tools/dvsim/xcelium.hjson index c146aee8c80a1..6e6deb056c42d 100644 --- a/hw/dv/tools/dvsim/xcelium.hjson +++ b/hw/dv/tools/dvsim/xcelium.hjson @@ -46,7 +46,7 @@ // Ignore warning "Include directory given but not used". This is benign. "-nowarn SPDUSD", // Needed for including "secded_enc.h". - "-I{build_dir}/src/lowrisc_dv_secded_enc_0", + "-I{build_dir}/fusesoc-work/src/lowrisc_dv_secded_enc_0", // This warning is thrown when a scalar enum variable is assigned to an enum array. // Other tools (e.g., FPV) treat such assignments as an error, hence we bump it to // an error in simulation so that this can be caught early in CI. diff --git a/hw/dv/verilator/cpp/scrambled_ecc32_mem_area.cc b/hw/dv/verilator/cpp/scrambled_ecc32_mem_area.cc index c67a92917b9cd..effe457abfc03 100644 --- a/hw/dv/verilator/cpp/scrambled_ecc32_mem_area.cc +++ b/hw/dv/verilator/cpp/scrambled_ecc32_mem_area.cc @@ -117,10 +117,8 @@ std::vector ScrambledEcc32MemArea::GetScrambleNonce() const { ScrambledEcc32MemArea::ScrambledEcc32MemArea(const std::string &scope, uint32_t size, uint32_t width_32, bool repeat_keystream) - : Ecc32MemArea( - SVScoped::join_sv_scopes( - scope, "u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic"), - size, width_32), + : Ecc32MemArea(SVScoped::join_sv_scopes(scope, "u_prim_ram_1p_adv.u_mem"), + size, width_32), scr_scope_(scope) { addr_width_ = vbits(size); repeat_keystream_ = repeat_keystream; diff --git a/hw/dv/verilator/memutil_dpi_scrambled_opts.hjson b/hw/dv/verilator/memutil_dpi_scrambled_opts.hjson index ee8ae81fa7a80..0e697ef368069 100644 --- a/hw/dv/verilator/memutil_dpi_scrambled_opts.hjson +++ b/hw/dv/verilator/memutil_dpi_scrambled_opts.hjson @@ -24,29 +24,29 @@ build_modes: [ { name: vcs_memutil_dpi_scrambled_build_opts - build_opts: ["-CFLAGS -I{build_dir}/src/{memutil_dpi_src_dir}/cpp", - "-CFLAGS -I{build_dir}/src/{memutil_dpi_scrambled_src_dir}/cpp", - "-CFLAGS -I{build_dir}/src/{secded_enc_src_dir}", - "-CFLAGS -I{build_dir}/src/{scramble_model_dir}", - "-CFLAGS -I{build_dir}/src/{prince_ref_src_dir}", + build_opts: ["-CFLAGS -I{build_dir}/fusesoc-work/src/{memutil_dpi_src_dir}/cpp", + "-CFLAGS -I{build_dir}/fusesoc-work/src/{memutil_dpi_scrambled_src_dir}/cpp", + "-CFLAGS -I{build_dir}/fusesoc-work/src/{secded_enc_src_dir}", + "-CFLAGS -I{build_dir}/fusesoc-work/src/{scramble_model_dir}", + "-CFLAGS -I{build_dir}/fusesoc-work/src/{prince_ref_src_dir}", "-lelf"] } { name: xcelium_memutil_dpi_scrambled_build_opts - build_opts: ["-I{build_dir}/src/{memutil_dpi_src_dir}/cpp", - "-I{build_dir}/src/{memutil_dpi_scrambled_src_dir}/cpp", - "-I{build_dir}/src/{prince_ref_src_dir}", - "-I{build_dir}/src/{scramble_model_dir}", + build_opts: ["-I{build_dir}/fusesoc-work/src/{memutil_dpi_src_dir}/cpp", + "-I{build_dir}/fusesoc-work/src/{memutil_dpi_scrambled_src_dir}/cpp", + "-I{build_dir}/fusesoc-work/src/{prince_ref_src_dir}", + "-I{build_dir}/fusesoc-work/src/{scramble_model_dir}", "-lelf"] } { name: dsim_memutil_dpi_scrambled_build_opts - build_opts: ["-c-opts -I{build_dir}/src/{memutil_dpi_src_dir}/cpp", - "-c-opts -I{build_dir}/src/{memutil_dpi_scrambled_src_dir}/cpp", - "-c-opts -I{build_dir}/src/{prince_ref_src_dir}", - "-c-opts -I{build_dir}/src/{scramble_model_dir}", + build_opts: ["-c-opts -I{build_dir}/fusesoc-work/src/{memutil_dpi_src_dir}/cpp", + "-c-opts -I{build_dir}/fusesoc-work/src/{memutil_dpi_scrambled_src_dir}/cpp", + "-c-opts -I{build_dir}/fusesoc-work/src/{prince_ref_src_dir}", + "-c-opts -I{build_dir}/fusesoc-work/src/{scramble_model_dir}", "-ld-opts -lelf"] } ] diff --git a/hw/ip/aes/model/aes_model_sim_opts.hjson b/hw/ip/aes/model/aes_model_sim_opts.hjson index 753ce55fc1d56..fb415cdfe936b 100644 --- a/hw/ip/aes/model/aes_model_sim_opts.hjson +++ b/hw/ip/aes/model/aes_model_sim_opts.hjson @@ -10,12 +10,12 @@ build_modes: [ { name: vcs_aes_model_build_opts - build_opts: ["-CFLAGS -I{build_dir}/src/{aes_model_src_dir}", "-lcrypto"] + build_opts: ["-CFLAGS -I{build_dir}/fusesoc-work/src/{aes_model_src_dir}", "-lcrypto"] } { name: xcelium_aes_model_build_opts - build_opts: ["-I{build_dir}/src/{aes_model_src_dir}", "-lcrypto"] + build_opts: ["-I{build_dir}/fusesoc-work/src/{aes_model_src_dir}", "-lcrypto"] } ] } diff --git a/hw/ip/entropy_src/dv/env/entropy_src_env_cfg.sv b/hw/ip/entropy_src/dv/env/entropy_src_env_cfg.sv index 94558a7d25446..d3daf8b60716c 100644 --- a/hw/ip/entropy_src/dv/env/entropy_src_env_cfg.sv +++ b/hw/ip/entropy_src/dv/env/entropy_src_env_cfg.sv @@ -281,7 +281,7 @@ class entropy_src_env_cfg extends cip_base_env_cfg #(.RAL_T(entropy_src_reg_bloc 0: path = {path, ".i_sync_n"}; 1: path = {path, ".i_sync_p"}; endcase - disabled_prim_cdc_rand_delays[i] = {path, ".gen_generic.u_impl_generic.u_prim_cdc_rand_delay"}; + disabled_prim_cdc_rand_delays[i] = {path, ".u_prim_cdc_rand_delay"}; end endfunction diff --git a/hw/ip/hmac/dv/hmac_sim_cfg.hjson b/hw/ip/hmac/dv/hmac_sim_cfg.hjson index eb715a8d058e0..527ddef469cee 100644 --- a/hw/ip/hmac/dv/hmac_sim_cfg.hjson +++ b/hw/ip/hmac/dv/hmac_sim_cfg.hjson @@ -100,7 +100,7 @@ name: hmac_test_sha256_vectors uvm_test_seq: hmac_test_vectors_sha_vseq // Increase timeout for all test iterations to pass - run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256"] + run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256"] reseed: 5 } @@ -123,34 +123,34 @@ { name: hmac_test_hmac256_vectors uvm_test_seq: hmac_test_vectors_hmac_vseq - run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256"] + run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256"] reseed: 5 } { name: hmac_test_hmac384_vectors uvm_test_seq: hmac_test_vectors_hmac_vseq - run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384"] + run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384"] reseed: 5 } { name: hmac_test_hmac512_vectors uvm_test_seq: hmac_test_vectors_hmac_vseq - run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512"] + run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512"] reseed: 5 } { // Append the common stress_tests.hjson entry for more run_opts. name: hmac_stress_all - run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0"] + run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0"] } { // Append the common stress_tests.hjson entry for more run_opts. name: hmac_stress_all_with_rand_reset - run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0"] + run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0"] reseed: 10 } ] diff --git a/hw/ip/kmac/dv/kmac_base_sim_cfg.hjson b/hw/ip/kmac/dv/kmac_base_sim_cfg.hjson index f498c22bac4f6..98cdb52aad5c1 100644 --- a/hw/ip/kmac/dv/kmac_base_sim_cfg.hjson +++ b/hw/ip/kmac/dv/kmac_base_sim_cfg.hjson @@ -115,7 +115,7 @@ { name: "{name}_test_vectors_sha3_224" uvm_test_seq: kmac_test_vectors_sha3_vseq - run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0", + run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0", "+test_timeout_ns=5_000_000_000", "+test_vectors_sha3_variant=224"] run_timeout_mins: 90 @@ -124,7 +124,7 @@ { name: "{name}_test_vectors_sha3_256" uvm_test_seq: kmac_test_vectors_sha3_vseq - run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0", + run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0", "+test_timeout_ns=5_000_000_000", "+test_vectors_sha3_variant=256"] run_timeout_mins: 90 @@ -133,7 +133,7 @@ { name: "{name}_test_vectors_sha3_384" uvm_test_seq: kmac_test_vectors_sha3_vseq - run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0", + run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0", "+test_timeout_ns=5_000_000_000", "+test_vectors_sha3_variant=384"] reseed: 5 @@ -141,7 +141,7 @@ { name: "{name}_test_vectors_sha3_512" uvm_test_seq: kmac_test_vectors_sha3_vseq - run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0", + run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0", "+test_timeout_ns=5_000_000_000", "+test_vectors_sha3_variant=512"] reseed: 5 @@ -149,7 +149,7 @@ { name: "{name}_test_vectors_shake_128" uvm_test_seq: kmac_test_vectors_shake_vseq - run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0", + run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0", "+test_timeout_ns=5_000_000_000", "+test_vectors_shake_variant=128"] run_timeout_mins: 90 @@ -158,7 +158,7 @@ { name: "{name}_test_vectors_shake_256" uvm_test_seq: kmac_test_vectors_shake_vseq - run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0", + run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0", "+test_timeout_ns=5_000_000_000", "+test_vectors_shake_variant=256"] run_timeout_mins: 90 @@ -167,13 +167,13 @@ { name: "{name}_test_vectors_kmac" uvm_test_seq: kmac_test_vectors_kmac_vseq - run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0"] + run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0"] reseed: 5 } { name: "{name}_test_vectors_kmac_xof" uvm_test_seq: kmac_test_vectors_kmac_xof_vseq - run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0"] + run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0"] reseed: 5 } { @@ -229,11 +229,11 @@ { name: kmac_stress_all run_opts: ["+test_timeout_ns=10_000_000_000", - "+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0"] + "+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0"] } { name: kmac_stress_all_with_rand_reset - run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0"] + run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0"] reseed: 10 } ] diff --git a/hw/ip/lc_ctrl/dv/cov/lc_ctrl_volatile_unlock_disabled_unr_exclude.el b/hw/ip/lc_ctrl/dv/cov/lc_ctrl_volatile_unlock_disabled_unr_exclude.el index d8e0ee1233382..bfa30b2792320 100644 --- a/hw/ip/lc_ctrl/dv/cov/lc_ctrl_volatile_unlock_disabled_unr_exclude.el +++ b/hw/ip/lc_ctrl/dv/cov/lc_ctrl_volatile_unlock_disabled_unr_exclude.el @@ -9,7 +9,7 @@ // ExclMode: default //================================================== CHECKSUM: "1599929061 1913160869" -INSTANCE: tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay +INSTANCE: tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.u_prim_cdc_rand_delay ANNOTATION: "VC_COV_UNR" Toggle 0to1 dst_data_o [0] "logic dst_data_o[0:0]" ANNOTATION: "VC_COV_UNR" diff --git a/hw/ip/lc_ctrl/dv/cov/lc_ctrl_volatile_unlock_enabled_unr_exclude.el b/hw/ip/lc_ctrl/dv/cov/lc_ctrl_volatile_unlock_enabled_unr_exclude.el index a4f59c9642079..a6b7c5de7d1d0 100644 --- a/hw/ip/lc_ctrl/dv/cov/lc_ctrl_volatile_unlock_enabled_unr_exclude.el +++ b/hw/ip/lc_ctrl/dv/cov/lc_ctrl_volatile_unlock_enabled_unr_exclude.el @@ -9,7 +9,7 @@ // ExclMode: default //================================================== CHECKSUM: "1599929061 1913160869" -INSTANCE: tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay +INSTANCE: tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.u_prim_cdc_rand_delay ANNOTATION: "VC_COV_UNR" Toggle 0to1 dst_data_o [0] "logic dst_data_o[0:0]" ANNOTATION: "VC_COV_UNR" diff --git a/hw/ip/otbn/dv/memutil/otbn_memutil_sim_opts.hjson b/hw/ip/otbn/dv/memutil/otbn_memutil_sim_opts.hjson index 0b020c8b62625..5ed991ca6b523 100644 --- a/hw/ip/otbn/dv/memutil/otbn_memutil_sim_opts.hjson +++ b/hw/ip/otbn/dv/memutil/otbn_memutil_sim_opts.hjson @@ -13,17 +13,17 @@ build_modes: [ { name: vcs_otbn_memutil_build_opts - build_opts: ["-CFLAGS -I{build_dir}/src/{otbn_memutil_src_dir}"] + build_opts: ["-CFLAGS -I{build_dir}/fusesoc-work/src/{otbn_memutil_src_dir}"] } { name: xcelium_otbn_memutil_build_opts - build_opts: ["-I{build_dir}/src/{otbn_memutil_src_dir}"] + build_opts: ["-I{build_dir}/fusesoc-work/src/{otbn_memutil_src_dir}"] } { name: dsim_otbn_memutil_build_opts - build_opts: ["-c-opts -I{build_dir}/src/{otbn_memutil_src_dir}"] + build_opts: ["-c-opts -I{build_dir}/fusesoc-work/src/{otbn_memutil_src_dir}"] } ] } diff --git a/hw/ip/otbn/dv/tracer/otbn_tracer_sim_opts.hjson b/hw/ip/otbn/dv/tracer/otbn_tracer_sim_opts.hjson index 6a26b7483cf03..ca1bd49bbc058 100644 --- a/hw/ip/otbn/dv/tracer/otbn_tracer_sim_opts.hjson +++ b/hw/ip/otbn/dv/tracer/otbn_tracer_sim_opts.hjson @@ -5,7 +5,7 @@ // Additional build-time options needed to compile C++ sources in // simulators such as VCS and Xcelium for anything that uses // otbn_tracer. - otbn_tracer_inc_dir: "{build_dir}/src/lowrisc_ip_otbn_tracer_0/cpp" + otbn_tracer_inc_dir: "{build_dir}/fusesoc-work/src/lowrisc_ip_otbn_tracer_0/cpp" build_modes: [ { diff --git a/hw/ip/otbn/dv/uvm/tb.sv b/hw/ip/otbn/dv/uvm/tb.sv index 9dbdfc7bd1820..b3b197ec1960e 100644 --- a/hw/ip/otbn/dv/uvm/tb.sv +++ b/hw/ip/otbn/dv/uvm/tb.sv @@ -343,7 +343,7 @@ module tb; // Note that n_bits is the number of bits in the memory, including ECC check bits. imem_util = new(.name ("imem_util"), .path ({"tb.dut.u_imem.u_prim_ram_1p_adv.", - "u_mem.gen_generic.u_impl_generic.mem"}), + "u_mem.mem"}), .depth (ImemSizeByte / 4), .n_bits (ImemSizeByte / 4 * 39), .err_detection_scheme (mem_bkdr_util_pkg::EccInv_39_32)); @@ -351,7 +351,7 @@ module tb; // DMEM is twice as big as the bus-accessible part dmem_util = new(.name ("dmem_util"), .path ({"tb.dut.u_dmem.u_prim_ram_1p_adv.", - "u_mem.gen_generic.u_impl_generic.mem"}), + "u_mem.mem"}), .depth (DmemSizeByte / 32), .n_bits (DmemSizeByte / 32 * 312), .err_detection_scheme (mem_bkdr_util_pkg::EccInv_39_32)); diff --git a/hw/ip/otbn/dv/verilator/otbn_top_sim.cc b/hw/ip/otbn/dv/verilator/otbn_top_sim.cc index df1004e12177b..d48d35efc20bf 100644 --- a/hw/ip/otbn/dv/verilator/otbn_top_sim.cc +++ b/hw/ip/otbn/dv/verilator/otbn_top_sim.cc @@ -195,8 +195,8 @@ void set_up_down_prim_count(PrimCountT *prim_count, uint32_t new_cnt) { auto up_cnt_flop = prim_count->gen_cnts__BRA__0__KET____DOT__u_cnt_flop; auto down_cnt_flop = prim_count->gen_cnts__BRA__1__KET____DOT__u_cnt_flop; - up_cnt_flop->gen_generic__DOT__u_impl_generic->d_i = new_cnt; - down_cnt_flop->gen_generic__DOT__u_impl_generic->d_i = 0xFFFFFFFF - new_cnt; + up_cnt_flop->d_i = new_cnt; + down_cnt_flop->d_i = 0xFFFFFFFF - new_cnt; } template diff --git a/hw/ip/otbn/dv/verilator/otbn_top_sim.core b/hw/ip/otbn/dv/verilator/otbn_top_sim.core index 2b02aabc7c0a5..a2b192fa5ec89 100644 --- a/hw/ip/otbn/dv/verilator/otbn_top_sim.core +++ b/hw/ip/otbn/dv/verilator/otbn_top_sim.core @@ -12,6 +12,7 @@ filesets: - lowrisc:dv:otbn_model - lowrisc:ip:otbn_tracer - lowrisc:ip:keymgr_pkg + - lowrisc:prim_generic:all files_verilator: depend: - lowrisc:dv:otbn_memutil diff --git a/hw/ip/otp_ctrl/data/otp_ctrl.hjson b/hw/ip/otp_ctrl/data/otp_ctrl.hjson index 44844724b52a8..dddbefed48603 100644 --- a/hw/ip/otp_ctrl/data/otp_ctrl.hjson +++ b/hw/ip/otp_ctrl/data/otp_ctrl.hjson @@ -58,7 +58,7 @@ scan_en: "true", // Enable `scan_en_i` port bus_interfaces: [ { protocol: "tlul", direction: "device", name: "core" } - { protocol: "tlul", direction: "device", name: "prim", hier_path: "u_otp.gen_generic.u_impl_generic.u_reg_top" } + { protocol: "tlul", direction: "device", name: "prim", hier_path: "u_otp.u_reg_top" } ], available_output_list: [ diff --git a/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl b/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl index f9e96a5c05193..bee4fb6847cbf 100644 --- a/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl +++ b/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl @@ -68,7 +68,7 @@ otp_size_as_uint32 = otp_size_as_bytes // 4 scan_en: "true", // Enable `scan_en_i` port bus_interfaces: [ { protocol: "tlul", direction: "device", name: "core" } - { protocol: "tlul", direction: "device", name: "prim", hier_path: "u_otp.gen_generic.u_impl_generic.u_reg_top" } + { protocol: "tlul", direction: "device", name: "prim", hier_path: "u_otp.u_reg_top" } ], available_output_list: [ diff --git a/hw/ip/otp_ctrl/data/otp_ctrl_if.sv.tpl b/hw/ip/otp_ctrl/data/otp_ctrl_if.sv.tpl index 4fac06be38100..69dcc3850c082 100644 --- a/hw/ip/otp_ctrl/data/otp_ctrl_if.sv.tpl +++ b/hw/ip/otp_ctrl/data/otp_ctrl_if.sv.tpl @@ -40,7 +40,7 @@ buf_parts_without_lc = [part for part in otp_mmap.config["partitions"] if `ifndef PRIM_GENERIC_OTP_CMD_I_PATH `define PRIM_GENERIC_OTP_CMD_I_PATH ${"\\"} - `PRIM_GENERIC_OTP_PATH.gen_generic.u_impl_generic.cmd_i + `PRIM_GENERIC_OTP_PATH.cmd_i `endif interface otp_ctrl_if(input clk_i, input rst_ni); diff --git a/hw/ip/otp_ctrl/dv/cov/otp_ctrl_cov_unr_excl.el b/hw/ip/otp_ctrl/dv/cov/otp_ctrl_cov_unr_excl.el index 99dfe4f72ff2c..b622e16e90fc9 100644 --- a/hw/ip/otp_ctrl/dv/cov/otp_ctrl_cov_unr_excl.el +++ b/hw/ip/otp_ctrl/dv/cov/otp_ctrl_cov_unr_excl.el @@ -2243,7 +2243,7 @@ Block 19 "4019242409" "wptr_wrap_cnt_q <= (wptr_wrap_cnt_q + {{(WrapPtrW - 1) {1 ANNOTATION: "VC_COV_UNR" Block 28 "1113085816" "rptr_wrap_cnt_q <= (rptr_wrap_cnt_q + {{(WrapPtrW - 1) {1'b0}}, 1'b1});" CHECKSUM: "3171246264 1537087436" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic +INSTANCE: tb.dut.u_otp ANNOTATION: "VC_COV_UNR" Block 24 "3494210324" ";" CHECKSUM: "3665351474 3190968676" @@ -2361,59 +2361,59 @@ INSTANCE: tb.dut.u_otp_ctrl_scrmbl ANNOTATION: "VC_COV_UNR" Block 28 "3494210324" ";" CHECKSUM: "4255502330 223073768" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field3 ANNOTATION: "VC_COV_UNR" Block 4 "1824183207" "q <= wr_data;" CHECKSUM: "4255502330 223073768" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field4 ANNOTATION: "VC_COV_UNR" Block 4 "1824183207" "q <= wr_data;" CHECKSUM: "4255502330 223073768" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field5 ANNOTATION: "VC_COV_UNR" Block 4 "1824183207" "q <= wr_data;" CHECKSUM: "4255502330 223073768" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field6 ANNOTATION: "VC_COV_UNR" Block 4 "1824183207" "q <= wr_data;" CHECKSUM: "4255502330 223073768" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field7 ANNOTATION: "VC_COV_UNR" Block 4 "1824183207" "q <= wr_data;" CHECKSUM: "4255502330 223073768" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field8 ANNOTATION: "VC_COV_UNR" Block 4 "1824183207" "q <= wr_data;" CHECKSUM: "4255502330 223073768" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field2 ANNOTATION: "VC_COV_UNR" Block 4 "1824183207" "q <= wr_data;" CHECKSUM: "4255502330 223073768" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field3 ANNOTATION: "VC_COV_UNR" Block 4 "1824183207" "q <= wr_data;" CHECKSUM: "4255502330 223073768" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field4 ANNOTATION: "VC_COV_UNR" Block 4 "1824183207" "q <= wr_data;" CHECKSUM: "4255502330 223073768" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field5 ANNOTATION: "VC_COV_UNR" Block 4 "1824183207" "q <= wr_data;" CHECKSUM: "4255502330 223073768" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field0 ANNOTATION: "VC_COV_UNR" Block 4 "1824183207" "q <= wr_data;" CHECKSUM: "4255502330 223073768" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field1 ANNOTATION: "VC_COV_UNR" Block 4 "1824183207" "q <= wr_data;" CHECKSUM: "4255502330 223073768" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field2 ANNOTATION: "VC_COV_UNR" Block 4 "1824183207" "q <= wr_data;" CHECKSUM: "4255502330 223073768" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field3 ANNOTATION: "VC_COV_UNR" Block 4 "1824183207" "q <= wr_data;" CHECKSUM: "3162909804 919553166" @@ -2443,13 +2443,13 @@ INSTANCE: tb.dut.u_otp_ctrl_kdi ANNOTATION: "VC_COV_UNR" Block 88 "3038555774" "state_d = DigLoadSt;" CHECKSUM: "1611327958 113940473" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top +INSTANCE: tb.dut.u_otp.u_reg_top ANNOTATION: "VC_COV_UNR" Condition 20 "3585319611" "(reg_we && ((!addrmiss))) 1 -1" (2 "10") ANNOTATION: "VC_COV_UNR" Condition 22 "1026062099" "(addrmiss | wr_err | intg_err) 1 -1" (4 "100") CHECKSUM: "3171246264 2882888745" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic +INSTANCE: tb.dut.u_otp ANNOTATION: "VC_COV_UNR" Condition 1 "2104830463" "(cmd_i == Init) 1 -1" (1 "0") CHECKSUM: "3162909804 3458814989" @@ -5066,75 +5066,75 @@ INSTANCE: tb.dut.u_reg_core.u_reg_if ANNOTATION: "VC_COV_UNR" Condition 18 "3340270436" "(addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error) 1 -1" (5 "01000") CHECKSUM: "74367784 3785313510" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if +INSTANCE: tb.dut.u_otp.u_reg_top.u_reg_if ANNOTATION: "VC_COV_UNR" Condition 18 "3340270436" "(addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error) 1 -1" (5 "01000") CHECKSUM: "4255502330 3274445021" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field3 ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") CHECKSUM: "4255502330 3274445021" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field4 ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") CHECKSUM: "4255502330 3274445021" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field5 ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") CHECKSUM: "4255502330 3274445021" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field6 ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") CHECKSUM: "4255502330 3274445021" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field7 ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") CHECKSUM: "4255502330 3274445021" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field8 ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") CHECKSUM: "4255502330 3274445021" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field2 ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") CHECKSUM: "4255502330 3274445021" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field4 ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") CHECKSUM: "4255502330 3274445021" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field5 ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") CHECKSUM: "4255502330 3274445021" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field2 ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") CHECKSUM: "4255502330 3274445021" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field3 ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") CHECKSUM: "4255502330 3858770513" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field3 ANNOTATION: "VC_COV_UNR" Condition 1 "1301967206" "(wr_en ? wr_data : qs) 1 -1" (2 "1") CHECKSUM: "4255502330 3858770513" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field1 ANNOTATION: "VC_COV_UNR" Condition 1 "1301967206" "(wr_en ? wr_data : qs) 1 -1" (2 "1") CHECKSUM: "4255502330 3201188367" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field0 ANNOTATION: "VC_COV_UNR" Condition 1 "1807203824" "(wr_en ? wr_data : qs) 1 -1" (2 "1") CHECKSUM: "2099741489 1445279304" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field0.wr_en_data_arb +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field0.wr_en_data_arb ANNOTATION: "VC_COV_UNR" Condition 1 "505266581" "(we | de) 1 -1" (2 "01") CHECKSUM: "2099741489 1445279304" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1.wr_en_data_arb +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field1.wr_en_data_arb ANNOTATION: "VC_COV_UNR" Condition 1 "505266581" "(we | de) 1 -1" (2 "01") CHECKSUM: "2099741489 3636044484" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2.wr_en_data_arb +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field2.wr_en_data_arb ANNOTATION: "VC_COV_UNR" Condition 1 "505266581" "(we | de) 1 -1" (2 "01") ANNOTATION: "VC_COV_UNR" @@ -5144,15 +5144,15 @@ Condition 2 "2306794614" "((de ? d : q) & (we ? ((~wd)) : '1)) 1 -1" (3 "11") ANNOTATION: "VC_COV_UNR" Condition 3 "2289961458" "(de ? d : q) 1 -1" (2 "1") CHECKSUM: "2099741489 1283100255" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6.wr_en_data_arb +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field6.wr_en_data_arb ANNOTATION: "VC_COV_UNR" Condition 1 "505266581" "(we | de) 1 -1" (2 "01") CHECKSUM: "2099741489 1077956591" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0.wr_en_data_arb +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field0.wr_en_data_arb ANNOTATION: "VC_COV_UNR" Condition 1 "505266581" "(we | de) 1 -1" (2 "01") CHECKSUM: "2099741489 4164822555" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1.wr_en_data_arb +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field1.wr_en_data_arb ANNOTATION: "VC_COV_UNR" Condition 1 "505266581" "(we | de) 1 -1" (2 "01") CHECKSUM: "662936270 2081652359" @@ -5774,7 +5774,7 @@ Condition 5 "3619927060" "(wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPt ANNOTATION: "VC_COV_UNR" Condition 7 "4040012966" "(full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))) 1 -1" (2 "1") CHECKSUM: "3171246264 3336016746" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic +INSTANCE: tb.dut.u_otp ANNOTATION: "VC_COV_UNR" Branch 3 "1554177250" "state_q" (1) "state_q ResetSt ,1,0,-,-,-,-,-,-,-,-,-,-" ANNOTATION: "VC_COV_UNR" @@ -5788,85 +5788,85 @@ INSTANCE: tb.dut.u_reg_core.u_socket ANNOTATION: "VC_COV_UNR" Branch 4 "3202860295" "(!rst_ni)" (2) "(!rst_ni) 0,1,0,-" CHECKSUM: "4255502330 3554514034" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field3 ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (0) "wr_en 1" ANNOTATION: "VC_COV_UNR" Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" CHECKSUM: "4255502330 3554514034" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field4 ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (0) "wr_en 1" ANNOTATION: "VC_COV_UNR" Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" CHECKSUM: "4255502330 3554514034" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field5 ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (0) "wr_en 1" ANNOTATION: "VC_COV_UNR" Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" CHECKSUM: "4255502330 3554514034" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field6 ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (0) "wr_en 1" ANNOTATION: "VC_COV_UNR" Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" CHECKSUM: "4255502330 3554514034" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field7 ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (0) "wr_en 1" ANNOTATION: "VC_COV_UNR" Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" CHECKSUM: "4255502330 3554514034" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field8 ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (0) "wr_en 1" ANNOTATION: "VC_COV_UNR" Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" CHECKSUM: "4255502330 3554514034" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field2 ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (0) "wr_en 1" ANNOTATION: "VC_COV_UNR" Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" CHECKSUM: "4255502330 3554514034" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field3 ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (0) "wr_en 1" ANNOTATION: "VC_COV_UNR" Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" CHECKSUM: "4255502330 3554514034" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field4 ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (0) "wr_en 1" ANNOTATION: "VC_COV_UNR" Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" CHECKSUM: "4255502330 3554514034" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field5 ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (0) "wr_en 1" ANNOTATION: "VC_COV_UNR" Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" CHECKSUM: "4255502330 3554514034" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field0 ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (0) "wr_en 1" ANNOTATION: "VC_COV_UNR" Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" CHECKSUM: "4255502330 3554514034" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field1 ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (0) "wr_en 1" ANNOTATION: "VC_COV_UNR" Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" CHECKSUM: "4255502330 3554514034" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field2 ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (0) "wr_en 1" ANNOTATION: "VC_COV_UNR" Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" CHECKSUM: "4255502330 3554514034" -INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3 +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field3 ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (0) "wr_en 1" ANNOTATION: "VC_COV_UNR" diff --git a/hw/ip/otp_ctrl/dv/env/otp_ctrl_if.sv b/hw/ip/otp_ctrl/dv/env/otp_ctrl_if.sv index a2ae621cdbf53..39b76d4bbaf49 100644 --- a/hw/ip/otp_ctrl/dv/env/otp_ctrl_if.sv +++ b/hw/ip/otp_ctrl/dv/env/otp_ctrl_if.sv @@ -32,7 +32,7 @@ `ifndef PRIM_GENERIC_OTP_CMD_I_PATH `define PRIM_GENERIC_OTP_CMD_I_PATH \ - `PRIM_GENERIC_OTP_PATH.gen_generic.u_impl_generic.cmd_i + `PRIM_GENERIC_OTP_PATH.cmd_i `endif interface otp_ctrl_if(input clk_i, input rst_ni); diff --git a/hw/ip/otp_ctrl/dv/tb.sv b/hw/ip/otp_ctrl/dv/tb.sv index e1b2664699ee9..efab27344366e 100644 --- a/hw/ip/otp_ctrl/dv/tb.sv +++ b/hw/ip/otp_ctrl/dv/tb.sv @@ -180,10 +180,10 @@ module tb; if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_impl_generic `define MEM_MODULE_PATH \ - tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv + tb.dut.u_otp.u_prim_ram_1p_adv `define MEM_ARRAY_PATH \ - `MEM_MODULE_PATH.u_mem.gen_generic.u_impl_generic.mem + `MEM_MODULE_PATH.u_mem.mem initial begin : mem_bkdr_util_gen mem_bkdr_util m_mem_bkdr_util; diff --git a/hw/ip/otp_ctrl/otp_ctrl.core b/hw/ip/otp_ctrl/otp_ctrl.core index 302558501b050..f94c950317da6 100644 --- a/hw/ip/otp_ctrl/otp_ctrl.core +++ b/hw/ip/otp_ctrl/otp_ctrl.core @@ -25,6 +25,8 @@ filesets: - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:edn_pkg - lowrisc:prim:sparse_fsm + # TODO: prim_pkg is deprecated + - lowrisc:prim:prim_pkg - "fileset_partner ? (partner:systems:ast_pkg)" - "!fileset_partner ? (lowrisc:systems:ast_pkg)" files: diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl.sv index 5558e2ac0960d..1b4deaefa996d 100644 --- a/hw/ip/otp_ctrl/rtl/otp_ctrl.sv +++ b/hw/ip/otp_ctrl/rtl/otp_ctrl.sv @@ -1563,8 +1563,8 @@ end `endif if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_reg_we_assert_generic `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(PrimFsmCheck_A, - u_otp.gen_generic.u_impl_generic.u_state_regs, alert_tx_o[3]) + u_otp.u_state_regs, alert_tx_o[3]) `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(PrimRegWeOnehotCheck_A, - u_otp.gen_generic.u_impl_generic.u_reg_top, alert_tx_o[3]) + u_otp.u_reg_top, alert_tx_o[3]) end endmodule : otp_ctrl diff --git a/hw/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson b/hw/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson index 9f2e9c6fd842e..29a6550735c7a 100644 --- a/hw/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson +++ b/hw/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson @@ -11,12 +11,12 @@ build_modes: [ { name: vcs_crypto_dpi_prince_build_opts - build_opts: ["-CFLAGS -I{build_dir}/src/{crypto_prince_ref_src_dir}"] + build_opts: ["-CFLAGS -I{build_dir}/fusesoc-work/src/{crypto_prince_ref_src_dir}"] } { name: xcelium_crypto_dpi_prince_build_opts - build_opts: ["-I{build_dir}/src/{crypto_prince_ref_src_dir}"] + build_opts: ["-I{build_dir}/fusesoc-work/src/{crypto_prince_ref_src_dir}"] } ] } diff --git a/hw/ip/prim/prim.core b/hw/ip/prim/prim.core index 5aa7a57ca5224..8801e4b1ab7df 100644 --- a/hw/ip/prim/prim.core +++ b/hw/ip/prim/prim.core @@ -13,7 +13,6 @@ filesets: - lowrisc:prim:util - lowrisc:prim:diff_decode # for prim_alert_sender/receiver - lowrisc:prim:pad_wrapper - - lowrisc:prim:prim_pkg - lowrisc:prim:clock_mux2 - lowrisc:prim:clock_inv - lowrisc:prim:buf diff --git a/hw/ip/prim/prim_and2.core b/hw/ip/prim/prim_and2.core deleted file mode 100644 index 10cfee5c45a08..0000000000000 --- a/hw/ip/prim/prim_and2.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:and2" -description: "Generic 2-input and" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - lowrisc:prim:assert - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_and2.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: and2 - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_buf.core b/hw/ip/prim/prim_buf.core deleted file mode 100644 index 9f10e8d67082c..0000000000000 --- a/hw/ip/prim/prim_buf.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:buf" -description: "Generic buffer" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - lowrisc:prim:assert - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_buf.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: buf - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_clock_buf.core b/hw/ip/prim/prim_clock_buf.core deleted file mode 100644 index 54b95ae1bf6d8..0000000000000 --- a/hw/ip/prim/prim_clock_buf.core +++ /dev/null @@ -1,47 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:clock_buf" -description: "Generic clock buffer" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - lowrisc:prim:assert - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_clock_buf.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: clock_buf - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_clock_div.core b/hw/ip/prim/prim_clock_div.core deleted file mode 100644 index 954f08d185062..0000000000000 --- a/hw/ip/prim/prim_clock_div.core +++ /dev/null @@ -1,46 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:clock_div" -description: "Generic clock divide" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_clock_div.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: clock_div - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_clock_gating.core b/hw/ip/prim/prim_clock_gating.core deleted file mode 100644 index 04cf68bd1ece7..0000000000000 --- a/hw/ip/prim/prim_clock_gating.core +++ /dev/null @@ -1,47 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:clock_gating" -description: "Clock gating primitives" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_clock_gating.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: clock_gating - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_clock_inv.core b/hw/ip/prim/prim_clock_inv.core deleted file mode 100644 index a6dcab935a14c..0000000000000 --- a/hw/ip/prim/prim_clock_inv.core +++ /dev/null @@ -1,47 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:clock_inv" -description: "Clock inverter with scanmode bypass mux" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_clock_inv.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: clock_inv - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_clock_mux2.core b/hw/ip/prim/prim_clock_mux2.core deleted file mode 100644 index 5f703aded3eed..0000000000000 --- a/hw/ip/prim/prim_clock_mux2.core +++ /dev/null @@ -1,47 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:clock_mux2" -description: "2-input clock multiplexer" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_clock_mux2.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: clock_mux2 - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_flash.core b/hw/ip/prim/prim_flash.core deleted file mode 100644 index 7e293a1dde4aa..0000000000000 --- a/hw/ip/prim/prim_flash.core +++ /dev/null @@ -1,52 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:flash" -description: "Flash memory" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - # TODO olofk/fusesoc#404: The below dependency is already added to prim_generic_flash.core. - # However, the generator for the prim:ram1p does not kick in, causing compile errors. - - lowrisc:prim:ram_1p - - lowrisc:prim:clock_inv - - lowrisc:prim:clock_gating - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_flash.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: flash - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_flop.core b/hw/ip/prim/prim_flop.core deleted file mode 100644 index b707f1c473ece..0000000000000 --- a/hw/ip/prim/prim_flop.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:flop" -description: "Generic flop" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - lowrisc:prim:assert - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_flop.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: flop - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_flop_2sync.core b/hw/ip/prim/prim_flop_2sync.core deleted file mode 100644 index 698580be257df..0000000000000 --- a/hw/ip/prim/prim_flop_2sync.core +++ /dev/null @@ -1,47 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:flop_2sync" -description: "Flop-based synchronizer" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_flop_2sync.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: flop_2sync - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_flop_en.core b/hw/ip/prim/prim_flop_en.core deleted file mode 100644 index 608384d18be81..0000000000000 --- a/hw/ip/prim/prim_flop_en.core +++ /dev/null @@ -1,47 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:flop_en" -description: "Generic enable flop" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_flop_en.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: flop_en - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/util/primgen/prim_pkg.core.tpl b/hw/ip/prim/prim_legacy_pkg.core similarity index 65% rename from hw/ip/prim/util/primgen/prim_pkg.core.tpl rename to hw/ip/prim/prim_legacy_pkg.core index b51a34c5e00fc..ff442985789af 100644 --- a/hw/ip/prim/util/primgen/prim_pkg.core.tpl +++ b/hw/ip/prim/prim_legacy_pkg.core @@ -2,13 +2,16 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:prim_abstract:prim_pkg:0.1" -description: "Constants used by the primitives" + +name: "lowrisc:prim:prim_legacy_pkg" +description: "Legacy prim_pkg core for old enums" +virtual: + - lowrisc:prim:prim_pkg filesets: files_rtl: files: - - prim_pkg.sv + - rtl/prim_legacy_pkg.sv file_type: systemVerilogSource targets: diff --git a/hw/ip/prim/prim_onehot_check.core b/hw/ip/prim/prim_onehot_check.core index ed8a7aaf17e6a..35643db4e4957 100644 --- a/hw/ip/prim/prim_onehot_check.core +++ b/hw/ip/prim/prim_onehot_check.core @@ -10,8 +10,6 @@ filesets: depend: - lowrisc:prim:util - lowrisc:prim:assert - # TODO: remove then #13337 is resolved. - - lowrisc:prim:prim_pkg files: - rtl/prim_onehot_check.sv file_type: systemVerilogSource diff --git a/hw/ip/prim/prim_otp.core b/hw/ip/prim/prim_otp.core deleted file mode 100644 index 90d0eca468171..0000000000000 --- a/hw/ip/prim/prim_otp.core +++ /dev/null @@ -1,50 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:otp" -description: "One-Time Programmable (OTP) memory" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - # TODO(#6604): these two dependencies are needed to - # make sure the corresponding prims are generated by primgen. - - lowrisc:prim:clock_gating - - lowrisc:prim:clock_inv - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_otp.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: otp - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_pad_attr.core b/hw/ip/prim/prim_pad_attr.core deleted file mode 100644 index 10219fbfcb9fc..0000000000000 --- a/hw/ip/prim/prim_pad_attr.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:pad_attr" -description: "PAD wrapper attributes" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:pad_wrapper_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_pad_attr.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: pad_attr - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_pad_wrapper.core b/hw/ip/prim/prim_pad_wrapper.core deleted file mode 100644 index e700faf1ce605..0000000000000 --- a/hw/ip/prim/prim_pad_wrapper.core +++ /dev/null @@ -1,49 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:pad_wrapper" -description: "PAD wrapper" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:pad_wrapper_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_pad_wrapper.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: pad_wrapper - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_pkg.core b/hw/ip/prim/prim_pkg.core deleted file mode 100644 index eea8326962f1e..0000000000000 --- a/hw/ip/prim/prim_pkg.core +++ /dev/null @@ -1,23 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:prim:prim_pkg:0.1" -description: "Constants used by the primitives" -filesets: - primgen_dep: - depend: - - lowrisc:prim:primgen - -generate: - impl: - generator: primgen - parameters: - action: generate_prim_pkg - -targets: - default: - filesets: - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_ram_1p.core b/hw/ip/prim/prim_ram_1p.core deleted file mode 100644 index b12882c61c3a3..0000000000000 --- a/hw/ip/prim/prim_ram_1p.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:ram_1p" -description: "1 port random-access memory" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:ram_1p_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_ram_1p.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: ram_1p - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_ram_1r1w.core b/hw/ip/prim/prim_ram_1r1w.core deleted file mode 100644 index 18acb86209730..0000000000000 --- a/hw/ip/prim/prim_ram_1r1w.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:ram_1r1w" -description: "Random-access memory with 1 read-only port and 1 write-only port" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:ram_2p_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_ram_1r1w.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: ram_1r1w - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_ram_2p.core b/hw/ip/prim/prim_ram_2p.core deleted file mode 100644 index 696c2248d689b..0000000000000 --- a/hw/ip/prim/prim_ram_2p.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:ram_2p" -description: "2 port random-access memory" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:ram_2p_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_ram_2p.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: ram_2p - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_rom.core b/hw/ip/prim/prim_rom.core deleted file mode 100644 index 0aa76a4e310e0..0000000000000 --- a/hw/ip/prim/prim_rom.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:rom" -description: "Read-only memory (ROM)" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:rom_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_rom.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: rom - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_rst_sync.core b/hw/ip/prim/prim_rst_sync.core index 9657f877164e0..4821bddc958ee 100644 --- a/hw/ip/prim/prim_rst_sync.core +++ b/hw/ip/prim/prim_rst_sync.core @@ -8,9 +8,7 @@ description: "Primitive Reset synchronizer" filesets: files_rtl: depend: - - lowrisc:prim:prim_pkg - # Needed because the generic prim_flop_2sync has a - # dependency on prim:flop. + - lowrisc:prim:clock_mux2 - lowrisc:prim:flop_2sync - lowrisc:prim:mubi - lowrisc:prim:cdc_rand_delay diff --git a/hw/ip/prim/prim_usb_diff_rx.core b/hw/ip/prim/prim_usb_diff_rx.core deleted file mode 100644 index c323df0a2acab..0000000000000 --- a/hw/ip/prim/prim_usb_diff_rx.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:usb_diff_rx" -description: "Differential receiver for USB." -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - lowrisc:prim:assert - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_usb_diff_rx.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: usb_diff_rx - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_xnor2.core b/hw/ip/prim/prim_xnor2.core deleted file mode 100644 index becb3067a26f2..0000000000000 --- a/hw/ip/prim/prim_xnor2.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:xnor2" -description: "Generic 2-input xnor" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - lowrisc:prim:assert - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_xnor2.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: xnor2 - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_xor2.core b/hw/ip/prim/prim_xor2.core deleted file mode 100644 index 7bf51d9f4c16e..0000000000000 --- a/hw/ip/prim/prim_xor2.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:xor2" -description: "Generic 2-input xor" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - lowrisc:prim:assert - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_xor2.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: xor2 - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/primgen.core b/hw/ip/prim/primgen.core deleted file mode 100644 index 167f7965937d0..0000000000000 --- a/hw/ip/prim/primgen.core +++ /dev/null @@ -1,10 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:prim:primgen:0.1" - -generators: - primgen: - interpreter: python3 - command: util/primgen.py diff --git a/hw/ip/prim/util/primgen/prim_pkg.sv.tpl b/hw/ip/prim/rtl/prim_legacy_pkg.sv similarity index 53% rename from hw/ip/prim/util/primgen/prim_pkg.sv.tpl rename to hw/ip/prim/rtl/prim_legacy_pkg.sv index def5d496250c0..0f8c114d38c43 100644 --- a/hw/ip/prim/util/primgen/prim_pkg.sv.tpl +++ b/hw/ip/prim/rtl/prim_legacy_pkg.sv @@ -2,14 +2,21 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // -// Constants for use in primitives - -// This file is auto-generated. +// Legacy constants that were used in some IPs +// These are deprecated and should be removed. package prim_pkg; // Implementation target specialization typedef enum integer { - ${',\n '.join(techlib_enums)} + ImplGeneric, + ImplXilinx, + ImplBadbit, + ImplXilinx_ultrascale } impl_e; + + `ifndef PRIM_DEFAULT_IMPL + `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric + `endif + endpackage : prim_pkg diff --git a/hw/ip/prim/util/primgen.py b/hw/ip/prim/util/primgen.py deleted file mode 100755 index 3e3ba4123d4df..0000000000000 --- a/hw/ip/prim/util/primgen.py +++ /dev/null @@ -1,497 +0,0 @@ -#!/usr/bin/env python3 -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -import os -import re -import shutil -import sys - -import yaml -from mako.template import Template - -# Make vendored packages available in the search path. -sys.path.append(os.path.join(os.path.dirname(__file__), 'vendor')) - -try: - from yaml import CSafeDumper as YamlDumper - from yaml import CSafeLoader as YamlLoader -except ImportError: - from yaml import SafeDumper as YamlDumper - from yaml import SafeLoader as YamlLoader - - -def _split_vlnv(core_vlnv): - (vendor, library, name, version) = core_vlnv.split(':', 4) - return { - 'vendor': vendor, - 'library': library, - 'name': name, - 'version': version - } - - -def _prim_cores(cores, prim_name=None): - """ Get all cores of primitives found by fusesoc - - If prim_name is given, only primitives with the given name are returned. - Otherwise, all primitives are returned, independent of their name. - """ - - def _filter_primitives(core): - """ Filter a list of cores to find the primitives we're interested in - - Matching cores follow the pattern - "lowrisc:prim_:", where "" and - "" are placeholders. - """ - - vlnv = _split_vlnv(core[0]) - if (vlnv['vendor'] == 'lowrisc' and - vlnv['library'].startswith('prim_') and - (prim_name is None or vlnv['name'] == prim_name)): - - return core - return None - - return dict(filter(_filter_primitives, cores.items())) - - -def _techlibs(prim_cores): - techlibs = set() - for name, info in prim_cores.items(): - vlnv = _split_vlnv(name) - techlibs.add(_library_to_techlib_name(vlnv['library'])) - return techlibs - - -def _library_to_techlib_name(library): - return library[len("prim_"):] - - -def _core_info_for_techlib(prim_cores, techlib): - for name, info in prim_cores.items(): - vlnv = _split_vlnv(name) - if _library_to_techlib_name(vlnv['library']) == techlib: - return (name, info) - - -def _enum_name_for_techlib(techlib_name, qualified=True): - name = "Impl" + techlib_name.capitalize() - if qualified: - name = "prim_pkg::" + name - return name - - -def _top_module_file(core_files, module_name): - module_filename = module_name + '.sv' - for file in core_files: - if os.path.basename(file) == module_filename: - return file - - -def _parse_module_header_verible(generic_impl_filepath, module_name): - """ Parse a SystemVerilog file to extract the 'module' header using Verible - - Implementation of _parse_module_header() which uses verible-verilog-syntax - to do the parsing. This is the primary implementation and is used when - supported Verible version is available. - - See _parse_module_header() for API details. - """ - - from google_verible_verilog_syntax_py.verible_verilog_syntax import ( - PreOrderTreeIterator, VeribleVerilogSyntax) - - parser = VeribleVerilogSyntax() - - data = parser.parse_file(generic_impl_filepath, - options={"skip_null": True}) - if data.errors: - for err in data.errors: - print( - f'Verible: {err.phase} error in line {err.line} column {err.column}' + - (': {err.message}' if err.message else '.')) - # Intentionally not raising an exception here. - # There are chances that Verible recovered from errors. - if not data.tree: - raise ValueError(f"Unable to parse {generic_impl_filepath!r}.") - - module = data.tree.find({"tag": "kModuleDeclaration"}) - header = module.find({"tag": "kModuleHeader"}) - if not header: - raise ValueError("Unable to extract module header from %s." % - (generic_impl_filepath, )) - - name = header.find({"tag": ["SymbolIdentifier", "EscapedIdentifier"]}, - iter_=PreOrderTreeIterator) - if not name: - raise ValueError("Unable to extract module name from %s." % - (generic_impl_filepath, )) - - imports = header.find_all({"tag": "kPackageImportDeclaration"}) - - parameters_list = header.find({"tag": "kFormalParameterList"}) - parameters = set() - if parameters_list: - for parameter in sorted( - parameters_list.iter_find_all({"tag": "kParamDeclaration"})): - if parameter.find({"tag": "parameter"}): - parameter_id = parameter.find( - {"tag": ["SymbolIdentifier", "EscapedIdentifier"]}) - parameters.add(parameter_id.text) - - ports = header.find({"tag": "kPortDeclarationList"}) - - return { - 'module_header': header.text, - 'package_import_declaration': '\n'.join([i.text for i in imports]), - 'parameter_port_list': parameters_list.text if parameters_list else '', - 'ports': ports.text if ports else '', - 'parameters': parameters, - 'parser': 'Verible' - } - - -def _parse_module_header_fallback(generic_impl_filepath, module_name): - """ Parse a SystemVerilog file to extract the 'module' header using RegExp - - Legacy implementation of _parse_module_header() using regular expressions. - It is not as robust as Verible-backed implementation, but doesn't need - Verible to work. - - See _parse_module_header() for API details. - """ - - # Grammar fragments from the SV2017 spec: - # - # module_nonansi_header ::= - # { attribute_instance } module_keyword [ lifetime ] module_identifier - # { package_import_declaration } [ parameter_port_list ] list_of_ports ; - # module_ansi_header ::= - # { attribute_instance } module_keyword [ lifetime ] module_identifier - # { package_import_declaration }1 [ parameter_port_list ] [ list_of_port_declarations ] - # package_import_declaration ::= - # import package_import_item { , package_import_item } ; - # package_import_item ::= - # package_identifier :: identifier - # | package_identifier :: * - - RE_MODULE_HEADER = ( - r'(?:\s|^)' - r'(?P' # start: capture the whole module header - r'module\s+' # module_keyword - r'(?:(?:static|automatic)\s+)?' + # lifetime (optional) - module_name + # module_identifier - # package_import_declaration (optional, skipped) - r'\s*(?P(?:import\s+[^;]+;)+)?' - r'\s*(?:#\s*\((?P[^;]+)\))?' # parameter_port_list (optional) - r'\s*\(\s*(?P[^;]+)\s*\)' # list_of_port_declarations or list_of_ports - r'\s*;' # trailing semicolon - r')' # end: capture the whole module header - ) - - data = "" - with open(generic_impl_filepath, encoding="utf-8") as file: - data = file.read() - re_module_header = re.compile(RE_MODULE_HEADER, re.DOTALL) - matches = re_module_header.search(data) - if not matches: - raise ValueError("Unable to extract module header from %s." % - (generic_impl_filepath, )) - - parameter_port_list = matches.group('parameter_port_list') or '' - return { - 'module_header': - matches.group('module_header').strip(), - 'package_import_declaration': - matches.group('package_import_declaration') or '', - 'parameter_port_list': - parameter_port_list, - 'ports': - matches.group('ports').strip() or '', - 'parameters': - _parse_parameter_port_list(parameter_port_list), - 'parser': - 'Fallback (regex)' - } - - -def test_parse_parameter_port_list(): - assert _parse_parameter_port_list("parameter enum_t P") == {'P'} - assert _parse_parameter_port_list("parameter integer P") == {'P'} - assert _parse_parameter_port_list("parameter logic [W-1:0] P") == {'P'} - assert _parse_parameter_port_list("parameter logic [W-1:0] P = '0") == { - 'P' - } - assert _parse_parameter_port_list("parameter logic [W-1:0] P = 'b0") == { - 'P' - } - assert _parse_parameter_port_list("parameter logic [W-1:0] P = 2'd0") == { - 'P' - } - - -def _parse_parameter_port_list(parameter_port_list): - """ Parse a list of ports in a module header into individual parameters """ - - # Grammar (SV2017): - # - # parameter_port_list ::= - # # ( list_of_param_assignments { , parameter_port_declaration } ) - # | # ( parameter_port_declaration { , parameter_port_declaration } ) - # | #( ) - # parameter_port_declaration ::= - # parameter_declaration - # | local_parameter_declaration - # | data_type list_of_param_assignments - # | type list_of_type_assignments - - # XXX: Not covering the complete grammar, e.g. `parameter x, y` - RE_PARAMS = ( - r'parameter\s+' - r'(?:[a-zA-Z0-9_\]\[:\s\$-]+\s+)?' # type - r'(?P\w+)' # name - r'(?:\s*=\s*[^,;]+)?' # initial value - ) - re_params = re.compile(RE_PARAMS) - parameters = set() - for m in re_params.finditer(parameter_port_list): - parameters.add(m.group('name')) - return list(sorted(parameters)) - - -def _parse_module_header(generic_impl_filepath, module_name): - """ Parse a SystemVerilog file to extract the 'module' header - - Return a dict with the following entries: - - module_header: the whole module header (including the 'module' keyword) - - package_import_declaration: import declarations - - parameter_port_list: parameter/localparam declarations in the header - - ports: the list of ports. The portlist can be ANSI or non-ANSI style (with - or without signal declarations; see the SV spec for details). - - parser: parser used to extract the data. - """ - - try: - return _parse_module_header_verible(generic_impl_filepath, module_name) - except Exception as e: - print(e) - print("Verible parser failed, using regex fallback instead.") - return _parse_module_header_fallback(generic_impl_filepath, - module_name) - - -def _check_gapi(gapi): - if 'cores' not in gapi: - print("Key 'cores' not found in GAPI structure. " - "Install a compatible version with " - "'pip3 install --user -r python-requirements.txt'.") - return False - return True - - -def _generate_prim_pkg(gapi): - all_prim_cores = _prim_cores(gapi['cores']) - techlibs = _techlibs(all_prim_cores) - - techlib_enums = [] - - # Insert the required generic library first to ensure it gets enum value 0 - techlib_enums.append(_enum_name_for_techlib('generic', qualified=False)) - - for techlib in techlibs: - if techlib == 'generic': - # The generic implementation is required and handled separately. - continue - techlib_enums.append(_enum_name_for_techlib(techlib, qualified=False)) - - # Render prim_pkg.sv file - print("Creating prim_pkg.sv") - prim_pkg_sv_tpl_filepath = os.path.join(os.path.dirname(__file__), - 'primgen', 'prim_pkg.sv.tpl') - prim_pkg_sv_tpl = Template(filename=prim_pkg_sv_tpl_filepath) - - prim_pkg_sv = prim_pkg_sv_tpl.render(encoding="utf-8", - techlib_enums=techlib_enums) - with open('prim_pkg.sv', 'w') as f: - f.write(prim_pkg_sv) - - # Copy prim_pkg.core (no changes needed) - prim_pkg_core_src = os.path.join(os.path.dirname(__file__), 'primgen', - 'prim_pkg.core.tpl') - prim_pkg_core_dest = 'prim_pkg.core' - shutil.copyfile(prim_pkg_core_src, prim_pkg_core_dest) - print("Core file written to %s." % (prim_pkg_core_dest, )) - - -def _instance_sv(prim_name, techlib, parameters): - if not parameters: - s = " prim_{techlib}_{prim_name} u_impl_{techlib} (\n" - else: - s = " prim_{techlib}_{prim_name} #(\n" - s += ",\n".join(" .{p}({p})".format(p=p) for p in parameters) - s += "\n ) u_impl_{techlib} (\n" - s += " .*\n" \ - " );\n" - return s.format(prim_name=prim_name, techlib=techlib) - - -def _create_instances(prim_name, techlibs, parameters): - """ Build SystemVerilog code instantiating primitives from the techlib """ - - # Sort list of technology libraries to produce a stable ordering in the - # generated wrapper. - techlibs_wo_generic = sorted( - [techlib for techlib in techlibs if techlib != 'generic']) - techlibs_generic_last = techlibs_wo_generic + ['generic'] - - if not techlibs_wo_generic: - # Don't output the if/else blocks if there no alternatives exist. - # We still want the generate block to keep hierarchical path names - # stable, even if more than one techlib is found. - s = " if (1) begin : gen_generic\n" - s += _instance_sv(prim_name, "generic", parameters) + "\n" - s += " end" - return s - - nr_techlibs = len(techlibs_generic_last) - out = "" - for pos, techlib in enumerate(techlibs_generic_last): - is_first = pos == 0 - is_last = pos == nr_techlibs - 1 - - s = "" - if not is_first: - s += "else " - if not is_last: - s += "if (Impl == {techlib_enum}) " - - # TODO: wildcard port lists are against our style guide, but it's safer - # to let the synthesis tool figure out the connectivity than us trying - # to parse the port list into individual signals. - s += "begin : gen_{techlib}\n" + _instance_sv(prim_name, techlib, - parameters) + "end" - - if not is_last: - s += " " - - out += s.format(prim_name=prim_name, - techlib=techlib, - techlib_enum=_enum_name_for_techlib(techlib)) - return out - - -def _generate_abstract_impl(gapi): - prim_name = gapi['parameters']['prim_name'] - prim_cores = _prim_cores(gapi['cores'], prim_name) - - techlibs = _techlibs(prim_cores) - - if 'generic' not in techlibs: - raise ValueError("Techlib generic is required, but not found for " - "primitive %s." % prim_name) - print("Implementations for primitive %s: %s" % - (prim_name, ', '.join(techlibs))) - - # Extract port list out of generic implementation - generic_core = _core_info_for_techlib(prim_cores, 'generic')[1] - generic_module_name = 'prim_generic_' + prim_name - top_module_filename = _top_module_file(generic_core['files'], - generic_module_name) - top_module_file = os.path.join(generic_core['core_root'], - top_module_filename) - - print("Inspecting generic module %s" % (top_module_file, )) - generic_hdr = _parse_module_header(top_module_file, generic_module_name) - - # Render abstract primitive HDL from template - print("Creating SystemVerilog module for abstract primitive") - abstract_prim_sv_tpl_filepath = os.path.join(os.path.dirname(__file__), - 'primgen', - 'abstract_prim.sv.tpl') - abstract_prim_sv_tpl = Template(filename=abstract_prim_sv_tpl_filepath) - - abstract_prim_sv = abstract_prim_sv_tpl.render( - encoding="utf-8", - prim_name=prim_name, - module_header_imports=generic_hdr['package_import_declaration'], - module_header_params=generic_hdr['parameter_port_list'], - module_header_ports=generic_hdr['ports'], - num_techlibs=len(techlibs), - # Creating the code to instantiate the primitives in the Mako templating - # language is tricky to do; do it in Python instead. - instances=_create_instances(prim_name, techlibs, - generic_hdr['parameters']), - parser_info=generic_hdr['parser']) - abstract_prim_sv_filepath = 'prim_%s.sv' % (prim_name) - with open(abstract_prim_sv_filepath, 'w') as f: - f.write(abstract_prim_sv) - print("Abstract primitive written to %s" % - (os.path.abspath(abstract_prim_sv_filepath), )) - - # Create core file depending on all primitive implementations we have in the - # techlibs. - print("Creating core file for primitive %s." % (prim_name, )) - abstract_prim_core_filepath = os.path.abspath('prim_%s.core' % (prim_name)) - dependencies = [] - dependencies.append('lowrisc:prim:prim_pkg') - dependencies += [ - _core_info_for_techlib(prim_cores, t)[0] for t in techlibs - ] - abstract_prim_core = { - 'name': "lowrisc:prim_abstract:%s" % (prim_name, ), - 'filesets': { - 'files_rtl': { - 'depend': dependencies, - 'files': [ - abstract_prim_sv_filepath, - ], - 'file_type': 'systemVerilogSource' - }, - }, - 'targets': { - 'default': { - 'filesets': [ - 'files_rtl', - ], - }, - }, - } - with open(abstract_prim_core_filepath, 'w') as f: - # FuseSoC requires this line to appear first in the YAML file. - # Inserting this line through the YAML serializer requires ordered dicts - # to be used everywhere, which is annoying syntax-wise on Python <3.7, - # where native dicts are not sorted. - f.write('CAPI=2:\n') - yaml.dump(abstract_prim_core, f, encoding="utf-8", Dumper=YamlDumper) - print("Core file written to %s" % (abstract_prim_core_filepath, )) - - -def _get_action_from_gapi(gapi, default_action): - if 'parameters' in gapi and 'action' in gapi['parameters']: - return gapi['parameters']['action'] - return default_action - - -def main(): - gapi_filepath = sys.argv[1] - with open(gapi_filepath) as f: - gapi = yaml.load(f, Loader=YamlLoader) - - if not _check_gapi(gapi): - sys.exit(1) - - action = _get_action_from_gapi(gapi, 'generate_abstract_impl') - - if action == 'generate_abstract_impl': - return _generate_abstract_impl(gapi) - elif action == 'generate_prim_pkg': - return _generate_prim_pkg(gapi) - else: - raise ValueError("Invalid action: %s" % (action, )) - - -if __name__ == '__main__': - main() diff --git a/hw/ip/prim/util/primgen/abstract_prim.sv.tpl b/hw/ip/prim/util/primgen/abstract_prim.sv.tpl deleted file mode 100644 index 9b3432a3fecea..0000000000000 --- a/hw/ip/prim/util/primgen/abstract_prim.sv.tpl +++ /dev/null @@ -1,33 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// This file is auto-generated. -// Used parser: ${parser_info} - -% if num_techlibs > 1: -`ifndef PRIM_DEFAULT_IMPL - `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric -`endif -% endif - -// This is to prevent AscentLint warnings in the generated -// abstract prim wrapper. These warnings occur due to the .* -// use. TODO: we may want to move these inline waivers -// into a separate, generated waiver file for consistency. -//ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ HIER_BRANCH_NOT_READ -module prim_${prim_name} -${module_header_imports} -#( -${module_header_params} -) ( - ${module_header_ports} -); -% if num_techlibs > 1: - localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL; -% endif - -${instances} - -endmodule -//ri lint_check_on OUTPUT_NOT_DRIVEN INPUT_NOT_READ HIER_BRANCH_NOT_READ diff --git a/hw/ip/prim_generic/prim_generic.core b/hw/ip/prim_generic/prim_generic.core new file mode 100644 index 0000000000000..ca5abc125e81b --- /dev/null +++ b/hw/ip/prim_generic/prim_generic.core @@ -0,0 +1,37 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +name: "lowrisc:prim_generic:all:0.1" +description: "Technology-independent prim library" + +filesets: + files_rtl: + depend: + - lowrisc:prim_generic:and2 + - lowrisc:prim_generic:buf + - lowrisc:prim_generic:clock_buf + - lowrisc:prim_generic:clock_div + - lowrisc:prim_generic:clock_gating + - lowrisc:prim_generic:clock_inv + - lowrisc:prim_generic:clock_mux2 + - lowrisc:prim_generic:flash + - lowrisc:prim_generic:flop + - lowrisc:prim_generic:flop_2sync + - lowrisc:prim_generic:flop_en + - lowrisc:prim_generic:otp + - lowrisc:prim_generic:pad_attr + - lowrisc:prim_generic:pad_wrapper + - lowrisc:prim_generic:ram_1p + - lowrisc:prim_generic:ram_1r1w + - lowrisc:prim_generic:ram_2p + - lowrisc:prim_generic:rom + - lowrisc:prim_generic:usb_diff_rx + - lowrisc:prim_generic:xnor2 + - lowrisc:prim_generic:xor2 + +targets: + default: + filesets: + - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_and2.core b/hw/ip/prim_generic/prim_generic_and2.core index 35bf0a05b8ba6..84ff84b786cb5 100644 --- a/hw/ip/prim_generic/prim_generic_and2.core +++ b/hw/ip/prim_generic/prim_generic_and2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:and2" description: "Generic 2-input and" +virtual: + - lowrisc:prim:and2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_generic/prim_generic_buf.core b/hw/ip/prim_generic/prim_generic_buf.core index 1e9380006dee3..42342e7cfe583 100644 --- a/hw/ip/prim_generic/prim_generic_buf.core +++ b/hw/ip/prim_generic/prim_generic_buf.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:buf" description: "buffer" +virtual: + - lowrisc:prim:buf + filesets: files_rtl: files: diff --git a/hw/ip/prim_generic/prim_generic_clock_buf.core b/hw/ip/prim_generic/prim_generic_clock_buf.core index a0527957ea17d..d9cb24827fbce 100644 --- a/hw/ip/prim_generic/prim_generic_clock_buf.core +++ b/hw/ip/prim_generic/prim_generic_clock_buf.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:clock_buf" description: "clock buffer" +virtual: + - lowrisc:prim:clock_buf + filesets: files_rtl: files: diff --git a/hw/ip/prim_generic/prim_generic_clock_div.core b/hw/ip/prim_generic/prim_generic_clock_div.core index 806654072b0d8..6bd3aee3f0291 100644 --- a/hw/ip/prim_generic/prim_generic_clock_div.core +++ b/hw/ip/prim_generic/prim_generic_clock_div.core @@ -5,10 +5,13 @@ CAPI=2: name: "lowrisc:prim_generic:clock_div" description: "Generic clock divide" +virtual: + - lowrisc:prim:clock_div + filesets: files_rtl: depend: - - lowrisc:prim:prim_pkg + - lowrisc:prim:assert - lowrisc:prim:flop - lowrisc:prim:clock_inv - lowrisc:prim:clock_buf diff --git a/hw/ip/prim_generic/prim_generic_clock_gating.core b/hw/ip/prim_generic/prim_generic_clock_gating.core index c1e878180b117..ce65b1b9e3c87 100644 --- a/hw/ip/prim_generic/prim_generic_clock_gating.core +++ b/hw/ip/prim_generic/prim_generic_clock_gating.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:clock_gating" description: "prim" +virtual: + - lowrisc:prim:clock_gating + filesets: files_rtl: files: diff --git a/hw/ip/prim_generic/prim_generic_clock_inv.core b/hw/ip/prim_generic/prim_generic_clock_inv.core index 4f48b07a98d94..e9982ef38a07c 100644 --- a/hw/ip/prim_generic/prim_generic_clock_inv.core +++ b/hw/ip/prim_generic/prim_generic_clock_inv.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:clock_inv" description: "Clock inverter with scanmode bypass mux" +virtual: + - lowrisc:prim:clock_inv + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_clock_mux2.core b/hw/ip/prim_generic/prim_generic_clock_mux2.core index f4f343d498a7d..7cfca422af065 100644 --- a/hw/ip/prim_generic/prim_generic_clock_mux2.core +++ b/hw/ip/prim_generic/prim_generic_clock_mux2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:clock_mux2" description: "two-input clock multiplexer primitive" +virtual: + - lowrisc:prim:clock_mux2 + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_flash.core b/hw/ip/prim_generic/prim_generic_flash.core index 736caad5944fd..08a6f9b74b09a 100644 --- a/hw/ip/prim_generic/prim_generic_flash.core +++ b/hw/ip/prim_generic/prim_generic_flash.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:flash" description: "prim" +virtual: + - lowrisc:prim:flash + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_flop.core b/hw/ip/prim_generic/prim_generic_flop.core index c66701bc1adb4..162735a9bbc02 100644 --- a/hw/ip/prim_generic/prim_generic_flop.core +++ b/hw/ip/prim_generic/prim_generic_flop.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:flop" description: "generic flop" +virtual: + - lowrisc:prim:flop + filesets: files_rtl: files: diff --git a/hw/ip/prim_generic/prim_generic_flop_2sync.core b/hw/ip/prim_generic/prim_generic_flop_2sync.core index f3159068d6c00..82f2b6e98718d 100644 --- a/hw/ip/prim_generic/prim_generic_flop_2sync.core +++ b/hw/ip/prim_generic/prim_generic_flop_2sync.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:flop_2sync" description: "Generic implementation of a flop-based synchronizer" +virtual: + - lowrisc:prim:flop_2sync + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_flop_en.core b/hw/ip/prim_generic/prim_generic_flop_en.core index 8e39916ee5880..556ee9abec0e8 100644 --- a/hw/ip/prim_generic/prim_generic_flop_en.core +++ b/hw/ip/prim_generic/prim_generic_flop_en.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:flop_en" description: "generic enable flop" +virtual: + - lowrisc:prim:flop_en + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_otp.core b/hw/ip/prim_generic/prim_generic_otp.core index db270f07437e3..054d97a55b251 100644 --- a/hw/ip/prim_generic/prim_generic_otp.core +++ b/hw/ip/prim_generic/prim_generic_otp.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:otp" description: "Technology-independent One-Time Programmable (OTP) memory emulation" +virtual: + - lowrisc:prim:otp + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_pad_attr.core b/hw/ip/prim_generic/prim_generic_pad_attr.core index 0629996c26265..451ae4c8d63eb 100644 --- a/hw/ip/prim_generic/prim_generic_pad_attr.core +++ b/hw/ip/prim_generic/prim_generic_pad_attr.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:pad_attr" description: "Technology-independent pad attribute WARL module (for sim only!)" +virtual: + - lowrisc:prim:pad_attr + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_pad_wrapper.core b/hw/ip/prim_generic/prim_generic_pad_wrapper.core index ab7f0a1c737ba..9e7ffc6ba1d4d 100644 --- a/hw/ip/prim_generic/prim_generic_pad_wrapper.core +++ b/hw/ip/prim_generic/prim_generic_pad_wrapper.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:pad_wrapper" description: "Technology-independent pad wrapper implementation (for sim only!)" +virtual: + - lowrisc:prim:pad_wrapper + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_ram_1p.core b/hw/ip/prim_generic/prim_generic_ram_1p.core index ea3848b121dac..52b98b589910d 100644 --- a/hw/ip/prim_generic/prim_generic_ram_1p.core +++ b/hw/ip/prim_generic/prim_generic_ram_1p.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:ram_1p" description: "Single port RAM" +virtual: + - lowrisc:prim:ram_1p + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_ram_1r1w.core b/hw/ip/prim_generic/prim_generic_ram_1r1w.core index 2cc6529619fb9..302a516a2d566 100644 --- a/hw/ip/prim_generic/prim_generic_ram_1r1w.core +++ b/hw/ip/prim_generic/prim_generic_ram_1r1w.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:ram_1r1w" description: "prim" +virtual: + - lowrisc:prim:ram_1r1w + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_ram_2p.core b/hw/ip/prim_generic/prim_generic_ram_2p.core index 13c411459d11e..7da402948ca41 100644 --- a/hw/ip/prim_generic/prim_generic_ram_2p.core +++ b/hw/ip/prim_generic/prim_generic_ram_2p.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:ram_2p" description: "prim" +virtual: + - lowrisc:prim:ram_2p + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_rom.core b/hw/ip/prim_generic/prim_generic_rom.core index 5bf3b6ce38ea2..32d3cb04e240f 100644 --- a/hw/ip/prim_generic/prim_generic_rom.core +++ b/hw/ip/prim_generic/prim_generic_rom.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:rom" description: "Technology-independent Read-Only Memory (ROM) implementation" +virtual: + - lowrisc:prim:rom + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_usb_diff_rx.core b/hw/ip/prim_generic/prim_generic_usb_diff_rx.core index d1c34a6a04a16..59d18043ab0f8 100644 --- a/hw/ip/prim_generic/prim_generic_usb_diff_rx.core +++ b/hw/ip/prim_generic/prim_generic_usb_diff_rx.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:usb_diff_rx" description: "Generic differential USB receiver for emulation purposes" +virtual: + - lowrisc:prim:usb_diff_rx + filesets: files_rtl: files: diff --git a/hw/ip/prim_generic/prim_generic_xnor2.core b/hw/ip/prim_generic/prim_generic_xnor2.core index 24e3a125e3267..c8e86b4017401 100644 --- a/hw/ip/prim_generic/prim_generic_xnor2.core +++ b/hw/ip/prim_generic/prim_generic_xnor2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:xnor2" description: "Generic 2-input xnor" +virtual: + - lowrisc:prim:xnor2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_generic/prim_generic_xor2.core b/hw/ip/prim_generic/prim_generic_xor2.core index e3cf88c20c430..6d945cef6be27 100644 --- a/hw/ip/prim_generic/prim_generic_xor2.core +++ b/hw/ip/prim_generic/prim_generic_xor2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:xor2" description: "Generic 2-input xor" +virtual: + - lowrisc:prim:xor2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_generic/rtl/prim_generic_and2.sv b/hw/ip/prim_generic/rtl/prim_generic_and2.sv index df1b65fa3b7ca..6a9cca480bfd9 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_and2.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_and2.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_and2 #( +module prim_and2 #( parameter int Width = 1 ) ( input [Width-1:0] in0_i, diff --git a/hw/ip/prim_generic/rtl/prim_generic_buf.sv b/hw/ip/prim_generic/rtl/prim_generic_buf.sv index ede99f1d64062..82517a7cf5b5a 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_buf.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_buf.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_buf #( +module prim_buf #( parameter int Width = 1 ) ( input [Width-1:0] in_i, diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_buf.sv b/hw/ip/prim_generic/rtl/prim_generic_clock_buf.sv index d660aab686bfd..ab39001b55cff 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_clock_buf.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_clock_buf.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_clock_buf #( +module prim_clock_buf #( // Turning off these verilator lints because keeping these parameters makes it consistent with // the IP in hw/ip/prim_xilinx/rtl/ . /* verilator lint_off UNUSED */ @@ -20,4 +20,4 @@ module prim_generic_clock_buf #( assign inv = ~clk_i; assign clk_o = ~inv; -endmodule // prim_generic_clock_buf +endmodule // prim_clock_buf diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_div.sv b/hw/ip/prim_generic/rtl/prim_generic_clock_div.sv index 798aa35ec0e12..ae9fd2c78f3c7 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_clock_div.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_clock_div.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_clock_div #( +module prim_clock_div #( parameter int unsigned Divisor = 2, parameter logic ResetValue = 0 ) ( diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_gating.sv b/hw/ip/prim_generic/rtl/prim_generic_clock_gating.sv index 6f80f6e89baa7..dc092ea56f881 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_clock_gating.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_clock_gating.sv @@ -7,7 +7,7 @@ // The logic assumes that en_i is synchronized (so the instantiation site might need to put a // synchronizer before en_i). -module prim_generic_clock_gating #( +module prim_clock_gating #( parameter bit NoFpgaGate = 1'b0, // this parameter has no function in generic parameter bit FpgaBufGlobal = 1'b1 // this parameter has no function in generic ) ( diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_inv.sv b/hw/ip/prim_generic/rtl/prim_generic_clock_inv.sv index 2f56d3287fa8a..2867dfb88135a 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_clock_inv.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_clock_inv.sv @@ -5,7 +5,7 @@ // Clock inverter // Varies on the process -module prim_generic_clock_inv #( +module prim_clock_inv #( parameter bit HasScanMode = 1'b1, parameter bit NoFpgaBufG = 1'b0 // only used in FPGA case ) ( @@ -29,4 +29,4 @@ module prim_generic_clock_inv #( assign clk_no = ~clk_i; end -endmodule : prim_generic_clock_inv +endmodule : prim_clock_inv diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_mux2.sv b/hw/ip/prim_generic/rtl/prim_generic_clock_mux2.sv index 85418e0da2d49..c9d8a429271ef 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_clock_mux2.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_clock_mux2.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_clock_mux2 #( +module prim_clock_mux2 #( parameter bit NoFpgaBufG = 1'b0 // this parameter serves no function in the generic model ) ( input clk0_i, @@ -22,4 +22,4 @@ module prim_generic_clock_mux2 #( `ASSERT(selKnown0, ##1 !$isunknown(sel_i), clk0_i, 0) `ASSERT(selKnown1, ##1 !$isunknown(sel_i), clk1_i, 0) -endmodule : prim_generic_clock_mux2 +endmodule : prim_clock_mux2 diff --git a/hw/ip/prim_generic/rtl/prim_generic_flash.sv b/hw/ip/prim_generic/rtl/prim_generic_flash.sv index 2349dd8f2e231..f76ed3ac23619 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_flash.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_flash.sv @@ -5,7 +5,7 @@ // Overall flash wrapper // -module prim_generic_flash #( +module prim_flash #( parameter int NumBanks = 2, // number of banks parameter int InfosPerBank = 1, // info pages per bank parameter int InfoTypes = 1, // different info types @@ -143,4 +143,4 @@ module prim_generic_flash #( assign fla_obs_o = '0; -endmodule // prim_generic_flash +endmodule // prim_flash diff --git a/hw/ip/prim_generic/rtl/prim_generic_flash_bank.sv b/hw/ip/prim_generic/rtl/prim_generic_flash_bank.sv index 566a2e8fa2084..4312f3700bf75 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_flash_bank.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_flash_bank.sv @@ -452,4 +452,4 @@ module prim_generic_flash_bank #( logic unused_he; assign unused_he = he_i; -endmodule // prim_generic_flash +endmodule // prim_generic_flash_bank diff --git a/hw/ip/prim_generic/rtl/prim_generic_flop.sv b/hw/ip/prim_generic/rtl/prim_generic_flop.sv index 426b44e042eaf..d2357d2725dc9 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_flop.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_flop.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_flop #( +module prim_flop #( parameter int Width = 1, parameter logic [Width-1:0] ResetValue = 0 ) ( diff --git a/hw/ip/prim_generic/rtl/prim_generic_flop_2sync.sv b/hw/ip/prim_generic/rtl/prim_generic_flop_2sync.sv index c59ae850829fe..8f7864ee04e4c 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_flop_2sync.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_flop_2sync.sv @@ -4,7 +4,7 @@ // // Double-flop-based synchronizer -module prim_generic_flop_2sync #( +module prim_flop_2sync #( parameter int Width = 16, parameter logic [Width-1:0] ResetValue = '0, parameter bit EnablePrimCdcRand = 1 @@ -56,4 +56,4 @@ module prim_generic_flop_2sync #( .q_o ); -endmodule : prim_generic_flop_2sync +endmodule : prim_flop_2sync diff --git a/hw/ip/prim_generic/rtl/prim_generic_flop_en.sv b/hw/ip/prim_generic/rtl/prim_generic_flop_en.sv index 94ca795fca2a1..aaea0ea7a1498 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_flop_en.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_flop_en.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_flop_en #( +module prim_flop_en #( parameter int Width = 1, parameter bit EnSecBuf = 0, parameter logic [Width-1:0] ResetValue = 0 diff --git a/hw/ip/prim_generic/rtl/prim_generic_otp.sv b/hw/ip/prim_generic/rtl/prim_generic_otp.sv index 5fe826d6602bd..ee6f750bf3daa 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_otp.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_otp.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -module prim_generic_otp +module prim_otp import prim_otp_pkg::*; #( // Native OTP word size. This determines the size_i granule. @@ -431,4 +431,4 @@ module prim_generic_otp |-> cmd_i inside {Read, ReadRaw, Write, WriteRaw}) -endmodule : prim_generic_otp +endmodule : prim_otp diff --git a/hw/ip/prim_generic/rtl/prim_generic_pad_attr.sv b/hw/ip/prim_generic/rtl/prim_generic_pad_attr.sv index 80e93f82bcb8f..a79b6a0435d3f 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_pad_attr.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_pad_attr.sv @@ -5,7 +5,7 @@ `include "prim_assert.sv" -module prim_generic_pad_attr +module prim_pad_attr import prim_pad_wrapper_pkg::*; #( parameter pad_type_e PadType = BidirStd // currently ignored in the generic model @@ -68,4 +68,4 @@ module prim_generic_pad_attr assert_static_in_generate_config_not_available(); end -endmodule : prim_generic_pad_attr +endmodule : prim_pad_attr diff --git a/hw/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv b/hw/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv index 7ff382c302a33..47ef644ce5c3b 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv @@ -7,7 +7,7 @@ `include "prim_assert.sv" -module prim_generic_pad_wrapper +module prim_pad_wrapper import prim_pad_wrapper_pkg::*; #( // These parameters are ignored in this model. @@ -120,4 +120,4 @@ module prim_generic_pad_wrapper assert_static_in_generate_config_not_available(); end -endmodule : prim_generic_pad_wrapper +endmodule : prim_pad_wrapper diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv b/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv index d2e835ac33915..ab4b5ca282ad6 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv @@ -6,7 +6,7 @@ `include "prim_assert.sv" -module prim_generic_ram_1p import prim_ram_1p_pkg::*; #( +module prim_ram_1p import prim_ram_1p_pkg::*; #( parameter int Width = 32, // bit parameter int Depth = 128, parameter int DataBitsPerMask = 1, // Number of data bits per bit of write mask diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv b/hw/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv index aafecf8adba8f..292f4df3fe608 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv @@ -6,7 +6,7 @@ // This module is for simulation and small size SRAM. // Implementing ECC should be done inside wrapper not this model. `include "prim_assert.sv" -module prim_generic_ram_1r1w import prim_ram_2p_pkg::*; #( +module prim_ram_1r1w import prim_ram_2p_pkg::*; #( parameter int Width = 32, // bit parameter int Depth = 128, parameter int DataBitsPerMask = 1, // Number of data bits per bit of write mask diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv b/hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv index f44e828bfbf44..2160ba88e607c 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv @@ -6,7 +6,7 @@ // This module is for simulation and small size SRAM. // Implementing ECC should be done inside wrapper not this model. `include "prim_assert.sv" -module prim_generic_ram_2p import prim_ram_2p_pkg::*; #( +module prim_ram_2p import prim_ram_2p_pkg::*; #( parameter int Width = 32, // bit parameter int Depth = 128, parameter int DataBitsPerMask = 1, // Number of data bits per bit of write mask diff --git a/hw/ip/prim_generic/rtl/prim_generic_rom.sv b/hw/ip/prim_generic/rtl/prim_generic_rom.sv index acf5f379ca454..00f531ca1f0f8 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_rom.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_rom.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_rom import prim_rom_pkg::*; #( +module prim_rom import prim_rom_pkg::*; #( parameter int Width = 32, parameter int Depth = 2048, // 8kB default parameter MemInitFile = "", // VMEM file to initialize the memory with diff --git a/hw/ip/prim_generic/rtl/prim_generic_usb_diff_rx.sv b/hw/ip/prim_generic/rtl/prim_generic_usb_diff_rx.sv index a0b8e19c87cb6..a7c7fe00fd8a2 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_usb_diff_rx.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_usb_diff_rx.sv @@ -7,7 +7,7 @@ `include "prim_assert.sv" -module prim_generic_usb_diff_rx #( +module prim_usb_diff_rx #( parameter int CalibW = 32 ) ( inout input_pi, // differential input @@ -47,4 +47,4 @@ module prim_generic_usb_diff_rx #( .out_o (usb_diff_rx_obs_o) ); -endmodule : prim_generic_usb_diff_rx +endmodule : prim_usb_diff_rx diff --git a/hw/ip/prim_generic/rtl/prim_generic_xnor2.sv b/hw/ip/prim_generic/rtl/prim_generic_xnor2.sv index f80869abc99a4..9a64c4dd776b2 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_xnor2.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_xnor2.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_xnor2 #( +module prim_xnor2 #( parameter int Width = 1 ) ( input [Width-1:0] in0_i, diff --git a/hw/ip/prim_generic/rtl/prim_generic_xor2.sv b/hw/ip/prim_generic/rtl/prim_generic_xor2.sv index 4f303c7730a8b..059dd60b2ecc9 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_xor2.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_xor2.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_xor2 #( +module prim_xor2 #( parameter int Width = 1 ) ( input [Width-1:0] in0_i, diff --git a/hw/ip/prim_xilinx/prim_xilinx.core b/hw/ip/prim_xilinx/prim_xilinx.core new file mode 100644 index 0000000000000..bb4891f74eddf --- /dev/null +++ b/hw/ip/prim_xilinx/prim_xilinx.core @@ -0,0 +1,36 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +name: "lowrisc:prim_xilinx:all:0.1" +description: "Xilinx 7-series prim library" + +filesets: + files_rtl: + depend: + - lowrisc:prim_xilinx:and2 + - lowrisc:prim_xilinx:buf + - lowrisc:prim_xilinx:clock_buf + - lowrisc:prim_generic:clock_div + - lowrisc:prim_xilinx:clock_gating + - lowrisc:prim_generic:clock_inv + - lowrisc:prim_xilinx:clock_mux2 + - lowrisc:prim_generic:flash + - lowrisc:prim_xilinx:flop + - lowrisc:prim_generic:flop_2sync + - lowrisc:prim_xilinx:flop_en + - lowrisc:prim_generic:otp + - lowrisc:prim_xilinx:pad_attr + - lowrisc:prim_xilinx:pad_wrapper + - lowrisc:prim_generic:ram_1p + - lowrisc:prim_generic:ram_1r1w + - lowrisc:prim_generic:ram_2p + - lowrisc:prim_generic:rom + - lowrisc:prim_generic:xnor2 + - lowrisc:prim_xilinx:xor2 + +targets: + default: + filesets: + - files_rtl diff --git a/hw/ip/prim_xilinx/prim_xilinx_and2.core b/hw/ip/prim_xilinx/prim_xilinx_and2.core index 9c86c83f4eafa..5db713bd5b3dd 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_and2.core +++ b/hw/ip/prim_xilinx/prim_xilinx_and2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:and2" description: "Xilinx 2-input and" +virtual: + - lowrisc:prim:and2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx/prim_xilinx_buf.core b/hw/ip/prim_xilinx/prim_xilinx_buf.core index bc4e7a2e262bd..d5cd793214d94 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_buf.core +++ b/hw/ip/prim_xilinx/prim_xilinx_buf.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:buf" description: "buffer" +virtual: + - lowrisc:prim:buf + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx/prim_xilinx_clock_buf.core b/hw/ip/prim_xilinx/prim_xilinx_clock_buf.core index f1bfbe8f126b7..b458d4db454f3 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_clock_buf.core +++ b/hw/ip/prim_xilinx/prim_xilinx_clock_buf.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:clock_buf" description: "clock buffer" +virtual: + - lowrisc:prim:clock_buf + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx/prim_xilinx_clock_gating.core b/hw/ip/prim_xilinx/prim_xilinx_clock_gating.core index 587c7e5a3589e..e80bd4a44114a 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_clock_gating.core +++ b/hw/ip/prim_xilinx/prim_xilinx_clock_gating.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:clock_gating" description: "prim" +virtual: + - lowrisc:prim:clock_gating + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core b/hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core index 5d94cd0c71a14..e08e8301d829e 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core +++ b/hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:clock_mux2" description: "two-input clock multiplexer primitive" +virtual: + - lowrisc:prim:clock_mux2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx/prim_xilinx_flop.core b/hw/ip/prim_xilinx/prim_xilinx_flop.core index b94d12c75e912..427449775d7e2 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_flop.core +++ b/hw/ip/prim_xilinx/prim_xilinx_flop.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:flop" description: "Xilinx flop" +virtual: + - lowrisc:prim:flop + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx/prim_xilinx_flop_en.core b/hw/ip/prim_xilinx/prim_xilinx_flop_en.core index e40394b832c6a..0edee3a33f08a 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_flop_en.core +++ b/hw/ip/prim_xilinx/prim_xilinx_flop_en.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:flop_en" description: "Xilinx enable flop" +virtual: + - lowrisc:prim:flop_en + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core b/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core index 6c1031337b918..866ef847ac2c8 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core +++ b/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:pad_attr" description: "Pad attribute WARL module for Xilinx pads" +virtual: + - lowrisc:prim:pad_attr + filesets: files_rtl: depend: diff --git a/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core b/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core index 765845a0bc83f..cba9144762ec8 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core +++ b/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:pad_wrapper" description: "prim" +virtual: + - lowrisc:prim:pad_wrapper + filesets: files_rtl: depend: diff --git a/hw/ip/prim_xilinx/prim_xilinx_xor2.core b/hw/ip/prim_xilinx/prim_xilinx_xor2.core index e7f699cf84ba0..e46943e84115a 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_xor2.core +++ b/hw/ip/prim_xilinx/prim_xilinx_xor2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:xor2" description: "Xilinx 2-input xor" +virtual: + - lowrisc:prim:xor2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_and2.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_and2.sv index 69d8683612d7f..76a0699a018ec 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_and2.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_and2.sv @@ -6,7 +6,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_and2 #( +module prim_and2 #( parameter int Width = 1 ) ( input [Width-1:0] in0_i, diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_buf.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_buf.sv index 7bdeea9cb7976..dd772bbd12ac5 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_buf.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_buf.sv @@ -4,7 +4,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_buf #( +module prim_buf #( parameter int Width = 1 ) ( input [Width-1:0] in_i, diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv index 51945f4402097..0169f74048d62 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -module prim_xilinx_clock_buf #( +module prim_clock_buf #( // The following options allow a user to choose the type of buffer // associated with this cell. // NoFpgaBuf -> No fpga clock buffer is selected, this will be constructed diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv index 7eaac02a07440..99bc6850a2d2f 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -module prim_xilinx_clock_gating #( +module prim_clock_gating #( parameter bit NoFpgaGate = 1'b0, parameter bit FpgaBufGlobal = 1'b1 ) ( diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv index ee7390d9c2765..81066ad40bb14 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_xilinx_clock_mux2 #( +module prim_clock_mux2 #( parameter bit NoFpgaBufG = 1'b0 ) ( input clk0_i, @@ -33,4 +33,4 @@ module prim_xilinx_clock_mux2 #( `ASSERT(selKnown0, ##1 !$isunknown(sel_i), clk0_i, 0) `ASSERT(selKnown1, ##1 !$isunknown(sel_i), clk1_i, 0) -endmodule : prim_xilinx_clock_mux2 +endmodule : prim_clock_mux2 diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv index 45deeadeec8d1..04c8962e5c17f 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv @@ -6,7 +6,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_flop #( +module prim_flop #( parameter int Width = 1, parameter logic [Width-1:0] ResetValue = 0 ) ( diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv index c4de058a91bd2..bc95d39e5c758 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv @@ -6,7 +6,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_flop_en #( +module prim_flop_en #( parameter int Width = 1, // This parmaeter does nothing for prim_xilinx parameter bit EnSecBuf = 0, diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv index 7267465e8c15f..5955d72b18315 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv @@ -5,7 +5,7 @@ `include "prim_assert.sv" -module prim_xilinx_pad_attr +module prim_pad_attr import prim_pad_wrapper_pkg::*; #( // This parameter is ignored in this Xilinx variant. @@ -56,4 +56,4 @@ module prim_xilinx_pad_attr end -endmodule : prim_xilinx_pad_attr +endmodule : prim_pad_attr diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv index afb9c1794e216..4c2a539de9ae1 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv @@ -7,7 +7,7 @@ `include "prim_assert.sv" -module prim_xilinx_pad_wrapper +module prim_pad_wrapper import prim_pad_wrapper_pkg::*; #( // These parameters are ignored in this Xilinx variant. @@ -123,4 +123,4 @@ module prim_xilinx_pad_wrapper assert_static_in_generate_config_not_available(); end -endmodule : prim_xilinx_pad_wrapper +endmodule : prim_pad_wrapper diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv index 0eb9c14235d9e..d00a027eec727 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv @@ -6,7 +6,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_xor2 #( +module prim_xor2 #( parameter int Width = 1 ) ( input [Width-1:0] in0_i, diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale.core new file mode 100644 index 0000000000000..471e14f974c06 --- /dev/null +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale.core @@ -0,0 +1,36 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +name: "lowrisc:prim_xilinx_ultrascale:all:0.1" +description: "Xilinx Ultrascale prim library" + +filesets: + files_rtl: + depend: + - lowrisc:prim_xilinx_ultrascale:and2 + - lowrisc:prim_xilinx_ultrascale:buf + - lowrisc:prim_xilinx_ultrascale:clock_buf + - lowrisc:prim_xilinx_ultrascale:clock_div + - lowrisc:prim_xilinx_ultrascale:clock_gating + - lowrisc:prim_xilinx_ultrascale:clock_inv + - lowrisc:prim_xilinx_ultrascale:clock_mux2 + - lowrisc:prim_generic:flash + - lowrisc:prim_xilinx_ultrascale:flop + - lowrisc:prim_generic:flop_2sync + - lowrisc:prim_xilinx_ultrascale:flop_en + - lowrisc:prim_generic:otp + - lowrisc:prim_xilinx_ultrascale:pad_attr + - lowrisc:prim_xilinx_ultrascale:pad_wrapper + - lowrisc:prim_generic:ram_1p + - lowrisc:prim_generic:ram_1r1w + - lowrisc:prim_generic:ram_2p + - lowrisc:prim_generic:rom + - lowrisc:prim_generic:xnor2 + - lowrisc:prim_xilinx_ultrascale:xor2 + +targets: + default: + filesets: + - files_rtl diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_and2.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_and2.core index 61d31548bff88..ee2214956f8f7 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_and2.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_and2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:and2" description: "Xilinx 2-input and" +virtual: + - lowrisc:prim:and2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_buf.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_buf.core index 11ca450bed127..616e78504f6f8 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_buf.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_buf.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:buf" description: "buffer" +virtual: + - lowrisc:prim:buf + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_buf.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_buf.core index 086ff20487efd..f182ea3d71a18 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_buf.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_buf.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:clock_buf" description: "clock buffer" +virtual: + - lowrisc:prim:clock_buf + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_div.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_div.core index 1a24d8c4ef3e4..af7ee41bb1dee 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_div.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_div.core @@ -5,10 +5,13 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:clock_div" description: "Xilinx ultrascale clock divide" +virtual: + - lowrisc:prim:clock_div + filesets: files_rtl: depend: - - lowrisc:prim:prim_pkg + - lowrisc:prim:assert - lowrisc:prim:flop - lowrisc:prim:clock_inv - lowrisc:prim:clock_buf diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_gating.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_gating.core index 8440287fe548f..26df5f421777c 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_gating.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_gating.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:clock_gating" description: "prim" +virtual: + - lowrisc:prim:clock_gating + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_inv.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_inv.core index da24344f1ebe5..af0561157981f 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_inv.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_inv.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:clock_inv" description: "clock buffer" +virtual: + - lowrisc:prim:clock_inv + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_mux2.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_mux2.core index 8159e4c616eed..642464ca36a61 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_mux2.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_mux2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:clock_mux2" description: "two-input clock multiplexer primitive" +virtual: + - lowrisc:prim:clock_mux2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop.core index a85e3be191a8f..2406237e2e7a3 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:flop" description: "Xilinx flop" +virtual: + - lowrisc:prim:flop + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop_en.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop_en.core index 8b79324323b00..9b0f752c6c030 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop_en.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop_en.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:flop_en" description: "Xilinx enable flop" +virtual: + - lowrisc:prim:flop_en + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_attr.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_attr.core index 4a205e5eb037f..6c99f0177a674 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_attr.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_attr.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:pad_attr" description: "Pad attribute WARL module for Xilinx pads" +virtual: + - lowrisc:prim:pad_attr + filesets: files_rtl: depend: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_wrapper.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_wrapper.core index 4356a9f661db7..623620aeb1a77 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_wrapper.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_wrapper.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:pad_wrapper" description: "prim" +virtual: + - lowrisc:prim:pad_wrapper + filesets: files_rtl: depend: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xor2.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xor2.core index 3b14815dcdfd0..6318ace2a5867 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xor2.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xor2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:xor2" description: "Xilinx 2-input xor" +virtual: + - lowrisc:prim:xor2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_and2.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_and2.sv index a2d3b5fd2769c..76a0699a018ec 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_and2.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_and2.sv @@ -6,7 +6,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_ultrascale_and2 #( +module prim_and2 #( parameter int Width = 1 ) ( input [Width-1:0] in0_i, diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_buf.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_buf.sv index 2a4a7436c32cf..dd772bbd12ac5 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_buf.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_buf.sv @@ -4,7 +4,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_ultrascale_buf #( +module prim_buf #( parameter int Width = 1 ) ( input [Width-1:0] in_i, diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_buf.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_buf.sv index 773505b626317..055cf23d4626c 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_buf.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_buf.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -module prim_xilinx_ultrascale_clock_buf #( +module prim_clock_buf #( parameter bit NoFpgaBuf = 1'b0, parameter bit RegionSel = 1'b0 // serves no function in Ultrascale ) ( diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_div.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_div.sv index 1787584fe2142..fa264d51a4310 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_div.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_div.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_xilinx_ultrascale_clock_div #( +module prim_clock_div #( parameter int unsigned Divisor = 2, parameter logic ResetValue = 0 ) ( diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_gating.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_gating.sv index c554e71eee5f5..ff01102bc9215 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_gating.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_gating.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -module prim_xilinx_ultrascale_clock_gating #( +module prim_clock_gating #( parameter bit NoFpgaGate = 1'b0, parameter bit FpgaBufGlobal = 1'b1 // No function in Ultrascale ) ( diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_inv.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_inv.sv index 581dbc3c35210..1bddcee17acb3 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_inv.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_inv.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -module prim_xilinx_ultrascale_clock_inv #( +module prim_clock_inv #( parameter bit HasScanMode = 1'b1, parameter bit NoFpgaBufG = 1'b0 ) ( diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_mux2.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_mux2.sv index b6341d6edc696..81066ad40bb14 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_mux2.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_mux2.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_xilinx_ultrascale_clock_mux2 #( +module prim_clock_mux2 #( parameter bit NoFpgaBufG = 1'b0 ) ( input clk0_i, @@ -33,4 +33,4 @@ module prim_xilinx_ultrascale_clock_mux2 #( `ASSERT(selKnown0, ##1 !$isunknown(sel_i), clk0_i, 0) `ASSERT(selKnown1, ##1 !$isunknown(sel_i), clk1_i, 0) -endmodule : prim_xilinx_ultrascale_clock_mux2 +endmodule : prim_clock_mux2 diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop.sv index 1cc12692c8405..04c8962e5c17f 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop.sv @@ -6,7 +6,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_ultrascale_flop #( +module prim_flop #( parameter int Width = 1, parameter logic [Width-1:0] ResetValue = 0 ) ( diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop_en.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop_en.sv index f1acacda6f54e..bc95d39e5c758 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop_en.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop_en.sv @@ -6,7 +6,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_ultrascale_flop_en #( +module prim_flop_en #( parameter int Width = 1, // This parmaeter does nothing for prim_xilinx parameter bit EnSecBuf = 0, diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_attr.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_attr.sv index e28b665b2a298..5955d72b18315 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_attr.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_attr.sv @@ -5,7 +5,7 @@ `include "prim_assert.sv" -module prim_xilinx_ultrascale_pad_attr +module prim_pad_attr import prim_pad_wrapper_pkg::*; #( // This parameter is ignored in this Xilinx variant. @@ -56,4 +56,4 @@ module prim_xilinx_ultrascale_pad_attr end -endmodule : prim_xilinx_ultrascale_pad_attr +endmodule : prim_pad_attr diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_wrapper.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_wrapper.sv index a3d05a39ae8bf..e43770c28837a 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_wrapper.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_wrapper.sv @@ -7,7 +7,7 @@ `include "prim_assert.sv" -module prim_xilinx_ultrascale_pad_wrapper +module prim_pad_wrapper import prim_pad_wrapper_pkg::*; #( // These parameters are ignored in this Xilinx variant. @@ -120,4 +120,4 @@ module prim_xilinx_ultrascale_pad_wrapper assert_static_in_generate_config_not_available(); end -endmodule : prim_xilinx_ultrascale_pad_wrapper +endmodule : prim_pad_wrapper diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xor2.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xor2.sv index 373ba583088da..d00a027eec727 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xor2.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xor2.sv @@ -6,7 +6,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_ultrascale_xor2 #( +module prim_xor2 #( parameter int Width = 1 ) ( input [Width-1:0] in0_i, diff --git a/hw/ip/rom_ctrl/dv/tb.sv b/hw/ip/rom_ctrl/dv/tb.sv index d8803eed0f2cb..5e178812fbd18 100644 --- a/hw/ip/rom_ctrl/dv/tb.sv +++ b/hw/ip/rom_ctrl/dv/tb.sv @@ -75,7 +75,7 @@ module tb; // Instantitate the memory backdoor util instance. `define ROM_CTRL_MEM_HIER \ - tb.dut.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.gen_generic.u_impl_generic.mem + tb.dut.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.mem initial begin mem_bkdr_util m_mem_bkdr_util; diff --git a/hw/ip/spi_device/dv/env/seq_lib/spi_device_mem_parity_vseq.sv b/hw/ip/spi_device/dv/env/seq_lib/spi_device_mem_parity_vseq.sv index 826cc00c7459c..4d8f3076e0ec2 100644 --- a/hw/ip/spi_device/dv/env/seq_lib/spi_device_mem_parity_vseq.sv +++ b/hw/ip/spi_device/dv/env/seq_lib/spi_device_mem_parity_vseq.sv @@ -27,7 +27,7 @@ class spi_device_mem_parity_vseq extends spi_device_common_vseq; logic [BitPerByte*BytePerWord-1:0] mem_data; // TODO: Add support for the gen_ram1r1w variant. string path_fmt = - "tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[%0d]"; + "tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[%0d]"; string egress_path = $sformatf(path_fmt, offset); string ingress_path = $sformatf(path_fmt, ingress_sram_offset + offset); diff --git a/hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_ram_cfg_vseq.sv b/hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_ram_cfg_vseq.sv index d6dd8d934e55f..a35ed0d7b0984 100644 --- a/hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_ram_cfg_vseq.sv +++ b/hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_ram_cfg_vseq.sv @@ -12,7 +12,7 @@ class sram_ctrl_ram_cfg_vseq extends sram_ctrl_base_vseq; prim_ram_1p_pkg::ram_1p_cfg_t src_ram_cfg, dst_ram_cfg; string src_path = "tb.dut.cfg_i"; string dst_path = - "tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.cfg_i"; + "tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_mem.cfg_i"; repeat (100) begin `DV_CHECK_STD_RANDOMIZE_FATAL(src_ram_cfg) diff --git a/hw/ip/sram_ctrl/dv/tb.sv b/hw/ip/sram_ctrl/dv/tb.sv index b9c596dbd7b40..a32711637d75e 100644 --- a/hw/ip/sram_ctrl/dv/tb.sv +++ b/hw/ip/sram_ctrl/dv/tb.sv @@ -104,7 +104,7 @@ module tb; // Instantitate the memory backdoor util instance. `define SRAM_CTRL_MEM_HIER \ - tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.mem + tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_mem.mem initial begin mem_bkdr_util m_mem_bkdr_util; diff --git a/hw/ip/uart/dv/env/seq_lib/uart_noise_filter_vseq.sv b/hw/ip/uart/dv/env/seq_lib/uart_noise_filter_vseq.sv index b8560daaddf5c..49443cfd594fa 100644 --- a/hw/ip/uart/dv/env/seq_lib/uart_noise_filter_vseq.sv +++ b/hw/ip/uart/dv/env/seq_lib/uart_noise_filter_vseq.sv @@ -8,7 +8,7 @@ class uart_noise_filter_vseq extends uart_tx_rx_vseq; `uvm_object_new - string cdc_sel_path = {"tb.dut.uart_core.sync_rx.gen_generic.u_impl_generic", + string cdc_sel_path = {"tb.dut.uart_core.sync_rx.gen_generic", ".u_prim_cdc_rand_delay.gen_enable.data_sel"}; virtual task dut_init(string reset_kind = "HARD"); diff --git a/hw/ip/usbdev/dv/tb/tb.sv b/hw/ip/usbdev/dv/tb/tb.sv index 02f43a17ddd1d..25c2d7df2c1a8 100644 --- a/hw/ip/usbdev/dv/tb/tb.sv +++ b/hw/ip/usbdev/dv/tb/tb.sv @@ -102,7 +102,7 @@ module tb; // External differential receiver; USBDEV supports an external differential receiver // with USB protocol-compliant robustness against jitter and slew, to produce a clean // data signal for sampling into the USBDEV clock domain. - prim_generic_usb_diff_rx u_usb_diff_rx ( + prim_usb_diff_rx u_usb_diff_rx ( .input_pi (usb_p), .input_ni (usb_n), .input_en_i (usb_rx_enable), diff --git a/hw/ip_templates/alert_handler/dv/alert_handler_sim.core.tpl b/hw/ip_templates/alert_handler/dv/alert_handler_sim.core.tpl index 9e085a7f3a8bb..260de0a4f70bb 100644 --- a/hw/ip_templates/alert_handler/dv/alert_handler_sim.core.tpl +++ b/hw/ip_templates/alert_handler/dv/alert_handler_sim.core.tpl @@ -12,27 +12,17 @@ filesets: files_dv: depend: - - lowrisc:dv:ralgen - - lowrisc:dv:alert_handler_tb + - ${instance_vlnv("lowrisc:dv:alert_handler_tb:0.1")} - lowrisc:dv:alert_handler_cov - ${instance_vlnv("lowrisc:dv:alert_handler_sva:0.1")} file_type: systemVerilogSource -generate: - ral: - generator: ralgen - parameters: - name: alert_handler - ip_hjson: ../data/alert_handler.hjson - targets: sim: &sim_target toplevel: tb filesets: - files_rtl - files_dv - generate: - - ral default_tool: vcs lint: diff --git a/hw/ip_templates/alert_handler/dv/env/alert_handler_env.core b/hw/ip_templates/alert_handler/dv/env/alert_handler_env.core.tpl similarity index 88% rename from hw/ip_templates/alert_handler/dv/env/alert_handler_env.core rename to hw/ip_templates/alert_handler/dv/env/alert_handler_env.core.tpl index 8103212c1975f..b32d2370f949d 100644 --- a/hw/ip_templates/alert_handler/dv/env/alert_handler_env.core +++ b/hw/ip_templates/alert_handler/dv/env/alert_handler_env.core.tpl @@ -2,11 +2,12 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:alert_handler_env:0.1" +name: ${instance_vlnv("lowrisc:dv:alert_handler_env:0.1")} description: "ALERT_HANDLER DV UVM environment" filesets: files_dv: depend: + - lowrisc:dv:ralgen - lowrisc:dv:cip_lib - lowrisc:ip:alert_handler_component # import alert_pkg - lowrisc:prim:mubi # import prim_mubi_pkg @@ -36,7 +37,17 @@ filesets: - seq_lib/alert_handler_alert_accum_saturation_vseq.sv: {is_include_file: true} file_type: systemVerilogSource +generate: + ral: + generator: ralgen + parameters: + name: alert_handler + ip_hjson: ../../data/alert_handler.hjson + position: prepend + targets: default: filesets: - files_dv + generate: + - ral diff --git a/hw/ip_templates/alert_handler/dv/tb/alert_handler_tb.core b/hw/ip_templates/alert_handler/dv/tb/alert_handler_tb.core.tpl similarity index 75% rename from hw/ip_templates/alert_handler/dv/tb/alert_handler_tb.core rename to hw/ip_templates/alert_handler/dv/tb/alert_handler_tb.core.tpl index bbf6842a74308..0fd7f81112c8e 100644 --- a/hw/ip_templates/alert_handler/dv/tb/alert_handler_tb.core +++ b/hw/ip_templates/alert_handler/dv/tb/alert_handler_tb.core.tpl @@ -2,12 +2,12 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:alert_handler_tb:0.1" +name: ${instance_vlnv("lowrisc:dv:alert_handler_tb:0.1")} description: "ALERT_HANDLER UVM TB environment" filesets: files_dv: depend: - - lowrisc:dv:alert_handler_test:0.1 + - ${instance_vlnv("lowrisc:dv:alert_handler_test:0.1")} files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip_templates/alert_handler/dv/tests/alert_handler_test.core b/hw/ip_templates/alert_handler/dv/tests/alert_handler_test.core.tpl similarity index 79% rename from hw/ip_templates/alert_handler/dv/tests/alert_handler_test.core rename to hw/ip_templates/alert_handler/dv/tests/alert_handler_test.core.tpl index 767c0654f1c6d..c5055ffb1b8d9 100644 --- a/hw/ip_templates/alert_handler/dv/tests/alert_handler_test.core +++ b/hw/ip_templates/alert_handler/dv/tests/alert_handler_test.core.tpl @@ -2,12 +2,12 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:alert_handler_test:0.1" +name: ${instance_vlnv("lowrisc:dv:alert_handler_test:0.1")} description: "ALERT_HANDLER DV UVM test" filesets: files_dv: depend: - - lowrisc:dv:alert_handler_env + - ${instance_vlnv("lowrisc:dv:alert_handler_env")} files: - alert_handler_test_pkg.sv - alert_handler_base_test.sv: {is_include_file: true} diff --git a/hw/ip_templates/flash_ctrl/data/flash_ctrl.hjson.tpl b/hw/ip_templates/flash_ctrl/data/flash_ctrl.hjson.tpl index 6199255fa10e3..8c466ec6b5110 100644 --- a/hw/ip_templates/flash_ctrl/data/flash_ctrl.hjson.tpl +++ b/hw/ip_templates/flash_ctrl/data/flash_ctrl.hjson.tpl @@ -54,7 +54,7 @@ ] bus_interfaces: [ { protocol: "tlul", direction: "device", name: "core" } - { protocol: "tlul", direction: "device", name: "prim" , hier_path: "u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top"} + { protocol: "tlul", direction: "device", name: "prim" , hier_path: "u_eflash.u_flash.u_reg_top"} { protocol: "tlul", direction: "device", name: "mem" } ], available_input_list: [ diff --git a/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env.core b/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env.core index f339e44e1f82c..642b4318b70ec 100644 --- a/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env.core +++ b/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env.core @@ -15,6 +15,8 @@ filesets: - lowrisc:dv:flash_phy_prim_agent - lowrisc:ip_interfaces:flash_ctrl_pkg - lowrisc:constants:top_pkg + # TODO: prim_legacy_pkg is deprecated + - lowrisc:prim:prim_legacy_pkg files: - flash_ctrl_eflash_ral_pkg.sv - flash_ctrl_env_pkg.sv diff --git a/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_seq_cfg.sv b/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_seq_cfg.sv index 19cc6622428f9..5df795b031853 100644 --- a/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_seq_cfg.sv +++ b/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_seq_cfg.sv @@ -272,7 +272,7 @@ class flash_ctrl_seq_cfg extends uvm_object; disable_flash_init = 1'b0; // Off - flash_path_str = "tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic"; + flash_path_str = "tb.dut.u_eflash.u_flash"; // NOTE: Make sure to keep // cfg.flash_ctrl_vif.rst_to_pd_time_ns < reset_width_clks_lo * min clock period in ns. diff --git a/hw/ip_templates/flash_ctrl/dv/tb/tb.sv b/hw/ip_templates/flash_ctrl/dv/tb/tb.sv index b8b741f5c9942..24529b8ec0ad0 100644 --- a/hw/ip_templates/flash_ctrl/dv/tb/tb.sv +++ b/hw/ip_templates/flash_ctrl/dv/tb/tb.sv @@ -237,25 +237,24 @@ module tb; // For eflash of a specific vendor implementation, set the hierarchy to the memory element // correctly when creating these instances in the extended testbench. `define FLASH_BANK_HIER(i) \ - tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[i]. \ + tb.dut.u_eflash.u_flash.gen_prim_flash_banks[i]. \ u_prim_flash_bank `define FLASH_DATA_MEM_HIER(i) \ - `FLASH_BANK_HIER(i).u_mem.gen_generic.u_impl_generic.mem + `FLASH_BANK_HIER(i).u_mem.mem `define FLASH_DATA_MEM_HIER_STR(i) \ - $sformatf({"tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.", \ - "gen_prim_flash_banks[%0d].u_prim_flash_bank.u_mem.gen_generic.", \ - "u_impl_generic.mem"}, i) + $sformatf({"tb.dut.u_eflash.u_flash.", \ + "gen_prim_flash_banks[%0d].u_prim_flash_bank.u_mem.mem"}, i) `define FLASH_INFO_MEM_HIER(i, j) \ - tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[i]. \ - u_prim_flash_bank.gen_info_types[j].u_info_mem.gen_generic.u_impl_generic.mem + tb.dut.u_eflash.u_flash.gen_prim_flash_banks[i]. \ + u_prim_flash_bank.gen_info_types[j].u_info_mem.mem `define FLASH_INFO_MEM_HIER_STR(i, j) \ - $sformatf({"tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.", \ + $sformatf({"tb.dut.u_eflash.u_flash.", \ "gen_prim_flash_banks[%0d].u_prim_flash_bank.gen_info_types[%0d].", \ - "u_info_mem.gen_generic.u_impl_generic.mem"}, i, j) + "u_info_mem.mem"}, i, j) if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_generic for (genvar i = 0; i < flash_ctrl_pkg::NumBanks; i++) begin : gen_each_bank diff --git a/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl b/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl index 72b5ab9c58143..c1f23f6d2f90c 100644 --- a/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl +++ b/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl @@ -21,6 +21,8 @@ filesets: - lowrisc:prim:lfsr - lowrisc:prim:secded - lowrisc:prim:sparse_fsm + # TODO: prim_legacy_pkg is deprecated + - lowrisc:prim:prim_legacy_pkg - lowrisc:ip:otp_ctrl_pkg - ${instance_vlnv("lowrisc:ip:flash_ctrl_pkg")} - ${instance_vlnv("lowrisc:ip:flash_ctrl_reg")} diff --git a/hw/ip_templates/flash_ctrl/rtl/flash_ctrl.sv.tpl b/hw/ip_templates/flash_ctrl/rtl/flash_ctrl.sv.tpl index f459b46ac6a9c..34618341cdb29 100644 --- a/hw/ip_templates/flash_ctrl/rtl/flash_ctrl.sv.tpl +++ b/hw/ip_templates/flash_ctrl/rtl/flash_ctrl.sv.tpl @@ -1527,7 +1527,7 @@ module flash_ctrl `endif if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_reg_we_assert_generic `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(PrimRegWeOnehotCheck_A, - u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top, alert_tx_o[3]) + u_eflash.u_flash.u_reg_top, alert_tx_o[3]) end endmodule diff --git a/hw/top_earlgrey/cdc/cdc_waivers.data.tcl b/hw/top_earlgrey/cdc/cdc_waivers.data.tcl index c2816bf8447f8..bf5832aa352de 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.data.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.data.tcl @@ -4,7 +4,7 @@ # # Verix CDC waiver file -set_rule_status -rule {CNTL} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal =~ "IO*") && (Association == "None") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD} +set_rule_status -rule {CNTL} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.q_o[0]") && (Signal =~ "IO*") && (Association == "None") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.q_o[0]")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD} set_rule_status -rule {DATA} -expression {(ReceivingFlop == "top_earlgrey.u_i2c2.i2c_core.scl_rx_val[0]") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD} set_rule_status -rule {DATA} -expression {(ReceivingFlop == "top_earlgrey.u_i2c2.i2c_core.sda_rx_val[0]") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD} set_rule_status -rule {DATA} -expression {(ReceivingFlop == "top_earlgrey.u_i2c1.i2c_core.scl_rx_val[0]") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD} @@ -20,8 +20,8 @@ set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "J set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_DEV_D*") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD} set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "JTAG_TCK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_DEV_D*") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD} -set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.st_q[2:0]") && (Signal == "IOB2") && (Association == "Load-Control")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} -set_rule_status -rule {data s_net_no_wave} -expression {(multiclockdomains == "io_div2_clk,io_div4_clk::ast_ext_clk,main_clk") && (receivingflop == "top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.st_q[2:0]") && (signal == "iob2") && (association == "load-control")} -status {waived} -comment {Multiple clocks can be assigned on the same pad} +set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.st_q[2:0]") && (Signal == "IOB2") && (Association == "Load-Control")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} +set_rule_status -rule {data s_net_no_wave} -expression {(multiclockdomains == "io_div2_clk,io_div4_clk::ast_ext_clk,main_clk") && (receivingflop == "top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.st_q[2:0]") && (signal == "iob2") && (association == "load-control")} -status {waived} -comment {Multiple clocks can be assigned on the same pad} set_rule_status -rule {data s_net_no_wave} -expression {(multiclockdomains == "io_div2_clk,io_div4_clk::io_div4_clk,jtag_tck") && (receivingflop == "top_earlgrey.u_lc_ctrl.u_dmi_jtag.dr_q[40]") && (signal == "ior2") && (association == "none")} -status {waived} -comment {Multiple clocks can be assigned on the same pad} set_rule_status -rule {data s_net_no_wave} -expression {(multiclockdomains == "io_div2_clk,io_div4_clk::io_div4_clk,jtag_tck") && (receivingflop == "top_earlgrey.u_lc_ctrl.u_dmi_jtag.dtmcs_q.zero1[31]") && (signal == "ior2") && (association == "none")} -status {waived} -comment {Multiple clocks can be assigned on the same pad} set_rule_status -rule {data s_net_no_wave} -expression {(multiclockdomains == "io_div2_clk,io_div4_clk::io_div4_clk,jtag_tck") && (receivingflop == "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31]") && (signal == "ior2") && (association == "none")} -status {waived} -comment {Multiple clocks can be assigned on the same pad} @@ -34,8 +34,8 @@ set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "I set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap_q[1]") && (Signal == "IOC4") && (Association == "None")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[0]") && (Signal == "IOC8") && (Association == "None")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1]") && (Signal == "IOC5") && (Association == "None")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} -set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[11:0]") && (Signal == "IOB1") && (Association == "None")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} -set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[11:0]") && (Signal == "IOB2") && (Association == "None")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} +set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.q_o[11:0]") && (Signal == "IOB1") && (Association == "None")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} +set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.q_o[11:0]") && (Signal == "IOB2") && (Association == "None")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_rv_dm.dap.dr_q[40]") && (Signal == "IOR2") && (Association == "None")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31]") && (Signal == "IOR2") && (Association == "None")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.idcode_q[31]") && (Signal == "IOR2") && (Association == "None")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} @@ -57,7 +57,7 @@ set_rule_status -rule {DATA} -expression {(MultiClockDomains == "SPI_DEV_CLK,SPI set_rule_status -rule {DATA} -expression {(MultiClockDomains == "SPI_HOST_CLK,SPI_HOST_PASSTHRU_CLK::IO_DIV4_CLK") && (ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q*") && (Signal =~ "SPI_HOST_*") && (Association == "None")} -status {Waived} -comment {pinmux dio_out_retreg is quasi-static} set_rule_status -rule {DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.*io_o*_retreg_q*") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {pinmux io_out_retreg is quasi-static} set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} -set_rule_status -rule {DATA} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.st_q[2:0]") && (Signal == "IOB2") && (Association == "Load-Control")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} +set_rule_status -rule {DATA} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.st_q[2:0]") && (Signal == "IOB2") && (Association == "Load-Control")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} set_rule_status -rule {DATA} -expression {(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cmd_info*.q*")} -status {Waived} -comment {spi_device reg is quasi-static} set_rule_status -rule {DATA} -expression {(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cfg*.q*")} -status {Waived} -comment {spi_device reg is quasi-static} set_rule_status -rule {DATA} -expression {(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Signal =~ "top_earlgrey.u_pinmux_aon.dio_pad_attr_q*.invert")} -status {Waived} -comment {pinmux dio_out_retreg is quasi-static} diff --git a/hw/top_earlgrey/cdc/cdc_waivers.misc.tcl b/hw/top_earlgrey/cdc/cdc_waivers.misc.tcl index ddbf9b743c012..4ae3aea2ee503 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.misc.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.misc.tcl @@ -7,7 +7,7 @@ # W_DATA : included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[2:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.wptr_o[2:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_xbar_main.u_asf_39.reqfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_xbar_main.u_asf_39.reqfifo.sync_wptr.u_sync_2.q_o[0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_reg.u_socket.num_req_outstanding[8:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][45]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][1]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} @@ -23,46 +23,46 @@ set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_sp set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spi_tpm.sck_hw_reg_idx[3:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_cfg.tpm_mode") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.dtmcs_q.zero1[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.dtmcs_q.zero1[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.dtmcs_q.zero1[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.dtmcs_q.zero1[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.dtmcs_q.zero1[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.dtmcs_q.zero1[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[4]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[4]") && (Signal =~ "top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[4]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[4]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[4]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[4]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.tap_state_q[3:0]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.tap_state_q[3:0]") && (Signal =~ "top_earlgrey.u_pinmux_aon.mio_pad_attr_q[35].invert") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.tap_state_q[3:0]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.tap_state_q[3:0]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dr_q[40]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.tap_state_q[3:0]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.tap_state_q[3:0]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dr_q[40]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dr_q[40]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dr_q[40]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dr_q[40]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dr_q[40]") && (Signal =~ "top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.idcode_q[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.idcode_q[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.idcode_q[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.idcode_q[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.idcode_q[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.idcode_q[31]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.jtag_ir_shift_q[4]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.jtag_ir_shift_q[4]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.jtag_ir_shift_q[4]") && (Signal =~ "top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.jtag_ir_shift_q[4]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.jtag_ir_shift_q[4]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[11:0]") && (Signal =~ "IOB2") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[11:0]") && (Signal =~ "IOB1") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.tap_state_q[3:0]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.tap_state_q[3:0]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.jtag_ir_shift_q[4]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.q_o[11:0]") && (Signal =~ "IOB2") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.q_o[11:0]") && (Signal =~ "IOB1") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.tap_state_q[3:0]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.tap_state_q[3:0]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.tap_state_q[3:0]") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.tap_state_q[3:0]") && (Signal =~ "top_earlgrey.u_pinmux_aon.mio_pad_attr_q[35].invert") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[0]") && (Signal =~ "top_earlgrey.u_usbdev.u_reg.u_phy_pins_drive_dp_o.q[0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[1]") && (Signal =~ "top_earlgrey.u_usbdev.u_reg.u_phy_pins_drive_dn_o.q[0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[0]") && (Signal =~ "top_earlgrey.u_usbdev.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx.u_usb_dp_o_flop.gen_generic.u_impl_generic.q_o[0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[1]") && (Signal =~ "top_earlgrey.u_usbdev.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx.u_usb_dn_o_flop.gen_generic.u_impl_generic.q_o[0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[0]") && (Signal =~ "top_earlgrey.u_usbdev.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx.u_usb_dp_o_flop.q_o[0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[1]") && (Signal =~ "top_earlgrey.u_usbdev.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx.u_usb_dn_o_flop.q_o[0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[1:0]") && (Signal =~ "top_earlgrey.u_usbdev.u_reg.u_phy_pins_drive_en.q[0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dr_q[40]") && (Signal =~ "IOR2") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31]") && (Signal =~ "IOR2") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} @@ -82,8 +82,8 @@ set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pi set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[5:2]") && (Signal =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.wptr_o[2:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[5:2]") && (Signal =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][45]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_reg.u_socket.dev_select_outstanding[1:0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[3:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[3:1]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[3:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_wptr.u_sync_2.q_o[3:1]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_wptr.u_sync_2.q_o[0]") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} # W_MASYNC : included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_rxf_overflow.src_level") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0]")} -status {Waived} -comment {static info in IO_DIV4_CLK} @@ -103,5 +103,5 @@ set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_ set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[19:16]") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_rptr_sync_q[0]")} -status {Waived} -comment {reg data is muxed with spi data in spi clock domain} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[19:16]") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.storage[1:0][31:0]")} -status {Waived} -comment {reg data is muxed with spi data in spi clock domain} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q*") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK") && (Driver =~ "IOR2")} -status {Waived} -comment {reg data is muxed with spi data in spi clock domain} -lastedit_user {root} -set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o*") && (MultiClockDomains =~ "RI_WAVEFORM_ASYNC_1::AST_EXT_CLK,USB_CLK") && (Driver =~ "USB_*")} -status {Waived} -comment {reg data is muxed with spi data in spi clock domain} +set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.q_o*") && (MultiClockDomains =~ "RI_WAVEFORM_ASYNC_1::AST_EXT_CLK,USB_CLK") && (Driver =~ "USB_*")} -status {Waived} -comment {reg data is muxed with spi data in spi clock domain} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.tap_state_q*") && (Driver =~ "IO*")} -status {Waived} diff --git a/hw/top_earlgrey/cdc/cdc_waivers.multclk_crossings.tcl b/hw/top_earlgrey/cdc/cdc_waivers.multclk_crossings.tcl index cc8bffd4a18ed..0df1b4a4b9b71 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.multclk_crossings.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.multclk_crossings.tcl @@ -6,38 +6,38 @@ # Multiple clocks on PAD are muxed in or out as designed. These waivers are included in other waivers such as cdc_waivers.w_masync, cdc_waivers.w_data, etc. # tpm csb is a muxed connection. PAD input (mio_pad[38]) is recognized in JTAG_TCK domain and transferred to SPI clock domain. -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "-") && (MultiClockDomains == "JTAG_TCK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_sck_csb_edge.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.in_o") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "-") && (MultiClockDomains == "JTAG_TCK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.in_o") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "-") && (MultiClockDomains == "JTAG_TCK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_sck_csb_edge.g_sync.u_sync.u_sync_1.q_o[0]") && (SampleTxSignal == "u_padring.gen_mio_pads[38].u_mio_pad.in_o") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "-") && (MultiClockDomains == "JTAG_TCK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.sync_wptr.u_sync_1.q_o[0]") && (SampleTxSignal == "u_padring.gen_mio_pads[38].u_mio_pad.in_o") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} # Signals from SPI clock domain are transferred to PAD outputs in IO_DIV4_CLK domain. -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic.in_o") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "u_padring.gen_dio_pads[19].u_dio_pad.in_o") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} # Signals from IO_DIV4_CLK and SPI clock domains are transferred to regs in IO_DIV4_CLK domain. -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_sel.gen_generic.u_impl_generic.clk_o") && (MultiClockDomains == "IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr_q[0]") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_sel.clk_o") && (MultiClockDomains == "IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr_q[0]") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} # Signals from IO_DIV2/4_CLK and SPI clock domains are transferred to regs in SPI clk domain. -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_sel.gen_generic.u_impl_generic.clk_o") && (MultiClockDomains == "IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_gray_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr_q[0]") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_gray_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "SPI_DEV_CLK") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_sel.clk_o") && (MultiClockDomains == "IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_rptr.u_sync_1.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_gray_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.clk_o") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr_q[0]") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.clk_o") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_rptr.u_sync_1.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_gray_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "SPI_DEV_CLK") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} # Signals from JTAG_TCK clock domains are transferred to regs in SPI clk domain. -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "-") && (MultiClockDomains == "JTAG_TCK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_sck_csb_edge.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "IOR3") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "-") && (MultiClockDomains == "JTAG_TCK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "IOR3") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "-") && (MultiClockDomains == "JTAG_TCK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_sck_csb_edge.g_sync.u_sync.u_sync_1.q_o[0]") && (SampleTxSignal == "IOR3") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "-") && (MultiClockDomains == "JTAG_TCK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.sync_wptr.u_sync_1.q_o[0]") && (SampleTxSignal == "IOR3") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} # Signals from IO_DIV2/4_CLK clock domains are transferred to regs in SPI clk domain. -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_mux.gen_generic.u_impl_generic.clk_o") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_mux.gen_generic.u_impl_generic.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_csb_edge_spiclk.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_mux.clk_o") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_mux.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_csb_edge_spiclk.g_sync.u_sync.u_sync_1.q_o[0]") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_p2s.cnt[0]") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_csb_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK") && (SampleRxSignal == "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[0]") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_lc_ctrl.u_prim_clock_mux2.gen_generic.u_impl_generic.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_sram_clk_cg.gen_generic.u_impl_generic.clk_o") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_cg.gen_generic.u_impl_generic.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div2_div.clk_o") && (MultiClockDomains == "IO_DIV2_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_gray_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.q_o[0]") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_csb_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK") && (SampleRxSignal == "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[0]") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_lc_ctrl.u_prim_clock_mux2.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.clk_o") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_sram_clk_cg.clk_o") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_cg.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div2_div.clk_o") && (MultiClockDomains == "IO_DIV2_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_rptr.u_sync_1.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_gray_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} # Signals from SPI clock domains are transferred to regs in IO_DIV4_CLK domain. -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "SPI_DEV_CLK") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "SPI_DEV_CLK") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr_q[0]") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_csb_buf.clk_o") && (MultiClockDomains == "SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[2]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0]") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o") && (MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_txf_underflow.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_txf_underflow.src_level") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_s2p.data_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_csb_buf.clk_o") && (MultiClockDomains == "SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[2]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.q_o[0]") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o") && (MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_txf_underflow.prim_flop_2sync.u_sync_1.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_txf_underflow.src_level") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_s2p.data_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} # Signals from SPI clock domains are transferred to regs in SPI clock domain. -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "SPI_DEV_CLK") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "SPI_DEV_CLK") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o") && (MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spid_status.byte_sel_q[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_p2s.cnt[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o") && (MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_rptr_gray_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_csb_buf.clk_o") && (MultiClockDomains == "SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} -set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_spid_status.sck_status_staged[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_csb_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o") && (MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.sync_rptr.u_sync_1.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_rptr_gray_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_csb_buf.clk_o") && (MultiClockDomains == "SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.q_o[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} +set_rule_status -rule {MULTCLK_CROSSINGS} -expression {(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_spid_status.sck_status_staged[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_csb_buf.clk_o")} -status {Waived} -comment {Reviewed : a normal CDC path handled properly} diff --git a/hw/top_earlgrey/cdc/cdc_waivers.rst_sync.tcl b/hw/top_earlgrey/cdc/cdc_waivers.rst_sync.tcl index 3281d839fe4e0..5ac2dbb981489 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.rst_sync.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.rst_sync.tcl @@ -4,15 +4,15 @@ # # Verix CDC waiver file -set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.gen_generic.u_impl_generic.q_o*") && (ResetSignal =~ "top_earlgrey.u_pinmux_aon.mio_pad_attr_q*.invert")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} -set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.gen_generic.u_impl_generic.q_o*") && (ResetSignal =~ "IO*")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} -#set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.gen_generic.u_impl_generic.q_o*") && (ResetSignal =~ "u_ast.dft_scan_md_o*")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} +set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.q_o*") && (ResetSignal =~ "top_earlgrey.u_pinmux_aon.mio_pad_attr_q*.invert")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} +set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.q_o*") && (ResetSignal =~ "IO*")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} +#set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.q_o*") && (ResetSignal =~ "u_ast.dft_scan_md_o*")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*_o*") && (ResetSignal =~ "u_ast.dft_scan_md_o*")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} -#set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.gen_generic.u_impl_generic.q_o*") && (ResetSignal == "u_ast.scan_reset_no")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} +#set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.q_o*") && (ResetSignal == "u_ast.scan_reset_no")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*_o*") && (ResetSignal == "u_ast.scan_reset_no")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} -set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.gen_generic.u_impl_generic.q_o*") && (ResetSignal =~ "top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_46.q*")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} -set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.gen_generic.u_impl_generic.q_o*") && (ResetSignal == "top_earlgrey.u_rstmgr_aon.u_d0_spi_device.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} -set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.gen_generic.u_impl_generic.q_o*") && (ResetSignal == "top_earlgrey.u_rstmgr_aon.u_daon_lc_io_div4.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} -set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.gen_generic.u_impl_generic.q_o*") && (ResetSignal == "top_earlgrey.u_rstmgr_aon.u_lc_src.gen_rst_pd_n[0].u_pd_rst.u_sync_2.gen_generic.u_impl_generic.q_o[0]")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} -set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.gen_generic.u_impl_generic.q_o*") && (ResetSignal == "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[1]")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} -set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.gen_generic.u_impl_generic.q_o*") && (ResetSignal == "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[0]")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} +set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.q_o*") && (ResetSignal =~ "top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_46.q*")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} +set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.q_o*") && (ResetSignal == "top_earlgrey.u_rstmgr_aon.u_d0_spi_device.u_rst_sync.u_sync_2.q_o[0]")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} +set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.q_o*") && (ResetSignal == "top_earlgrey.u_rstmgr_aon.u_daon_lc_io_div4.u_rst_sync.u_sync_2.q_o[0]")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} +set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.q_o*") && (ResetSignal == "top_earlgrey.u_rstmgr_aon.u_lc_src.gen_rst_pd_n[0].u_pd_rst.u_sync_2.q_o[0]")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} +set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.q_o*") && (ResetSignal == "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.q_o[1]")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} +set_rule_status -rule {RST_SYNC} -expression {(ReceivingFlop =~ "top_earlgrey.*.u_sync_1.q_o*") && (ResetSignal == "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[0]")} -status {Waived} -comment {Reviewed : reset source to reset synchronizer} diff --git a/hw/top_earlgrey/cdc/cdc_waivers.spi_device.tcl b/hw/top_earlgrey/cdc/cdc_waivers.spi_device.tcl index 32fb895b6e24a..c32481adc4fdc 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.spi_device.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.spi_device.tcl @@ -68,7 +68,7 @@ set_rule_status -rule {W_CNTL} -status {Waived} \ # DPSRAM waiver # DPSRAM B port has clock mux. Unless in SPI Generic mode, B port is in DEV_IN_CLK or SPI_DEV_PASSTHRU_IN_CLK set_rule_status -rule {W_DATA} -status {Waived} \ - -expression {(ReceivingFlop=~"*u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && \ + -expression {(ReceivingFlop=~"*u_spi_device.u_memory_2p.u_mem.b_rdata_o*") && \ (MultiClockDomains=="SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK,SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")} \ -comment {DPSRAM B port has clock mux. Unless in SPI Generic mode, B port is in DEV_IN_CLK or SPI_DEV_PASSTHRU_IN_CLK} @@ -92,13 +92,13 @@ set_rule_status -rule {W_DATA} -status {Waived} \ # Set from iDebug -set_rule_status -rule {W_CNTL} -expression {(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_reg.u_cfg_addr_4b_en.q[0]") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")} -status {Waived} -lastedit_user {root} -lastedit_time {Thursday, 24 March 2022 13:46:23 PDT} \ +set_rule_status -rule {W_CNTL} -expression {(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_sync_1.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_reg.u_cfg_addr_4b_en.q[0]") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_sync_2.q_o[0]")} -status {Waived} -lastedit_user {root} -lastedit_time {Thursday, 24 March 2022 13:46:23 PDT} \ -comment {addr_4b_en signal is static not a pulse signal. No intention of the bit value being changed.} -set_rule_status -rule {W_CNTL} -expression {(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_spid_status.sck_status_busy") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")} -status {Waived} -lastedit_user {root} -lastedit_time {Thursday, 24 March 2022 13:55:28 PDT} \ +set_rule_status -rule {W_CNTL} -expression {(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_sync.u_sync_1.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_spid_status.sck_status_busy") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_sync.u_sync_2.q_o[0]")} -status {Waived} -lastedit_user {root} -lastedit_time {Thursday, 24 March 2022 13:55:28 PDT} \ -comment {busy signal is set then stay. 2FF to SYS clock domain is fine} -set_rule_status -rule {W_CNTL} -expression {(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_clr_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_spid_status.u_busy_clr_sync.src_level") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_clr_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")} -status {Waived} -lastedit_user {root} -lastedit_time {Thursday, 24 March 2022 14:02:56 PDT} -set_rule_status -rule {W_CNTL} -expression {(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_status.u_status_23_to_1_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_spid_status.u_busy_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]") && (Association == "Blocked-Dangling") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_status.u_status_23_to_1_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")} -status {Waived} -lastedit_user {root} -lastedit_time {Thursday, 24 March 2022 14:03:01 PDT} -set_rule_status -rule {W_CNTL} -expression {(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.src_level") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")} -status {Waived} -lastedit_user {root} -lastedit_time {Thursday, 24 March 2022 14:05:55 PDT} +set_rule_status -rule {W_CNTL} -expression {(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_clr_sync.prim_flop_2sync.u_sync_1.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_spid_status.u_busy_clr_sync.src_level") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_clr_sync.prim_flop_2sync.u_sync_2.q_o[0]")} -status {Waived} -lastedit_user {root} -lastedit_time {Thursday, 24 March 2022 14:02:56 PDT} +set_rule_status -rule {W_CNTL} -expression {(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_status.u_status_23_to_1_sync.u_sync_1.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_spid_status.u_busy_sync.u_sync_2.q_o[0]") && (Association == "Blocked-Dangling") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_status.u_status_23_to_1_sync.u_sync_2.q_o[0]")} -status {Waived} -lastedit_user {root} -lastedit_time {Thursday, 24 March 2022 14:03:01 PDT} +set_rule_status -rule {W_CNTL} -expression {(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_1.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.src_level") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_2.q_o[0]")} -status {Waived} -lastedit_user {root} -lastedit_time {Thursday, 24 March 2022 14:05:55 PDT} set_rule_status -rule {W_INTERFACE} -expression {(ComponentClass == "DATA") && (ErrorType == "Uncontrolled-Tx-MASYNC") && (MultiClockDomains == "IO_DIV4_CLK::IO_DIV4_CLK,SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (Signal == "top_earlgrey.u_spi_device.u_reg.u_rxf_ptr_rptr.q[12:2]")} -status {Waived} -lastedit_user {root} -lastedit_time {Thursday, 24 March 2022 14:11:36 PDT} set_rule_status -rule {W_INTERFACE} -expression {(ComponentClass == "CNTL") && (ErrorType == "") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK,SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (Signal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_wptr_gray_q[3:0]")} -status {Waived} -lastedit_user {root} -lastedit_time {Thursday, 24 March 2022 14:11:36 PDT} diff --git a/hw/top_earlgrey/cdc/cdc_waivers.synch_rst_crossing.tcl b/hw/top_earlgrey/cdc/cdc_waivers.synch_rst_crossing.tcl index 98b697d73f387..e8f171320c23e 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.synch_rst_crossing.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.synch_rst_crossing.tcl @@ -4,4 +4,4 @@ # # Verix CDC waiver file -set_rule_status -rule {SYNCH_RST_CROSSING} -expression {(ResetSyncFlop =~ "top_earlgrey.*.u_sync_2.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {REVIEW items : flops driven by reset synchronizers} +set_rule_status -rule {SYNCH_RST_CROSSING} -expression {(ResetSyncFlop =~ "top_earlgrey.*.u_sync_2.q_o*")} -status {Waived} -comment {REVIEW items : flops driven by reset synchronizers} diff --git a/hw/top_earlgrey/cdc/cdc_waivers.tcl b/hw/top_earlgrey/cdc/cdc_waivers.tcl index 4657f1e76aab7..bf866cfde7d44 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.tcl @@ -72,7 +72,7 @@ set_rule_status -rule {W_RECON_GROUPS} -status {Waived} # W_GLITCH from unrecognized sync logics set_rule_status -rule {W_GLITCH} -status {Waived} \ - -expression {(GlitchOutput=~"*.u_sync_1.gen_generic.u_impl_generic.q_o*")} \ + -expression {(GlitchOutput=~"*.u_sync_1.q_o*")} \ -comment {Waive glitch paths that meet at and/or gates at the same clock but synchronization logics are not recognized} set_rule_status -rule {W_RECON_GROUPS} -status {Waived} \ @@ -90,14 +90,14 @@ set_rule_status -rule {W_RECON_GROUPS} -status {Waived} # Misc RV PLIC signals reconverged set_rule_status -rule {W_RECON_GROUPS} -status {Waived} \ - -expression {(ControlSignal =~ "*u_sync_1.gen_generic.u_impl_generic.q_o*") && (ReconSignal=~"*u_rv_plic.u_gateway.ia*")} \ + -expression {(ControlSignal =~ "*u_sync_1.q_o*") && (ReconSignal=~"*u_rv_plic.u_gateway.ia*")} \ -comment {Reconverged signals in RV PLIC} set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ReconSignal=~"top_earlgrey.u_xbar_main.u_asf_35.rspfifo.storage[0]*")} -comment {Intended reconvergence in xbar main} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ReconSignal=~"top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o*")} -comment {Intended reconvergence in pwrmgr fsm} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"top_earlgrey.u_xbar_main.u_asf_*.rs*fifo.sync_*ptr.u_sync_1.gen_generic.u_impl_generic.q_o*")} -comment {reconvergence caused by unrecognized qualification in async fifo} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"top_earlgrey.*.*sync*.*sync_1.gen_generic.u_impl_generic.q_o*")} -comment {reconvergence caused by unrecognized qualification in async fifo} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"top_earlgrey.*.*cdc*.*sync_1.gen_generic.u_impl_generic.q_o*")} -comment {reconvergence caused by unrecognized qualification in async fifo} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ReconSignal=~"top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.q_o*")} -comment {Intended reconvergence in pwrmgr fsm} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"top_earlgrey.u_xbar_main.u_asf_*.rs*fifo.sync_*ptr.u_sync_1.q_o*")} -comment {reconvergence caused by unrecognized qualification in async fifo} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"top_earlgrey.*.*sync*.*sync_1.q_o*")} -comment {reconvergence caused by unrecognized qualification in async fifo} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"top_earlgrey.*.*cdc*.*sync_1.q_o*")} -comment {reconvergence caused by unrecognized qualification in async fifo} # PADs attribute to multiple IPs @@ -172,13 +172,13 @@ set_rule_status -rule {W_INTERFACE} -status {Waived} -expression \ (ReceivingFlop=~ "top_earlgrey.u_pinmux_aon.mio_out_retreg_q*")} -comment {W_INTERFACE issues from u_reg to pinmux} set_rule_status -rule {W_CNTL} -status {Waived} \ - -expression {(Signal=~"top_earlgrey.*.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.*.u_sync_1.gen_generic.u_impl_generic.q_o*")} \ + -expression {(Signal=~"top_earlgrey.*.q_o*") && (ReceivingFlop=~"top_earlgrey.*.u_sync_1.q_o*")} \ -comment {PAD driving to I2C. PADs are not clock bounded} set_rule_status -rule {W_CNTL} -status {Waived} \ - -expression {(Signal=~"top_earlgrey.*.u_reg.*_cdc.u_src_to_dst_req.src_level") && (ReceivingFlop=~"top_earlgrey.*.u_sync_1.gen_generic.u_impl_generic.q_o*")} \ + -expression {(Signal=~"top_earlgrey.*.u_reg.*_cdc.u_src_to_dst_req.src_level") && (ReceivingFlop=~"top_earlgrey.*.u_sync_1.q_o*")} \ -comment {PAD driving to I2C. PADs are not clock bounded} set_rule_status -rule {W_CNTL} -status {Waived} \ - -expression {(Signal=~"top_earlgrey.*.u_reg.*_cdc.u_arb.*_sync.*.dst_ack_q") && (ReceivingFlop=~"top_earlgrey.*.u_sync_1.gen_generic.u_impl_generic.q_o*")} \ + -expression {(Signal=~"top_earlgrey.*.u_reg.*_cdc.u_arb.*_sync.*.dst_ack_q") && (ReceivingFlop=~"top_earlgrey.*.u_sync_1.q_o*")} \ -comment {PAD driving to I2C. PADs are not clock bounded} diff --git a/hw/top_earlgrey/cdc/cdc_waivers.w_async_rst_flops.tcl b/hw/top_earlgrey/cdc/cdc_waivers.w_async_rst_flops.tcl index 5971e230a2e88..214b4e03bd029 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.w_async_rst_flops.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.w_async_rst_flops.tcl @@ -45,8 +45,8 @@ set_rule_status -rule {W_ASYNC_RST_FLOPS} -status {Waived} -expression {(Driving set_rule_status -rule {W_ASYNC_RST_FLOPS} -status {Waived} -expression {(DrivingSignal=~"*.u_pinmux_strap_sampling.*hw_debug_en*.q_o*")} -comment {Tester should ensure no jtag transactions when tap_strap is sampled} set_rule_status -rule {W_ASYNC_RST_FLOPS} -status {Waived} -expression {(DrivingSignal=~"*.u_pinmux_strap_sampling.*dft_en*.q_o*")} -comment {Tester should ensure no jtag transactions when tap_strap is sampled} set_rule_status -rule {W_ASYNC_RST_FLOPS} -status {Waived} -expression {(DrivingSignal=~"top_earlgrey.u_pinmux_aon.*io_pad_attr_q*")} -comment {pinmux driving} -set_rule_status -rule {W_ASYNC_RST_FLOPS} -status {Waived} -expression {(DrivingSignal=~"top_earlgrey.u_rstmgr_aon.*.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o*")} -comment {rstmgr driving} -set_rule_status -rule {W_ASYNC_RST_FLOPS} -status {Waived} -expression {(DrivingSignal=~"top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap*")} -comment {rv_dm driving} +set_rule_status -rule {W_ASYNC_RST_FLOPS} -status {Waived} -expression {(DrivingSignal=~"top_earlgrey.u_rstmgr_aon.*.u_rst_sync.u_sync_2.q_o*")} -comment {rstmgr driving} +set_rule_status -rule {W_ASYNC_RST_FLOPS} -status {Waived} -expression {(DrivingSignal=~"top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap*")} -comment {rv_dm driving} set_rule_status -rule {W_ASYNC_RST_FLOPS} -status {Waived} -expression {(DrivingSignal=~"top_earlgrey.u_spi_device.u_reg.u_control*.q*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_fwmode.*")} -comment {spi_tx_fifo driving} set_rule_status -rule {W_ASYNC_RST_FLOPS} -status {Waived} -expression {(DrivingSignal=~"top_earlgrey.u_spi_device.u_reg.u_control*.q*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*")} -comment {spi_tx_fifo driving} -set_rule_status -rule {W_ASYNC_RST_FLOPS} -status {Waived} -expression {(DrivingSignal=~"top_earlgrey.*.i_dmi_cdc.u_combined_rstn_sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.*.i_dmi_cdc.i_cdc_resp.fifo_rptr*_q[0]*")} -comment {async reset after jtag mux} +set_rule_status -rule {W_ASYNC_RST_FLOPS} -status {Waived} -expression {(DrivingSignal=~"top_earlgrey.*.i_dmi_cdc.u_combined_rstn_sync.u_sync_2.q_o*") && (ReceivingFlop =~ "top_earlgrey.*.i_dmi_cdc.i_cdc_resp.fifo_rptr*_q[0]*")} -comment {async reset after jtag mux} diff --git a/hw/top_earlgrey/cdc/cdc_waivers.w_data.tcl b/hw/top_earlgrey/cdc/cdc_waivers.w_data.tcl index e6f0501be1b48..c6096e5c0fba7 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.w_data.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.w_data.tcl @@ -88,27 +88,27 @@ set_rule_status -rule {W_DATA} -status {Waived} -expression \ (ReceivingFlop =~ "*top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.*q*")} -comment {SPI read cmds combined} set_rule_status -rule {W_DATA} -status {Waived} -expression \ - {(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && \ + {(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.b_rdata_o*") && \ (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.storage*")} -comment {SPI fwmode mux} set_rule_status -rule {W_DATA} -status {Waived} -expression \ - {(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && \ + {(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.b_rdata_o*") && \ (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.sram_rdata_q*")} -comment {SPI fwmode mux} set_rule_status -rule {W_DATA} -status {Waived} -expression \ - {(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && \ + {(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.b_rdata_o*") && \ (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.p2s_byte_o*")} -comment {SPI readcmd mux} set_rule_status -rule {W_DATA} -status {Waived} -expression \ - {(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && \ + {(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.b_rdata_o*") && \ (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage*")} -comment {SPI readcmd mux} set_rule_status -rule {W_DATA} -status {Waived} -expression \ - {(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && \ + {(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.b_rdata_o*") && \ (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo.storage*")} -comment {SPI readcmd mux} set_rule_status -rule {W_DATA} -status {Waived} -expression \ - {(Signal=~"top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[3:0]") && \ + {(Signal=~"top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_wptr.u_sync_2.q_o[3:0]") && \ (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata*")} -comment {SPI reg mux} set_rule_status -rule {W_DATA} -status {Waived} -expression \ @@ -137,7 +137,7 @@ set_rule_status -rule {W_DATA} -status {Waived} -expression \ (ReceivingFlop =~ "u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_ext_en_q")} -comment {W_DATA issues in AST block} set_rule_status -rule {W_DATA} -status {Waived} -expression \ - {(Signal=~"u_ast.u_ast_clks_byp.*_clk_byp_dgl.gen_generic.u_impl_generic.q_o*") && \ + {(Signal=~"u_ast.u_ast_clks_byp.*_clk_byp_dgl.q_o*") && \ (ReceivingFlop =~ "u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_*_sel")} -comment {W_DATA issues in AST block} set_rule_status -rule {W_DATA} -status {Waived} -expression {(Signal=~"u_ast.dft_scan_md_o*") && (ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon*_scan*")} -comment {W_DATA issues in AST block} @@ -156,21 +156,21 @@ set_rule_status -rule {W_DATA} -status {Waived} -expression {(ReceivingFlop=~"to set_rule_status -rule {W_DATA} -status {Waived} -expression {(Signal=~"IO*") && (ReceivingFlop =~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.rx_buf_q[3:0]*")} -comment {W_DATA issues caused by duplicate clocks on PAD} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon*_scan*") && (Signal =~ "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.*_o") && (Association =~ "None")} -status {Waived} -comment {clock mux} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_step_down_acks_sync.gen_generic.u_impl_generic.q_o[1]") && (Signal =~ "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.step_down_ack_o") && (Association =~ "None")} -status {Waived} -comment {clock mux} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_step_down_acks_sync.gen_generic.u_impl_generic.q_o[0]") && (Signal =~ "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div2_div.gen_div2.step_down_nq") && (Association =~ "None")} -status {Waived} -comment {clock mux} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[23:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_spid_status.sck_status_staged[23:0]") && (Association =~ "None")} -status {Waived} -comment {tool doesn't recognize multiple spi clocks on the same domain} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_step_down_acks_sync.q_o[1]") && (Signal =~ "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.step_down_ack_o") && (Association =~ "None")} -status {Waived} -comment {clock mux} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_step_down_acks_sync.q_o[0]") && (Signal =~ "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div2_div.gen_div2.step_down_nq") && (Association =~ "None")} -status {Waived} -comment {clock mux} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.q_o[23:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_spid_status.sck_status_staged[23:0]") && (Association =~ "None")} -status {Waived} -comment {tool doesn't recognize multiple spi clocks on the same domain} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.sd_i_q[3:0]") && (Signal =~ "IOR3") && (Association =~ "None")} -status {Waived} -comment {tool does not recognize duplicate clocks on PAD} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.sr_q[3:0]") && (Signal =~ "IOR3") && (Association =~ "None")} -status {Waived} -comment {tool does not recognize duplicate clocks on PAD} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o*") && (Signal =~ "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o*") && (Association =~ "None")} -status {Waived} -comment {tool does not recognize duplicate clocks on PAD} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spid_status.sys_status_o[23:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[23:0]") && (Association =~ "None")} -status {Waived} -comment {signal is qualified by synchronized pulse} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.*_q*") && (Signal =~ "top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {signal is synchronized and qualified} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o*") && (Signal =~ "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.q_o*") && (Association =~ "None")} -status {Waived} -comment {tool does not recognize duplicate clocks on PAD} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spid_status.sys_status_o[23:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.q_o[23:0]") && (Association =~ "None")} -status {Waived} -comment {signal is qualified by synchronized pulse} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.*_q*") && (Signal =~ "top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.q_o[3:0]") && (Association =~ "None")} -status {Waived} -comment {signal is synchronized and qualified} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.*_q*") && (Signal =~ "IOR*") && (Association =~ "None")} -status {Waived} -comment {W_DATA issues caused by duplicate clocks on PAD} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spi_tpm.is_*_reg*") && (Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_cfg*") && (Association =~ "None")} -status {Waived} -comment {signal is qualified by synchronized pulse} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_upload.*_cmdfifo_set*") && (Signal =~ "top_earlgrey.u_spi_device.u_upload.*_cmdfifo_set*") && (Association =~ "None")} -status {Waived} -comment {tool doesn't recognize multiple spi clocks on the same domain} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.u_readbuffer.watermark_crossed*") && (Signal =~ "top_earlgrey.u_spi_device.u_reg.u_read_threshold.q[9:0]*") && (Association =~ "None")} -status {Waived} -comment {tool doesn't recognize multiple spi clocks on the same domain} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.*.i_dmi_jtag_tap.bypass_q*") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*") && (Association =~ "None")} -status {Waived} -comment {JTAG mux in quasi-static} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.*.i_dmi_jtag_tap.bypass_q*") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.q_o*") && (Association =~ "None")} -status {Waived} -comment {JTAG mux in quasi-static} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.*.i_dmi_jtag_tap.bypass_q*") && (Signal =~ "top_earlgrey.u_pinmux_aon.mio_pad_attr_q*") && (Association =~ "None")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -comment {JTAG mux in quasi-static} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.*.i_dmi_jtag_tap.bypass_q*") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q*") && (Association =~ "None")} -status {Waived} -comment {JTAG mux in quasi-static} -set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.*.i_dmi_jtag_tap.bypass_q*") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (Association =~ "None")} -status {Waived} -comment {JTAG mux in quasi-static} +set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "top_earlgrey.*.i_dmi_jtag_tap.bypass_q*") && (Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.q_o*") && (Association =~ "None")} -status {Waived} -comment {JTAG mux in quasi-static} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "u_ast.rng_en_i*") && (Signal =~ "top_earlgrey.u_entropy_src.*") && (Association =~ "None")} -status {Waived} -comment {Clarified by Nuvoton : ast liberty model does not have a synchronizer} set_rule_status -rule {W_DATA} -expression {(ReceivingFlop =~ "u_ast.rng_fips_i*") && (Signal =~ "top_earlgrey.u_entropy_src.*") && (Association =~ "None")} -status {Waived} -comment {Clarified by Nuvoton : ast liberty model does not have a synchronizer} diff --git a/hw/top_earlgrey/cdc/cdc_waivers.w_fanout.tcl b/hw/top_earlgrey/cdc/cdc_waivers.w_fanout.tcl index 1ac9c08749254..5a0160d9fddce 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.w_fanout.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.w_fanout.tcl @@ -5,14 +5,14 @@ # Verix CDC waiver file set_rule_status -rule {W_FANOUT} -expression {Driver =~ "*u_lc_ctrl*.u_prim_lc_sender_escalate_en*"} -status {Waived} -comment {No Reconvergence issue. Each IP handles Escalate En individually} -set_rule_status -rule {W_FANOUT} -expression {(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_alert_handler.u_alert_handler_lpg_ctrl.gen_lpgs*.u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o*") && (Driver =~ "top_earlgrey.u_rstmgr_aon.*.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {Independent fanout in different clock domains} -set_rule_status -rule {W_FANOUT} -expression {(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[124]") && (Driver =~ "top_earlgrey.u_rv_timer.gen_harts[0].u_intr_hw.intr_o[0]")} -status {Waived} -comment {Independent fanout in different clock domains} -set_rule_status -rule {W_FANOUT} -expression {(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_rv_core_ibex.u_intr_timer_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Driver =~ "top_earlgrey.u_rv_timer.gen_harts[0].u_intr_hw.intr_o[0]")} -status {Waived} -comment {Independent fanout in different clock domains} -set_rule_status -rule {W_FANOUT} -expression {(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_clkmgr_aon.u_main_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Driver =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.ip_clk_en_q")} -status {Waived} -comment {Independent fanout in different clock domains} -set_rule_status -rule {W_FANOUT} -expression {(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_clkmgr_aon.u_io_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Driver =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.ip_clk_en_q")} -status {Waived} -comment {Independent fanout in different clock domains} -set_rule_status -rule {W_FANOUT} -expression {(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_clkmgr_aon.u_io_div2_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Driver =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.ip_clk_en_q")} -status {Waived} -comment {Independent fanout in different clock domains} -set_rule_status -rule {W_FANOUT} -expression {(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Driver =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[0]")} -status {Waived} -comment {Independent fanout in different clock domains} -set_rule_status -rule {W_FANOUT} -expression {(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_over.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o*") && (Driver =~ "top_earlgrey.u_otp_ctrl.gen_partitions*.gen_buffered.u_part_buf.dout_locked_q*")} -status {Waived} -comment {Independent fanout in different clock domains} -set_rule_status -rule {W_FANOUT} -expression {(Fanout =~ "top_earlgrey.u_alert_handler.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Driver =~ "top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_main_infra.gen_flops.u_prim_flop.gen_generic.u_impl_generic.q_o[0]")} -status {Waived} -comment {Independent fanout in different clock domains} -set_rule_status -rule {W_FANOUT} -expression {(Fanout =~ "top_earlgrey.u_alert_handler.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Driver =~ "top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_main_infra.gen_flops.u_prim_flop.gen_generic.u_impl_generic.q_o[0]")} -status {Waived} -comment {Independent fanout in different clock domains} -set_rule_status -rule {W_FANOUT} -expression {(Fanout =~ "top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Driver =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[0]")} -status {Waived} -comment {included in waived paths} +set_rule_status -rule {W_FANOUT} -expression {(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_alert_handler.u_alert_handler_lpg_ctrl.gen_lpgs*.u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.u_sync_1.q_o*") && (Driver =~ "top_earlgrey.u_rstmgr_aon.*.u_prim_mubi4_sender.gen_flops.u_prim_flop.q_o*")} -status {Waived} -comment {Independent fanout in different clock domains} +set_rule_status -rule {W_FANOUT} -expression {(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.q_o[124]") && (Driver =~ "top_earlgrey.u_rv_timer.gen_harts[0].u_intr_hw.intr_o[0]")} -status {Waived} -comment {Independent fanout in different clock domains} +set_rule_status -rule {W_FANOUT} -expression {(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_rv_core_ibex.u_intr_timer_sync.u_sync_1.q_o[0]") && (Driver =~ "top_earlgrey.u_rv_timer.gen_harts[0].u_intr_hw.intr_o[0]")} -status {Waived} -comment {Independent fanout in different clock domains} +set_rule_status -rule {W_FANOUT} -expression {(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_clkmgr_aon.u_main_root_ctrl.u_cg.i_sync.u_sync_1.q_o[0]") && (Driver =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.ip_clk_en_q")} -status {Waived} -comment {Independent fanout in different clock domains} +set_rule_status -rule {W_FANOUT} -expression {(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_clkmgr_aon.u_io_root_ctrl.u_cg.i_sync.u_sync_1.q_o[0]") && (Driver =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.ip_clk_en_q")} -status {Waived} -comment {Independent fanout in different clock domains} +set_rule_status -rule {W_FANOUT} -expression {(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_clkmgr_aon.u_io_div2_root_ctrl.u_cg.i_sync.u_sync_1.q_o[0]") && (Driver =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.ip_clk_en_q")} -status {Waived} -comment {Independent fanout in different clock domains} +set_rule_status -rule {W_FANOUT} -expression {(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_1.q_o[0]") && (Driver =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[0]")} -status {Waived} -comment {Independent fanout in different clock domains} +set_rule_status -rule {W_FANOUT} -expression {(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_over.gen_flops.u_prim_flop_2sync.u_sync_1.q_o*") && (Driver =~ "top_earlgrey.u_otp_ctrl.gen_partitions*.gen_buffered.u_part_buf.dout_locked_q*")} -status {Waived} -comment {Independent fanout in different clock domains} +set_rule_status -rule {W_FANOUT} -expression {(Fanout =~ "top_earlgrey.u_alert_handler.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.u_sync_1.q_o[0]") && (Driver =~ "top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_main_infra.gen_flops.u_prim_flop.q_o[0]")} -status {Waived} -comment {Independent fanout in different clock domains} +set_rule_status -rule {W_FANOUT} -expression {(Fanout =~ "top_earlgrey.u_alert_handler.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.u_sync_1.q_o[0]") && (Driver =~ "top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_main_infra.gen_flops.u_prim_flop.q_o[0]")} -status {Waived} -comment {Independent fanout in different clock domains} +set_rule_status -rule {W_FANOUT} -expression {(Fanout =~ "top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_read.gen_flops.u_prim_flop_2sync.u_sync_1.q_o[0]") && (Driver =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[0]")} -status {Waived} -comment {included in waived paths} diff --git a/hw/top_earlgrey/cdc/cdc_waivers.w_g_clk_glitch.tcl b/hw/top_earlgrey/cdc/cdc_waivers.w_g_clk_glitch.tcl index 0edbc2ea01bfc..634669003b6c6 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.w_g_clk_glitch.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.w_g_clk_glitch.tcl @@ -43,15 +43,15 @@ set_rule_status -rule {W_G_CLK_GLITCH} -status {Waived} -expression set_rule_status -rule {W_G_CLK_GLITCH} -status {Waived} -expression \ {(GatedClockInput=~"u_ast.*.*h_o*") && \ - (GatedClock=~ "u_ast.u_*_clk.u_*_osc.u_clk_ckgt.gen_generic.u_impl_generic.clk_o*")} -comment {W_G_CLK_GLITCH issues in AST} + (GatedClock=~ "u_ast.u_*_clk.u_*_osc.u_clk_ckgt.clk_o*")} -comment {W_G_CLK_GLITCH issues in AST} -set_rule_status -rule {W_G_CLK_GLITCH} -status {Waived} -expression {(GatedClock=~ "top_earlgrey.u_clkmgr_aon.*.gen_generic.u_impl_generic.clk_o*")} -comment {W_G_CLK_GLITCH issues caused by AST and PAD} -set_rule_status -rule {W_G_CLK_GLITCH} -status {Waived} -expression {(GatedClock=~ "top_earlgrey.u_clkmgr_aon.*.gen_generic.u_impl_generic.clk_o*")} -comment {W_G_CLK_GLITCH issues caused by AST and PAD} -set_rule_status -rule {W_G_CLK_GLITCH} -status {Waived} -expression {(GatedClock=~ "top_earlgrey.u_lc_ctrl.*.gen_generic.u_impl_generic.clk_o*")} -comment {W_G_CLK_GLITCH issues caused by AST and PAD} -set_rule_status -rule {W_G_CLK_GLITCH} -status {Waived} -expression {(GatedClock=~ "top_earlgrey.u_rv_core_ibex.*.gen_generic.u_impl_generic.clk_o*")} -comment {W_G_CLK_GLITCH issues caused by AST and PAD} -set_rule_status -rule {W_G_CLK_GLITCH} -status {Waived} -expression {(GatedClock=~ "top_earlgrey.u_spi_device.*.gen_generic.u_impl_generic.clk_o*")} -comment {W_G_CLK_GLITCH issues caused by AST and PAD} +set_rule_status -rule {W_G_CLK_GLITCH} -status {Waived} -expression {(GatedClock=~ "top_earlgrey.u_clkmgr_aon.*.clk_o*")} -comment {W_G_CLK_GLITCH issues caused by AST and PAD} +set_rule_status -rule {W_G_CLK_GLITCH} -status {Waived} -expression {(GatedClock=~ "top_earlgrey.u_clkmgr_aon.*.clk_o*")} -comment {W_G_CLK_GLITCH issues caused by AST and PAD} +set_rule_status -rule {W_G_CLK_GLITCH} -status {Waived} -expression {(GatedClock=~ "top_earlgrey.u_lc_ctrl.*.clk_o*")} -comment {W_G_CLK_GLITCH issues caused by AST and PAD} +set_rule_status -rule {W_G_CLK_GLITCH} -status {Waived} -expression {(GatedClock=~ "top_earlgrey.u_rv_core_ibex.*.clk_o*")} -comment {W_G_CLK_GLITCH issues caused by AST and PAD} +set_rule_status -rule {W_G_CLK_GLITCH} -status {Waived} -expression {(GatedClock=~ "top_earlgrey.u_spi_device.*.clk_o*")} -comment {W_G_CLK_GLITCH issues caused by AST and PAD} set_rule_status -rule {W_G_CLK_GLITCH} -status {Waived} -expression {(GatedClock=~ "u_ast.clk_src*_o*")} -comment {W_G_CLK_GLITCH issues caused by AST and PAD} set_rule_status -rule {W_G_CLK_GLITCH} -status {Waived} -expression {(GatedClock=~ "top_earlgrey.u_rv_dm.jtag_in_int.tck*")} -comment {W_G_CLK_GLITCH issues caused by AST and PAD} -set_rule_status -rule {W_G_CLK_GLITCH} -status {Waived} -expression {(GatedClock=~ "u_padring.gen_*io_pads*.u_*io_pad.gen_generic.u_impl_generic.in_o*")} -comment {W_G_CLK_GLITCH issues in PAD logic} -set_rule_status -rule {W_G_CLK_GLITCH} -expression {(GatedClock == "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic.clk_o") && (GlitchType == "ASYNC_INPUT")} -status {Waived} -comment {W_G_CLK_GLITCH issues in clkmux library. We created another clock mux to avoid any potential glitch} -set_rule_status -rule {W_G_CLK_GLITCH} -expression {(GatedClock == "top_earlgrey.u_rv_dm.u_prim_clock_mux2.gen_generic.u_impl_generic.clk_o") && (GlitchType == "ASYNC_INPUT")} -status {Waived} -comment {W_G_CLK_GLITCH issues in clkmux library. We created another clock mux to avoid any potential glitch} +set_rule_status -rule {W_G_CLK_GLITCH} -status {Waived} -expression {(GatedClock=~ "u_padring.gen_*io_pads*.u_*io_pad.in_o*")} -comment {W_G_CLK_GLITCH issues in PAD logic} +set_rule_status -rule {W_G_CLK_GLITCH} -expression {(GatedClock == "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.i_tck_inv.gen_scan.i_dft_tck_mux.clk_o") && (GlitchType == "ASYNC_INPUT")} -status {Waived} -comment {W_G_CLK_GLITCH issues in clkmux library. We created another clock mux to avoid any potential glitch} +set_rule_status -rule {W_G_CLK_GLITCH} -expression {(GatedClock == "top_earlgrey.u_rv_dm.u_prim_clock_mux2.clk_o") && (GlitchType == "ASYNC_INPUT")} -status {Waived} -comment {W_G_CLK_GLITCH issues in clkmux library. We created another clock mux to avoid any potential glitch} diff --git a/hw/top_earlgrey/cdc/cdc_waivers.w_interface.tcl b/hw/top_earlgrey/cdc/cdc_waivers.w_interface.tcl index ce4aa55987f17..0d3b26324e20c 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.w_interface.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.w_interface.tcl @@ -31,12 +31,12 @@ set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_ set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo.u_fifo_cnt.*ptr_o[1:0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_readcmd.u_readsram.st_q[1:0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_upload.st_q[1:0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_2.q_o[4:0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_upload.u_cmdfifo.w_wptr_q[4:0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.gen_normal_case.mask[2:0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_upload.addrcnt[4:0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_upload.u_addrfifo.w_wptr_q[4:0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_2.q_o[4:0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_wptr_gray_q[3:0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_rx_order.q[0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.storage*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} @@ -54,7 +54,7 @@ set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_ set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.fifo_rptr_gray_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo.fifo_rptr_gray_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_out_retreg_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.q_o*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dr_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_xbar_main.u_asf_35.reqfifo.fifo_*ptr_gray_q[0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.src_level")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} @@ -78,31 +78,31 @@ set_rule_status -rule {W_INTERFACE} -expression {(ComponentClass =~ "CNTL") && ( set_rule_status -rule {W_INTERFACE} -expression {(ComponentClass =~ "CNTL") && (ErrorType =~ "") && (MultiClockDomains =~ "AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (Signal =~ "top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.src_fsm_q")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(ComponentClass =~ "FEEDBACK") && (ErrorType =~ "") && (MultiClockDomains =~ "AST_EXT_CLK,JTAG_TCK,MAIN_CLK::AST_EXT_CLK,MAIN_CLK") && (Signal =~ "top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.dst_fsm_q")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_*xf_ctrl.*ptr*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_*x*.q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.dst_fsm_q") && (ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors and fifo with feedback path} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_rom_ctrl.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_done_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {rom_ctrl_i.good is not synchronized as it acts as a "payload" signal to "done". Good is only observed if "done" is high} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "IOB*") && (ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {rom_ctrl_i.good is not synchronized as it acts as a "payload" signal to "done". Good is only observed if "done" is high} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_rv_core_ibex.core_sleep_q*") && (ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_cdc.*.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {Handled by CDC handshaking} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_rom_ctrl.gen_fsm_scramble_enabled.u_checker_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_cdc.*.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_flash_ctrl.u_reg_idle.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_cdc.*.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.u_fetch_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.ip_clk_en_q*") && (ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.*.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_io_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.*.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_reg.u_clk_enables_clk_io_peri_en.q*") && (ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.*.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_io_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_alert_handler.*.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_host0.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_alert_handler.*.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_host0.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_alert_handler.*.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.dst_fsm_q") && (ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors and fifo with feedback path} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_rom_ctrl.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_done_sender.gen_flops.u_prim_flop.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.q_o*")} -status {Waived} -comment {rom_ctrl_i.good is not synchronized as it acts as a "payload" signal to "done". Good is only observed if "done" is high} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "IOB*") && (ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.q_o*")} -status {Waived} -comment {rom_ctrl_i.good is not synchronized as it acts as a "payload" signal to "done". Good is only observed if "done" is high} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_rv_core_ibex.core_sleep_q*") && (ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_cdc.*.u_sync_1.q_o*")} -status {Waived} -comment {Handled by CDC handshaking} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_rom_ctrl.gen_fsm_scramble_enabled.u_checker_fsm.u_state_regs.u_state_flop.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_cdc.*.u_sync_1.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_flash_ctrl.u_reg_idle.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_cdc.*.u_sync_1.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.u_fetch_en.gen_flops.u_prim_flop.u_secure_anchor_flop.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.u_prim_flop_2sync.u_sync_1.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.ip_clk_en_q*") && (ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.*.u_sync_1.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_io_root_ctrl.u_cg.i_sync.u_sync_2.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.*.u_sync_1.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_reg.u_clk_enables_clk_io_peri_en.q*") && (ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.*.u_sync_1.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_io_peri.gen_flops.u_prim_flop.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_alert_handler.*.u_sync_1.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_host0.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_alert_handler.*.u_sync_1.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_host0.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_alert_handler.*.u_sync_1.q_o*")} -status {Waived} -comment {Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pinmux_aon.mio_pad_attr_q*") && (ReceivingFlop =~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.rx_buf_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q*") && (ReceivingFlop =~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.rx_buf_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.rx_buf_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.rx_buf_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.rx_buf_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.rx_buf_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_*.q*") && (ReceivingFlop =~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.rx_buf_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_reg.u_clk_enables_clk_io_div2_peri_en.q*") && (ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.u_clk_io_div2_peri_sw_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_io_div2_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.u_clk_io_div2_peri_sw_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_host1.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_alert_handler.gen_alerts[20].u_alert_receiver.u_decode_alert.gen_async.i_sync_*.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_io_div2_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.u_io_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_io_div2_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_alert_handler.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_reg.u_clk_enables_clk_io_div2_peri_en.q*") && (ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.u_clk_io_div2_peri_sw_en_sync.u_sync_1.q_o*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_io_div2_peri.gen_flops.u_prim_flop.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.u_clk_io_div2_peri_sw_en_sync.u_sync_1.q_o*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_host1.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_alert_handler.gen_alerts[20].u_alert_receiver.u_decode_alert.gen_async.i_sync_*.u_sync_1.q_o*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_io_div2_root_ctrl.u_cg.i_sync.u_sync_2.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.u_io_status.u_en_sync.u_sync_1.q_o*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_io_div2_peri.gen_flops.u_prim_flop.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_alert_handler.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.u_sync_1.q_o*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pinmux_aon.mio_pad_attr_q*") && (ReceivingFlop =~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.*_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q*") && (ReceivingFlop =~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.*_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.*_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.*_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.*_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.*_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_*.q*") && (ReceivingFlop =~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.*_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} diff --git a/hw/top_earlgrey/cdc/cdc_waivers.w_masync.tcl b/hw/top_earlgrey/cdc/cdc_waivers.w_masync.tcl index 997f28db61da5..8adcd48dd2478 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.w_masync.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.w_masync.tcl @@ -8,7 +8,7 @@ # Two paths from different clock domains are muxed and CDC is processed by the following Tx_FIFO. # But, the tool seems not to recognize the FIFO after the mux. set_rule_status -rule {W_MASYNC} -status {Waived} \ - -expression {(Driver =~ "top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_fwmode.*")} \ + -expression {(Driver =~ "top_earlgrey.u_spi_device.u_memory_2p.u_mem.b_rdata_o*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_fwmode.*")} \ -comment {Dual port memory read port to SPI} set_rule_status -rule {W_MASYNC} -status {Waived} \ @@ -78,7 +78,7 @@ set_rule_status -rule {W_MASYNC} -status {Waived} \ # PAD to sync FFs set_rule_status -rule {W_MASYNC} -status {Waived} \ - -expression {(Driver =~ "IO*") && (ReceivingFlop=~"*u_sync_1.gen_generic.u_impl_generic.q_o*")} \ + -expression {(Driver =~ "IO*") && (ReceivingFlop=~"*u_sync_1.q_o*")} \ -comment {retention regs} # PAD to sync FFs @@ -99,7 +99,7 @@ set_rule_status -rule {W_MASYNC} -status {Waived} \ -comment {retention regs} set_rule_status -rule {W_MASYNC} -status {Waived} \ - -expression {(Driver =~ "top_earlgrey.u_rv_dm.u_lc_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_lc_ctrl.u_dmi_jtag.*_q*")} \ + -expression {(Driver =~ "top_earlgrey.u_rv_dm.u_lc_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.q_o*") && (ReceivingFlop=~"top_earlgrey.u_lc_ctrl.u_dmi_jtag.*_q*")} \ -comment {retention regs} @@ -112,7 +112,7 @@ set_rule_status -rule {W_MASYNC} -status {Waived} \ -comment {retention regs} set_rule_status -rule {W_MASYNC} -status {Waived} \ - -expression {(Driver =~ "top_earlgrey.u_rv_dm.u_lc_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.bypass_q*")} \ + -expression {(Driver =~ "top_earlgrey.u_rv_dm.u_lc_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.q_o*") && (ReceivingFlop=~"top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.bypass_q*")} \ -comment {retention regs} @@ -129,7 +129,7 @@ set_rule_status -rule {W_MASYNC} -status {Waived} \ -comment {retention regs} set_rule_status -rule {W_MASYNC} -status {Waived} \ - -expression {(Driver =~ "top_earlgrey.u_rv_dm.u_lc_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_rv_dm.dap.*zero1*")} \ + -expression {(Driver =~ "top_earlgrey.u_rv_dm.u_lc_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.q_o*") && (ReceivingFlop=~"top_earlgrey.u_rv_dm.dap.*zero1*")} \ -comment {retention regs} set_rule_status -rule {W_MASYNC} -status {Waived} \ @@ -137,7 +137,7 @@ set_rule_status -rule {W_MASYNC} -status {Waived} \ -comment {retention regs} set_rule_status -rule {W_MASYNC} -status {Waived} \ - -expression {(Driver =~ "top_earlgrey.u_lc_ctrl.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_xbar_main.*num_req_outstanding*")} \ + -expression {(Driver =~ "top_earlgrey.u_lc_ctrl.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.q_o*") && (ReceivingFlop=~"top_earlgrey.u_xbar_main.*num_req_outstanding*")} \ -comment {retention regs} set_rule_status -rule {W_MASYNC} -status {Waived} \ @@ -165,7 +165,7 @@ set_rule_status -rule {W_MASYNC} -status {Waived} \ -comment {retention regs} set_rule_status -rule {W_MASYNC} -status {Waived} \ - -expression {(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.reqfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_usbdev.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.a_*_i")} \ + -expression {(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.reqfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_usbdev.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.a_*_i")} \ -comment {retention regs} # rspfifo to normal_fifo in tlul xbar_main @@ -190,15 +190,15 @@ set_rule_status -rule {W_MASYNC} -status {Waived} \ # tlul xbar_main rspfifo to spi_device set_rule_status -rule {W_MASYNC} -status {Waived} \ - -expression {(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.a_*")} \ + -expression {(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.a_*")} \ -comment {tlul xbar_main rspfifo to spi_device} set_rule_status -rule {W_MASYNC} -status {Waived} \ - -expression {(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.reqfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.a_*")} \ + -expression {(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.reqfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.a_*")} \ -comment {tlul xbar_main rspfifo to spi_device} set_rule_status -rule {W_MASYNC} -status {Waived} \ - -expression {(Driver =~ "*SPI_DEV*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_*")} \ + -expression {(Driver =~ "*SPI_DEV*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.b_*")} \ -comment {PAD to spi_device} set_rule_status -rule {W_MASYNC} -status {Waived} \ @@ -206,11 +206,11 @@ set_rule_status -rule {W_MASYNC} -status {Waived} \ -comment {PAD to spi_device} set_rule_status -rule {W_MASYNC} -status {Waived} \ - -expression {(Driver =~ "*SPI_*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.gen_wkup_detect*.u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o*")} \ + -expression {(Driver =~ "*SPI_*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.gen_wkup_detect*.u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.q_o*")} \ -comment {PAD to spi_device} set_rule_status -rule {W_MASYNC} -status {Waived} \ - -expression {(Driver =~ "*USB_*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.gen_wkup_detect*.u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o*")} \ + -expression {(Driver =~ "*USB_*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.gen_wkup_detect*.u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.q_o*")} \ -comment {PAD to spi_device} set_rule_status -rule {W_MASYNC} -status {Waived} \ @@ -222,7 +222,7 @@ set_rule_status -rule {W_MASYNC} -status {Waived} \ -comment {PAD to pinmux} set_rule_status -rule {W_MASYNC} -status {Waived} \ - -expression {(Driver =~ "top_earlgrey.u_spi_device*.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")} \ + -expression {(Driver =~ "top_earlgrey.u_spi_device*.q_o*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")} \ -comment {another path overlapped with PAD to pinmux} set_rule_status -rule {W_MASYNC} -status {Waived} \ @@ -239,7 +239,7 @@ set_rule_status -rule {W_MASYNC} -status {Waived} \ # tlul xbar_main rspfifo to usb device set_rule_status -rule {W_MASYNC} -status {Waived} \ - -expression {(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_usbdev.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.a_*")} \ + -expression {(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_usbdev.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.a_*")} \ -comment {tlul xbar_main rspfifo to usb device} # W_MASYNC in AST @@ -248,7 +248,7 @@ set_rule_status -rule {W_MASYNC} -status {Waived} \ -comment {w_masync issues in AST block} set_rule_status -rule {W_MASYNC} -status {Waived} \ - -expression {(Driver =~ "u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_*_aoff*") && (ReceivingFlop=~"top_earlgrey.u_pwrmgr_aon.u_cdc.u_ast_sync.u_sync_1.gen_generic.u_impl_generic.q_o*")} \ + -expression {(Driver =~ "u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_*_aoff*") && (ReceivingFlop=~"top_earlgrey.u_pwrmgr_aon.u_cdc.u_ast_sync.u_sync_1.q_o*")} \ -comment {w_masync issues from AST block} set_rule_status -rule {W_MASYNC} -status {Waived} \ @@ -267,30 +267,30 @@ set_rule_status -rule {W_MASYNC} -status {Waived} \ -expression {(Driver =~ "IO*") && (ReceivingFlop=~"top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.*_q*")} \ -comment {w_masync issues from PAD} -set_rule_status -rule {W_MASYNC} -status {Waived} -expression {(ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.a_*_i*")} -comment {multiple source to 2p memory in SPI } -set_rule_status -rule {W_MASYNC} -status {Waived} -expression {(ReceivingFlop=~"top_earlgrey.u_usbdev.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.a_*_i*")} -comment {multiple source to 2p memory in USB} +set_rule_status -rule {W_MASYNC} -status {Waived} -expression {(ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.a_*_i*")} -comment {multiple source to 2p memory in SPI } +set_rule_status -rule {W_MASYNC} -status {Waived} -expression {(ReceivingFlop=~"top_earlgrey.u_usbdev.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.a_*_i*")} -comment {multiple source to 2p memory in USB} set_rule_status -rule {W_MASYNC} -status {Waived} -expression {(Driver =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage*")} -comment {multiple source to readcmd sram in spi device} set_rule_status -rule {W_MASYNC} -status {Waived} -expression {(Driver =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_readcmd.p2s_byte_o*")} -comment {multiple source to 2p memory in spi device} -set_rule_status -rule {W_MASYNC} -status {Waived} -expression {(Driver =~ "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o*")} -comment {multiple source to 2p memory in spi device} -set_rule_status -rule {W_MASYNC} -status {Waived} -expression {(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage[0]*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*")} -comment {xbar main async fifo to rv_core_ibex.gen-alert_senders} +set_rule_status -rule {W_MASYNC} -status {Waived} -expression {(Driver =~ "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.q_o*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o*")} -comment {multiple source to 2p memory in spi device} +set_rule_status -rule {W_MASYNC} -status {Waived} -expression {(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage[0]*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.q_o*")} -comment {xbar main async fifo to rv_core_ibex.gen-alert_senders} set_rule_status -rule {W_MASYNC} -status {Waived} -expression {(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage[0]*") && (ReceivingFlop=~"top_earlgrey.u_xbar_main.u_s1n_57.fifo_h.rspfifo.gen_normal_fifo.u_fifo_cnt.wptr_o*")} -comment {xbar main async fifo to rv_core_ibex.gen-alert_senders} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_p2s.out_shift[7:0]") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_tx_order.q[0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.sram_wdata[31:0]") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.storage[7:0][7:0]")} -status {Waived} -lastedit_user {root} -lastedit_time {Wednesday, 16 November 2022 11:51:02 PDT} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31]") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK") && (Driver =~ "IOR2")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.dtmcs_q.zero1[31]") && (Driver =~ "IOR2")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_lc_ctrl_fsm.u_fsm_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[15:0]") && (Driver =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.data_q[0]")} -status {Waived} -comment {cdc handshaking is not recognized} +set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_lc_ctrl_fsm.u_fsm_state_regs.u_state_flop.q_o[15:0]") && (Driver =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.data_q[0]")} -status {Waived} -comment {cdc handshaking is not recognized} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.dr_q[40]") && (Driver =~ "IOR*")} -status {Waived} -comment {Multiple clocks on PAD} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.dr_q[40]") && (Driver =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.data_q[0]")} -status {Waived} -comment {Multiple clocks on PAD} -set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {Multiple clocks on PAD} -set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[11:0]") && (Driver =~ "top_earlgrey.u_rom_ctrl.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_done_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic.q_o[0]")} -status {Waived} -comment {rom_ctrl_i.good is not synchronized as it acts as a "payload" signal to "done". Good is only observed if "done" is high} -set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[11:0]") && (Driver =~ "IOB1")} -status {Waived} -comment {Multiple clocks on PAD & included in waived path} +set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.q_o*")} -status {Waived} -comment {Multiple clocks on PAD} +set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.q_o[11:0]") && (Driver =~ "top_earlgrey.u_rom_ctrl.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_done_sender.gen_flops.u_prim_flop.q_o[0]")} -status {Waived} -comment {rom_ctrl_i.good is not synchronized as it acts as a "payload" signal to "done". Good is only observed if "done" is high} +set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.q_o[11:0]") && (Driver =~ "IOB1")} -status {Waived} -comment {Multiple clocks on PAD & included in waived path} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0]") && (Driver =~ "u_ast.ast2padmux_o[0]")} -status {Waived} -comment {Multiple clocks on PAD & included in waived path} -set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_*.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o*") && (Driver =~ "USB*")} -status {Waived} -comment {Paired clocks are not recognized by tool} +set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_*.gen_async.prim_flop_2sync.u_sync_1.q_o*") && (Driver =~ "USB*")} -status {Waived} -comment {Paired clocks are not recognized by tool} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.*io_o*_retreg_q*")} -status {Waived} -comment {Multiple clocks on PAD & included in waived path} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "USB_*") && (Driver =~ "top_earlgrey.u_usbdev.u_reg.u_phy_pins_drive_dp_o.q[0]")} -status {Waived} -comment {Paired clocks are not recognized by tool} -set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks*.u_prim_flash_bank.st_q*")} -status {Waived} -comment {Multiple clocks on PAD & included in waived path} +set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks*.u_prim_flash_bank.st_q*")} -status {Waived} -comment {Multiple clocks on PAD & included in waived path} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.*_q*")} -status {Waived} -comment {Multiple clocks on PAD & included in waived path} -set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31]") && (MultiClockDomains =~ "AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (Driver =~ "top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")} -status {Waived} -lastedit_user {root} -lastedit_time {Wednesday, 16 November 2022 16:19:54 PDT} +set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31]") && (MultiClockDomains =~ "AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (Driver =~ "top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.q_o[0]")} -status {Waived} -lastedit_user {root} -lastedit_time {Wednesday, 16 November 2022 16:19:54 PDT} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dr_q[40]") && (Driver =~ "top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dr_q[40]") && (Driver =~ "top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.data_q[0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "USB_*")} -status {Waived} -comment {Paired clocks are not recognized by tool} diff --git a/hw/top_earlgrey/cdc/cdc_waivers.w_net_no_wave.tcl b/hw/top_earlgrey/cdc/cdc_waivers.w_net_no_wave.tcl index 6fbd31ff7383f..7aab2e4312346 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.w_net_no_wave.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.w_net_no_wave.tcl @@ -5,4 +5,4 @@ # Verix CDC waiver file set_rule_status -rule {S_NET_NO_WAVE} -expression {(Signal =~ "ast_init_done[3:1]") && (DriverType =~ "Undriven") && (FanoutClockDomain == "IO_DIV4_CLK")} -status {Waived} -comment {prim_mubi4_sync was not recognized by CDC tool} -set_rule_status -rule {S_NET_NO_WAVE} -expression {(Signal =~ "top_earlgrey.*.u_memory_2p*u_mem.gen_generic.u_impl_generic.*_rdata_o*")} -status {Waived} -comment {Signals from 2p memory} +set_rule_status -rule {S_NET_NO_WAVE} -expression {(Signal =~ "top_earlgrey.*.u_memory_2p*u_mem.*_rdata_o*")} -status {Waived} -comment {Signals from 2p memory} diff --git a/hw/top_earlgrey/cdc/cdc_waivers.w_recon.tcl b/hw/top_earlgrey/cdc/cdc_waivers.w_recon.tcl index 5f449280b5819..c98772081c078 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.w_recon.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.w_recon.tcl @@ -4,35 +4,35 @@ # # Verix CDC waiver file -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_rv_core_ibex*.*rdata*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_rv_core_ibex*.*gen_alert_senders*.*alert_test_seq_q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*gen_alert_tx*.u_prim_alert_sender*.*q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_sram_ctrl_main.u_prim_alert_sender*.*q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_flash_ctrl*.*u_state_flop*.*impl_generic*.q_o*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_flash_ctrl*.*gen_alert_senders*.*alert_test_seq_q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_keymgr.u_ctrl.key_state_ecc_q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_keymgr.u_falut_alert.state_q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_keymgr.*.lfsr_q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_keymgr.*.u_fault_alert_state_q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_alert_handler.gen_classes*.u_accu.*impl_generic*.q_o*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*.u_reg.*.src_busy_q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*.u_reg.*.u_intr_state.q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_alert_sender.alert_test_seq_q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_reg.u_reg_if.rdata*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_sysrst_ctrl_aon.u_reg.*.u_intr_state.q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_aon_timer_aon.u_reg.*.src_busy_q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pinmux_aon.u_reg.*.src_busy_q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pinmux_aon.u_reg.*.u_dio_pad_sleep_statue_en_0.q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_rv_core_ibex*.*rdata*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_rv_core_ibex*.*gen_alert_senders*.*alert_test_seq_q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*gen_alert_tx*.u_prim_alert_sender*.*q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_sram_ctrl_main.u_prim_alert_sender*.*q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_flash_ctrl*.*u_state_flop*.*impl_generic*.q_o*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_flash_ctrl*.*gen_alert_senders*.*alert_test_seq_q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_keymgr.u_ctrl.key_state_ecc_q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_keymgr.u_falut_alert.state_q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_keymgr.*.lfsr_q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_keymgr.*.u_fault_alert_state_q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_alert_handler.gen_classes*.u_accu.*impl_generic*.q_o*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*.u_reg.*.src_busy_q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*.u_reg.*.u_intr_state.q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_alert_sender.alert_test_seq_q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_reg.u_reg_if.rdata*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_sysrst_ctrl_aon.u_reg.*.u_intr_state.q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_aon_timer_aon.u_reg.*.src_busy_q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_pinmux_aon.u_reg.*.src_busy_q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_pinmux_aon.u_reg.*.u_dio_pad_sleep_statue_en_0.q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_clkmgr_aon.u_reg.*.*meas_ctrl_en_cdc*.id_q*")} -comment {Intended reconvergence in clkmgr} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_clkmgr_aon.u_reg.*.*u_io_meas.src_err_req")} -comment {Intended reconvergence in clkmgr} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_alert_handler.gen_alerts**.u_alert_receiver*.*impl_generic*.q_o*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_kmac.gen_entropy.*.u_lfsr_chunk.lfsr_q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pwrmgr_aon.u_reg.u_intr_state.q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pwrmgr_aon.u_reg.u_reg_if.rdata*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pwrmgr_aon.i_wake_info.info*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_rstmgr_aon.u_reg.u_reg_if.rdata*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_adc_ctrl_aon.u_reg.u_intr_state.q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_adc_ctrl_aon.u_reg.*.src_busy_q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_clkmgr_aon.u_reg.*.*meas_ctrl_en_cdc*.id_q*")} -comment {Intended reconvergence in clkmgr} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_clkmgr_aon.u_reg.*.*u_io_meas.src_err_req")} -comment {Intended reconvergence in clkmgr} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_alert_handler.gen_alerts**.u_alert_receiver*.*impl_generic*.q_o*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_kmac.gen_entropy.*.u_lfsr_chunk.lfsr_q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_pwrmgr_aon.u_reg.u_intr_state.q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_pwrmgr_aon.u_reg.u_reg_if.rdata*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_pwrmgr_aon.i_wake_info.info*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_rstmgr_aon.u_reg.u_reg_if.rdata*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_adc_ctrl_aon.u_reg.u_intr_state.q*")} -comment {multiple sources with mux} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_adc_ctrl_aon.u_reg.*.src_busy_q*")} -comment {multiple sources with mux} -set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_ast_clks_byp.*io_clk*src*")} -comment {Intended reconvergence in clkmgr} +set_rule_status -rule {W_RECON_GROUPS} -status {Waived} -expression {(ControlSignal=~"*u_sync_1.q_o**") && (ReconSignal=~"*u_ast_clks_byp.*io_clk*src*")} -comment {Intended reconvergence in clkmgr} diff --git a/hw/top_earlgrey/chip_earlgrey_asic.core b/hw/top_earlgrey/chip_earlgrey_asic.core index ff10ddbc9768d..af1d800e7e987 100644 --- a/hw/top_earlgrey/chip_earlgrey_asic.core +++ b/hw/top_earlgrey/chip_earlgrey_asic.core @@ -14,6 +14,8 @@ filesets: - "fileset_partner ? (partner:systems:scan_role_pkg)" - "!fileset_partner ? (lowrisc:systems:ast)" - "!fileset_partner ? (lowrisc:systems:scan_role_pkg)" + - "!fileset_partner ? (lowrisc:prim:prim_legacy_pkg)" + - "!fileset_partner ? (lowrisc:prim_generic:all)" files: - rtl/autogen/chip_earlgrey_asic.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/chip_earlgrey_cw310.core b/hw/top_earlgrey/chip_earlgrey_cw310.core index 63a60d53d2940..2422902ab102d 100644 --- a/hw/top_earlgrey/chip_earlgrey_cw310.core +++ b/hw/top_earlgrey/chip_earlgrey_cw310.core @@ -13,6 +13,8 @@ filesets: - lowrisc:systems:ast - lowrisc:systems:padring - lowrisc:systems:scan_role_pkg + - lowrisc:prim:prim_legacy_pkg + - lowrisc:prim_xilinx:all files: - rtl/clkgen_xil7series.sv - rtl/usr_access_xil7series.sv diff --git a/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core b/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core index 2b9d8a98b1983..764370d85be36 100644 --- a/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core +++ b/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core @@ -13,6 +13,8 @@ filesets: - lowrisc:systems:ast - lowrisc:systems:padring - lowrisc:systems:scan_role_pkg + - lowrisc:prim:prim_legacy_pkg + - lowrisc:prim_xilinx:all files: - rtl/clkgen_xil7series.sv - rtl/usr_access_xil7series.sv diff --git a/hw/top_earlgrey/chip_earlgrey_cw340.core b/hw/top_earlgrey/chip_earlgrey_cw340.core index 9aa63ad4ea0ab..9fbbf891d9ff2 100644 --- a/hw/top_earlgrey/chip_earlgrey_cw340.core +++ b/hw/top_earlgrey/chip_earlgrey_cw340.core @@ -13,6 +13,8 @@ filesets: - lowrisc:systems:ast - lowrisc:systems:padring - lowrisc:systems:scan_role_pkg + - lowrisc:prim:prim_legacy_pkg + - lowrisc:prim_xilinx_ultrascale:all files: - rtl/clkgen_xil_ultrascale.sv - rtl/usr_access_xil7series.sv diff --git a/hw/top_earlgrey/chip_earlgrey_verilator.core b/hw/top_earlgrey/chip_earlgrey_verilator.core index 6c6b694f7021a..48d115e54412a 100644 --- a/hw/top_earlgrey/chip_earlgrey_verilator.core +++ b/hw/top_earlgrey/chip_earlgrey_verilator.core @@ -13,6 +13,8 @@ filesets: - lowrisc:prim:clock_div - lowrisc:systems:ast - lowrisc:systems:scan_role_pkg + - lowrisc:prim:prim_legacy_pkg + - lowrisc:prim_generic:all files: - rtl/chip_earlgrey_verilator.sv: { file_type: systemVerilogSource } diff --git a/hw/top_earlgrey/data/clocks.xdc b/hw/top_earlgrey/data/clocks.xdc index 4d54bcf4ba0f1..c6f2cb28c9a0a 100644 --- a/hw/top_earlgrey/data/clocks.xdc +++ b/hw/top_earlgrey/data/clocks.xdc @@ -10,7 +10,7 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports IO_ create_generated_clock -name clk_main [get_pin clkgen/pll/CLKOUT0] create_generated_clock -name clk_usb_48 [get_pin clkgen/pll/CLKOUT1] create_generated_clock -name clk_aon [get_pin clkgen/pll/CLKOUT4] -set clk_io_pin [get_pin u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_generic.u_impl_generic/u_clk_div_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O] +set clk_io_pin [get_pin u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/u_clk_div_buf/gen_fpga_buf.gen_bufg.bufg_i/O] create_generated_clock -name clk_io -divide_by 1 -add \ -master_clock [get_clocks clk_main] \ -source [get_pins clkgen/pll/CLKOUT0] \ @@ -26,23 +26,23 @@ set clks_aon_unbuf [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT4]] ## destination flops few enough. set u_pll clkgen/pll -set u_div2 top_*/u_clkmgr_aon/u_no_scan_io_div2_div/gen_generic.u_impl_generic -create_generated_clock -name clk_io_div2 -divide_by 2 -source ${clk_io_pin} [get_pin ${u_div2}/gen_div2.u_div2/gen_xilinx.u_impl_xilinx/q_o[0]] +set u_div2 top_*/u_clkmgr_aon/u_no_scan_io_div2_div +create_generated_clock -name clk_io_div2 -divide_by 2 -source ${clk_io_pin} [get_pin ${u_div2}/gen_div2.u_div2/q_o[0]] # TODO: Use pin names explicitly exist from the source instead of the ones # after synthesis. -set u_div4 top_*/u_clkmgr_aon/u_no_scan_io_div4_div/gen_generic.u_impl_generic +set u_div4 top_*/u_clkmgr_aon/u_no_scan_io_div4_div create_generated_clock -name clk_io_div4 -divide_by 4 -source [get_pins ${u_div4}/gen_div.clk_int_reg/C] [get_pins ${u_div4}/gen_div.clk_int_reg/Q] -set ast_src_io u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_generic.u_impl_generic +set ast_src_io u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2 #create_generated_clock -name clk_src_io -divide_by 1 -source [get_pins ${u_pll}/CLKOUT0] \ -# [get_pins ${ast_src_io}/gen_div2.u_div2/gen_xilinx.u_impl_xilinx/q_o[0]] +# [get_pins ${ast_src_io}/gen_div2.u_div2/q_o[0]] set_clock_sense -positive \ [get_pins -filter {DIRECTION == OUT && IS_LEAF} -of_objects \ [get_nets -segments -of_objects \ - [get_pins ${ast_src_io}/u_clk_div_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/I] \ + [get_pins ${ast_src_io}/u_clk_div_buf/gen_fpga_buf.gen_bufg.bufg_i/I] \ ] \ ] @@ -53,7 +53,7 @@ set_clock_sense -positive \ set_clock_sense -positive \ [get_pins -filter {DIRECTION == OUT && IS_LEAF} -of_objects \ [get_nets -segments -of_objects \ - [get_pins top_*/u_clkmgr_aon/u_no_scan_io_div2_div/gen_generic.u_impl_generic/u_clk_div_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/I] \ + [get_pins top_*/u_clkmgr_aon/u_no_scan_io_div2_div/u_clk_div_buf/gen_fpga_buf.gen_bufg.bufg_i/I] \ ] \ ] @@ -67,17 +67,17 @@ set all_muxed_ports "${ioa_muxed_ports} ${iob_muxed_ports} ${ioc_muxed_ports} ${ ## JTAG clocks and I/O delays # Create clocks for the various TAPs. create_clock -add -name jtag_tck -period 100.00 -waveform {0 50} [get_ports IOR3] -create_generated_clock -name lc_jtag_tck -source [get_ports IOR3] -divide_by 1 [get_pins top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_lc/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O] -create_generated_clock -name rv_jtag_tck -source [get_ports IOR3] -divide_by 1 [get_pins top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O] +create_generated_clock -name lc_jtag_tck -source [get_ports IOR3] -divide_by 1 [get_pins top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_lc/prim_clock_buf_tck/gen_fpga_buf.gen_bufg.bufg_i/O] +create_generated_clock -name rv_jtag_tck -source [get_ports IOR3] -divide_by 1 [get_pins top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_fpga_buf.gen_bufg.bufg_i/O] set lc_jtag_tck_inv_pin \ [get_pins -filter {DIRECTION == OUT && IS_LEAF} -of_objects \ [get_nets -segments -of_objects \ - [get_pins top_earlgrey/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_lc/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/I]]] + [get_pins top_earlgrey/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_lc/prim_clock_buf_tck/gen_fpga_buf.gen_bufg.bufg_i/I]]] set rv_jtag_tck_inv_pin \ [get_pins -filter {DIRECTION == OUT && IS_LEAF} -of_objects \ [get_nets -segments -of_objects \ - [get_pins top_earlgrey/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/I]]] + [get_pins top_earlgrey/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_fpga_buf.gen_bufg.bufg_i/I]]] set_clock_sense -negative ${lc_jtag_tck_inv_pin} set_clock_sense -negative ${rv_jtag_tck_inv_pin} @@ -144,7 +144,7 @@ set_output_delay -clock clk_spi -clock_fall -max ${spi_dev_out_setup} ${spi_dev_ set_clock_sense -positive \ [get_pins -filter {DIRECTION == OUT && IS_LEAF} -of_objects \ [get_nets -segments -of_objects \ - [get_pins top_earlgrey/u_spi_device/u_passthrough/u_pt_sck_cg/gen_xilinx.u_impl_xilinx/gen_gate.gen_bufgce.u_bufgce/I0] \ + [get_pins top_earlgrey/u_spi_device/u_passthrough/u_pt_sck_cg/gen_gate.gen_bufgce.u_bufgce/I0] \ ] \ ] \ -clocks clk_spi @@ -152,7 +152,7 @@ set_clock_sense -positive \ set_clock_sense -negative \ [get_pins -filter {DIRECTION == OUT && IS_LEAF} -of_objects \ [get_nets -segments -of_objects \ - [get_pins top_earlgrey/u_spi_device/u_clk_spi_out_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufr.bufr_i/I] \ + [get_pins top_earlgrey/u_spi_device/u_clk_spi_out_buf/gen_fpga_buf.gen_bufr.bufr_i/I] \ ] \ ] \ -clocks clk_spi @@ -160,15 +160,15 @@ set_clock_sense -negative \ set_clock_sense -positive \ [get_pins -filter {DIRECTION == OUT && IS_LEAF} -of_objects \ [get_nets -segments -of_objects \ - [get_pins top_earlgrey/u_spi_device/u_clk_spi_in_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufr.bufr_i/I] \ + [get_pins top_earlgrey/u_spi_device/u_clk_spi_in_buf/gen_fpga_buf.gen_bufr.bufr_i/I] \ ] \ ] \ -clocks clk_spi create_generated_clock -name clk_spi_in -divide_by 1 \ - -source [get_ports SPI_DEV_CLK] [get_pins top_*/u_spi_device/u_clk_spi_in_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufr.bufr_i/O] + -source [get_ports SPI_DEV_CLK] [get_pins top_*/u_spi_device/u_clk_spi_in_buf/gen_fpga_buf.gen_bufr.bufr_i/O] create_generated_clock -name clk_spi_out -divide_by 1 \ - -source [get_ports SPI_DEV_CLK] [get_pins top_*/u_spi_device/u_clk_spi_out_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufr.bufr_i/O] -invert + -source [get_ports SPI_DEV_CLK] [get_pins top_*/u_spi_device/u_clk_spi_out_buf/gen_fpga_buf.gen_bufr.bufr_i/O] -invert ## SPI TPM constraints set spi_tpm_period 125.00 @@ -177,7 +177,7 @@ create_clock -add -name clk_spi_tpm -period ${spi_tpm_period} [get_ports SPI_DEV set_clock_sense -negative \ [get_pins -filter {DIRECTION == OUT && IS_LEAF} -of_objects \ [get_nets -segments -of_objects \ - [get_pins top_earlgrey/u_spi_device/u_clk_spi_out_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufr.bufr_i/I] \ + [get_pins top_earlgrey/u_spi_device/u_clk_spi_out_buf/gen_fpga_buf.gen_bufr.bufr_i/I] \ ] \ ] \ -clocks clk_spi_tpm @@ -185,7 +185,7 @@ set_clock_sense -negative \ set_clock_sense -positive \ [get_pins -filter {DIRECTION == OUT && IS_LEAF} -of_objects \ [get_nets -segments -of_objects \ - [get_pins top_earlgrey/u_spi_device/u_clk_spi_in_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufr.bufr_i/I] \ + [get_pins top_earlgrey/u_spi_device/u_clk_spi_in_buf/gen_fpga_buf.gen_bufr.bufr_i/I] \ ] \ ] \ -clocks clk_spi_tpm @@ -206,9 +206,9 @@ set_output_delay -clock clk_spi_tpm -min ${spi_dev_out_hold} ${spi_dev_data} -a set_output_delay -clock clk_spi_tpm -max ${spi_dev_out_setup} ${spi_dev_data} -add_delay create_generated_clock -name clk_spi_tpm_in -divide_by 1 -add -master_clock clk_spi_tpm \ - -source [get_ports SPI_DEV_CLK] [get_pins top_*/u_spi_device/u_clk_spi_in_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufr.bufr_i/O] + -source [get_ports SPI_DEV_CLK] [get_pins top_*/u_spi_device/u_clk_spi_in_buf/gen_fpga_buf.gen_bufr.bufr_i/O] create_generated_clock -name clk_spi_tpm_out -divide_by 1 -add -master_clock clk_spi_tpm \ - -source [get_ports SPI_DEV_CLK] [get_pins top_*/u_spi_device/u_clk_spi_out_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufr.bufr_i/O] -invert + -source [get_ports SPI_DEV_CLK] [get_pins top_*/u_spi_device/u_clk_spi_out_buf/gen_fpga_buf.gen_bufr.bufr_i/O] -invert ## SPI Passthrough constraints create_generated_clock -name clk_spi_pt -divide_by 1 -source [get_ports SPI_DEV_CLK] [get_ports SPI_HOST_CLK] @@ -234,7 +234,7 @@ set_input_delay -clock clk_spi_pt -clock_fall -max ${spi_host_in_delay_max} \ ## SPI Host constraints # SPI Host clock origin buffer -set spi_host_0_peri [get_pins top_earlgrey/u_clkmgr_aon/u_clk_io_peri_cg/gen_xilinx.u_impl_xilinx/gen_gate.gen_bufgce.u_bufgce/O] +set spi_host_0_peri [get_pins top_earlgrey/u_clkmgr_aon/u_clk_io_peri_cg/gen_gate.gen_bufgce.u_bufgce/O] create_generated_clock -name clk_spi_host0 -divide_by 2 -add \ -source ${spi_host_0_peri} \ @@ -324,7 +324,7 @@ set_multicycle_path -hold -end -from [get_clocks clk_spi_tpm] \ ## The usb calibration handling inside ast is assumed to be async to the outside world ## even though its interface is also a usb clock. -set_false_path -from ${clks_48_unbuf} -to [get_pins u_ast/u_usb_clk/u_ref_pulse_sync/u_sync*/gen_generic.u_impl_generic/u_sync_1/gen_*/q_o_reg[0]/D] +set_false_path -from ${clks_48_unbuf} -to [get_pins u_ast/u_usb_clk/u_ref_pulse_sync/u_sync*/u_sync_1/q_o_reg[0]/D] ## USB input delay to accommodate T_FST (full-speed transition time) and the ## PHY's sampling logic. The PHY expects to only see up to one transient / fake diff --git a/hw/top_earlgrey/data/clocks_cw341.xdc b/hw/top_earlgrey/data/clocks_cw341.xdc index 12a8b3da7ec12..8bea0f73d9884 100644 --- a/hw/top_earlgrey/data/clocks_cw341.xdc +++ b/hw/top_earlgrey/data/clocks_cw341.xdc @@ -17,46 +17,46 @@ create_generated_clock -name clk_aon [get_pin clkgen/pll/CLKOUT4] # invalid combinations. # The 48 MHz ext clocks all have a _lc suffix. create_generated_clock -name clk_io -divide_by 1 \ - -source [get_pins u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_div_bufg.u_bufg_div_stepdown/I] \ - [get_pins u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_div_bufg.u_bufg_div_stepdown/O] + -source [get_pins u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_div_bufg.u_bufg_div_stepdown/I] \ + [get_pins u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_div_bufg.u_bufg_div_stepdown/O] set u_div2 top_*/u_clkmgr_aon/u_no_scan_io_div2_div create_generated_clock -name clk_io_div2 -divide_by 2 \ -add -master_clock clk_io \ - -source [get_pins u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_div_bufg.u_bufg_div_mux/O] \ - [get_pins ${u_div2}/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_div_bufg.u_bufg_div_full/O] + -source [get_pins u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_div_bufg.u_bufg_div_mux/O] \ + [get_pins ${u_div2}/gen_div_bufg.u_bufg_div_full/O] set_clock_sense -stop_propagation -clocks clk_io \ - [get_pins ${u_div2}/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_div_bufg.u_bufg_div_stepdown/I] + [get_pins ${u_div2}/gen_div_bufg.u_bufg_div_stepdown/I] set u_div4 top_*/u_clkmgr_aon/u_no_scan_io_div4_div create_generated_clock -name clk_io_div4 -divide_by 4 \ -add -master_clock clk_io \ - -source [get_pins u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_div_bufg.u_bufg_div_mux/O] \ - [get_pins ${u_div4}/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_div_bufg.u_bufg_div_full/O] + -source [get_pins u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_div_bufg.u_bufg_div_mux/O] \ + [get_pins ${u_div4}/gen_div_bufg.u_bufg_div_full/O] set_clock_sense -stop_propagation -clocks clk_io \ - [get_pins ${u_div4}/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_div_bufg.u_bufg_div_stepdown/I] + [get_pins ${u_div4}/gen_div_bufg.u_bufg_div_stepdown/I] create_generated_clock -name clk_io_ext_lc -divide_by 2 \ - -source [get_pins u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_div_bufg.u_bufg_div_full/I] \ - [get_pins u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_div_bufg.u_bufg_div_full/O] + -source [get_pins u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_div_bufg.u_bufg_div_full/I] \ + [get_pins u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_div_bufg.u_bufg_div_full/O] create_generated_clock -name clk_io_div2_ext_lc -divide_by 1 \ -add -master_clock clk_io_ext_lc \ - -source [get_pins u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_div_bufg.u_bufg_div_mux/O] \ - [get_pins ${u_div2}/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_div_bufg.u_bufg_div_stepdown/O] + -source [get_pins u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_div_bufg.u_bufg_div_mux/O] \ + [get_pins ${u_div2}/gen_div_bufg.u_bufg_div_stepdown/O] set_clock_sense -stop_propagation -clocks clk_io_ext_lc \ - [get_pins ${u_div2}/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_div_bufg.u_bufg_div_full/I] + [get_pins ${u_div2}/gen_div_bufg.u_bufg_div_full/I] create_generated_clock -name clk_io_div4_ext_lc -divide_by 2 \ -add -master_clock clk_io_ext_lc \ - -source [get_pins u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_div_bufg.u_bufg_div_mux/O] \ - [get_pins ${u_div4}/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_div_bufg.u_bufg_div_stepdown/O] + -source [get_pins u_ast/u_ast_clks_byp/u_no_scan_clk_src_io_d1ord2/gen_div_bufg.u_bufg_div_mux/O] \ + [get_pins ${u_div4}/gen_div_bufg.u_bufg_div_stepdown/O] set_clock_sense -stop_propagation -clocks clk_io_ext_lc \ - [get_pin ${u_div4}/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_div_bufg.u_bufg_div_full/I] + [get_pin ${u_div4}/gen_div_bufg.u_bufg_div_full/I] set_clock_groups -physically_exclusive \ -group [get_clocks [list clk_io clk_io_div2 clk_io_div4]] \ @@ -92,9 +92,9 @@ set all_muxed_ports "${ioa_muxed_ports} ${iob_muxed_ports} ${ioc_muxed_ports} ${ # Create clocks for the various TAPs. create_clock -add -name jtag_tck -period 100.00 -waveform {0 50} [get_ports IOR3] create_generated_clock -name lc_jtag_tck -source [get_ports IOR3] -divide_by 1 \ - [get_pins top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_lc/prim_clock_buf_tck/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_fpga_buf.bufg_i/O] + [get_pins top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_lc/prim_clock_buf_tck/gen_fpga_buf.bufg_i/O] create_generated_clock -name rv_jtag_tck -source [get_ports IOR3] -divide_by 1 \ - [get_pins top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_fpga_buf.bufg_i/O] + [get_pins top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_fpga_buf.bufg_i/O] # Assign input and output delays. # Note that incidental combinatorial paths through the pinmux do not get removed @@ -136,11 +136,11 @@ create_clock -add -name clk_spi -period ${spi_dev_period} \ create_generated_clock -name clk_spi_in -divide_by 1 -add \ -source [get_ports SPI_DEV_CLK] \ -master_clock [get_clocks clk_spi] \ - [get_pins top_*/u_spi_device/u_clk_spi_in_buf/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_fpga_buf.bufg_i/O] + [get_pins top_*/u_spi_device/u_clk_spi_in_buf/gen_fpga_buf.bufg_i/O] create_generated_clock -name clk_spi_out -divide_by 1 -invert -add \ -source [get_ports SPI_DEV_CLK] \ -master_clock [get_clocks clk_spi] \ - [get_pins top_*/u_spi_device/u_clk_spi_out_buf/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_fpga_buf.bufg_i/O] + [get_pins top_*/u_spi_device/u_clk_spi_out_buf/gen_fpga_buf.bufg_i/O] set spi_dev_data [get_ports {SPI_DEV_D0 SPI_DEV_D1 SPI_DEV_D2 SPI_DEV_D3}] set_input_delay -clock clk_spi -clock_fall -min ${spi_dev_in_delay_min} ${spi_dev_data} -add_delay @@ -199,10 +199,10 @@ create_clock -add -name clk_spi_tpm -period ${spi_tpm_period} [get_ports SPI_DEV create_generated_clock -name clk_spi_tpm_in -divide_by 1 -add -master_clock clk_spi_tpm \ -source [get_ports SPI_DEV_CLK] \ - [get_pins top_*/u_spi_device/u_clk_spi_in_buf/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_fpga_buf.bufg_i/O] + [get_pins top_*/u_spi_device/u_clk_spi_in_buf/gen_fpga_buf.bufg_i/O] create_generated_clock -name clk_spi_tpm_out -divide_by 1 -add -master_clock clk_spi_tpm \ -source [get_ports SPI_DEV_CLK] \ - [get_pins top_*/u_spi_device/u_clk_spi_out_buf/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_fpga_buf.bufg_i/O] -invert + [get_pins top_*/u_spi_device/u_clk_spi_out_buf/gen_fpga_buf.bufg_i/O] -invert set_input_delay -clock clk_spi_tpm -clock_fall -min ${spi_dev_in_delay_min} \ ${spi_dev_data} -add_delay @@ -258,7 +258,7 @@ set_multicycle_path -hold 1 -end \ ## SPI Host constraints # SPI Host clock origin buffer -set spi_host_0_peri [get_pins top_earlgrey/u_clkmgr_aon/u_clk_io_peri_cg/gen_xilinx_ultrascale.u_impl_xilinx_ultrascale/gen_gate.u_bufgce/O] +set spi_host_0_peri [get_pins top_earlgrey/u_clkmgr_aon/u_clk_io_peri_cg/gen_gate.u_bufgce/O] # Even though it's 2x the max possible frequency, keep the peripheral clock # frequency for the output. This will enable shifting the latch edge for hold @@ -350,4 +350,4 @@ set_multicycle_path -hold -end -from [get_clocks clk_spi_tpm] \ ## The usb calibration handling inside ast is assumed to be async to the outside world ## even though its interface is also a usb clock. -set_false_path -from [get_clocks clk_usb_48] -to [get_pins u_ast/u_usb_clk/u_ref_pulse_sync/u_sync*/gen_generic.u_impl_generic/u_sync_1/gen_*/q_o_reg[0]/D] +set_false_path -from [get_clocks clk_usb_48] -to [get_pins u_ast/u_usb_clk/u_ref_pulse_sync/u_sync*/u_sync_1/q_o_reg[0]/D] diff --git a/hw/top_earlgrey/data/placement.xdc b/hw/top_earlgrey/data/placement.xdc index dc887192bc6ca..0e1c315897be9 100644 --- a/hw/top_earlgrey/data/placement.xdc +++ b/hw/top_earlgrey/data/placement.xdc @@ -12,10 +12,10 @@ # The evaluation has been performed using commit df3c4caee8df70af6b6f3182078ca94ad0022578. # It may become necessary in the future to tweak this if other congestion issues arise. -# Clock net "top_earlgrey/u_clkmgr_aon/u_clk_main_aes_trans/u_cg/gen_xilinx.u_impl_xilinx/clocks_o[clk_main_aes]" driven by instance "top_earlgrey/u_clkmgr_aon/u_clk_main_aes_trans/u_cg/gen_xilinx.u_impl_xilinx/gen_gate.gen_bufhce.u_bufhce" located at site "BUFHCE_X0Y2" +# Clock net "top_earlgrey/u_clkmgr_aon/u_clk_main_aes_trans/u_cg/clocks_o[clk_main_aes]" driven by instance "top_earlgrey/u_clkmgr_aon/u_clk_main_aes_trans/u_cg/gen_gate.gen_bufhce.u_bufhce" located at site "BUFHCE_X0Y2" #startgroup -create_pblock {CLKAG_top_earlgrey/u_clkmgr_aon/u_clk_main_aes_trans/u_cg/gen_xilinx.u_impl_xilinx/clocks_o[clk_main_aes]} -set aes_cells [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="top_earlgrey/u_clkmgr_aon/u_clk_main_aes_trans/u_cg/gen_xilinx.u_impl_xilinx/clocks_o[clk_main_aes]"}]]] -add_cells_to_pblock [get_pblocks {CLKAG_top_earlgrey/u_clkmgr_aon/u_clk_main_aes_trans/u_cg/gen_xilinx.u_impl_xilinx/clocks_o[clk_main_aes]}] ${aes_cells} -resize_pblock [get_pblocks {CLKAG_top_earlgrey/u_clkmgr_aon/u_clk_main_aes_trans/u_cg/gen_xilinx.u_impl_xilinx/clocks_o[clk_main_aes]}] -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y2} +create_pblock {CLKAG_top_earlgrey/u_clkmgr_aon/u_clk_main_aes_trans/u_cg/clocks_o[clk_main_aes]} +set aes_cells [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="top_earlgrey/u_clkmgr_aon/u_clk_main_aes_trans/u_cg/clocks_o[clk_main_aes]"}]]] +add_cells_to_pblock [get_pblocks {CLKAG_top_earlgrey/u_clkmgr_aon/u_clk_main_aes_trans/u_cg/clocks_o[clk_main_aes]}] ${aes_cells} +resize_pblock [get_pblocks {CLKAG_top_earlgrey/u_clkmgr_aon/u_clk_main_aes_trans/u_cg/clocks_o[clk_main_aes]}] -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y2} #endgroup diff --git a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh index ebb9c8fda1c0e..7f9a02af8d59b 100644 --- a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh +++ b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh @@ -39,8 +39,8 @@ // Memory hierarchies. // TODO: Temporarily only reference info type0 of the info partitions in flash. In the future, this // needs to be upgraded to support all info types. -`define MEM_ARRAY_SUB gen_generic.u_impl_generic.mem -`define EFLASH_GENERIC_HIER `EFLASH_HIER.gen_generic.u_impl_generic +`define MEM_ARRAY_SUB mem +`define EFLASH_GENERIC_HIER `EFLASH_HIER `define FLASH_BANK0_HIER `EFLASH_GENERIC_HIER.gen_prim_flash_banks[0].u_prim_flash_bank `define FLASH_BANK1_HIER `EFLASH_GENERIC_HIER.gen_prim_flash_banks[1].u_prim_flash_bank `define FLASH0_DATA_MEM_HIER `FLASH_BANK0_HIER.u_mem.`MEM_ARRAY_SUB @@ -56,7 +56,7 @@ `define RAM_MAIN_MEM_HIER `RAM_MAIN_HIER.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB `define RAM_RET_MEM_HIER `RAM_RET_HIER.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB `define ROM_MEM_HIER `ROM_CTRL_HIER.`ROM_CTRL_INT_PATH -`define OTP_GENERIC_HIER `OTP_CTRL_HIER.u_otp.gen_generic.u_impl_generic +`define OTP_GENERIC_HIER `OTP_CTRL_HIER.u_otp `define OTP_MEM_HIER `OTP_GENERIC_HIER.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB `define OTBN_IMEM_HIER `OTBN_HIER.u_imem.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB `define OTBN_DMEM_HIER `OTBN_HIER.u_dmem.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB diff --git a/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc b/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc index c8625a7d7c072..df6941ad6d823 100644 --- a/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc +++ b/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc @@ -19,37 +19,30 @@ int main(int argc, char **argv) { VerilatorSimCtrlFlags::ResetPolarityNegative); std::string top_scope("TOP.chip_sim_tb.u_dut.top_earlgrey"); - std::string ram1p_adv_scope( - "u_prim_ram_1p_adv.u_mem." - "gen_generic.u_impl_generic"); + std::string ram1p_adv_scope("u_prim_ram_1p_adv.u_mem"); MemArea rom(top_scope + (".u_rom_ctrl.gen_rom_scramble_enabled.u_rom.u_rom." - "u_prim_rom.gen_generic.u_impl_generic"), + "u_prim_rom"), 0x4000 / 4, 4); MemArea ram(top_scope + ".u_ram1p_ram_main." + ram1p_adv_scope, 0x20000 / 4, 4); // Only handle the lower bank of flash for now. - MemArea flash0( - top_scope + - ".u_flash_ctrl.u_eflash.u_flash.gen_generic.u_impl_generic." - "gen_prim_flash_banks[0].u_prim_flash_bank.u_mem." - "gen_generic.u_impl_generic", - 0x80000 / 8, 8); - MemArea flash1( - top_scope + - ".u_flash_ctrl.u_eflash.u_flash.gen_generic.u_impl_generic." - "gen_prim_flash_banks[1].u_prim_flash_bank.u_mem." - "gen_generic.u_impl_generic", - 0x80000 / 8, 8); + MemArea flash0(top_scope + + ".u_flash_ctrl.u_eflash.u_flash." + "gen_prim_flash_banks[0].u_prim_flash_bank.u_mem", + 0x80000 / 8, 8); + MemArea flash1(top_scope + + ".u_flash_ctrl.u_eflash.u_flash." + "gen_prim_flash_banks[1].u_prim_flash_bank.u_mem", + 0x80000 / 8, 8); // Start with the flash region erased. Future loads can overwrite. std::vector all_ones(flash0.GetSizeBytes()); std::fill(all_ones.begin(), all_ones.end(), 0xffu); flash0.Write(/*word_offset=*/0, all_ones); flash1.Write(/*word_offset=*/0, all_ones); - MemArea otp(top_scope + ".u_otp_ctrl.u_otp.gen_generic.u_impl_generic." + - ram1p_adv_scope, - 0x4000 / 4, 4); + MemArea otp(top_scope + ".u_otp_ctrl.u_otp." + ram1p_adv_scope, 0x4000 / 4, + 4); memutil.RegisterMemoryArea("rom", 0x8000, &rom); memutil.RegisterMemoryArea("ram", 0x10000000u, &ram); diff --git a/hw/top_earlgrey/ip/ast/ast.core b/hw/top_earlgrey/ip/ast/ast.core index b26d491101f18..d517b94fe62fe 100644 --- a/hw/top_earlgrey/ip/ast/ast.core +++ b/hw/top_earlgrey/ip/ast/ast.core @@ -17,9 +17,11 @@ filesets: - lowrisc:prim:lfsr - lowrisc:ip_interfaces:pinmux_pkg - lowrisc:prim:assert - - lowrisc:prim:prim_pkg - lowrisc:prim:mubi - lowrisc:prim:multibit_sync + # TODO: prim_pkg is deprecated. + - lowrisc:prim:prim_pkg + - lowrisc:prim:multibit_sync - lowrisc:ip:lc_ctrl_pkg - lowrisc:ip:edn_pkg - lowrisc:ip_interfaces:alert_handler_reg diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/dv/alert_handler_sim.core b/hw/top_earlgrey/ip_autogen/alert_handler/dv/alert_handler_sim.core index 847be468a73cf..52a322f4a6ea2 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/dv/alert_handler_sim.core +++ b/hw/top_earlgrey/ip_autogen/alert_handler/dv/alert_handler_sim.core @@ -12,27 +12,17 @@ filesets: files_dv: depend: - - lowrisc:dv:ralgen - - lowrisc:dv:alert_handler_tb + - lowrisc:opentitan:top_earlgrey_alert_handler_tb:0.1 - lowrisc:dv:alert_handler_cov - lowrisc:opentitan:top_earlgrey_alert_handler_sva:0.1 file_type: systemVerilogSource -generate: - ral: - generator: ralgen - parameters: - name: alert_handler - ip_hjson: ../data/alert_handler.hjson - targets: sim: &sim_target toplevel: tb filesets: - files_rtl - files_dv - generate: - - ral default_tool: vcs lint: diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/dv/env/alert_handler_env.core b/hw/top_earlgrey/ip_autogen/alert_handler/dv/env/alert_handler_env.core index 8103212c1975f..946b95ac99618 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/dv/env/alert_handler_env.core +++ b/hw/top_earlgrey/ip_autogen/alert_handler/dv/env/alert_handler_env.core @@ -2,11 +2,12 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:alert_handler_env:0.1" +name: lowrisc:opentitan:top_earlgrey_alert_handler_env:0.1 description: "ALERT_HANDLER DV UVM environment" filesets: files_dv: depend: + - lowrisc:dv:ralgen - lowrisc:dv:cip_lib - lowrisc:ip:alert_handler_component # import alert_pkg - lowrisc:prim:mubi # import prim_mubi_pkg @@ -36,7 +37,17 @@ filesets: - seq_lib/alert_handler_alert_accum_saturation_vseq.sv: {is_include_file: true} file_type: systemVerilogSource +generate: + ral: + generator: ralgen + parameters: + name: alert_handler + ip_hjson: ../../data/alert_handler.hjson + position: prepend + targets: default: filesets: - files_dv + generate: + - ral diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/dv/tb/alert_handler_tb.core b/hw/top_earlgrey/ip_autogen/alert_handler/dv/tb/alert_handler_tb.core index bbf6842a74308..f7b971a049585 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/dv/tb/alert_handler_tb.core +++ b/hw/top_earlgrey/ip_autogen/alert_handler/dv/tb/alert_handler_tb.core @@ -2,12 +2,12 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:alert_handler_tb:0.1" +name: lowrisc:opentitan:top_earlgrey_alert_handler_tb:0.1 description: "ALERT_HANDLER UVM TB environment" filesets: files_dv: depend: - - lowrisc:dv:alert_handler_test:0.1 + - lowrisc:opentitan:top_earlgrey_alert_handler_test:0.1 files: - tb.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/dv/tests/alert_handler_test.core b/hw/top_earlgrey/ip_autogen/alert_handler/dv/tests/alert_handler_test.core index 767c0654f1c6d..61ed9bb86d3b8 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/dv/tests/alert_handler_test.core +++ b/hw/top_earlgrey/ip_autogen/alert_handler/dv/tests/alert_handler_test.core @@ -2,12 +2,12 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:alert_handler_test:0.1" +name: lowrisc:opentitan:top_earlgrey_alert_handler_test:0.1 description: "ALERT_HANDLER DV UVM test" filesets: files_dv: depend: - - lowrisc:dv:alert_handler_env + - lowrisc:opentitan:top_earlgrey_alert_handler_env files: - alert_handler_test_pkg.sv - alert_handler_base_test.sv: {is_include_file: true} diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/data/flash_ctrl.hjson b/hw/top_earlgrey/ip_autogen/flash_ctrl/data/flash_ctrl.hjson index 4bc9d19dff7c1..e3ab2480ed09e 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/data/flash_ctrl.hjson +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/data/flash_ctrl.hjson @@ -43,7 +43,7 @@ ] bus_interfaces: [ { protocol: "tlul", direction: "device", name: "core" } - { protocol: "tlul", direction: "device", name: "prim" , hier_path: "u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top"} + { protocol: "tlul", direction: "device", name: "prim" , hier_path: "u_eflash.u_flash.u_reg_top"} { protocol: "tlul", direction: "device", name: "mem" } ], available_input_list: [ diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env.core index f339e44e1f82c..642b4318b70ec 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env.core +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env.core @@ -15,6 +15,8 @@ filesets: - lowrisc:dv:flash_phy_prim_agent - lowrisc:ip_interfaces:flash_ctrl_pkg - lowrisc:constants:top_pkg + # TODO: prim_legacy_pkg is deprecated + - lowrisc:prim:prim_legacy_pkg files: - flash_ctrl_eflash_ral_pkg.sv - flash_ctrl_env_pkg.sv diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_seq_cfg.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_seq_cfg.sv index 19cc6622428f9..5df795b031853 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_seq_cfg.sv +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_seq_cfg.sv @@ -272,7 +272,7 @@ class flash_ctrl_seq_cfg extends uvm_object; disable_flash_init = 1'b0; // Off - flash_path_str = "tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic"; + flash_path_str = "tb.dut.u_eflash.u_flash"; // NOTE: Make sure to keep // cfg.flash_ctrl_vif.rst_to_pd_time_ns < reset_width_clks_lo * min clock period in ns. diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/tb/tb.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/tb/tb.sv index b8b741f5c9942..24529b8ec0ad0 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/tb/tb.sv +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/tb/tb.sv @@ -237,25 +237,24 @@ module tb; // For eflash of a specific vendor implementation, set the hierarchy to the memory element // correctly when creating these instances in the extended testbench. `define FLASH_BANK_HIER(i) \ - tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[i]. \ + tb.dut.u_eflash.u_flash.gen_prim_flash_banks[i]. \ u_prim_flash_bank `define FLASH_DATA_MEM_HIER(i) \ - `FLASH_BANK_HIER(i).u_mem.gen_generic.u_impl_generic.mem + `FLASH_BANK_HIER(i).u_mem.mem `define FLASH_DATA_MEM_HIER_STR(i) \ - $sformatf({"tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.", \ - "gen_prim_flash_banks[%0d].u_prim_flash_bank.u_mem.gen_generic.", \ - "u_impl_generic.mem"}, i) + $sformatf({"tb.dut.u_eflash.u_flash.", \ + "gen_prim_flash_banks[%0d].u_prim_flash_bank.u_mem.mem"}, i) `define FLASH_INFO_MEM_HIER(i, j) \ - tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[i]. \ - u_prim_flash_bank.gen_info_types[j].u_info_mem.gen_generic.u_impl_generic.mem + tb.dut.u_eflash.u_flash.gen_prim_flash_banks[i]. \ + u_prim_flash_bank.gen_info_types[j].u_info_mem.mem `define FLASH_INFO_MEM_HIER_STR(i, j) \ - $sformatf({"tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.", \ + $sformatf({"tb.dut.u_eflash.u_flash.", \ "gen_prim_flash_banks[%0d].u_prim_flash_bank.gen_info_types[%0d].", \ - "u_info_mem.gen_generic.u_impl_generic.mem"}, i, j) + "u_info_mem.mem"}, i, j) if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_generic for (genvar i = 0; i < flash_ctrl_pkg::NumBanks; i++) begin : gen_each_bank diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core index 03e07aa98faac..6e585c4dcccc8 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core @@ -21,6 +21,8 @@ filesets: - lowrisc:prim:lfsr - lowrisc:prim:secded - lowrisc:prim:sparse_fsm + # TODO: prim_legacy_pkg is deprecated + - lowrisc:prim:prim_legacy_pkg - lowrisc:ip:otp_ctrl_pkg - lowrisc:opentitan:top_earlgrey_flash_ctrl_pkg - lowrisc:opentitan:top_earlgrey_flash_ctrl_reg diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv index a891d8f4eeff1..7b871508ff0e6 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv @@ -1528,7 +1528,7 @@ module flash_ctrl `endif if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_reg_we_assert_generic `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(PrimRegWeOnehotCheck_A, - u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top, alert_tx_o[3]) + u_eflash.u_flash.u_reg_top, alert_tx_o[3]) end endmodule diff --git a/hw/top_earlgrey/rdc/chip_earlgrey_asic_scenario.tcl b/hw/top_earlgrey/rdc/chip_earlgrey_asic_scenario.tcl index 9ef395f1918b6..1ceed38c2d2e3 100644 --- a/hw/top_earlgrey/rdc/chip_earlgrey_asic_scenario.tcl +++ b/hw/top_earlgrey/rdc/chip_earlgrey_asic_scenario.tcl @@ -111,7 +111,7 @@ set_reset_scenario { \ # PWRMGR Reset Cause # RSTMGR SW Resets -#set_reset_scenario { {{top_earlgrey.u_rstmgr_aon.u_ndm_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]} {reset { @t0 1 } { #10 0}} }} -name Scenario8 -comment "functional reset" +#set_reset_scenario { {{top_earlgrey.u_rstmgr_aon.u_ndm_sync.u_sync_2.q_o[0]} {reset { @t0 1 } { #10 0}} }} -name Scenario8 -comment "functional reset" set_reset_scenario { \ {{top_earlgrey.u_rstmgr_aon.u_reg.u_sw_rst_ctrl_n_0.q[0]} {reset { @t0 1 } { #2 0 } { #10 1}} } \ {{top_earlgrey.u_rstmgr_aon.u_reg.u_sw_rst_ctrl_n_1.q[0]} {reset { @t0 1 } { #2 0 } { #10 1}} } \ diff --git a/hw/top_earlgrey/rdc/rdc_waivers.tcl b/hw/top_earlgrey/rdc/rdc_waivers.tcl index e03d7b0d03a88..939993ebdac21 100644 --- a/hw/top_earlgrey/rdc/rdc_waivers.tcl +++ b/hw/top_earlgrey/rdc/rdc_waivers.tcl @@ -62,8 +62,8 @@ set_rule_status -rule {E_RST_METASTABILITY} -status {Waived} \ # Ibex Clock Gating set_rule_status -rule E_RST_METASTABILITY -status Waived \ -expression { \ - (ResetFlop=~"*.u_rv_core_ibex.u_core.g_clock_en_secure.u_prim_core_busy_flop.gen_generic.u_impl_generic.q_o[0]") && \ - (MetaStableFlop=~"*.u_rv_core_ibex.u_core.core_clock_gate_i.gen_generic.u_impl_generic.en_latch")} \ + (ResetFlop=~"*.u_rv_core_ibex.u_core.g_clock_en_secure.u_prim_core_busy_flop.q_o[0]") && \ + (MetaStableFlop=~"*.u_rv_core_ibex.u_core.core_clock_gate_i.en_latch")} \ -comment {If clockgating enble is reset, it affects the gating cell when \ CLK is 0 value.} diff --git a/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core b/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core index 22b0e1d6d588a..c8b442bfb808f 100644 --- a/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core +++ b/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core @@ -13,6 +13,8 @@ filesets: - lowrisc:systems:ast - lowrisc:systems:topgen - lowrisc:systems:padring + - lowrisc:prim:prim_legacy_pkg + - lowrisc:prim_xilinx:all file_type: systemVerilogSource files_constraints: diff --git a/hw/top_englishbreakfast/chip_englishbreakfast_verilator.cc b/hw/top_englishbreakfast/chip_englishbreakfast_verilator.cc index 9f9c8b43e6d39..6d62587733318 100644 --- a/hw/top_englishbreakfast/chip_englishbreakfast_verilator.cc +++ b/hw/top_englishbreakfast/chip_englishbreakfast_verilator.cc @@ -18,22 +18,18 @@ int main(int argc, char **argv) { std::string top_scope( "TOP.chip_englishbreakfast_verilator." "top_englishbreakfast"); - std::string ram1p_adv_scope( - "u_prim_ram_1p_adv.u_mem." - "gen_generic.u_impl_generic"); + std::string ram1p_adv_scope("u_prim_ram_1p_adv.u_mem"); MemArea rom(top_scope + ".u_rom_ctrl.gen_rom_scramble_disabled.u_rom." - "u_prim_rom.gen_generic.u_impl_generic", + "u_prim_rom", 0x4000 / 4, 4); MemArea ram(top_scope + ".u_ram1p_ram_main." + ram1p_adv_scope, 0x20000 / 4, 4); - MemArea flash0( - top_scope + - ".u_flash_ctrl.u_eflash.u_flash.gen_generic.u_impl_generic." - "gen_prim_flash_banks[0].u_prim_flash_bank.u_mem." - "gen_generic.u_impl_generic", - 0x100000 / 8, 8); + MemArea flash0(top_scope + + ".u_flash_ctrl.u_eflash.u_flash." + "gen_prim_flash_banks[0].u_prim_flash_bank.u_mem", + 0x100000 / 8, 8); memutil.RegisterMemoryArea("rom", 0x8000, &rom); memutil.RegisterMemoryArea("ram", 0x10000000u, &ram); diff --git a/hw/top_englishbreakfast/chip_englishbreakfast_verilator.core b/hw/top_englishbreakfast/chip_englishbreakfast_verilator.core index a3002ac3a9e03..b038d733e6461 100644 --- a/hw/top_englishbreakfast/chip_englishbreakfast_verilator.core +++ b/hw/top_englishbreakfast/chip_englishbreakfast_verilator.core @@ -28,6 +28,8 @@ filesets: - lowrisc:dv:sw_test_status - lowrisc:dv:dv_test_status - lowrisc:prim:clock_div + - lowrisc:prim:prim_legacy_pkg + - lowrisc:prim_generic:all files: - rtl/chip_englishbreakfast_verilator.sv: { file_type: systemVerilogSource } diff --git a/hw/top_englishbreakfast/data/clocks.xdc b/hw/top_englishbreakfast/data/clocks.xdc index ec9b609705939..1aa27d0f4db9e 100644 --- a/hw/top_englishbreakfast/data/clocks.xdc +++ b/hw/top_englishbreakfast/data/clocks.xdc @@ -15,10 +15,10 @@ set clks_aon_unbuf [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT4]] ## destination flops few enough. set u_pll clkgen/pll -set u_div2 top_*/u_clkmgr_aon/u_no_scan_io_div2_div/gen_generic.u_impl_generic -create_generated_clock -name clk_io_div2 -source [get_pins ${u_pll}/CLKOUT0] -divide_by 2 [get_pin ${u_div2}/gen_div2.u_div2/gen_xilinx.u_impl_xilinx/q_o[0]] +set u_div2 top_*/u_clkmgr_aon/u_no_scan_io_div2_div +create_generated_clock -name clk_io_div2 -source [get_pins ${u_pll}/CLKOUT0] -divide_by 2 [get_pin ${u_div2}/gen_div2.u_div2/q_o[0]] -set u_div4 top_*/u_clkmgr_aon/u_no_scan_io_div4_div/gen_generic.u_impl_generic +set u_div4 top_*/u_clkmgr_aon/u_no_scan_io_div4_div create_generated_clock -name clk_io_div4 -divide_by 4 -source [get_pins ${u_div4}/gen_div.clk_int_reg/C] [get_pins ${u_div4}/gen_div.clk_int_reg/Q] @@ -29,7 +29,7 @@ create_generated_clock -name clk_io_div4 -divide_by 4 -source [get_pins ${u_div4 set_clock_sense -positive \ [get_pins -filter {DIRECTION == OUT && IS_LEAF} -of_objects \ [get_nets -segments -of_objects \ - [get_pins top_*/u_clkmgr_aon/u_no_scan_io_div2_div/gen_generic.u_impl_generic/u_clk_div_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/I] \ + [get_pins top_*/u_clkmgr_aon/u_no_scan_io_div2_div/u_clk_div_buf/gen_fpga_buf.gen_bufg.bufg_i/I] \ ] \ ] @@ -62,22 +62,22 @@ set_output_delay -clock clk_spi 5 [get_ports SPI_DEV_D1] -add_delay ## create_generated_clock appraoch ## create_generated_clock is preferred since the buffer cell used here is hand-instantiated, while the set_clock_sense point is simply a LUT -create_generated_clock -name clk_spi_in -divide_by 1 -source [get_ports SPI_DEV_CLK] [get_pins top_*/u_spi_device/u_clk_spi_in_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufr.bufr_i/O] -create_generated_clock -name clk_spi_out -divide_by 1 -source [get_ports SPI_DEV_CLK] [get_pins top_*/u_spi_device/u_clk_spi_out_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufr.bufr_i/O] -invert +create_generated_clock -name clk_spi_in -divide_by 1 -source [get_ports SPI_DEV_CLK] [get_pins top_*/u_spi_device/u_clk_spi_in_buf/gen_fpga_buf.gen_bufr.bufr_i/O] +create_generated_clock -name clk_spi_out -divide_by 1 -source [get_ports SPI_DEV_CLK] [get_pins top_*/u_spi_device/u_clk_spi_out_buf/gen_fpga_buf.gen_bufr.bufr_i/O] -invert ## JTAG clocks and I/O delays # Create clocks for the various TAPs. -create_generated_clock -name lc_jtag_tck -source [get_ports SPI_DEV_CLK] -divide_by 1 [get_pin top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_lc/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O] -create_generated_clock -name rv_jtag_tck -source [get_ports SPI_DEV_CLK] -divide_by 1 [get_pin top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O] +create_generated_clock -name lc_jtag_tck -source [get_ports SPI_DEV_CLK] -divide_by 1 [get_pin top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_lc/prim_clock_buf_tck/gen_fpga_buf.gen_bufg.bufg_i/O] +create_generated_clock -name rv_jtag_tck -source [get_ports SPI_DEV_CLK] -divide_by 1 [get_pin top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_fpga_buf.gen_bufg.bufg_i/O] set lc_jtag_tck_inv_pin \ [get_pins -filter {DIRECTION == OUT && IS_LEAF} -of_objects \ [get_nets -segments -of_objects \ - [get_pins top_earlgrey/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/I]]] + [get_pins top_englishbreakfast/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_fpga_buf.gen_bufg.bufg_i/I]]] set rv_jtag_tck_inv_pin \ [get_pins -filter {DIRECTION == OUT && IS_LEAF} -of_objects \ [get_nets -segments -of_objects \ - [get_pins top_earlgrey/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/I]]] + [get_pins top_englishbreakfast/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_fpga_buf.gen_bufg.bufg_i/I]]] set_clock_sense -negative ${lc_jtag_tck_inv_pin} set_clock_sense -negative ${rv_jtag_tck_inv_pin} @@ -87,4 +87,4 @@ set_clock_groups -group ${clks_10_unbuf} -group ${clks_48_unbuf} -group ${clks_a ## The usb calibration handling inside ast is assumed to be async to the outside world ## even though its interface is also a usb clock. -set_false_path -from ${clks_48_unbuf} -to [get_pins u_ast/u_usb_clk/u_ref_pulse_sync/u_sync*/gen_generic.u_impl_generic/u_sync_1/gen_*/q_o_reg[0]/D] +set_false_path -from ${clks_48_unbuf} -to [get_pins u_ast/u_usb_clk/u_ref_pulse_sync/u_sync*/u_sync_1/q_o_reg[0]/D] From 5be44013a645ef0f6a570645dc5f4320ecc02666 Mon Sep 17 00:00:00 2001 From: Hugo McNally Date: Mon, 25 Nov 2024 10:00:58 +0000 Subject: [PATCH 04/24] [python] Updated fusesoc to upstream version 2.4 Signed-off-by: Hugo McNally --- pyproject.toml | 6 +----- python-requirements.txt | 16 ++++++++++++---- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/pyproject.toml b/pyproject.toml index a2bb96327be5f..f96726f88d795 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -75,11 +75,7 @@ dependencies = [ # Dependency of third_party/tock "tockloader==1.13", - # Development version with OT-specific changes - "fusesoc@https://github.com/lowRISC/fusesoc/archive/refs/tags/ot-0.5.dev0.zip", - - # Development version with OT-specific changes - "edalize@https://github.com/lowRISC/edalize/archive/refs/tags/v0.4.0.zip", + "fusesoc==2.4", # Development version of minimal ChipWhisperer toolchain with latest features # and bug fixes. We fix the version for improved stability and manually update diff --git a/python-requirements.txt b/python-requirements.txt index 090f0b4cc0488..86b73ecadd83b 100644 --- a/python-requirements.txt +++ b/python-requirements.txt @@ -183,16 +183,21 @@ cython==3.0.1 \ distro==1.8.0 \ --hash=sha256:02e111d1dc6a50abb8eed6bf31c3e48ed8b0830d1ea2a1b78c61765c2513fdd8 \ --hash=sha256:99522ca3e365cac527b44bde033f64c6945d90eb9f769703caaec52b09bbd3ff -edalize @ https://github.com/lowRISC/edalize/archive/refs/tags/v0.4.0.zip \ - --hash=sha256:da816ef1040d8063d4aa7377ef1fea33f0bffeca1f79a68b7a8930ef9d90c7c8 +edalize==0.6.0 \ + --hash=sha256:9fe1ddbf0d860d78e437dbd3bc951bda616e4f79803a189a4c64f7a828ca9162 \ + --hash=sha256:dab4b602faee41028924a73a97917f4911c676a5cfadcee5548ac38168f70034 enlighten==1.10.2 \ --hash=sha256:7a5b83cd0f4d095e59d80c648ebb5f7ffca0cd8bcf7ae6639828ee1ad000632a \ --hash=sha256:b237fe562b320bf9f1d4bb76d0c98e0daf914372a76ab87c35cd02f57aa9d8c1 +fastjsonschema==2.20.0 \ + --hash=sha256:3d48fc5300ee96f5d116f10fe6f28d938e6008f59a6a025c2649475b87f76a23 \ + --hash=sha256:5875f0b0fa7a0043a91e93a9b8f793bcbbba9691e7fd83dca95c28ba26d21f0a flake8==7.1.1 \ --hash=sha256:049d058491e228e03e67b390f311bbf88fce2dbaa8fa673e7aea87b7198b8d38 \ --hash=sha256:597477df7860daa5aa0fdd84bf5208a043ab96b8e96ab708770ae0364dd03213 -fusesoc @ https://github.com/lowRISC/fusesoc/archive/refs/tags/ot-0.5.dev0.zip \ - --hash=sha256:6d1d9b202748d160bc6da70ea8cf7a700ca80e1e7e4a78cbc1ec039bde595c65 +fusesoc==2.4 \ + --hash=sha256:6fecf1ef2e39d6ad38ddb3dc294bcfde302686e627c14359c52444129b246bb1 \ + --hash=sha256:a9392dc0be5d1dcc54ed7b20f247bb8d5a9665c90775952cd5129e398487fa96 gitdb==4.0.10 \ --hash=sha256:6eb990b69df4e15bad899ea868dc46572c3f75339735663b81de79b06f17eb9a \ --hash=sha256:c286cf298426064079ed96a9e4a9d39e7f3e9bf15ba60701e95f5492f28415c7 @@ -220,6 +225,9 @@ jinja2==3.1.2 \ jsonschema==4.17.3 \ --hash=sha256:0f864437ab8b6076ba6707453ef8f98a6a0d512a80e93f8abdb676f737ecb60d \ --hash=sha256:a870ad254da1a8ca84b6a2905cac29d265f805acc57af304784962a2aa6508f6 +jsonschema2md==0.9.0 \ + --hash=sha256:3ef34181679c48bbd1ac228ad1d6441051ceef58ba90cba6b931d0368e00ec77 \ + --hash=sha256:b6b7ae067c355c887949646296fb04375f6e995d862cbe7ae81a34f085a63a67 libclang==16.0.0 \ --hash=sha256:2adce42ae652f312245b8f4eda6f30b4076fb61f7619f2dfd0a0c31dee4c32b9 \ --hash=sha256:65258a6bb3e7dc31dc9b26f8d42f53c9d3b959643ade291fcd1aef4855303ca6 \ From 408d0531deec31dfb7960e9677ac8a14e18cb00e Mon Sep 17 00:00:00 2001 From: Alexander Williams Date: Fri, 14 Jun 2024 11:33:19 -0700 Subject: [PATCH 05/24] [dv] Retarget forced signal for prim_sparse_fsm_flop_if Because the prim hierarchy has changed, reusing the path would target the flop directly for forcing. This meant that the forcing would delay u_state_flop from snapping back to the FsmError state that should've been held by the flop. Instead, the original path caused the flop in the new hierarchy to be targeted *directly*, delaying update until the next posedge, instead of the negedge when forcing is released. Retarget forcing to prim_sparse_fsm_flop's state_o output. Signed-off-by: Alexander Williams --- hw/dv/sv/sec_cm/prim_sparse_fsm_flop_if.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/dv/sv/sec_cm/prim_sparse_fsm_flop_if.sv b/hw/dv/sv/sec_cm/prim_sparse_fsm_flop_if.sv index 6ec8e76ac746d..d432546c91645 100644 --- a/hw/dv/sv/sec_cm/prim_sparse_fsm_flop_if.sv +++ b/hw/dv/sv/sec_cm/prim_sparse_fsm_flop_if.sv @@ -23,7 +23,7 @@ interface prim_sparse_fsm_flop_if #( string msg_id = $sformatf("%m"); string path = dv_utils_pkg::get_parent_hier($sformatf("%m")); - string signal_forced = $sformatf("%s.u_state_flop.q_o", path); + string signal_forced = $sformatf("%s.state_o", path); // This signal only has to be forced if the associated parameter // CustomForceName in prim_sparse_fsm_flop is set to a non-empty string. From d7d97fa7a9ac14d30a963d6ad6ed9b2e03733935 Mon Sep 17 00:00:00 2001 From: Hugo McNally Date: Mon, 25 Nov 2024 12:53:33 +0000 Subject: [PATCH 06/24] [fpga,sim_verilator] Adjust paths for new fusesoc Adjust the paths to fusesoc FPGA outputs to accommodate the extra layer of hierarchy for --build-root. We might want to consider using --work-root to shorten these long paths in the future. Co-authored-by: Alexander Williams Signed-off-by: Hugo McNally --- .github/workflows/bitstream.yml | 14 ++++++++++++-- ci/scripts/build-chip-verilator.sh | 4 +++- hw/BUILD | 2 +- hw/bitstream/vivado/BUILD | 20 +++++++++++--------- 4 files changed, 27 insertions(+), 13 deletions(-) diff --git a/.github/workflows/bitstream.yml b/.github/workflows/bitstream.yml index 01dea5947e039..7539decd29aa4 100644 --- a/.github/workflows/bitstream.yml +++ b/.github/workflows/bitstream.yml @@ -82,11 +82,21 @@ jobs: if: steps.strategy.outputs.bitstreamStrategy != 'cached' run: | . util/build_consts.sh + + vlnv_path=lowrisc_systems_chip_${{ inputs.top_name }}_${{ inputs.design_suffix }}_0.1 + design_name=chip_${{ inputs.top_name }}_${{ inputs.design_suffix }} + echo "Synthesis log" - cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/build.fpga_${{ inputs.design_suffix }}/synth-vivado/lowrisc_systems_chip_${{ inputs.top_name }}_${{ inputs.design_suffix }}_0.1.runs/synth_1/runme.log || true + cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/${design_name}/build.fpga_${{ inputs.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/synth_1/runme.log || true echo "Implementation log" - cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/build.fpga_${{ inputs.design_suffix }}/synth-vivado/lowrisc_systems_chip_${{ inputs.top_name }}_${{ inputs.design_suffix }}_0.1.runs/impl_1/runme.log || true + cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/${design_name}/build.fpga_${{ inputs.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/impl_1/runme.log || true + + echo "Utilization report" + cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/${design_name}/build.fpga_${{ inputs.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/impl_1/${design_name}_utilization_placed.rpt || true + + echo "Timing summary report" + cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/${design_name}/build.fpga_${{ inputs.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/impl_1/${design_name}_timing_summary_routed.rpt || true - name: Upload step outputs uses: actions/upload-artifact@v4 diff --git a/ci/scripts/build-chip-verilator.sh b/ci/scripts/build-chip-verilator.sh index 80e17abdcde6b..bdb7e288d3842 100755 --- a/ci/scripts/build-chip-verilator.sh +++ b/ci/scripts/build-chip-verilator.sh @@ -20,6 +20,7 @@ case "$tl" in earlgrey) fileset=fileset_top fusesoc_core=lowrisc:dv:chip_verilator_sim + vlnv_path=lowrisc_dv_chip_verilator_sim_0.1 vname=Vchip_sim_tb verilator_options="--threads 4" make_options="-j 4" @@ -27,6 +28,7 @@ case "$tl" in englishbreakfast) fileset=fileset_topgen fusesoc_core=lowrisc:systems:chip_englishbreakfast_verilator + vlnv_path=lowrisc_systems_chip_englishbreakfast_verilator_0.1 vname=Vchip_englishbreakfast_verilator # Englishbreakfast on CI runs on a 2-core CPU verilator_options="--threads 2" @@ -55,5 +57,5 @@ fusesoc --cores-root=. \ --verilator_options="${verilator_options}" \ --make_options="${make_options}" -cp "$OBJ_DIR/hw/sim-verilator/${vname}" \ +cp "$OBJ_DIR/hw/${vlnv_path}/sim-verilator/${vname}" \ "$BIN_DIR/hw/top_${tl}/Vchip_${tl}_verilator" diff --git a/hw/BUILD b/hw/BUILD index c6b06081767c7..978633548de86 100644 --- a/hw/BUILD +++ b/hw/BUILD @@ -43,7 +43,7 @@ fusesoc_build( data = ["//hw/ip/otbn:all_files"], make_options = ":make_options", output_groups = { - "binary": ["sim-verilator/Vchip_sim_tb"], + "binary": ["lowrisc_dv_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb"], }, systems = ["lowrisc:dv:chip_verilator_sim"], tags = [ diff --git a/hw/bitstream/vivado/BUILD b/hw/bitstream/vivado/BUILD index 6bc8ba0558cd7..9ae52657fea41 100644 --- a/hw/bitstream/vivado/BUILD +++ b/hw/bitstream/vivado/BUILD @@ -32,6 +32,8 @@ _CW340_TESTROM_PATH = _CW310_TESTROM_PATH _OTP_RMA_PATH = "{}/$(location {})".format(_PREFIX, _OTP_RMA) +_FPGA_PATH_TMPL = "lowrisc_systems_{}_0.1/synth-vivado/{}" + # Note: all of the targets are tagged with "manual" to prevent them from being # matched by bazel wildcards like "//...". In order to build the bitstream, # you need to ask for it directly or by dependency via another rule, such as @@ -51,9 +53,9 @@ fusesoc_build( "--OtpCtrlMemInitFile=" + _OTP_RMA_PATH, ], output_groups = { - "bitstream": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_0.1.bit"], - "mmi": ["synth-vivado/memories.mmi"], - "logs": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_0.1.runs/"], + "bitstream": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "lowrisc_systems_chip_earlgrey_cw310_0.1.bit")], + "mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "memories.mmi")], + "logs": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "lowrisc_systems_chip_earlgrey_cw310_0.1.runs/")], }, systems = ["lowrisc:systems:chip_earlgrey_cw310"], tags = ["manual"], @@ -92,9 +94,9 @@ fusesoc_build( "--OtpCtrlMemInitFile=" + _OTP_RMA_PATH, ], output_groups = { - "bitstream": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.bit"], - "mmi": ["synth-vivado/memories.mmi"], - "logs": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.runs/"], + "bitstream": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.bit")], + "mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "memories.mmi")], + "logs": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.runs/")], }, systems = ["lowrisc:systems:chip_earlgrey_cw310_hyperdebug"], tags = ["manual"], @@ -133,9 +135,9 @@ fusesoc_build( "--OtpCtrlMemInitFile=" + _OTP_RMA_PATH, ], output_groups = { - "bitstream": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw340_0.1.bit"], - "mmi": ["synth-vivado/memories.mmi"], - "logs": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw340_0.1.runs/"], + "bitstream": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "lowrisc_systems_chip_earlgrey_cw340_0.1.bit")], + "mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "memories.mmi")], + "logs": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "lowrisc_systems_chip_earlgrey_cw340_0.1.runs/")], }, systems = ["lowrisc:systems:chip_earlgrey_cw340"], tags = ["manual"], From 05b2dbac593a3c91aa33841f93c9722ad49cf204 Mon Sep 17 00:00:00 2001 From: Alexander Williams Date: Fri, 14 Jun 2024 21:34:12 -0700 Subject: [PATCH 07/24] [prim] Rename all files to match virtual cores We expect file names to match module names. Now that the IPs are virtual cores, rename the files to match the module names that are the new "ABI" (so to speak). Adjust prim_generic, prim_xilinx, and prim_xilinx_ultrascale libraries. Co-authored-by: Hugo McNally Signed-off-by: Alexander Williams --- doc/contributing/fpga/ref_manual_fpga.md | 2 +- hw/ip/otp_ctrl/README.md | 2 +- .../lint/prim_generic_clock_buf.vlt | 2 +- .../lint/prim_generic_clock_buf.waiver | 4 +- .../lint/prim_generic_clock_div.waiver | 12 ++-- .../lint/prim_generic_clock_gating.vlt | 4 +- .../lint/prim_generic_clock_gating.waiver | 8 +-- .../lint/prim_generic_clock_mux2.vlt | 2 +- .../lint/prim_generic_clock_mux2.waiver | 2 +- .../lint/prim_generic_flash.waiver | 4 +- hw/ip/prim_generic/lint/prim_generic_otp.vlt | 4 +- .../prim_generic/lint/prim_generic_otp.waiver | 8 +-- .../lint/prim_generic_pad_wrapper.waiver | 20 +++---- .../lint/prim_generic_ram_1p.waiver | 8 +-- .../lint/prim_generic_ram_1r1w.waiver | 8 +-- .../prim_generic/lint/prim_generic_ram_2p.vlt | 2 +- .../lint/prim_generic_ram_2p.waiver | 10 ++-- .../prim_generic/lint/prim_generic_rom.waiver | 4 +- .../lint/prim_generic_usb_diff_rx.waiver | 8 +-- hw/ip/prim_generic/prim_generic_and2.core | 2 +- hw/ip/prim_generic/prim_generic_buf.core | 2 +- .../prim_generic/prim_generic_clock_buf.core | 2 +- .../prim_generic/prim_generic_clock_div.core | 2 +- .../prim_generic_clock_gating.core | 2 +- .../prim_generic/prim_generic_clock_inv.core | 2 +- .../prim_generic/prim_generic_clock_mux2.core | 2 +- hw/ip/prim_generic/prim_generic_flash.core | 2 +- hw/ip/prim_generic/prim_generic_flop.core | 2 +- .../prim_generic/prim_generic_flop_2sync.core | 2 +- hw/ip/prim_generic/prim_generic_flop_en.core | 2 +- hw/ip/prim_generic/prim_generic_otp.core | 2 +- hw/ip/prim_generic/prim_generic_pad_attr.core | 2 +- .../prim_generic_pad_wrapper.core | 2 +- hw/ip/prim_generic/prim_generic_ram_1p.core | 2 +- hw/ip/prim_generic/prim_generic_ram_1r1w.core | 2 +- hw/ip/prim_generic/prim_generic_ram_2p.core | 2 +- hw/ip/prim_generic/prim_generic_rom.core | 2 +- .../prim_generic_usb_diff_rx.core | 2 +- hw/ip/prim_generic/prim_generic_xnor2.core | 2 +- hw/ip/prim_generic/prim_generic_xor2.core | 2 +- .../{prim_generic_and2.sv => prim_and2.sv} | 0 .../rtl/{prim_generic_buf.sv => prim_buf.sv} | 0 ...generic_clock_buf.sv => prim_clock_buf.sv} | 0 ...generic_clock_div.sv => prim_clock_div.sv} | 0 ...c_clock_gating.sv => prim_clock_gating.sv} | 0 ...generic_clock_inv.sv => prim_clock_inv.sv} | 0 ...neric_clock_mux2.sv => prim_clock_mux2.sv} | 0 .../{prim_generic_flash.sv => prim_flash.sv} | 0 .../{prim_generic_flop.sv => prim_flop.sv} | 0 ...neric_flop_2sync.sv => prim_flop_2sync.sv} | 0 ...rim_generic_flop_en.sv => prim_flop_en.sv} | 0 .../rtl/{prim_generic_otp.sv => prim_otp.sv} | 0 ...m_generic_pad_attr.sv => prim_pad_attr.sv} | 0 ...ric_pad_wrapper.sv => prim_pad_wrapper.sv} | 0 ...{prim_generic_ram_1p.sv => prim_ram_1p.sv} | 0 ...m_generic_ram_1r1w.sv => prim_ram_1r1w.sv} | 0 ...{prim_generic_ram_2p.sv => prim_ram_2p.sv} | 0 .../rtl/{prim_generic_rom.sv => prim_rom.sv} | 0 ...ric_usb_diff_rx.sv => prim_usb_diff_rx.sv} | 0 .../{prim_generic_xnor2.sv => prim_xnor2.sv} | 0 .../{prim_generic_xor2.sv => prim_xor2.sv} | 0 .../lint/prim_xilinx_pad_wrapper.waiver | 4 +- hw/ip/prim_xilinx/prim_xilinx.core | 4 +- hw/ip/prim_xilinx/prim_xilinx_and2.core | 2 +- hw/ip/prim_xilinx/prim_xilinx_buf.core | 2 +- hw/ip/prim_xilinx/prim_xilinx_clock_buf.core | 2 +- .../prim_xilinx/prim_xilinx_clock_gating.core | 2 +- hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core | 2 +- hw/ip/prim_xilinx/prim_xilinx_flop.core | 2 +- hw/ip/prim_xilinx/prim_xilinx_flop_en.core | 2 +- hw/ip/prim_xilinx/prim_xilinx_pad_attr.core | 2 +- .../prim_xilinx/prim_xilinx_pad_wrapper.core | 2 +- hw/ip/prim_xilinx/prim_xilinx_ram_1p.core | 6 +- hw/ip/prim_xilinx/prim_xilinx_xnor2.core | 2 +- hw/ip/prim_xilinx/prim_xilinx_xor2.core | 2 +- .../rtl/{prim_xilinx_and2.sv => prim_and2.sv} | 0 .../rtl/{prim_xilinx_buf.sv => prim_buf.sv} | 0 ..._xilinx_clock_buf.sv => prim_clock_buf.sv} | 0 ...x_clock_gating.sv => prim_clock_gating.sv} | 0 ...ilinx_clock_mux2.sv => prim_clock_mux2.sv} | 0 .../rtl/{prim_xilinx_flop.sv => prim_flop.sv} | 0 ...prim_xilinx_flop_en.sv => prim_flop_en.sv} | 0 ...im_xilinx_pad_attr.sv => prim_pad_attr.sv} | 0 ...inx_pad_wrapper.sv => prim_pad_wrapper.sv} | 0 .../{prim_xilinx_ram_1p.sv => prim_ram_1p.sv} | 52 ++++++++++++---- .../{prim_xilinx_xnor2.sv => prim_xnor2.sv} | 2 +- .../rtl/{prim_xilinx_xor2.sv => prim_xor2.sv} | 0 .../prim_xilinx_ultrascale_clock_mux2.vlt | 4 -- .../prim_xilinx_ultrascale_clock_mux2.waiver | 4 -- .../prim_xilinx_ultrascale_pad_wrapper.waiver | 4 +- .../prim_xilinx_ultrascale.core | 18 +++--- .../prim_xilinx_ultrascale_and2.core | 40 ------------- .../prim_xilinx_ultrascale_buf.core | 40 ------------- .../prim_xilinx_ultrascale_clock_buf.core | 2 +- .../prim_xilinx_ultrascale_clock_div.core | 2 +- .../prim_xilinx_ultrascale_clock_gating.core | 2 +- .../prim_xilinx_ultrascale_clock_inv.core | 2 +- .../prim_xilinx_ultrascale_clock_mux2.core | 44 -------------- .../prim_xilinx_ultrascale_flop.core | 40 ------------- .../prim_xilinx_ultrascale_flop_en.core | 40 ------------- .../prim_xilinx_ultrascale_pad_attr.core | 41 ------------- .../prim_xilinx_ultrascale_pad_wrapper.core | 2 +- .../prim_xilinx_ultrascale_ram_1p.core | 19 ------ .../prim_xilinx_ultrascale_xnor2.core | 37 ------------ .../prim_xilinx_ultrascale_xor2.core | 2 +- ...rascale_clock_buf.sv => prim_clock_buf.sv} | 0 ...rascale_clock_div.sv => prim_clock_div.sv} | 0 ...e_clock_gating.sv => prim_clock_gating.sv} | 0 ...rascale_clock_inv.sv => prim_clock_inv.sv} | 0 ...ale_pad_wrapper.sv => prim_pad_wrapper.sv} | 0 .../rtl/prim_xilinx_ultrascale_and2.sv | 19 ------ .../rtl/prim_xilinx_ultrascale_buf.sv | 16 ----- .../rtl/prim_xilinx_ultrascale_clock_mux2.sv | 36 ----------- .../rtl/prim_xilinx_ultrascale_flop.sv | 27 --------- .../rtl/prim_xilinx_ultrascale_flop_en.sv | 30 ---------- .../rtl/prim_xilinx_ultrascale_pad_attr.sv | 59 ------------------- .../rtl/prim_xilinx_ultrascale_ram_1p.sv | 35 ----------- .../rtl/prim_xilinx_ultrascale_xnor2.sv | 19 ------ ...xilinx_ultrascale_xor2.sv => prim_xor2.sv} | 0 util/verible-format-allowlist.txt | 26 ++++---- 120 files changed, 167 insertions(+), 689 deletions(-) rename hw/ip/prim_generic/rtl/{prim_generic_and2.sv => prim_and2.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_buf.sv => prim_buf.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_clock_buf.sv => prim_clock_buf.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_clock_div.sv => prim_clock_div.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_clock_gating.sv => prim_clock_gating.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_clock_inv.sv => prim_clock_inv.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_clock_mux2.sv => prim_clock_mux2.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_flash.sv => prim_flash.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_flop.sv => prim_flop.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_flop_2sync.sv => prim_flop_2sync.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_flop_en.sv => prim_flop_en.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_otp.sv => prim_otp.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_pad_attr.sv => prim_pad_attr.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_pad_wrapper.sv => prim_pad_wrapper.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_ram_1p.sv => prim_ram_1p.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_ram_1r1w.sv => prim_ram_1r1w.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_ram_2p.sv => prim_ram_2p.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_rom.sv => prim_rom.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_usb_diff_rx.sv => prim_usb_diff_rx.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_xnor2.sv => prim_xnor2.sv} (100%) rename hw/ip/prim_generic/rtl/{prim_generic_xor2.sv => prim_xor2.sv} (100%) rename hw/ip/prim_xilinx/rtl/{prim_xilinx_and2.sv => prim_and2.sv} (100%) rename hw/ip/prim_xilinx/rtl/{prim_xilinx_buf.sv => prim_buf.sv} (100%) rename hw/ip/prim_xilinx/rtl/{prim_xilinx_clock_buf.sv => prim_clock_buf.sv} (100%) rename hw/ip/prim_xilinx/rtl/{prim_xilinx_clock_gating.sv => prim_clock_gating.sv} (100%) rename hw/ip/prim_xilinx/rtl/{prim_xilinx_clock_mux2.sv => prim_clock_mux2.sv} (100%) rename hw/ip/prim_xilinx/rtl/{prim_xilinx_flop.sv => prim_flop.sv} (100%) rename hw/ip/prim_xilinx/rtl/{prim_xilinx_flop_en.sv => prim_flop_en.sv} (100%) rename hw/ip/prim_xilinx/rtl/{prim_xilinx_pad_attr.sv => prim_pad_attr.sv} (100%) rename hw/ip/prim_xilinx/rtl/{prim_xilinx_pad_wrapper.sv => prim_pad_wrapper.sv} (100%) rename hw/ip/prim_xilinx/rtl/{prim_xilinx_ram_1p.sv => prim_ram_1p.sv} (60%) rename hw/ip/prim_xilinx/rtl/{prim_xilinx_xnor2.sv => prim_xnor2.sv} (94%) rename hw/ip/prim_xilinx/rtl/{prim_xilinx_xor2.sv => prim_xor2.sv} (100%) delete mode 100644 hw/ip/prim_xilinx_ultrascale/lint/prim_xilinx_ultrascale_clock_mux2.vlt delete mode 100644 hw/ip/prim_xilinx_ultrascale/lint/prim_xilinx_ultrascale_clock_mux2.waiver delete mode 100644 hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_and2.core delete mode 100644 hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_buf.core delete mode 100644 hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_mux2.core delete mode 100644 hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop.core delete mode 100644 hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop_en.core delete mode 100644 hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_attr.core delete mode 100644 hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_ram_1p.core delete mode 100644 hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xnor2.core rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_clock_buf.sv => prim_clock_buf.sv} (100%) rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_clock_div.sv => prim_clock_div.sv} (100%) rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_clock_gating.sv => prim_clock_gating.sv} (100%) rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_clock_inv.sv => prim_clock_inv.sv} (100%) rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_pad_wrapper.sv => prim_pad_wrapper.sv} (100%) delete mode 100644 hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_and2.sv delete mode 100644 hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_buf.sv delete mode 100644 hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_mux2.sv delete mode 100644 hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop.sv delete mode 100644 hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop_en.sv delete mode 100644 hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_attr.sv delete mode 100644 hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_ram_1p.sv delete mode 100644 hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xnor2.sv rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_xor2.sv => prim_xor2.sv} (100%) diff --git a/doc/contributing/fpga/ref_manual_fpga.md b/doc/contributing/fpga/ref_manual_fpga.md index 61aa684bb30f4..8a8fb4d8b9a46 100644 --- a/doc/contributing/fpga/ref_manual_fpga.md +++ b/doc/contributing/fpga/ref_manual_fpga.md @@ -29,7 +29,7 @@ For example, see the `//hw/bitstream:rom` target defined in [hw/bitstream/BUILD] There are two prerequisites in order for this flow to work: * The boot ROM during the build process must be correctly inferred by the tool. - * See [prim_rom](https://github.com/lowRISC/opentitan/blob/master/hw/ip/prim_generic/rtl/prim_generic_rom.sv) and [vivado_hook_opt_design_post.tcl](https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/util/vivado_hook_opt_design_post.tcl). + * See [prim_rom](https://github.com/lowRISC/opentitan/blob/master/hw/ip/prim_generic/rtl/prim_rom.sv) and [vivado_hook_opt_design_post.tcl](https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/util/vivado_hook_opt_design_post.tcl). * The MMI file outlining the physical boot ROM placement and mapping to FPGA block RAM primitives needs to be generated by the tool. * See [vivado_hook_write_bitstream_pre.tcl](https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/util/vivado_hook_write_bitstream_pre.tcl). diff --git a/hw/ip/otp_ctrl/README.md b/hw/ip/otp_ctrl/README.md index 343f2d3a2e499..b1bee2d73fdd2 100644 --- a/hw/ip/otp_ctrl/README.md +++ b/hw/ip/otp_ctrl/README.md @@ -60,4 +60,4 @@ This split implies that every proprietary OTP IP must implement a translation la It also implies that no matter how the OTP storage or word size may change underneath, the open-source controller must present a consistent and coherent software and hardware interface. This standardized interface is defined further below, and the wrapper leverages the same [technology primitive mechanism](../prim/README.md) that is employed in other parts of OpenTitan in order to wrap and abstract technology-specific macros (such as memories and clocking cells) that are potentially closed-source. -In order to enable simulation and FPGA emulation of the OTP controller even without access to the proprietary OTP IP, a generalized and synthesizable model of the OTP IP is provided in the form of a [generic technology primitive](https://github.com/lowRISC/opentitan/blob/master/hw/ip/prim_generic/rtl/prim_generic_otp.sv). +In order to enable simulation and FPGA emulation of the OTP controller even without access to the proprietary OTP IP, a generalized and synthesizable model of the OTP IP is provided in the form of a [generic technology primitive](https://github.com/lowRISC/opentitan/blob/master/hw/ip/prim_generic/rtl/prim_otp.sv). diff --git a/hw/ip/prim_generic/lint/prim_generic_clock_buf.vlt b/hw/ip/prim_generic/lint/prim_generic_clock_buf.vlt index c61d4c6ea4579..3952982334e69 100644 --- a/hw/ip/prim_generic/lint/prim_generic_clock_buf.vlt +++ b/hw/ip/prim_generic/lint/prim_generic_clock_buf.vlt @@ -5,4 +5,4 @@ `verilator_config -lint_off -rule UNUSED -file "*/rtl/prim_generic_clock_buf.sv" -match "Parameter is not used: 'NoFpgaBuf'" +lint_off -rule UNUSED -file "*/rtl/prim_clock_buf.sv" -match "Parameter is not used: 'NoFpgaBuf'" diff --git a/hw/ip/prim_generic/lint/prim_generic_clock_buf.waiver b/hw/ip/prim_generic/lint/prim_generic_clock_buf.waiver index 89ab9b8ffb29d..4fedf9534568f 100644 --- a/hw/ip/prim_generic/lint/prim_generic_clock_buf.waiver +++ b/hw/ip/prim_generic/lint/prim_generic_clock_buf.waiver @@ -2,6 +2,6 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# primitives: prim_generic_clock_buf -waive -rules PARAM_NOT_USED -location {prim_generic_clock_buf.sv} -regexp {Parameter '(NoFpgaBuf|RegionSel)' not used} \ +# primitives: prim_clock_buf +waive -rules PARAM_NOT_USED -location {prim_clock_buf.sv} -regexp {Parameter '(NoFpgaBuf|RegionSel)' not used} \ -comment "parameter unused but required to maintain uniform interface" diff --git a/hw/ip/prim_generic/lint/prim_generic_clock_div.waiver b/hw/ip/prim_generic/lint/prim_generic_clock_div.waiver index b56857c068dc3..c4210149639cf 100644 --- a/hw/ip/prim_generic/lint/prim_generic_clock_div.waiver +++ b/hw/ip/prim_generic/lint/prim_generic_clock_div.waiver @@ -2,21 +2,21 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# waiver file for prim_generic_clock_div +# waiver file for prim_clock_div -waive -rules CLOCK_EDGE -location {prim_generic_clock_div.sv} -msg {Falling edge of clock 'clk_i' used here, should use rising edge} \ +waive -rules CLOCK_EDGE -location {prim_clock_div.sv} -msg {Falling edge of clock 'clk_i' used here, should use rising edge} \ -comment "The clock switch signal is synchronized on negative edge to ensure it is away from any transition" -waive -rules DUAL_EDGE_CLOCK -location {prim_generic_clock_div.sv} -regexp {.*} \ +waive -rules DUAL_EDGE_CLOCK -location {prim_clock_div.sv} -regexp {.*} \ -comment "The clock switch signal is synchronized on negative edge to ensure it is away from any transition" -waive -rules CLOCK_MUX -location {prim_generic_clock_div.sv} -regexp {.*reaches a multiplexer here, used as a clock.*} \ +waive -rules CLOCK_MUX -location {prim_clock_div.sv} -regexp {.*reaches a multiplexer here, used as a clock.*} \ -comment "A mux is used during scan bypass, and for switching between div by 2 and div by 1 clocks" -waive -rules CLOCK_USE -location {prim_generic_clock_div.sv} -regexp {'clk_i' is connected to 'prim_clock_mux2' port 'clk1_i', and used as a clock} \ +waive -rules CLOCK_USE -location {prim_clock_div.sv} -regexp {'clk_i' is connected to 'prim_clock_mux2' port 'clk1_i', and used as a clock} \ -comment "This clock mux usage is OK." -waive -rules SAME_NAME_TYPE -location {prim_generic_clock_div.sv} -regexp {'ResetValue' is used as a parameter here, and as an enumeration value at} \ +waive -rules SAME_NAME_TYPE -location {prim_clock_div.sv} -regexp {'ResetValue' is used as a parameter here, and as an enumeration value at} \ -comment "Reused parameter name." waive -rules CLOCK_DRIVER -location {prim_generic_clock_div.sv} -regexp {'gen_div2.q_p' is driven by instance 'gen_div2\^u_div2' of module 'prim_flop', and used as a clock 'clk_i'} \ diff --git a/hw/ip/prim_generic/lint/prim_generic_clock_gating.vlt b/hw/ip/prim_generic/lint/prim_generic_clock_gating.vlt index 2c6c5af87cebb..8663692959ad7 100644 --- a/hw/ip/prim_generic/lint/prim_generic_clock_gating.vlt +++ b/hw/ip/prim_generic/lint/prim_generic_clock_gating.vlt @@ -5,5 +5,5 @@ `verilator_config -lint_off -rule UNUSED -file "*/rtl/prim_generic_clock_gating.sv" -match "Parameter is not used: 'NoFpgaGate'" -lint_off -rule UNUSED -file "*/rtl/prim_generic_clock_gating.sv" -match "Parameter is not used: 'FpgaBufGlobal'" +lint_off -rule UNUSED -file "*/rtl/prim_clock_gating.sv" -match "Parameter is not used: 'NoFpgaGate'" +lint_off -rule UNUSED -file "*/rtl/prim_clock_gating.sv" -match "Parameter is not used: 'FpgaBufGlobal'" diff --git a/hw/ip/prim_generic/lint/prim_generic_clock_gating.waiver b/hw/ip/prim_generic/lint/prim_generic_clock_gating.waiver index 1eb8561142030..e68c145996c5c 100644 --- a/hw/ip/prim_generic/lint/prim_generic_clock_gating.waiver +++ b/hw/ip/prim_generic/lint/prim_generic_clock_gating.waiver @@ -3,11 +3,11 @@ # SPDX-License-Identifier: Apache-2.0 # # primitives: prim_clock_gating -waive -rules LATCH -location {prim_generic_clock_gating.sv} -regexp {'en_latch' is a latch} \ +waive -rules LATCH -location {prim_clock_gating.sv} -regexp {'en_latch' is a latch} \ -comment "clock gating cell creates a latch" -waive -rules COMBO_NBA -location {prim_generic_clock_gating.sv} -regexp {Non-blocking assignment to 'en_latch'} \ +waive -rules COMBO_NBA -location {prim_clock_gating.sv} -regexp {Non-blocking assignment to 'en_latch'} \ -comment "clock gating cell creates a latch" -waive -rules PARAM_NOT_USED -location {prim_generic_clock_gating.sv} -regexp {Parameter 'NoFpgaGate' not used} \ +waive -rules PARAM_NOT_USED -location {prim_clock_gating.sv} -regexp {Parameter 'NoFpgaGate' not used} \ -comment "parameter unused but required to maintain uniform interface" -waive -rules PARAM_NOT_USED -location {prim_generic_clock_gating.sv} -regexp {Parameter 'FpgaBufGlobal' not used} \ +waive -rules PARAM_NOT_USED -location {prim_clock_gating.sv} -regexp {Parameter 'FpgaBufGlobal' not used} \ -comment "parameter unused but required to maintain uniform interface" diff --git a/hw/ip/prim_generic/lint/prim_generic_clock_mux2.vlt b/hw/ip/prim_generic/lint/prim_generic_clock_mux2.vlt index d62099a9af538..23cd4fa4ab687 100644 --- a/hw/ip/prim_generic/lint/prim_generic_clock_mux2.vlt +++ b/hw/ip/prim_generic/lint/prim_generic_clock_mux2.vlt @@ -5,4 +5,4 @@ `verilator_config -lint_off -rule UNUSED -file "*/rtl/prim_generic_clock_mux2.sv" -match "Parameter is not used: 'NoFpgaBufG'" +lint_off -rule UNUSED -file "*/rtl/prim_clock_mux2.sv" -match "Parameter is not used: 'NoFpgaBufG'" diff --git a/hw/ip/prim_generic/lint/prim_generic_clock_mux2.waiver b/hw/ip/prim_generic/lint/prim_generic_clock_mux2.waiver index 42d76a8dfa003..62d6c52363ed0 100644 --- a/hw/ip/prim_generic/lint/prim_generic_clock_mux2.waiver +++ b/hw/ip/prim_generic/lint/prim_generic_clock_mux2.waiver @@ -4,5 +4,5 @@ # # waiver file for prim_clock_mux2 -waive -rules PARAM_NOT_USED -location {prim_generic_clock_mux2.sv} -regexp {.*Parameter 'NoFpgaBufG' not used in.*} \ +waive -rules PARAM_NOT_USED -location {prim_clock_mux2.sv} -regexp {.*Parameter 'NoFpgaBufG' not used in.*} \ -comment "This parameter serves no function in the generic model" diff --git a/hw/ip/prim_generic/lint/prim_generic_flash.waiver b/hw/ip/prim_generic/lint/prim_generic_flash.waiver index d733a25619b09..eb693f1f81959 100644 --- a/hw/ip/prim_generic/lint/prim_generic_flash.waiver +++ b/hw/ip/prim_generic/lint/prim_generic_flash.waiver @@ -2,8 +2,8 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# waiver file for prim_generic_flash +# waiver file for prim_flash # The prim generic module does not make use of the IO ports -waive -rules INOUT_AS_IN -location {prim_generic_flash.sv} \ +waive -rules INOUT_AS_IN -location {prim_flash.sv} \ -regexp {Inout port 'flash_.*_io' has no driver} diff --git a/hw/ip/prim_generic/lint/prim_generic_otp.vlt b/hw/ip/prim_generic/lint/prim_generic_otp.vlt index 3aa735e9887e3..2cb488200856b 100644 --- a/hw/ip/prim_generic/lint/prim_generic_otp.vlt +++ b/hw/ip/prim_generic/lint/prim_generic_otp.vlt @@ -6,5 +6,5 @@ `verilator_config // The generic OTP module doesn't use vendor-specific parameters -lint_off -rule UNUSED -file "*/rtl/prim_generic_otp.sv" -match "*VendorTestOffset*" -lint_off -rule UNUSED -file "*/rtl/prim_generic_otp.sv" -match "*VendorTestSize*" +lint_off -rule UNUSED -file "*/rtl/prim_otp.sv" -match "*VendorTestOffset*" +lint_off -rule UNUSED -file "*/rtl/prim_otp.sv" -match "*VendorTestSize*" diff --git a/hw/ip/prim_generic/lint/prim_generic_otp.waiver b/hw/ip/prim_generic/lint/prim_generic_otp.waiver index c2313ab038aed..fa309feacba2f 100644 --- a/hw/ip/prim_generic/lint/prim_generic_otp.waiver +++ b/hw/ip/prim_generic/lint/prim_generic_otp.waiver @@ -7,10 +7,10 @@ waive -rules {CONST_FF} -location {prim_ram_1p_adv.sv} \ -msg {Flip-flop 'rerror_q' is driven by constant zeros in module 'prim_ram_1p_adv' (Depth=1024,Width=22,EnableInputPipeline=1,EnableOutputPipeline=1)} \ -comment "The read error bits are unused and hence set to zero." -waive -rules {INOUT_AS_IN} -location {prim_generic_otp.sv} \ - -msg {Inout port 'ext_voltage_io' has no driver in module 'prim_generic_otp'} \ +waive -rules {INOUT_AS_IN} -location {prim_otp.sv} \ + -msg {Inout port 'ext_voltage_io' has no driver in module 'prim_otp'} \ -comment "This signal is not driven in the generic model." -waive -rules {PARAM_NOT_USED} -location {prim_generic_otp.sv} \ - -regexp {Parameter '(VendorTestOffset|VendorTestSize)' not used in module 'prim_generic_otp'} \ +waive -rules {PARAM_NOT_USED} -location {prim_otp.sv} \ + -regexp {Parameter '(VendorTestOffset|VendorTestSize)' not used in module 'prim_otp'} \ -comment "These two parameters are not used in the generic model." diff --git a/hw/ip/prim_generic/lint/prim_generic_pad_wrapper.waiver b/hw/ip/prim_generic/lint/prim_generic_pad_wrapper.waiver index 1286520ae27b2..527b7f8ac24e5 100644 --- a/hw/ip/prim_generic/lint/prim_generic_pad_wrapper.waiver +++ b/hw/ip/prim_generic/lint/prim_generic_pad_wrapper.waiver @@ -2,28 +2,28 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# waiver file for prim_generic_pad_wrapper +# waiver file for prim_pad_wrapper # note that this code is NOT synthesizable and meant for sim only -waive -rules TRI_DRIVER -regexp {'inout_io' is driven by a tristate driver} -location {prim_generic_pad_wrapper.sv} \ +waive -rules TRI_DRIVER -regexp {'inout_io' is driven by a tristate driver} -location {prim_pad_wrapper.sv} \ -comment "This is a bidirectional pad inout." waive -rules TRI_DRIVER -regexp {'in_raw_o' is driven by a tristate driver} \ -comment "This is a bidirectional pad inout." -waive -rules MULTI_DRIVEN -regexp {.* drivers on 'inout_io' here} -location {prim_generic_pad_wrapper.sv} \ +waive -rules MULTI_DRIVEN -regexp {.* drivers on 'inout_io' here} -location {prim_pad_wrapper.sv} \ -comment "The pad simulation model has multiple drivers to emulate different IO terminations." -waive -rules SELF_ASSIGN -regexp {LHS signal 'inout_io' encountered on the RHS of a continuous assignment statement} -location {prim_generic_pad_wrapper.sv} \ +waive -rules SELF_ASSIGN -regexp {LHS signal 'inout_io' encountered on the RHS of a continuous assignment statement} -location {prim_pad_wrapper.sv} \ -comment "This implements a keeper termination (it's basically an explicit TRIREG)" -waive -rules DRIVE_STRENGTH -regexp {Drive strength .* encountered on assignment to 'inout_io'} -location {prim_generic_pad_wrapper.sv} \ +waive -rules DRIVE_STRENGTH -regexp {Drive strength .* encountered on assignment to 'inout_io'} -location {prim_pad_wrapper.sv} \ -comment "The pad simulation model uses driving strength attributes to emulate different IO terminations." -waive -rules INPUT_NOT_READ -regexp {Input port 'attr\_i*' is not read from} -location {prim_generic_pad_wrapper.sv} \ +waive -rules INPUT_NOT_READ -regexp {Input port 'attr\_i*' is not read from} -location {prim_pad_wrapper.sv} \ -comment "Some IO attributes may not be implemented." -waive -rules Z_USE -regexp {Constant with 'Z literal value '1'bz' encountered} -location {prim_generic_pad_wrapper.sv} \ +waive -rules Z_USE -regexp {Constant with 'Z literal value '1'bz' encountered} -location {prim_pad_wrapper.sv} \ -comment "This z assignment is correct." -waive -rules PARAM_NOT_USED -regexp {Parameter 'Variant' not used in module 'prim_generic_pad_wrapper'} -location {prim_generic_pad_wrapper.sv} \ +waive -rules PARAM_NOT_USED -regexp {Parameter 'Variant' not used in module 'prim_pad_wrapper'} -location {prim_pad_wrapper.sv} \ -comment "This parameter has been provisioned for later and is currently unused." -waive -rules PARAM_NOT_USED -regexp {Parameter 'ScanRole' not used in module 'prim_generic_pad_wrapper'} -location {prim_generic_pad_wrapper.sv} \ +waive -rules PARAM_NOT_USED -regexp {Parameter 'ScanRole' not used in module 'prim_pad_wrapper'} -location {prim_pad_wrapper.sv} \ -comment "This parameter has been provisioned for later and is currently unused." -waive -rules INPUT_NOT_READ -msg {Input port 'clk_scan_i' is not read from in module 'prim_generic_pad_wrapper'} \ +waive -rules INPUT_NOT_READ -msg {Input port 'clk_scan_i' is not read from in module 'prim_pad_wrapper'} \ -comment "This clock is not read in RTL since it will be connected after synthesis during DFT insertion" waive -rules {CLOCK_DRIVER CLOCK_USE INV_CLOCK} -regexp {'gen_bidir.out' is (driven here|used for some other purpose|inverted), (and used|and|used) as( a)? clock} \ -comment "The pad simulation model may also be used for simulating clock pads" diff --git a/hw/ip/prim_generic/lint/prim_generic_ram_1p.waiver b/hw/ip/prim_generic/lint/prim_generic_ram_1p.waiver index 997c72c77cccc..0c4983f3f11f1 100644 --- a/hw/ip/prim_generic/lint/prim_generic_ram_1p.waiver +++ b/hw/ip/prim_generic/lint/prim_generic_ram_1p.waiver @@ -2,11 +2,11 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# waiver file for prim_generic_ram_1p +# waiver file for prim_ram_1p -waive -rules ALWAYS_SPEC -location {prim_generic_ram_1p.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \ +waive -rules ALWAYS_SPEC -location {prim_ram_1p.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \ -comment "Vivado requires here an always instead of always_ff" -waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_generic_ram_1p.sv.* is not read from in module 'prim_generic_ram_1p'} \ +waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_ram_1p.sv.* is not read from in module 'prim_ram_1p'} \ -comment "Ascentlint blackboxes very deep RAMs to speed up runtime. This blackboxing causes above lint errors." -waive -rules IFDEF_CODE -location {prim_generic_ram_1p.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \ +waive -rules IFDEF_CODE -location {prim_ram_1p.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \ -comment "Declaration of signal and assignment to it are in same `ifndef" diff --git a/hw/ip/prim_generic/lint/prim_generic_ram_1r1w.waiver b/hw/ip/prim_generic/lint/prim_generic_ram_1r1w.waiver index 0a717f45d065a..c57a0decaa36a 100644 --- a/hw/ip/prim_generic/lint/prim_generic_ram_1r1w.waiver +++ b/hw/ip/prim_generic/lint/prim_generic_ram_1r1w.waiver @@ -2,11 +2,11 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# waiver file for prim_generic_ram_1r1w +# waiver file for prim_ram_1r1w -waive -rules ALWAYS_SPEC -location {prim_generic_ram_1r1w.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \ +waive -rules ALWAYS_SPEC -location {prim_ram_1r1w.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \ -comment "Vivado requires here an always instead of always_ff" -waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_generic_ram_1r1w.sv.* is not read from in module 'prim_generic_ram_1r1w'} \ +waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_ram_1r1w.sv.* is not read from in module 'prim_ram_1r1w'} \ -comment "Ascentlint blackboxes very deep RAMs to speed up runtime. This blackboxing causes above lint errors." -waive -rules IFDEF_CODE -location {prim_generic_ram_1r1w.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \ +waive -rules IFDEF_CODE -location {prim_ram_1r1w.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \ -comment "Declaration of signal and assignment to it are in same `ifndef" diff --git a/hw/ip/prim_generic/lint/prim_generic_ram_2p.vlt b/hw/ip/prim_generic/lint/prim_generic_ram_2p.vlt index c2c00c8c1b7a8..5baf84e9a3c9c 100644 --- a/hw/ip/prim_generic/lint/prim_generic_ram_2p.vlt +++ b/hw/ip/prim_generic/lint/prim_generic_ram_2p.vlt @@ -6,4 +6,4 @@ `verilator_config // That is the nature of a dual-port memory: both write ports can access the same storage simultaneously. -lint_off -rule MULTIDRIVEN -file "*/rtl/prim_generic_ram_2p.sv" -match "Signal has multiple driving blocks with different clocking: '*.mem'*" +lint_off -rule MULTIDRIVEN -file "*/rtl/prim_ram_2p.sv" -match "Signal has multiple driving blocks with different clocking: '*.mem'*" diff --git a/hw/ip/prim_generic/lint/prim_generic_ram_2p.waiver b/hw/ip/prim_generic/lint/prim_generic_ram_2p.waiver index 69590e898d3a6..d3f9dcbedf48c 100644 --- a/hw/ip/prim_generic/lint/prim_generic_ram_2p.waiver +++ b/hw/ip/prim_generic/lint/prim_generic_ram_2p.waiver @@ -2,13 +2,13 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# waiver file for prim_generic_ram_2p +# waiver file for prim_ram_2p -waive -rules MULTI_PROC_ASSIGN -location {prim_generic_ram_2p.sv} -regexp {Assignment to 'mem' from more than one block} \ +waive -rules MULTI_PROC_ASSIGN -location {prim_ram_2p.sv} -regexp {Assignment to 'mem' from more than one block} \ -comment "That is the nature of a dual-port memory: both write ports can access the same storage simultaneously" -waive -rules ALWAYS_SPEC -location {prim_generic_ram_2p.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \ +waive -rules ALWAYS_SPEC -location {prim_ram_2p.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \ -comment "Vivado requires here an always instead of always_ff" -waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_generic_ram_2p.sv.* is not read from in module 'prim_generic_ram_2p'} \ +waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_ram_2p.sv.* is not read from in module 'prim_ram_2p'} \ -comment "Ascentlint blackboxes very deep RAMs to speed up runtime. This blackboxing causes above lint errors." -waive -rules IFDEF_CODE -location {prim_generic_ram_2p.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \ +waive -rules IFDEF_CODE -location {prim_ram_2p.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \ -comment "Declaration of signal and assignment to it are in same `ifndef" diff --git a/hw/ip/prim_generic/lint/prim_generic_rom.waiver b/hw/ip/prim_generic/lint/prim_generic_rom.waiver index 351694ba18c7b..c6a44351c6161 100644 --- a/hw/ip/prim_generic/lint/prim_generic_rom.waiver +++ b/hw/ip/prim_generic/lint/prim_generic_rom.waiver @@ -2,7 +2,7 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# waiver file for prim_generic_rom +# waiver file for prim_rom -waive -rules NOT_DRIVEN -location {prim_generic_rom.sv} -regexp {Signal 'mem' has no driver in module 'prim_generic_rom'} \ +waive -rules NOT_DRIVEN -location {prim_rom.sv} -regexp {Signal 'mem' has no driver in module 'prim_rom'} \ -comment "since this is a ROM, the signal mem has no driver, but it is populated using an initialization file" diff --git a/hw/ip/prim_generic/lint/prim_generic_usb_diff_rx.waiver b/hw/ip/prim_generic/lint/prim_generic_usb_diff_rx.waiver index 3ae5442bbe341..af8022ee4edc1 100644 --- a/hw/ip/prim_generic/lint/prim_generic_usb_diff_rx.waiver +++ b/hw/ip/prim_generic/lint/prim_generic_usb_diff_rx.waiver @@ -2,12 +2,12 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# waiver file for prim_generic_usb_diff_rx +# waiver file for prim_usb_diff_rx # note that this code is NOT synthesizable and meant for sim only -waive -rules TRI_DRIVER -regexp {'(input_pi|input_ni)' is driven by a tristate driver} -location {prim_generic_usb_diff_rx.sv} \ +waive -rules TRI_DRIVER -regexp {'(input_pi|input_ni)' is driven by a tristate driver} -location {prim_usb_diff_rx.sv} \ -comment "This models the pullup behavior, hence the TRI driver." -waive -rules MULTI_DRIVEN -regexp {'(input_pi|input_ni)' has 2 drivers, also driven at} -location {prim_generic_usb_diff_rx.sv} \ +waive -rules MULTI_DRIVEN -regexp {'(input_pi|input_ni)' has 2 drivers, also driven at} -location {prim_usb_diff_rx.sv} \ -comment "The simulation model has multiple drivers to emulate different IO terminations." -waive -rules DRIVE_STRENGTH -regexp {Drive strength '\(weak0,pull1\)' encountered on assignment to '(input_pi|input_ni)'} -location {prim_generic_usb_diff_rx.sv} \ +waive -rules DRIVE_STRENGTH -regexp {Drive strength '\(weak0,pull1\)' encountered on assignment to '(input_pi|input_ni)'} -location {prim_usb_diff_rx.sv} \ -comment "The simulation model uses driving strength attributes to emulate different IO terminations." diff --git a/hw/ip/prim_generic/prim_generic_and2.core b/hw/ip/prim_generic/prim_generic_and2.core index 84ff84b786cb5..e18e8b48a2d65 100644 --- a/hw/ip/prim_generic/prim_generic_and2.core +++ b/hw/ip/prim_generic/prim_generic_and2.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_generic_and2.sv + - rtl/prim_and2.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_buf.core b/hw/ip/prim_generic/prim_generic_buf.core index 42342e7cfe583..9db9568d253eb 100644 --- a/hw/ip/prim_generic/prim_generic_buf.core +++ b/hw/ip/prim_generic/prim_generic_buf.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_generic_buf.sv + - rtl/prim_buf.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_clock_buf.core b/hw/ip/prim_generic/prim_generic_clock_buf.core index d9cb24827fbce..d11883d9ea4f7 100644 --- a/hw/ip/prim_generic/prim_generic_clock_buf.core +++ b/hw/ip/prim_generic/prim_generic_clock_buf.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_generic_clock_buf.sv + - rtl/prim_clock_buf.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_clock_div.core b/hw/ip/prim_generic/prim_generic_clock_div.core index 6bd3aee3f0291..0c33b7398f10d 100644 --- a/hw/ip/prim_generic/prim_generic_clock_div.core +++ b/hw/ip/prim_generic/prim_generic_clock_div.core @@ -16,7 +16,7 @@ filesets: - lowrisc:prim:clock_inv - lowrisc:prim:clock_buf files: - - rtl/prim_generic_clock_div.sv + - rtl/prim_clock_div.sv file_type: systemVerilogSource files_ascentlint_waiver: diff --git a/hw/ip/prim_generic/prim_generic_clock_gating.core b/hw/ip/prim_generic/prim_generic_clock_gating.core index ce65b1b9e3c87..9d79c9d540303 100644 --- a/hw/ip/prim_generic/prim_generic_clock_gating.core +++ b/hw/ip/prim_generic/prim_generic_clock_gating.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_generic_clock_gating.sv + - rtl/prim_clock_gating.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_clock_inv.core b/hw/ip/prim_generic/prim_generic_clock_inv.core index e9982ef38a07c..399b220bb6f44 100644 --- a/hw/ip/prim_generic/prim_generic_clock_inv.core +++ b/hw/ip/prim_generic/prim_generic_clock_inv.core @@ -14,7 +14,7 @@ filesets: - lowrisc:prim:assert - lowrisc:prim:clock_mux2 files: - - rtl/prim_generic_clock_inv.sv + - rtl/prim_clock_inv.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_clock_mux2.core b/hw/ip/prim_generic/prim_generic_clock_mux2.core index 7cfca422af065..de600aea58b3d 100644 --- a/hw/ip/prim_generic/prim_generic_clock_mux2.core +++ b/hw/ip/prim_generic/prim_generic_clock_mux2.core @@ -13,7 +13,7 @@ filesets: depend: - lowrisc:prim:assert files: - - rtl/prim_generic_clock_mux2.sv + - rtl/prim_clock_mux2.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_flash.core b/hw/ip/prim_generic/prim_generic_flash.core index 08a6f9b74b09a..13035b8278b46 100644 --- a/hw/ip/prim_generic/prim_generic_flash.core +++ b/hw/ip/prim_generic/prim_generic_flash.core @@ -19,7 +19,7 @@ filesets: - lowrisc:ip:flash_ctrl_prim_reg_top files: - rtl/prim_generic_flash_bank.sv - - rtl/prim_generic_flash.sv + - rtl/prim_flash.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_flop.core b/hw/ip/prim_generic/prim_generic_flop.core index 162735a9bbc02..e899f79042ee0 100644 --- a/hw/ip/prim_generic/prim_generic_flop.core +++ b/hw/ip/prim_generic/prim_generic_flop.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_generic_flop.sv + - rtl/prim_flop.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_flop_2sync.core b/hw/ip/prim_generic/prim_generic_flop_2sync.core index 82f2b6e98718d..a67519a8696f9 100644 --- a/hw/ip/prim_generic/prim_generic_flop_2sync.core +++ b/hw/ip/prim_generic/prim_generic_flop_2sync.core @@ -16,7 +16,7 @@ filesets: # Needed for DV. - lowrisc:prim:cdc_rand_delay files: - - rtl/prim_generic_flop_2sync.sv + - rtl/prim_flop_2sync.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_flop_en.core b/hw/ip/prim_generic/prim_generic_flop_en.core index 556ee9abec0e8..e1c70ecfc605a 100644 --- a/hw/ip/prim_generic/prim_generic_flop_en.core +++ b/hw/ip/prim_generic/prim_generic_flop_en.core @@ -13,7 +13,7 @@ filesets: depend: - lowrisc:prim:sec_anchor files: - - rtl/prim_generic_flop_en.sv + - rtl/prim_flop_en.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_otp.core b/hw/ip/prim_generic/prim_generic_otp.core index 054d97a55b251..70e12ce53bdbc 100644 --- a/hw/ip/prim_generic/prim_generic_otp.core +++ b/hw/ip/prim_generic/prim_generic_otp.core @@ -19,7 +19,7 @@ filesets: - lowrisc:prim:otp_pkg - lowrisc:ip:otp_ctrl_prim_reg_top files: - - rtl/prim_generic_otp.sv + - rtl/prim_otp.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_pad_attr.core b/hw/ip/prim_generic/prim_generic_pad_attr.core index 451ae4c8d63eb..c80c59e00dbf3 100644 --- a/hw/ip/prim_generic/prim_generic_pad_attr.core +++ b/hw/ip/prim_generic/prim_generic_pad_attr.core @@ -14,7 +14,7 @@ filesets: - lowrisc:prim:assert - lowrisc:prim:pad_wrapper_pkg files: - - rtl/prim_generic_pad_attr.sv + - rtl/prim_pad_attr.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_pad_wrapper.core b/hw/ip/prim_generic/prim_generic_pad_wrapper.core index 9e7ffc6ba1d4d..764cd45f89ce3 100644 --- a/hw/ip/prim_generic/prim_generic_pad_wrapper.core +++ b/hw/ip/prim_generic/prim_generic_pad_wrapper.core @@ -14,7 +14,7 @@ filesets: - lowrisc:prim:assert - lowrisc:prim:pad_wrapper_pkg files: - - rtl/prim_generic_pad_wrapper.sv + - rtl/prim_pad_wrapper.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_ram_1p.core b/hw/ip/prim_generic/prim_generic_ram_1p.core index 52b98b589910d..661a96627b516 100644 --- a/hw/ip/prim_generic/prim_generic_ram_1p.core +++ b/hw/ip/prim_generic/prim_generic_ram_1p.core @@ -15,7 +15,7 @@ filesets: - lowrisc:prim:ram_1p_pkg - lowrisc:prim:util_memload files: - - rtl/prim_generic_ram_1p.sv + - rtl/prim_ram_1p.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_ram_1r1w.core b/hw/ip/prim_generic/prim_generic_ram_1r1w.core index 302a516a2d566..efcbc802748bd 100644 --- a/hw/ip/prim_generic/prim_generic_ram_1r1w.core +++ b/hw/ip/prim_generic/prim_generic_ram_1r1w.core @@ -15,7 +15,7 @@ filesets: - lowrisc:prim:ram_2p_pkg - lowrisc:prim:util_memload files: - - rtl/prim_generic_ram_1r1w.sv + - rtl/prim_ram_1r1w.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_ram_2p.core b/hw/ip/prim_generic/prim_generic_ram_2p.core index 7da402948ca41..b246ce1164f30 100644 --- a/hw/ip/prim_generic/prim_generic_ram_2p.core +++ b/hw/ip/prim_generic/prim_generic_ram_2p.core @@ -15,7 +15,7 @@ filesets: - lowrisc:prim:ram_2p_pkg - lowrisc:prim:util_memload files: - - rtl/prim_generic_ram_2p.sv + - rtl/prim_ram_2p.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_rom.core b/hw/ip/prim_generic/prim_generic_rom.core index 32d3cb04e240f..41d76d4fb95e4 100644 --- a/hw/ip/prim_generic/prim_generic_rom.core +++ b/hw/ip/prim_generic/prim_generic_rom.core @@ -15,7 +15,7 @@ filesets: - lowrisc:prim:rom_pkg - lowrisc:prim:util_memload files: - - rtl/prim_generic_rom.sv + - rtl/prim_rom.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_usb_diff_rx.core b/hw/ip/prim_generic/prim_generic_usb_diff_rx.core index 59d18043ab0f8..f77bdeee10838 100644 --- a/hw/ip/prim_generic/prim_generic_usb_diff_rx.core +++ b/hw/ip/prim_generic/prim_generic_usb_diff_rx.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_generic_usb_diff_rx.sv + - rtl/prim_usb_diff_rx.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_xnor2.core b/hw/ip/prim_generic/prim_generic_xnor2.core index c8e86b4017401..137af0183886b 100644 --- a/hw/ip/prim_generic/prim_generic_xnor2.core +++ b/hw/ip/prim_generic/prim_generic_xnor2.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_generic_xnor2.sv + - rtl/prim_xnor2.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/prim_generic_xor2.core b/hw/ip/prim_generic/prim_generic_xor2.core index 6d945cef6be27..b77448326d5a9 100644 --- a/hw/ip/prim_generic/prim_generic_xor2.core +++ b/hw/ip/prim_generic/prim_generic_xor2.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_generic_xor2.sv + - rtl/prim_xor2.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_generic/rtl/prim_generic_and2.sv b/hw/ip/prim_generic/rtl/prim_and2.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_and2.sv rename to hw/ip/prim_generic/rtl/prim_and2.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_buf.sv b/hw/ip/prim_generic/rtl/prim_buf.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_buf.sv rename to hw/ip/prim_generic/rtl/prim_buf.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_buf.sv b/hw/ip/prim_generic/rtl/prim_clock_buf.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_clock_buf.sv rename to hw/ip/prim_generic/rtl/prim_clock_buf.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_div.sv b/hw/ip/prim_generic/rtl/prim_clock_div.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_clock_div.sv rename to hw/ip/prim_generic/rtl/prim_clock_div.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_gating.sv b/hw/ip/prim_generic/rtl/prim_clock_gating.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_clock_gating.sv rename to hw/ip/prim_generic/rtl/prim_clock_gating.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_inv.sv b/hw/ip/prim_generic/rtl/prim_clock_inv.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_clock_inv.sv rename to hw/ip/prim_generic/rtl/prim_clock_inv.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_mux2.sv b/hw/ip/prim_generic/rtl/prim_clock_mux2.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_clock_mux2.sv rename to hw/ip/prim_generic/rtl/prim_clock_mux2.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_flash.sv b/hw/ip/prim_generic/rtl/prim_flash.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_flash.sv rename to hw/ip/prim_generic/rtl/prim_flash.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_flop.sv b/hw/ip/prim_generic/rtl/prim_flop.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_flop.sv rename to hw/ip/prim_generic/rtl/prim_flop.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_flop_2sync.sv b/hw/ip/prim_generic/rtl/prim_flop_2sync.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_flop_2sync.sv rename to hw/ip/prim_generic/rtl/prim_flop_2sync.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_flop_en.sv b/hw/ip/prim_generic/rtl/prim_flop_en.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_flop_en.sv rename to hw/ip/prim_generic/rtl/prim_flop_en.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_otp.sv b/hw/ip/prim_generic/rtl/prim_otp.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_otp.sv rename to hw/ip/prim_generic/rtl/prim_otp.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_pad_attr.sv b/hw/ip/prim_generic/rtl/prim_pad_attr.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_pad_attr.sv rename to hw/ip/prim_generic/rtl/prim_pad_attr.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv b/hw/ip/prim_generic/rtl/prim_pad_wrapper.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv rename to hw/ip/prim_generic/rtl/prim_pad_wrapper.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv b/hw/ip/prim_generic/rtl/prim_ram_1p.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv rename to hw/ip/prim_generic/rtl/prim_ram_1p.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv b/hw/ip/prim_generic/rtl/prim_ram_1r1w.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv rename to hw/ip/prim_generic/rtl/prim_ram_1r1w.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv b/hw/ip/prim_generic/rtl/prim_ram_2p.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv rename to hw/ip/prim_generic/rtl/prim_ram_2p.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_rom.sv b/hw/ip/prim_generic/rtl/prim_rom.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_rom.sv rename to hw/ip/prim_generic/rtl/prim_rom.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_usb_diff_rx.sv b/hw/ip/prim_generic/rtl/prim_usb_diff_rx.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_usb_diff_rx.sv rename to hw/ip/prim_generic/rtl/prim_usb_diff_rx.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_xnor2.sv b/hw/ip/prim_generic/rtl/prim_xnor2.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_xnor2.sv rename to hw/ip/prim_generic/rtl/prim_xnor2.sv diff --git a/hw/ip/prim_generic/rtl/prim_generic_xor2.sv b/hw/ip/prim_generic/rtl/prim_xor2.sv similarity index 100% rename from hw/ip/prim_generic/rtl/prim_generic_xor2.sv rename to hw/ip/prim_generic/rtl/prim_xor2.sv diff --git a/hw/ip/prim_xilinx/lint/prim_xilinx_pad_wrapper.waiver b/hw/ip/prim_xilinx/lint/prim_xilinx_pad_wrapper.waiver index 198eeeace1f7f..05764f141f796 100644 --- a/hw/ip/prim_xilinx/lint/prim_xilinx_pad_wrapper.waiver +++ b/hw/ip/prim_xilinx/lint/prim_xilinx_pad_wrapper.waiver @@ -5,8 +5,8 @@ # waiver file for prim_xilinx_pad_wrapper # note that this code is NOT synthesizable and meant for sim only waive -rules TRI_DRIVER -regexp {'inout_io' is driven by a tristate driver} \ - -location {prim_xilinx_pad_wrapper.sv} \ + -location {prim_pad_wrapper.sv} \ -comment "This is a bidirectional pad inout." waive -rules INPUT_NOT_READ -regexp {Input port 'attr\_i\[.:2\]' is not read from} \ - -location {prim_xilinx_pad_wrapper.sv} \ + -location {prim_pad_wrapper.sv} \ -comment "Some IO attributes may not be implemented." diff --git a/hw/ip/prim_xilinx/prim_xilinx.core b/hw/ip/prim_xilinx/prim_xilinx.core index bb4891f74eddf..ba79332ec27ea 100644 --- a/hw/ip/prim_xilinx/prim_xilinx.core +++ b/hw/ip/prim_xilinx/prim_xilinx.core @@ -23,11 +23,11 @@ filesets: - lowrisc:prim_generic:otp - lowrisc:prim_xilinx:pad_attr - lowrisc:prim_xilinx:pad_wrapper - - lowrisc:prim_generic:ram_1p + - lowrisc:prim_xilinx:ram_1p - lowrisc:prim_generic:ram_1r1w - lowrisc:prim_generic:ram_2p - lowrisc:prim_generic:rom - - lowrisc:prim_generic:xnor2 + - lowrisc:prim_xilinx:xnor2 - lowrisc:prim_xilinx:xor2 targets: diff --git a/hw/ip/prim_xilinx/prim_xilinx_and2.core b/hw/ip/prim_xilinx/prim_xilinx_and2.core index 5db713bd5b3dd..a88998653ab88 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_and2.core +++ b/hw/ip/prim_xilinx/prim_xilinx_and2.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_xilinx_and2.sv + - rtl/prim_and2.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_xilinx/prim_xilinx_buf.core b/hw/ip/prim_xilinx/prim_xilinx_buf.core index d5cd793214d94..a7402d416ea74 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_buf.core +++ b/hw/ip/prim_xilinx/prim_xilinx_buf.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_xilinx_buf.sv + - rtl/prim_buf.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_xilinx/prim_xilinx_clock_buf.core b/hw/ip/prim_xilinx/prim_xilinx_clock_buf.core index b458d4db454f3..c315943b88239 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_clock_buf.core +++ b/hw/ip/prim_xilinx/prim_xilinx_clock_buf.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_xilinx_clock_buf.sv + - rtl/prim_clock_buf.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_xilinx/prim_xilinx_clock_gating.core b/hw/ip/prim_xilinx/prim_xilinx_clock_gating.core index e80bd4a44114a..5345ab9fabe61 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_clock_gating.core +++ b/hw/ip/prim_xilinx/prim_xilinx_clock_gating.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_xilinx_clock_gating.sv + - rtl/prim_clock_gating.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core b/hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core index e08e8301d829e..a1e8463caab8e 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core +++ b/hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_xilinx_clock_mux2.sv + - rtl/prim_clock_mux2.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_xilinx/prim_xilinx_flop.core b/hw/ip/prim_xilinx/prim_xilinx_flop.core index 427449775d7e2..2cd60711776b2 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_flop.core +++ b/hw/ip/prim_xilinx/prim_xilinx_flop.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_xilinx_flop.sv + - rtl/prim_flop.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_xilinx/prim_xilinx_flop_en.core b/hw/ip/prim_xilinx/prim_xilinx_flop_en.core index 0edee3a33f08a..cc3176d0ee14d 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_flop_en.core +++ b/hw/ip/prim_xilinx/prim_xilinx_flop_en.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_xilinx_flop_en.sv + - rtl/prim_flop_en.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core b/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core index 866ef847ac2c8..ef179b09b09a4 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core +++ b/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core @@ -14,7 +14,7 @@ filesets: - lowrisc:prim:assert - lowrisc:prim:pad_wrapper_pkg files: - - rtl/prim_xilinx_pad_attr.sv + - rtl/prim_pad_attr.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core b/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core index cba9144762ec8..42e2495071a43 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core +++ b/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core @@ -14,7 +14,7 @@ filesets: - lowrisc:prim:assert - lowrisc:prim:pad_wrapper_pkg files: - - rtl/prim_xilinx_pad_wrapper.sv + - rtl/prim_pad_wrapper.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_xilinx/prim_xilinx_ram_1p.core b/hw/ip/prim_xilinx/prim_xilinx_ram_1p.core index 3ee8918a2bfa7..af5589dc026ff 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_ram_1p.core +++ b/hw/ip/prim_xilinx/prim_xilinx_ram_1p.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:ram_1p" description: "Single port RAM" +virtual: + - lowrisc:prim:ram_1p + filesets: files_rtl: depend: @@ -14,10 +17,9 @@ filesets: # It maps parameters to instructions for how to split memories into # logical groups of bits. See prim_xilinx_default_pkg for an example. - lowrisc:prim_xilinx:prim_xilinx_pkg - - lowrisc:prim_generic:ram_1p - lowrisc:prim:util_memload files: - - rtl/prim_xilinx_ram_1p.sv + - rtl/prim_ram_1p.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_xilinx/prim_xilinx_xnor2.core b/hw/ip/prim_xilinx/prim_xilinx_xnor2.core index 41cad7e91649b..65519b9747a9f 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_xnor2.core +++ b/hw/ip/prim_xilinx/prim_xilinx_xnor2.core @@ -8,7 +8,7 @@ description: "Xilinx 2-input xnor" filesets: files_rtl: files: - - rtl/prim_xilinx_xnor2.sv + - rtl/prim_xnor2.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_xilinx/prim_xilinx_xor2.core b/hw/ip/prim_xilinx/prim_xilinx_xor2.core index e46943e84115a..09b321f9d585f 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_xor2.core +++ b/hw/ip/prim_xilinx/prim_xilinx_xor2.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_xilinx_xor2.sv + - rtl/prim_xor2.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_and2.sv b/hw/ip/prim_xilinx/rtl/prim_and2.sv similarity index 100% rename from hw/ip/prim_xilinx/rtl/prim_xilinx_and2.sv rename to hw/ip/prim_xilinx/rtl/prim_and2.sv diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_buf.sv b/hw/ip/prim_xilinx/rtl/prim_buf.sv similarity index 100% rename from hw/ip/prim_xilinx/rtl/prim_xilinx_buf.sv rename to hw/ip/prim_xilinx/rtl/prim_buf.sv diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv b/hw/ip/prim_xilinx/rtl/prim_clock_buf.sv similarity index 100% rename from hw/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv rename to hw/ip/prim_xilinx/rtl/prim_clock_buf.sv diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv b/hw/ip/prim_xilinx/rtl/prim_clock_gating.sv similarity index 100% rename from hw/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv rename to hw/ip/prim_xilinx/rtl/prim_clock_gating.sv diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv b/hw/ip/prim_xilinx/rtl/prim_clock_mux2.sv similarity index 100% rename from hw/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv rename to hw/ip/prim_xilinx/rtl/prim_clock_mux2.sv diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv b/hw/ip/prim_xilinx/rtl/prim_flop.sv similarity index 100% rename from hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv rename to hw/ip/prim_xilinx/rtl/prim_flop.sv diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv b/hw/ip/prim_xilinx/rtl/prim_flop_en.sv similarity index 100% rename from hw/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv rename to hw/ip/prim_xilinx/rtl/prim_flop_en.sv diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv b/hw/ip/prim_xilinx/rtl/prim_pad_attr.sv similarity index 100% rename from hw/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv rename to hw/ip/prim_xilinx/rtl/prim_pad_attr.sv diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv b/hw/ip/prim_xilinx/rtl/prim_pad_wrapper.sv similarity index 100% rename from hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv rename to hw/ip/prim_xilinx/rtl/prim_pad_wrapper.sv diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_ram_1p.sv b/hw/ip/prim_xilinx/rtl/prim_ram_1p.sv similarity index 60% rename from hw/ip/prim_xilinx/rtl/prim_xilinx_ram_1p.sv rename to hw/ip/prim_xilinx/rtl/prim_ram_1p.sv index 582fa2a1f239b..46848cea756f9 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_ram_1p.sv +++ b/hw/ip/prim_xilinx/rtl/prim_ram_1p.sv @@ -6,7 +6,7 @@ `include "prim_assert.sv" -module prim_xilinx_ram_1p import prim_ram_1p_pkg::*; #( +module prim_ram_1p import prim_ram_1p_pkg::*; #( parameter int Width = 32, // bit parameter int Depth = 128, parameter int DataBitsPerMask = 1, // Number of data bits per bit of write mask @@ -27,29 +27,55 @@ module prim_xilinx_ram_1p import prim_ram_1p_pkg::*; #( localparam int PrimMaxWidth = prim_xilinx_pkg::get_ram_max_width(Width, Depth); + logic unused_cfg_i; + assign unused_cfg_i = ^cfg_i; + if (PrimMaxWidth <= 0) begin : gen_generic - prim_generic_ram_1p #( - .Width(Width), - .Depth(Depth), - .DataBitsPerMask(DataBitsPerMask), - .MemInitFile(MemInitFile) - ) u_ram_1p ( - .* - ); + // Width of internal write mask. Note wmask_i input into the module is always assumed + // to be the full bit mask + localparam int MaskWidth = Width / DataBitsPerMask; + + logic [Width-1:0] mem [Depth]; + logic [MaskWidth-1:0] wmask; + + for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask + assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask]; + + // Ensure that all mask bits within a group have the same value for a write + `ASSERT(MaskCheck_A, req_i && write_i |-> + wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0}, + clk_i, '0) + end + + // using always instead of always_ff to avoid 'ICPD - illegal combination of drivers' error + // thrown when using $readmemh system task to backdoor load an image + always @(posedge clk_i) begin + if (req_i) begin + if (write_i) begin + for (int i=0; i < MaskWidth; i = i + 1) begin + if (wmask[i]) begin + mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <= + wdata_i[i*DataBitsPerMask +: DataBitsPerMask]; + end + end + end else begin + rdata_o <= mem[addr_i]; + end + end + end + + `include "prim_util_memload.svh" end else begin : gen_xpm logic wr_en; assign wr_en = write_i & wmask_i[0]; - logic unused_cfg_i; - assign unused_cfg_i = cfg_i; - for (genvar k = 0; k < Width; k = k + PrimMaxWidth) begin : gen_split localparam int PrimWidth = ((Width - k) > PrimMaxWidth) ? PrimMaxWidth : Width - k; localparam string PrimMemoryInitFile = (MemInitFile != "") ? MemInitFile : "none"; xpm_memory_spram #( .ADDR_WIDTH_A(Aw), - .BYTE_WRITE_WIDTH_A(PrimWidth), // Masks are not supported + .BYTE_WRITE_WIDTH_A(PrimWidth), // Masks are not supported at this time .MEMORY_INIT_FILE(PrimMemoryInitFile), .MEMORY_SIZE(Depth * PrimWidth), .READ_DATA_WIDTH_A(PrimWidth), diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_xnor2.sv b/hw/ip/prim_xilinx/rtl/prim_xnor2.sv similarity index 94% rename from hw/ip/prim_xilinx/rtl/prim_xilinx_xnor2.sv rename to hw/ip/prim_xilinx/rtl/prim_xnor2.sv index 4ad7a71972934..659369adbffbf 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_xnor2.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xnor2.sv @@ -6,7 +6,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_xnor2 #( +module prim_xnor2 #( parameter int Width = 1 ) ( input [Width-1:0] in0_i, diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv b/hw/ip/prim_xilinx/rtl/prim_xor2.sv similarity index 100% rename from hw/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv rename to hw/ip/prim_xilinx/rtl/prim_xor2.sv diff --git a/hw/ip/prim_xilinx_ultrascale/lint/prim_xilinx_ultrascale_clock_mux2.vlt b/hw/ip/prim_xilinx_ultrascale/lint/prim_xilinx_ultrascale_clock_mux2.vlt deleted file mode 100644 index b8340b20851c2..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/lint/prim_xilinx_ultrascale_clock_mux2.vlt +++ /dev/null @@ -1,4 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// diff --git a/hw/ip/prim_xilinx_ultrascale/lint/prim_xilinx_ultrascale_clock_mux2.waiver b/hw/ip/prim_xilinx_ultrascale/lint/prim_xilinx_ultrascale_clock_mux2.waiver deleted file mode 100644 index 1e11afb4e8312..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/lint/prim_xilinx_ultrascale_clock_mux2.waiver +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -# diff --git a/hw/ip/prim_xilinx_ultrascale/lint/prim_xilinx_ultrascale_pad_wrapper.waiver b/hw/ip/prim_xilinx_ultrascale/lint/prim_xilinx_ultrascale_pad_wrapper.waiver index 198eeeace1f7f..05764f141f796 100644 --- a/hw/ip/prim_xilinx_ultrascale/lint/prim_xilinx_ultrascale_pad_wrapper.waiver +++ b/hw/ip/prim_xilinx_ultrascale/lint/prim_xilinx_ultrascale_pad_wrapper.waiver @@ -5,8 +5,8 @@ # waiver file for prim_xilinx_pad_wrapper # note that this code is NOT synthesizable and meant for sim only waive -rules TRI_DRIVER -regexp {'inout_io' is driven by a tristate driver} \ - -location {prim_xilinx_pad_wrapper.sv} \ + -location {prim_pad_wrapper.sv} \ -comment "This is a bidirectional pad inout." waive -rules INPUT_NOT_READ -regexp {Input port 'attr\_i\[.:2\]' is not read from} \ - -location {prim_xilinx_pad_wrapper.sv} \ + -location {prim_pad_wrapper.sv} \ -comment "Some IO attributes may not be implemented." diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale.core index 471e14f974c06..64714e9a26fa0 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale.core @@ -9,26 +9,26 @@ description: "Xilinx Ultrascale prim library" filesets: files_rtl: depend: - - lowrisc:prim_xilinx_ultrascale:and2 - - lowrisc:prim_xilinx_ultrascale:buf + - lowrisc:prim_xilinx:and2 + - lowrisc:prim_xilinx:buf - lowrisc:prim_xilinx_ultrascale:clock_buf - lowrisc:prim_xilinx_ultrascale:clock_div - lowrisc:prim_xilinx_ultrascale:clock_gating - lowrisc:prim_xilinx_ultrascale:clock_inv - - lowrisc:prim_xilinx_ultrascale:clock_mux2 + - lowrisc:prim_xilinx:clock_mux2 - lowrisc:prim_generic:flash - - lowrisc:prim_xilinx_ultrascale:flop + - lowrisc:prim_xilinx:flop - lowrisc:prim_generic:flop_2sync - - lowrisc:prim_xilinx_ultrascale:flop_en + - lowrisc:prim_xilinx:flop_en - lowrisc:prim_generic:otp - - lowrisc:prim_xilinx_ultrascale:pad_attr + - lowrisc:prim_xilinx:pad_attr - lowrisc:prim_xilinx_ultrascale:pad_wrapper - - lowrisc:prim_generic:ram_1p + - lowrisc:prim_xilinx:ram_1p - lowrisc:prim_generic:ram_1r1w - lowrisc:prim_generic:ram_2p - lowrisc:prim_generic:rom - - lowrisc:prim_generic:xnor2 - - lowrisc:prim_xilinx_ultrascale:xor2 + - lowrisc:prim_xilinx:xnor2 + - lowrisc:prim_xilinx:xor2 targets: default: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_and2.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_and2.core deleted file mode 100644 index ee2214956f8f7..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_and2.core +++ /dev/null @@ -1,40 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim_xilinx_ultrascale:and2" -description: "Xilinx 2-input and" -virtual: - - lowrisc:prim:and2 - -filesets: - files_rtl: - files: - - rtl/prim_xilinx_ultrascale_and2.sv - file_type: systemVerilogSource - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - files_rtl diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_buf.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_buf.core deleted file mode 100644 index 616e78504f6f8..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_buf.core +++ /dev/null @@ -1,40 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim_xilinx_ultrascale:buf" -description: "buffer" -virtual: - - lowrisc:prim:buf - -filesets: - files_rtl: - files: - - rtl/prim_xilinx_ultrascale_buf.sv - file_type: systemVerilogSource - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - files_rtl diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_buf.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_buf.core index f182ea3d71a18..18eb366e6eac8 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_buf.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_buf.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_xilinx_ultrascale_clock_buf.sv + - rtl/prim_clock_buf.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_div.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_div.core index af7ee41bb1dee..54a47d364e670 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_div.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_div.core @@ -16,7 +16,7 @@ filesets: - lowrisc:prim:clock_inv - lowrisc:prim:clock_buf files: - - rtl/prim_xilinx_ultrascale_clock_div.sv + - rtl/prim_clock_div.sv file_type: systemVerilogSource files_ascentlint_waiver: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_gating.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_gating.core index 26df5f421777c..31090b7ba36e6 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_gating.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_gating.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_xilinx_ultrascale_clock_gating.sv + - rtl/prim_clock_gating.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_inv.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_inv.core index af0561157981f..416e194c5ae8c 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_inv.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_inv.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_xilinx_ultrascale_clock_inv.sv + - rtl/prim_clock_inv.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_mux2.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_mux2.core deleted file mode 100644 index 642464ca36a61..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_mux2.core +++ /dev/null @@ -1,44 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim_xilinx_ultrascale:clock_mux2" -description: "two-input clock multiplexer primitive" -virtual: - - lowrisc:prim:clock_mux2 - -filesets: - files_rtl: - files: - - rtl/prim_xilinx_ultrascale_clock_mux2.sv - file_type: systemVerilogSource - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_xilinx_ultrascale_clock_mux2.vlt - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_xilinx_ultrascale_clock_mux2.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - files_rtl diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop.core deleted file mode 100644 index 2406237e2e7a3..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop.core +++ /dev/null @@ -1,40 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim_xilinx_ultrascale:flop" -description: "Xilinx flop" -virtual: - - lowrisc:prim:flop - -filesets: - files_rtl: - files: - - rtl/prim_xilinx_ultrascale_flop.sv - file_type: systemVerilogSource - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - files_rtl diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop_en.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop_en.core deleted file mode 100644 index 9b0f752c6c030..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop_en.core +++ /dev/null @@ -1,40 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim_xilinx_ultrascale:flop_en" -description: "Xilinx enable flop" -virtual: - - lowrisc:prim:flop_en - -filesets: - files_rtl: - files: - - rtl/prim_xilinx_ultrascale_flop_en.sv - file_type: systemVerilogSource - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - files_rtl diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_attr.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_attr.core deleted file mode 100644 index 6c99f0177a674..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_attr.core +++ /dev/null @@ -1,41 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim_xilinx_ultrascale:pad_attr" -description: "Pad attribute WARL module for Xilinx pads" -virtual: - - lowrisc:prim:pad_attr - -filesets: - files_rtl: - depend: - - lowrisc:prim:assert - - lowrisc:prim:pad_wrapper_pkg - files: - - rtl/prim_xilinx_ultrascale_pad_attr.sv - file_type: systemVerilogSource - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - files_rtl diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_wrapper.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_wrapper.core index 623620aeb1a77..a9e7ecaceff00 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_wrapper.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_wrapper.core @@ -14,7 +14,7 @@ filesets: - lowrisc:prim:assert - lowrisc:prim:pad_wrapper_pkg files: - - rtl/prim_xilinx_ultrascale_pad_wrapper.sv + - rtl/prim_pad_wrapper.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_ram_1p.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_ram_1p.core deleted file mode 100644 index 720fe34c26e52..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_ram_1p.core +++ /dev/null @@ -1,19 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim_xilinx_ultrascale:ram_1p" -description: "Single port RAM" -filesets: - files_rtl: - depend: - - lowrisc:prim_xilinx:ram_1p - files: - - rtl/prim_xilinx_ultrascale_ram_1p.sv - file_type: systemVerilogSource - -targets: - default: - filesets: - - files_rtl diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xnor2.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xnor2.core deleted file mode 100644 index 92db5126ca4ee..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xnor2.core +++ /dev/null @@ -1,37 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim_xilinx_ultrascale:xnor2" -description: "Xilinx 2-input xnor" -filesets: - files_rtl: - files: - - rtl/prim_xilinx_ultrascale_xnor2.sv - file_type: systemVerilogSource - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - files_rtl diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xor2.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xor2.core index 6318ace2a5867..4ebe867d64164 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xor2.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xor2.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: files: - - rtl/prim_xilinx_ultrascale_xor2.sv + - rtl/prim_xor2.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_buf.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_buf.sv similarity index 100% rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_buf.sv rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_buf.sv diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_div.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_div.sv similarity index 100% rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_div.sv rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_div.sv diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_gating.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_gating.sv similarity index 100% rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_gating.sv rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_gating.sv diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_inv.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_inv.sv similarity index 100% rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_inv.sv rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_inv.sv diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_wrapper.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_pad_wrapper.sv similarity index 100% rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_wrapper.sv rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_pad_wrapper.sv diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_and2.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_and2.sv deleted file mode 100644 index 76a0699a018ec..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_and2.sv +++ /dev/null @@ -1,19 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -`include "prim_assert.sv" - -// Prevent Vivado from performing optimizations on/across this module. -(* DONT_TOUCH = "yes" *) -module prim_and2 #( - parameter int Width = 1 -) ( - input [Width-1:0] in0_i, - input [Width-1:0] in1_i, - output logic [Width-1:0] out_o -); - - assign out_o = in0_i & in1_i; - -endmodule diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_buf.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_buf.sv deleted file mode 100644 index dd772bbd12ac5..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_buf.sv +++ /dev/null @@ -1,16 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// Prevent Vivado from performing optimizations on/across this module. -(* DONT_TOUCH = "yes" *) -module prim_buf #( - parameter int Width = 1 -) ( - input [Width-1:0] in_i, - output logic [Width-1:0] out_o -); - - assign out_o = in_i; - -endmodule diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_mux2.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_mux2.sv deleted file mode 100644 index 81066ad40bb14..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_mux2.sv +++ /dev/null @@ -1,36 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -`include "prim_assert.sv" - -module prim_clock_mux2 #( - parameter bit NoFpgaBufG = 1'b0 -) ( - input clk0_i, - input clk1_i, - input sel_i, - output logic clk_o -); - - if (NoFpgaBufG) begin : gen_no_bufg - assign clk_o = (sel_i) ? clk1_i : clk0_i; - end else begin : gen_bufg - // for more info, refer to the Xilinx technology primitives userguide, e.g.: - // ug953-vivado-7series-libraries.pdf - // ug974-vivado-ultrascale-libraries.pdf - BUFGMUX bufgmux_i ( - .S (sel_i), - .I0(clk0_i), - .I1(clk1_i), - .O (clk_o) - ); - end - - // make sure sel is never X (including during reset) - // need to use ##1 as this could break with inverted clocks that - // start with a rising edge at the beginning of the simulation. - `ASSERT(selKnown0, ##1 !$isunknown(sel_i), clk0_i, 0) - `ASSERT(selKnown1, ##1 !$isunknown(sel_i), clk1_i, 0) - -endmodule : prim_clock_mux2 diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop.sv deleted file mode 100644 index 04c8962e5c17f..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop.sv +++ /dev/null @@ -1,27 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -`include "prim_assert.sv" - -// Prevent Vivado from performing optimizations on/across this module. -(* DONT_TOUCH = "yes" *) -module prim_flop #( - parameter int Width = 1, - parameter logic [Width-1:0] ResetValue = 0 -) ( - input clk_i, - input rst_ni, - input [Width-1:0] d_i, - output logic [Width-1:0] q_o -); - - always_ff @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - q_o <= ResetValue; - end else begin - q_o <= d_i; - end - end - -endmodule diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop_en.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop_en.sv deleted file mode 100644 index bc95d39e5c758..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop_en.sv +++ /dev/null @@ -1,30 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -`include "prim_assert.sv" - -// Prevent Vivado from performing optimizations on/across this module. -(* DONT_TOUCH = "yes" *) -module prim_flop_en #( - parameter int Width = 1, - // This parmaeter does nothing for prim_xilinx - parameter bit EnSecBuf = 0, - parameter logic [Width-1:0] ResetValue = 0 -) ( - input clk_i, - input rst_ni, - input en_i, - input [Width-1:0] d_i, - output logic [Width-1:0] q_o -); - - always_ff @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - q_o <= ResetValue; - end else if (en_i) begin - q_o <= d_i; - end - end - -endmodule diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_attr.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_attr.sv deleted file mode 100644 index 5955d72b18315..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_attr.sv +++ /dev/null @@ -1,59 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// - -`include "prim_assert.sv" - -module prim_pad_attr - import prim_pad_wrapper_pkg::*; -#( - // This parameter is ignored in this Xilinx variant. - parameter pad_type_e PadType = BidirStd -) ( - output pad_attr_t attr_warl_o -); - - // Currently supported pad attributes of the Xilinx pad library. - // - // Input-only: - // - // - inversion - // - input disable - // - // Bidirectional: - // - // - inversion - // - virtual open drain - // - input disable - // - if (PadType == InputStd) begin : gen_input_only_warl - always_comb begin : p_attr - attr_warl_o = '0; - attr_warl_o.invert = 1'b1; - attr_warl_o.input_disable = 1'b1; - end - end else if (PadType == BidirStd || - PadType == BidirTol || - PadType == BidirOd) begin : gen_bidir_warl - always_comb begin : p_attr - attr_warl_o = '0; - attr_warl_o.invert = 1'b1; - attr_warl_o.virt_od_en = 1'b1; - attr_warl_o.input_disable = 1'b1; - end - end else if (PadType == AnalogIn0) begin : gen_analog0_warl - // The analog pad type is basically just a feedthrough, - // and hence only supports input disable. - always_comb begin : p_attr - attr_warl_o = '0; - attr_warl_o.input_disable = 1'b1; - end - end else begin : gen_invalid_config - // this should throw link warnings in elaboration - assert_static_in_generate_config_not_available - assert_static_in_generate_config_not_available(); - end - - -endmodule : prim_pad_attr diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_ram_1p.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_ram_1p.sv deleted file mode 100644 index 741a51ebc1fb5..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_ram_1p.sv +++ /dev/null @@ -1,35 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Synchronous single-port SRAM model - -`include "prim_assert.sv" - -module prim_xilinx_ultrascale_ram_1p import prim_ram_1p_pkg::*; #( - parameter int Width = 32, // bit - parameter int Depth = 128, - parameter int DataBitsPerMask = 1, // Number of data bits per bit of write mask - parameter MemInitFile = "", // VMEM file to initialize the memory with - - localparam int Aw = $clog2(Depth) // derived parameter -) ( - input logic clk_i, - - input logic req_i, - input logic write_i, - input logic [Aw-1:0] addr_i, - input logic [Width-1:0] wdata_i, - input logic [Width-1:0] wmask_i, - output logic [Width-1:0] rdata_o, // Read data. Data is returned one cycle after req_i is high. - input ram_1p_cfg_t cfg_i -); - - prim_xilinx_ram_1p #( - .Width(Width), - .Depth(Depth), - .DataBitsPerMask(DataBitsPerMask), - .MemInitFile(MemInitFile) - ) u_inst (.*); - -endmodule diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xnor2.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xnor2.sv deleted file mode 100644 index 11dcadc576303..0000000000000 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xnor2.sv +++ /dev/null @@ -1,19 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -`include "prim_assert.sv" - -// Prevent Vivado from performing optimizations on/across this module. -(* DONT_TOUCH = "yes" *) -module prim_xilinx_ultrascale_xnor2 #( - parameter int Width = 1 -) ( - input [Width-1:0] in0_i, - input [Width-1:0] in1_i, - output logic [Width-1:0] out_o -); - - assign out_o = ~(in0_i ^ in1_i); - -endmodule diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xor2.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xor2.sv similarity index 100% rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xor2.sv rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_xor2.sv diff --git a/util/verible-format-allowlist.txt b/util/verible-format-allowlist.txt index 0f971e66b751b..67558494cbd7b 100644 --- a/util/verible-format-allowlist.txt +++ b/util/verible-format-allowlist.txt @@ -140,19 +140,19 @@ hw/ip/prim/rtl/prim_secded_hamming_22_16_enc.sv hw/ip/prim/rtl/prim_secded_hamming_39_32_enc.sv hw/ip/prim/rtl/prim_secded_hamming_72_64_enc.sv hw/ip/prim/rtl/prim_util_pkg.sv -hw/ip/prim_generic/rtl/prim_generic_buf.sv -hw/ip/prim_generic/rtl/prim_generic_flop.sv -hw/ip/prim_generic/rtl/prim_generic_flop_2sync.sv -hw/ip/prim_generic/rtl/prim_generic_flop_en.sv -hw/ip/prim_generic/rtl/prim_generic_xor2.sv -hw/ip/prim_xilinx/rtl/prim_xilinx_buf.sv -hw/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv -hw/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv -hw/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv -hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv -hw/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv -hw/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv -hw/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv +hw/ip/prim_generic/rtl/prim_buf.sv +hw/ip/prim_generic/rtl/prim_flop.sv +hw/ip/prim_generic/rtl/prim_flop_2sync.sv +hw/ip/prim_generic/rtl/prim_flop_en.sv +hw/ip/prim_generic/rtl/prim_xor2.sv +hw/ip/prim_xilinx/rtl/prim_buf.sv +hw/ip/prim_xilinx/rtl/prim_clock_buf.sv +hw/ip/prim_xilinx/rtl/prim_clock_gating.sv +hw/ip/prim_xilinx/rtl/prim_clock_mux2.sv +hw/ip/prim_xilinx/rtl/prim_flop.sv +hw/ip/prim_xilinx/rtl/prim_flop_en.sv +hw/ip/prim_xilinx/rtl/prim_pad_attr.sv +hw/ip/prim_xilinx/rtl/prim_xor2.sv hw/ip/pwm/dv/env/pwm_env_cov.sv hw/ip/pwm/dv/env/pwm_env_pkg.sv hw/ip/pwm/dv/env/pwm_virtual_sequencer.sv From 3335982425aef7b1c94c08980f950cf597129e6d Mon Sep 17 00:00:00 2001 From: Alexander Williams Date: Mon, 9 Dec 2024 21:55:51 +0000 Subject: [PATCH 08/24] [otbn,sim] Adjust Verilator public module config for prims Adjust the Verilator public module configuration for the new prim hierarchy. All prim implementations now have the same module name for the same specific prim ABI, so the config targeting the prim_generic_flop module needed to change to prim_flop. Signed-off-by: Alexander Williams --- hw/ip/otbn/dv/verilator/otbn_top_sim_waivers.vlt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ip/otbn/dv/verilator/otbn_top_sim_waivers.vlt b/hw/ip/otbn/dv/verilator/otbn_top_sim_waivers.vlt index 350760a0a2752..f700ad7361606 100644 --- a/hw/ip/otbn/dv/verilator/otbn_top_sim_waivers.vlt +++ b/hw/ip/otbn/dv/verilator/otbn_top_sim_waivers.vlt @@ -20,7 +20,7 @@ public -module "otbn_loop_controller" -var "loop_stack_rd_idx" public -module "otbn_loop_controller" -var "prefetch_loop_iterations_o" public -module "prim_count" -var "max_val" public -module "prim_count" -var "down_cnt" -public -module "prim_generic_flop" -var "d_i" +public -module "prim_flop" -var "d_i" // Mark the "model_handle" variable in the core model as public. We // use this to pass the information from the ELF file to the ISS on From b1f6e76bc817fe2645ddaf567aa98f846731d883 Mon Sep 17 00:00:00 2001 From: Alexander Williams Date: Mon, 9 Dec 2024 20:48:25 -0800 Subject: [PATCH 09/24] [flash_ctrl] Fix lint error for size member Signed-off-by: Alexander Williams --- hw/ip_templates/flash_ctrl/rtl/flash_ctrl_pkg.sv.tpl | 2 +- hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_pkg.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ip_templates/flash_ctrl/rtl/flash_ctrl_pkg.sv.tpl b/hw/ip_templates/flash_ctrl/rtl/flash_ctrl_pkg.sv.tpl index c34d8ca644836..176ee24b9bd1c 100644 --- a/hw/ip_templates/flash_ctrl/rtl/flash_ctrl_pkg.sv.tpl +++ b/hw/ip_templates/flash_ctrl/rtl/flash_ctrl_pkg.sv.tpl @@ -293,7 +293,7 @@ package flash_ctrl_pkg; ecc_en: MuBi4True, he_en: MuBi4True, // HW assumes high endurance base: '0, - size: NumBanks * PagesPerBank + size: 10'(NumBanks * PagesPerBank) } } }; diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_pkg.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_pkg.sv index 9486caf2e5b83..b02d183bed9dc 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_pkg.sv @@ -293,7 +293,7 @@ package flash_ctrl_pkg; ecc_en: MuBi4True, he_en: MuBi4True, // HW assumes high endurance base: '0, - size: NumBanks * PagesPerBank + size: 10'(NumBanks * PagesPerBank) } } }; From 63a59a9d17639529c262def6c56c30bb836373c4 Mon Sep 17 00:00:00 2001 From: Hugo McNally Date: Sat, 30 Nov 2024 19:37:07 +0000 Subject: [PATCH 10/24] [ci] Temporary measure to fix container strangeness Signed-off-by: Hugo McNally --- util/build_consts.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/build_consts.sh b/util/build_consts.sh index 5550717f441ae..ba74a22aa3b0a 100644 --- a/util/build_consts.sh +++ b/util/build_consts.sh @@ -47,3 +47,6 @@ export OBJ_DIR readonly BIN_DIR="$BUILD_ROOT/build-bin" export BIN_DIR export PYTHONPATH="${REPO_TOP}" + +# TODO: add this in the private runner instead +export PATH=$HOME/.local/bin:$PATH From 1e24db47f2f94d1672c509440a24b3d64030c94b Mon Sep 17 00:00:00 2001 From: Hugo McNally Date: Wed, 4 Dec 2024 16:28:29 +0000 Subject: [PATCH 11/24] [dv/hmac] Adjust paths for fusesoc update Signed-off-by: Hugo McNally --- hw/ip/hmac/dv/hmac_sim_cfg.hjson | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ip/hmac/dv/hmac_sim_cfg.hjson b/hw/ip/hmac/dv/hmac_sim_cfg.hjson index 527ddef469cee..670f08611843c 100644 --- a/hw/ip/hmac/dv/hmac_sim_cfg.hjson +++ b/hw/ip/hmac/dv/hmac_sim_cfg.hjson @@ -108,7 +108,7 @@ name: hmac_test_sha384_vectors uvm_test_seq: hmac_test_vectors_sha_vseq // Increase timeout for all test iterations to pass - run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384"] + run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384"] reseed: 5 } @@ -116,7 +116,7 @@ name: hmac_test_sha512_vectors uvm_test_seq: hmac_test_vectors_sha_vseq // Increase timeout for all test iterations to pass - run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512"] + run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512"] reseed: 5 } From b97984ae416068382b72f4e010de39ba021233e9 Mon Sep 17 00:00:00 2001 From: Hugo McNally Date: Mon, 2 Dec 2024 07:29:33 +0000 Subject: [PATCH 12/24] [fpga] Adjust output paths for new fusesoc Signed-off-by: Hugo McNally --- ci/scripts/build-bitstream-vivado.sh | 7 +++++-- util/fpga/splice_rom.sh | 7 +++++-- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/ci/scripts/build-bitstream-vivado.sh b/ci/scripts/build-bitstream-vivado.sh index 29e039b712eb3..5a28aa75b3f97 100755 --- a/ci/scripts/build-bitstream-vivado.sh +++ b/ci/scripts/build-bitstream-vivado.sh @@ -102,8 +102,11 @@ fusesoc --verbose --cores-root=. \ --BootRomInitFile="$BOOTROM_VMEM" \ $OTP_ARG -BITSTREAM_FNAME="lowrisc_systems_chip_${FLAVOUR}_${TARGET}_0.1.bit" -BITSTREAM_PATH="$OBJ_DIR/hw/synth-vivado/$BITSTREAM_FNAME" + +VLNV_PATH="lowrisc_systems_chip_${FLAVOUR}_${TARGET}_0.1" + +BITSTREAM_FNAME="${VLNV_PATH}.bit" +BITSTREAM_PATH="$OBJ_DIR/hw/${VLNV_PATH}/synth-vivado/${BITSTREAM_FNAME}" cp "$BITSTREAM_PATH" "$TOPLEVEL_BIN_DIR" cp "$OBJ_DIR/hw/synth-vivado/memories.mmi" "$TOPLEVEL_BIN_DIR" diff --git a/util/fpga/splice_rom.sh b/util/fpga/splice_rom.sh index 166a4bf96719b..41d0fd79d5104 100755 --- a/util/fpga/splice_rom.sh +++ b/util/fpga/splice_rom.sh @@ -97,8 +97,11 @@ TARGET_FILE_EXT=".scr.39.vmem" TARGET="${BIN_DIR}/${TARGET_PREFIX}_fpga_${TARGET_BOARD}" TARGET_PATH="${TARGET}${TARGET_FILE_EXT}" -FPGA_BIN_DIR="${BIN_DIR}/hw/top_${TARGET_TOP}" -FPGA_BIT_NAME="lowrisc_systems_chip_${TARGET_TOP}_${TARGET_BOARD}_0.1" + +VLNV_PATH="lowrisc_systems_chip_${TARGET_TOP}_${TARGET_BOARD}_0.1" + +FPGA_BIN_DIR="${BIN_DIR}/hw/${VLNV_PATH}/synth-vivado" +FPGA_BIT_NAME="$VLNV_PATH" # Make sure all inputs are available. if [[ ! -f "${TARGET_PATH}" ]]; then From 74ece7bbc6f2d660e05af45f90ad49e24e05ec58 Mon Sep 17 00:00:00 2001 From: Hugo McNally Date: Wed, 4 Dec 2024 18:03:32 +0000 Subject: [PATCH 13/24] [dv] Added concrete prim implementation to some ip cores Signed-off-by: Hugo McNally --- hw/ip/gpio/dv/gpio_sim.core | 1 + hw/ip/spi_device/dv/spi_device_sim.core | 1 + hw/ip_templates/clkmgr/dv/clkmgr_sim.core | 1 + hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim.core | 1 + hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim.core | 1 + 5 files changed, 5 insertions(+) diff --git a/hw/ip/gpio/dv/gpio_sim.core b/hw/ip/gpio/dv/gpio_sim.core index a33d0dc74f66e..b9deda1f28bf7 100644 --- a/hw/ip/gpio/dv/gpio_sim.core +++ b/hw/ip/gpio/dv/gpio_sim.core @@ -13,6 +13,7 @@ filesets: depend: - lowrisc:dv:gpio_test - lowrisc:dv:gpio_sva + - lowrisc:prim_generic:all files: - tb/tb.sv file_type: systemVerilogSource diff --git a/hw/ip/spi_device/dv/spi_device_sim.core b/hw/ip/spi_device/dv/spi_device_sim.core index 411d0a93c058b..5cb510851f3e4 100644 --- a/hw/ip/spi_device/dv/spi_device_sim.core +++ b/hw/ip/spi_device/dv/spi_device_sim.core @@ -13,6 +13,7 @@ filesets: depend: - lowrisc:dv:spi_device_test - lowrisc:dv:spi_device_sva + - lowrisc:prim_generic:all files: - tb/tb.sv file_type: systemVerilogSource diff --git a/hw/ip_templates/clkmgr/dv/clkmgr_sim.core b/hw/ip_templates/clkmgr/dv/clkmgr_sim.core index 05b79c321b7d6..d588b2a119651 100644 --- a/hw/ip_templates/clkmgr/dv/clkmgr_sim.core +++ b/hw/ip_templates/clkmgr/dv/clkmgr_sim.core @@ -13,6 +13,7 @@ filesets: depend: - lowrisc:dv:clkmgr_test - lowrisc:dv:clkmgr_sva + - lowrisc:prim_generic:all files: - tb.sv - cov/clkmgr_cov_bind.sv diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim.core b/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim.core index 05b79c321b7d6..d588b2a119651 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim.core +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim.core @@ -13,6 +13,7 @@ filesets: depend: - lowrisc:dv:clkmgr_test - lowrisc:dv:clkmgr_sva + - lowrisc:prim_generic:all files: - tb.sv - cov/clkmgr_cov_bind.sv diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim.core b/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim.core index 05b79c321b7d6..d588b2a119651 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim.core +++ b/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim.core @@ -13,6 +13,7 @@ filesets: depend: - lowrisc:dv:clkmgr_test - lowrisc:dv:clkmgr_sva + - lowrisc:prim_generic:all files: - tb.sv - cov/clkmgr_cov_bind.sv From 9f4e67359fdaef6350b9a01e5f4117db1b09ead7 Mon Sep 17 00:00:00 2001 From: Hugo McNally Date: Tue, 10 Dec 2024 06:02:11 +0000 Subject: [PATCH 14/24] [dv] Added concrete prim implementation to all simulation top levels Signed-off-by: Hugo McNally --- hw/dv/sv/tl_agent/dv/tl_agent_sim.core | 1 + hw/ip/adc_ctrl/dv/adc_ctrl_sim.core | 1 + hw/ip/aes/dv/aes_sim.core | 1 + hw/ip/aon_timer/dv/aon_timer_sim.core | 1 + hw/ip/ascon/pre_dv/ascon_tb/ascon_sim.core | 1 + hw/ip/csrng/dv/csrng_sim.core | 1 + hw/ip/dma/dv/dma_sim.core | 1 + hw/ip/edn/dv/edn_sim.core | 1 + hw/ip/entropy_src/dv/entropy_src_sim.core | 1 + hw/ip/hmac/dv/hmac_sim.core | 1 + hw/ip/i2c/dv/i2c_sim.core | 1 + hw/ip/keymgr/dv/keymgr_sim.core | 1 + hw/ip/keymgr_dpe/dv/keymgr_dpe_sim.core | 1 + hw/ip/kmac/dv/kmac_sim.core | 1 + hw/ip/lc_ctrl/dv/lc_ctrl_sim.core | 1 + hw/ip/mbx/dv/mbx_sim.core | 1 + hw/ip/otbn/dv/uvm/otbn_sim.core | 1 + hw/ip/otbn/dv/verilator/otbn_top_sim.core | 1 + hw/ip/otp_ctrl/dv/otp_ctrl_sim.core | 1 + hw/ip/pattgen/dv/pattgen_sim.core | 1 + hw/ip/prim/dv/prim_alert/prim_alert_sim.core | 1 + hw/ip/prim/dv/prim_esc/prim_esc_sim.core | 1 + hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core | 1 + .../dv/prim_present/prim_present_sim.core | 1 + .../prim/dv/prim_prince/prim_prince_sim.core | 1 + .../pre_dv/prim_crc32/prim_crc32_sim.core | 1 + .../prim_flop_2sync/prim_flop_2sync_sim.core | 1 + hw/ip/pwm/dv/pwm_sim.core | 1 + hw/ip/rom_ctrl/dv/rom_ctrl_sim.core | 1 + hw/ip/rv_dm/dv/rv_dm_sim.core | 1 + hw/ip/rv_timer/dv/rv_timer_sim.core | 1 + hw/ip/spi_device/pre_dv/spi_tpm_sim.core | 1 + hw/ip/spi_host/dv/spi_host_sim.core | 1 + hw/ip/sram_ctrl/dv/sram_ctrl_sim.core | 1 + hw/ip/sysrst_ctrl/dv/sysrst_ctrl_sim.core | 1 + hw/ip/trial1/dv/trial1_sim.core | 1 + hw/ip/uart/dv/uart_sim.core | 1 + hw/ip/usbdev/dv/usbdev_sim.core | 1 + .../flash_ctrl/dv/flash_ctrl_sim.core | 1 + hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core | 1 + .../rstmgr_cnsty_chk_sim.core | 1 + hw/ip_templates/rstmgr/dv/rstmgr_sim.core | 1 + hw/top_darjeeling/ip/ast/lint/ast.waiver | 26 +++++++++---------- .../alert_handler/dv/alert_handler_sim.core | 12 +-------- .../dv/env/alert_handler_env.core | 13 +++++++++- .../alert_handler/dv/tb/alert_handler_tb.core | 4 +-- .../dv/tests/alert_handler_test.core | 4 +-- .../ip_autogen/clkmgr/dv/env/clkmgr_env.core | 1 + .../ip_autogen/pwrmgr/dv/env/pwrmgr_env.core | 1 + .../ip_autogen/pwrmgr/dv/pwrmgr_sim.core | 1 + .../ip_autogen/rstmgr/dv/env/rstmgr_env.core | 1 + .../rstmgr_cnsty_chk_sim.core | 1 + .../ip_autogen/rstmgr/dv/rstmgr_sim.core | 1 + hw/top_earlgrey/dv/chip_sim.core | 2 ++ hw/top_earlgrey/dv/verilator/chip_sim.core | 1 + .../flash_ctrl/dv/flash_ctrl_sim.core | 1 + .../ip_autogen/pwrmgr/dv/pwrmgr_sim.core | 1 + .../rstmgr_cnsty_chk_sim.core | 1 + .../ip_autogen/rstmgr/dv/rstmgr_sim.core | 1 + .../dv/uvm/icache/dv/ibex_icache_sim.core | 1 + ...e-prim-implementation-to-all-simulat.patch | 26 +++++++++++++++++++ 61 files changed, 112 insertions(+), 29 deletions(-) create mode 100644 hw/vendor/patches/lowrisc_ibex/dv/0001-dv-Added-concrete-prim-implementation-to-all-simulat.patch diff --git a/hw/dv/sv/tl_agent/dv/tl_agent_sim.core b/hw/dv/sv/tl_agent/dv/tl_agent_sim.core index 34f78b812a9fc..8f724263e106d 100644 --- a/hw/dv/sv/tl_agent/dv/tl_agent_sim.core +++ b/hw/dv/sv/tl_agent/dv/tl_agent_sim.core @@ -8,6 +8,7 @@ filesets: files_dv: depend: - lowrisc:dv:tl_agent_test + - lowrisc:prim_generic:all files: - tb/tb.sv file_type: systemVerilogSource diff --git a/hw/ip/adc_ctrl/dv/adc_ctrl_sim.core b/hw/ip/adc_ctrl/dv/adc_ctrl_sim.core index ead0c01bbe801..59d2416149d92 100644 --- a/hw/ip/adc_ctrl/dv/adc_ctrl_sim.core +++ b/hw/ip/adc_ctrl/dv/adc_ctrl_sim.core @@ -14,6 +14,7 @@ filesets: - lowrisc:dv:adc_ctrl_test - lowrisc:dv:adc_ctrl_sva - lowrisc:dv:adc_ctrl_cov + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip/aes/dv/aes_sim.core b/hw/ip/aes/dv/aes_sim.core index e7d74e76c24ff..3578339cca174 100644 --- a/hw/ip/aes/dv/aes_sim.core +++ b/hw/ip/aes/dv/aes_sim.core @@ -15,6 +15,7 @@ filesets: - lowrisc:dv:aes_sva - lowrisc:dv:aes_err_injection - lowrisc:dv:aes_cov + - lowrisc:prim_generic:all files: - tb/tb.sv file_type: systemVerilogSource diff --git a/hw/ip/aon_timer/dv/aon_timer_sim.core b/hw/ip/aon_timer/dv/aon_timer_sim.core index 059a4280b5047..c219919bc6bd7 100644 --- a/hw/ip/aon_timer/dv/aon_timer_sim.core +++ b/hw/ip/aon_timer/dv/aon_timer_sim.core @@ -13,6 +13,7 @@ filesets: depend: - lowrisc:dv:aon_timer_test - lowrisc:dv:aon_timer_sva + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip/ascon/pre_dv/ascon_tb/ascon_sim.core b/hw/ip/ascon/pre_dv/ascon_tb/ascon_sim.core index aa1d0dcb49ca2..66c16fff0099e 100644 --- a/hw/ip/ascon/pre_dv/ascon_tb/ascon_sim.core +++ b/hw/ip/ascon/pre_dv/ascon_tb/ascon_sim.core @@ -17,6 +17,7 @@ filesets: files_dv_verilator: depend: - lowrisc:dv_verilator:simutil_verilator + - lowrisc:prim_generic:all files: - cpp/ascon_tb.cc file_type: cppSource diff --git a/hw/ip/csrng/dv/csrng_sim.core b/hw/ip/csrng/dv/csrng_sim.core index b1fd2ed41b2a3..bf6a7fe6612e4 100644 --- a/hw/ip/csrng/dv/csrng_sim.core +++ b/hw/ip/csrng/dv/csrng_sim.core @@ -14,6 +14,7 @@ filesets: - lowrisc:dv:csrng_test - lowrisc:dv:csrng_sva - lowrisc:dv:csrng_cov + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip/dma/dv/dma_sim.core b/hw/ip/dma/dv/dma_sim.core index 9b320508ef3b9..38298ff2d987f 100644 --- a/hw/ip/dma/dv/dma_sim.core +++ b/hw/ip/dma/dv/dma_sim.core @@ -14,6 +14,7 @@ filesets: - lowrisc:dv:dma_test - lowrisc:dv:dma_cov - lowrisc:dv:dma_sva + - lowrisc:prim_generic:all files: - tb/tb.sv file_type: systemVerilogSource diff --git a/hw/ip/edn/dv/edn_sim.core b/hw/ip/edn/dv/edn_sim.core index fda3ec12b0db5..98e4ee66efbf9 100644 --- a/hw/ip/edn/dv/edn_sim.core +++ b/hw/ip/edn/dv/edn_sim.core @@ -14,6 +14,7 @@ filesets: - lowrisc:dv:edn_test - lowrisc:dv:edn_sva - lowrisc:dv:edn_cov + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip/entropy_src/dv/entropy_src_sim.core b/hw/ip/entropy_src/dv/entropy_src_sim.core index c4e2387575660..827d38df81663 100644 --- a/hw/ip/entropy_src/dv/entropy_src_sim.core +++ b/hw/ip/entropy_src/dv/entropy_src_sim.core @@ -15,6 +15,7 @@ filesets: - lowrisc:dv:entropy_src_sva - lowrisc:dv:entropy_src_cov - lowrisc:dv:digestpp_dpi:0.1 + - lowrisc:prim_generic:all files: - tb/tb.sv file_type: systemVerilogSource diff --git a/hw/ip/hmac/dv/hmac_sim.core b/hw/ip/hmac/dv/hmac_sim.core index 4f10b907b318c..a0fe09632e133 100644 --- a/hw/ip/hmac/dv/hmac_sim.core +++ b/hw/ip/hmac/dv/hmac_sim.core @@ -13,6 +13,7 @@ filesets: depend: - lowrisc:dv:hmac_test - lowrisc:dv:hmac_sva + - lowrisc:prim_generic:all files: - tb/tb.sv file_type: systemVerilogSource diff --git a/hw/ip/i2c/dv/i2c_sim.core b/hw/ip/i2c/dv/i2c_sim.core index d89e637ed5ab0..b4bca1bc7d135 100644 --- a/hw/ip/i2c/dv/i2c_sim.core +++ b/hw/ip/i2c/dv/i2c_sim.core @@ -13,6 +13,7 @@ filesets: depend: - lowrisc:dv:i2c_test - lowrisc:dv:i2c_sva + - lowrisc:prim_generic:all files: - tb/tb.sv - tb/i2c_port_conv.sv diff --git a/hw/ip/keymgr/dv/keymgr_sim.core b/hw/ip/keymgr/dv/keymgr_sim.core index 8498bf82c324b..21b01250834f2 100644 --- a/hw/ip/keymgr/dv/keymgr_sim.core +++ b/hw/ip/keymgr/dv/keymgr_sim.core @@ -13,6 +13,7 @@ filesets: depend: - lowrisc:dv:keymgr_test - lowrisc:dv:keymgr_sva + - lowrisc:prim_generic:all files: - tb.sv - cov/keymgr_cov_bind.sv diff --git a/hw/ip/keymgr_dpe/dv/keymgr_dpe_sim.core b/hw/ip/keymgr_dpe/dv/keymgr_dpe_sim.core index f21f3ece92bbe..2db15009ccd15 100644 --- a/hw/ip/keymgr_dpe/dv/keymgr_dpe_sim.core +++ b/hw/ip/keymgr_dpe/dv/keymgr_dpe_sim.core @@ -13,6 +13,7 @@ filesets: depend: - lowrisc:dv:keymgr_dpe_test - lowrisc:dv:keymgr_dpe_sva + - lowrisc:prim_generic:all files: - tb.sv - cov/keymgr_dpe_cov_bind.sv diff --git a/hw/ip/kmac/dv/kmac_sim.core b/hw/ip/kmac/dv/kmac_sim.core index 17fbd3d8a8a78..05bfdc296ec3c 100644 --- a/hw/ip/kmac/dv/kmac_sim.core +++ b/hw/ip/kmac/dv/kmac_sim.core @@ -14,6 +14,7 @@ filesets: - lowrisc:dv:kmac_test - lowrisc:dv:kmac_sva - lowrisc:dv:kmac_cov + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip/lc_ctrl/dv/lc_ctrl_sim.core b/hw/ip/lc_ctrl/dv/lc_ctrl_sim.core index 2335f26f20aab..e54c61ce71934 100644 --- a/hw/ip/lc_ctrl/dv/lc_ctrl_sim.core +++ b/hw/ip/lc_ctrl/dv/lc_ctrl_sim.core @@ -15,6 +15,7 @@ filesets: - lowrisc:dv:lc_ctrl_sva - lowrisc:dv:lc_ctrl_cov - lowrisc:tlul:jtag_dtm + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip/mbx/dv/mbx_sim.core b/hw/ip/mbx/dv/mbx_sim.core index 7a6db0723c85f..86277d62cfcd3 100644 --- a/hw/ip/mbx/dv/mbx_sim.core +++ b/hw/ip/mbx/dv/mbx_sim.core @@ -13,6 +13,7 @@ filesets: depend: - lowrisc:dv:mbx_test - lowrisc:dv:mbx_sva + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip/otbn/dv/uvm/otbn_sim.core b/hw/ip/otbn/dv/uvm/otbn_sim.core index 38cdac647579f..b254cff6dd2af 100644 --- a/hw/ip/otbn/dv/uvm/otbn_sim.core +++ b/hw/ip/otbn/dv/uvm/otbn_sim.core @@ -16,6 +16,7 @@ filesets: - lowrisc:dv:otbn_sva - lowrisc:dv:mem_bkdr_util - lowrisc:ip:edn_pkg + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip/otbn/dv/verilator/otbn_top_sim.core b/hw/ip/otbn/dv/verilator/otbn_top_sim.core index a2b192fa5ec89..2f617a7965536 100644 --- a/hw/ip/otbn/dv/verilator/otbn_top_sim.core +++ b/hw/ip/otbn/dv/verilator/otbn_top_sim.core @@ -18,6 +18,7 @@ filesets: - lowrisc:dv:otbn_memutil - lowrisc:dv_verilator:memutil_verilator - lowrisc:dv_verilator:simutil_verilator + - lowrisc:prim_generic:all files: - otbn_top_sim.cc: { file_type: cppSource } - otbn_top_sim.sv: { file_type: systemVerilogSource } diff --git a/hw/ip/otp_ctrl/dv/otp_ctrl_sim.core b/hw/ip/otp_ctrl/dv/otp_ctrl_sim.core index a3a0c7ba5fb66..2af5f4c5c096a 100644 --- a/hw/ip/otp_ctrl/dv/otp_ctrl_sim.core +++ b/hw/ip/otp_ctrl/dv/otp_ctrl_sim.core @@ -15,6 +15,7 @@ filesets: - lowrisc:dv:otp_ctrl_test - lowrisc:dv:otp_ctrl_sva - lowrisc:dv:otp_ctrl_cov + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip/pattgen/dv/pattgen_sim.core b/hw/ip/pattgen/dv/pattgen_sim.core index 94d6839575f0e..b989feafe9791 100644 --- a/hw/ip/pattgen/dv/pattgen_sim.core +++ b/hw/ip/pattgen/dv/pattgen_sim.core @@ -14,6 +14,7 @@ filesets: - lowrisc:dv:pattgen_test - lowrisc:dv:pattgen_sva - lowrisc:dv:pattgen_cov + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip/prim/dv/prim_alert/prim_alert_sim.core b/hw/ip/prim/dv/prim_alert/prim_alert_sim.core index b9dcc28e24993..4d23cafa6f6a9 100644 --- a/hw/ip/prim/dv/prim_alert/prim_alert_sim.core +++ b/hw/ip/prim/dv/prim_alert/prim_alert_sim.core @@ -15,6 +15,7 @@ filesets: - lowrisc:dv:dv_utils - lowrisc:dv:dv_test_status - lowrisc:dv:common_ifs + - lowrisc:prim_generic:all files: - tb/prim_alert_tb.sv file_type: systemVerilogSource diff --git a/hw/ip/prim/dv/prim_esc/prim_esc_sim.core b/hw/ip/prim/dv/prim_esc/prim_esc_sim.core index 2216ff03b0f7a..8f2f55fc5a8e2 100644 --- a/hw/ip/prim/dv/prim_esc/prim_esc_sim.core +++ b/hw/ip/prim/dv/prim_esc/prim_esc_sim.core @@ -15,6 +15,7 @@ filesets: - lowrisc:dv:dv_utils - lowrisc:dv:dv_test_status - lowrisc:dv:common_ifs + - lowrisc:prim_generic:all files: - tb/prim_esc_tb.sv file_type: systemVerilogSource diff --git a/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core b/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core index 3733ede73be77..0dd798d8990e3 100644 --- a/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core +++ b/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core @@ -15,6 +15,7 @@ filesets: - lowrisc:dv:dv_utils - lowrisc:dv:dv_test_status - lowrisc:dv:common_ifs + - lowrisc:prim_generic:all files: - prim_lfsr_tb.sv file_type: systemVerilogSource diff --git a/hw/ip/prim/dv/prim_present/prim_present_sim.core b/hw/ip/prim/dv/prim_present/prim_present_sim.core index 0755f0a086bf3..dcbd5caa45a15 100644 --- a/hw/ip/prim/dv/prim_present/prim_present_sim.core +++ b/hw/ip/prim/dv/prim_present/prim_present_sim.core @@ -16,6 +16,7 @@ filesets: - lowrisc:dv:dv_macros - lowrisc:dv:dv_test_status - lowrisc:dv:crypto_dpi_present:0.1 + - lowrisc:prim_generic:all files: - tb/prim_present_tb.sv file_type: systemVerilogSource diff --git a/hw/ip/prim/dv/prim_prince/prim_prince_sim.core b/hw/ip/prim/dv/prim_prince/prim_prince_sim.core index 35169eb25050d..d7d06687237ad 100644 --- a/hw/ip/prim/dv/prim_prince/prim_prince_sim.core +++ b/hw/ip/prim/dv/prim_prince/prim_prince_sim.core @@ -17,6 +17,7 @@ filesets: - lowrisc:dv:common_ifs - lowrisc:dv:dv_test_status - lowrisc:dv:crypto_dpi_prince + - lowrisc:prim_generic:all files: - tb/prim_prince_tb.sv file_type: systemVerilogSource diff --git a/hw/ip/prim/pre_dv/prim_crc32/prim_crc32_sim.core b/hw/ip/prim/pre_dv/prim_crc32/prim_crc32_sim.core index 23118823d12d8..92faf7e2791d4 100644 --- a/hw/ip/prim/pre_dv/prim_crc32/prim_crc32_sim.core +++ b/hw/ip/prim/pre_dv/prim_crc32/prim_crc32_sim.core @@ -12,6 +12,7 @@ filesets: files_verilator: depend: - lowrisc:dv_verilator:simutil_verilator + - lowrisc:prim_generic:all files: - prim_crc32_sim.cc: { file_type: cppSource } - prim_crc32_sim.sv: { file_type: systemVerilogSource } diff --git a/hw/ip/prim/pre_dv/prim_flop_2sync/prim_flop_2sync_sim.core b/hw/ip/prim/pre_dv/prim_flop_2sync/prim_flop_2sync_sim.core index a716d774216af..b30895c1072f8 100644 --- a/hw/ip/prim/pre_dv/prim_flop_2sync/prim_flop_2sync_sim.core +++ b/hw/ip/prim/pre_dv/prim_flop_2sync/prim_flop_2sync_sim.core @@ -15,6 +15,7 @@ filesets: - lowrisc:dv:dv_macros - lowrisc:dv:dv_utils - lowrisc:dv:dv_test_status + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip/pwm/dv/pwm_sim.core b/hw/ip/pwm/dv/pwm_sim.core index c7713285a805a..83457ab0b0466 100644 --- a/hw/ip/pwm/dv/pwm_sim.core +++ b/hw/ip/pwm/dv/pwm_sim.core @@ -14,6 +14,7 @@ filesets: depend: - lowrisc:dv:pwm_test - lowrisc:dv:pwm_sva + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip/rom_ctrl/dv/rom_ctrl_sim.core b/hw/ip/rom_ctrl/dv/rom_ctrl_sim.core index 255a2906d0c7e..14eec652747c5 100644 --- a/hw/ip/rom_ctrl/dv/rom_ctrl_sim.core +++ b/hw/ip/rom_ctrl/dv/rom_ctrl_sim.core @@ -15,6 +15,7 @@ filesets: - lowrisc:dv:rom_ctrl_test - lowrisc:dv:rom_ctrl_sva - lowrisc:dv:rom_ctrl_cov + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip/rv_dm/dv/rv_dm_sim.core b/hw/ip/rv_dm/dv/rv_dm_sim.core index ef91a64dcc38e..d466088b95672 100644 --- a/hw/ip/rv_dm/dv/rv_dm_sim.core +++ b/hw/ip/rv_dm/dv/rv_dm_sim.core @@ -14,6 +14,7 @@ filesets: - lowrisc:dv:rv_dm_env - lowrisc:dv:rv_dm_test - lowrisc:dv:rv_dm_sva + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip/rv_timer/dv/rv_timer_sim.core b/hw/ip/rv_timer/dv/rv_timer_sim.core index 0ebed9592f7e9..be593d311faaf 100644 --- a/hw/ip/rv_timer/dv/rv_timer_sim.core +++ b/hw/ip/rv_timer/dv/rv_timer_sim.core @@ -13,6 +13,7 @@ filesets: depend: - lowrisc:dv:rv_timer_test - lowrisc:dv:rv_timer_sva + - lowrisc:prim_generic:all files: - tb/tb.sv file_type: systemVerilogSource diff --git a/hw/ip/spi_device/pre_dv/spi_tpm_sim.core b/hw/ip/spi_device/pre_dv/spi_tpm_sim.core index 6408391ca2a18..c28dccb7d5dbd 100644 --- a/hw/ip/spi_device/pre_dv/spi_tpm_sim.core +++ b/hw/ip/spi_device/pre_dv/spi_tpm_sim.core @@ -15,6 +15,7 @@ filesets: - lowrisc:dv:dv_utils - lowrisc:dv:dv_test_status - lowrisc:dv:common_ifs + - lowrisc:prim_generic:all files: - tb/spi_tpm_tb.sv file_type: systemVerilogSource diff --git a/hw/ip/spi_host/dv/spi_host_sim.core b/hw/ip/spi_host/dv/spi_host_sim.core index fa4ae292881a6..5ab2a92e8d76d 100644 --- a/hw/ip/spi_host/dv/spi_host_sim.core +++ b/hw/ip/spi_host/dv/spi_host_sim.core @@ -14,6 +14,7 @@ filesets: depend: - lowrisc:dv:spi_host_test - lowrisc:dv:spi_host_sva + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip/sram_ctrl/dv/sram_ctrl_sim.core b/hw/ip/sram_ctrl/dv/sram_ctrl_sim.core index c5072951db940..bc4d3d2e91c4e 100644 --- a/hw/ip/sram_ctrl/dv/sram_ctrl_sim.core +++ b/hw/ip/sram_ctrl/dv/sram_ctrl_sim.core @@ -16,6 +16,7 @@ filesets: - lowrisc:dv:mem_bkdr_util - lowrisc:dv:sram_ctrl_test - lowrisc:dv:sram_ctrl_sva + - lowrisc:prim_generic:all files: - tb.sv - cov/sram_ctrl_cov_bind.sv diff --git a/hw/ip/sysrst_ctrl/dv/sysrst_ctrl_sim.core b/hw/ip/sysrst_ctrl/dv/sysrst_ctrl_sim.core index 4f15a5f06f787..06fcb5a3ca0cb 100644 --- a/hw/ip/sysrst_ctrl/dv/sysrst_ctrl_sim.core +++ b/hw/ip/sysrst_ctrl/dv/sysrst_ctrl_sim.core @@ -14,6 +14,7 @@ filesets: - lowrisc:dv:sysrst_ctrl_test - lowrisc:dv:sysrst_ctrl_sva - lowrisc:dv:sysrst_ctrl_cov + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip/trial1/dv/trial1_sim.core b/hw/ip/trial1/dv/trial1_sim.core index 4f2e22f451344..611d8200f70f6 100644 --- a/hw/ip/trial1/dv/trial1_sim.core +++ b/hw/ip/trial1/dv/trial1_sim.core @@ -18,6 +18,7 @@ filesets: files_dv: depend: - lowrisc:dv:dv_test_status + - lowrisc:prim_generic:all files: - bus_pkg.sv - trial1_test.sv diff --git a/hw/ip/uart/dv/uart_sim.core b/hw/ip/uart/dv/uart_sim.core index 7f9b1ec348051..a249d93ac3a83 100644 --- a/hw/ip/uart/dv/uart_sim.core +++ b/hw/ip/uart/dv/uart_sim.core @@ -13,6 +13,7 @@ filesets: depend: - lowrisc:dv:uart_test - lowrisc:dv:uart_sva + - lowrisc:prim_generic:all files: - tb/tb.sv file_type: systemVerilogSource diff --git a/hw/ip/usbdev/dv/usbdev_sim.core b/hw/ip/usbdev/dv/usbdev_sim.core index dc6dc64bb41cb..d54ecf53c6a5b 100644 --- a/hw/ip/usbdev/dv/usbdev_sim.core +++ b/hw/ip/usbdev/dv/usbdev_sim.core @@ -17,6 +17,7 @@ filesets: - lowrisc:dv_dpi_c:usbdpi - lowrisc:dv_dpi_sv:usbdpi - lowrisc:prim_generic:usb_diff_rx + - lowrisc:prim_generic:all files: - tb/tb.sv file_type: systemVerilogSource diff --git a/hw/ip_templates/flash_ctrl/dv/flash_ctrl_sim.core b/hw/ip_templates/flash_ctrl/dv/flash_ctrl_sim.core index 66ccd3d1ec3e5..8a2c40a7c64e8 100644 --- a/hw/ip_templates/flash_ctrl/dv/flash_ctrl_sim.core +++ b/hw/ip_templates/flash_ctrl/dv/flash_ctrl_sim.core @@ -18,6 +18,7 @@ filesets: - lowrisc:dv:flash_ctrl_test - lowrisc:dv:flash_ctrl_sva - lowrisc:dv:flash_ctrl_cov + - lowrisc:prim_generic:all files: - tb/tb.sv file_type: systemVerilogSource diff --git a/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core b/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core index 5ece9db65645d..5d554fb8ebdd8 100644 --- a/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core +++ b/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core @@ -13,6 +13,7 @@ filesets: - lowrisc:dv:pwrmgr_test - lowrisc:dv:pwrmgr_sva - lowrisc:dv:pwrmgr_unit_only_sva + - lowrisc:prim_generic:all files: - tb.sv - cov/pwrmgr_cov_bind.sv diff --git a/hw/ip_templates/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core b/hw/ip_templates/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core index 11c3cfc7e74fe..720433d592a5e 100644 --- a/hw/ip_templates/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core +++ b/hw/ip_templates/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core @@ -16,6 +16,7 @@ filesets: - lowrisc:dv:dv_utils - lowrisc:dv:dv_test_status - lowrisc:dv:common_ifs + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/ip_templates/rstmgr/dv/rstmgr_sim.core b/hw/ip_templates/rstmgr/dv/rstmgr_sim.core index c9d6ae318a74f..ef236226abaa2 100644 --- a/hw/ip_templates/rstmgr/dv/rstmgr_sim.core +++ b/hw/ip_templates/rstmgr/dv/rstmgr_sim.core @@ -13,6 +13,7 @@ filesets: depend: - lowrisc:dv:rstmgr_test - lowrisc:dv:rstmgr_sva + - lowrisc:prim_generic:all files: - tb.sv - cov/rstmgr_cov_bind.sv diff --git a/hw/top_darjeeling/ip/ast/lint/ast.waiver b/hw/top_darjeeling/ip/ast/lint/ast.waiver index 51e54e6ea60c0..ba1701f409a17 100644 --- a/hw/top_darjeeling/ip/ast/lint/ast.waiver +++ b/hw/top_darjeeling/ip/ast/lint/ast.waiver @@ -125,7 +125,7 @@ waive -rules CLOCK_USE -location {ast.sv} \ -comment {This is a valid clock signal and the connection is ok here.} waive -rules CLOCK_USE -location {ast.sv} \ - -regexp {'clk_ast_usb_i' is used for some other purpose, and as clock 'clk_i' at prim_generic_flop.sv} \ + -regexp {'clk_ast_usb_i' is used for some other purpose, and as clock 'clk_i' at prim_flop.sv} \ -comment {This is a valid clock signal and the connection is ok here.} waive -rules INV_CLOCK -location {ast.sv rglts_pdm_3p3v.sv} \ @@ -217,19 +217,19 @@ waive -rules RESET_DRIVER -location {ast.sv} \ -comment {This is reset generation logic, hence reset muxes are allowed.} waive -rules RESET_DRIVER -location {ast.sv} \ - -regexp {'rst_sys_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \ + -regexp {'rst_sys_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_flop.sv} \ -comment {This is reset generation logic, hence reset muxes are allowed.} waive -rules RESET_DRIVER -location {ast.sv} \ - -regexp {'rst_usb_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \ + -regexp {'rst_usb_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_flop.sv} \ -comment {This is reset generation logic, hence reset muxes are allowed.} waive -rules RESET_DRIVER -location {ast.sv} \ - -regexp {'rst_io_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \ + -regexp {'rst_io_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_flop.sv} \ -comment {This is reset generation logic, hence reset muxes are allowed.} waive -rules RESET_DRIVER -location {usb_clk.sv} \ - -regexp {'rst_da_n' is driven by instance 'u_rst_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \ + -regexp {'rst_da_n' is driven by instance 'u_rst_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_ni' at prim_flop.sv} \ -comment {This is reset generation logic, hence reset muxes are allowed.} waive -rules RESET_DRIVER -location {usb_clk.sv} \ @@ -241,11 +241,11 @@ waive -rules RESET_DRIVER -location {usb_clk.sv} \ -comment {This is reset generation logic, hence reset muxes are allowed.} waive -rules RESET_DRIVER -location {usb_clk.sv} \ - -regexp {'q_o[0]' driven in module 'prim_generic_flop' at prim_generic_flop.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop' at prim_flop.sv} \ -comment {This is reset generation logic, hence reset muxes are allowed.} waive -rules RESET_DRIVER -location {usb_clk.sv} \ - -regexp {'rst_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \ + -regexp {'rst_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_flop.sv} \ -comment {This is reset generation logic, hence reset muxes are allowed.} waive -rules RESET_DRIVER -location {usb_clk.sv} \ @@ -261,11 +261,11 @@ waive -rules RESET_DRIVER -location {usb_clk.sv} \ -comment {This is reset generation logic, hence reset muxes are allowed.} waive -rules RESET_DRIVER -location {usb_clk.sv} \ - -regexp {'q_o[0]' driven in module 'prim_generic_flop' at prim_generic_flop.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop' at prim_flop.sv} \ -comment {This is reset generation logic, hence reset muxes are allowed.} waive -rules RESET_DRIVER -location {usb_clk.sv} \ - -regexp {'rst_usb_n' is driven by instance 'u_rst_ast_usb_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \ + -regexp {'rst_usb_n' is driven by instance 'u_rst_ast_usb_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_ni' at prim_flop.sv} \ -comment {This is reset generation logic, hence reset muxes are allowed.} waive -rules RESET_DRIVER -location {usb_clk.sv} \ @@ -277,7 +277,7 @@ waive -rules RESET_DRIVER -location {usb_clk.sv} \ -comment {This is reset generation logic, hence reset muxes are allowed.} waive -rules RESET_DRIVER -location {usb_clk.sv} \ - -regexp {'q_o[0]' driven in module 'prim_generic_flop' at prim_generic_flop.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop' at prim_flop.sv} \ -comment {This is reset generation logic, hence reset muxes are allowed.} waive -rules RESET_MUX -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \ @@ -305,7 +305,7 @@ waive -rules RESET_MUX -location {rglts_pdm_3p3v.sv} \ -comment {This is reset generation logic, hence reset muxes are allowed.} waive -rules RESET_MUX -location {usb_clk.sv} \ - -regexp {Asynchronous reset 'rst_n' is driven by a multiplexer here, used as a reset 'rst_ni' at prim_generic_flop.sv} \ + -regexp {Asynchronous reset 'rst_n' is driven by a multiplexer here, used as a reset 'rst_ni' at prim_flop.sv} \ -comment {This is reset generation logic, hence reset muxes are allowed.} waive -rules RESET_USE -location {ast.sv} \ @@ -349,11 +349,11 @@ waive -rules RESET_USE -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \ -comment {This is reset / clock generation logic, hence special reset usage is allowed.} waive -rules RESET_USE -location {ast.sv} \ - -regexp {'rst_ast_usb_ni' is used for some other purpose, and as asynchronous reset 'rst_ni' at prim_generic_flop.sv} \ + -regexp {'rst_ast_usb_ni' is used for some other purpose, and as asynchronous reset 'rst_ni' at prim_flop.sv} \ -comment {This is reset generation logic, hence reset muxes are allowed.} waive -rules RESET_USE -location {usb_clk.sv} \ - -regexp {'rst_usb_clk_ni' is used for some other purpose, and as asynchronous reset 'rst_ni' at prim_generic_flop.sv} \ + -regexp {'rst_usb_clk_ni' is used for some other purpose, and as asynchronous reset 'rst_ni' at prim_flop.sv} \ -comment {This is reset generation logic, hence reset muxes are allowed.} waive -rules TRI_DRIVER -location {ast.sv} \ diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/alert_handler_sim.core b/hw/top_darjeeling/ip_autogen/alert_handler/dv/alert_handler_sim.core index 702f7bb9f0d81..696976404527a 100644 --- a/hw/top_darjeeling/ip_autogen/alert_handler/dv/alert_handler_sim.core +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/alert_handler_sim.core @@ -12,27 +12,17 @@ filesets: files_dv: depend: - - lowrisc:dv:ralgen - - lowrisc:dv:alert_handler_tb + - lowrisc:opentitan:top_darjeeling_alert_handler_tb:0.1 - lowrisc:dv:alert_handler_cov - lowrisc:opentitan:top_darjeeling_alert_handler_sva:0.1 file_type: systemVerilogSource -generate: - ral: - generator: ralgen - parameters: - name: alert_handler - ip_hjson: ../data/alert_handler.hjson - targets: sim: &sim_target toplevel: tb filesets: - files_rtl - files_dv - generate: - - ral default_tool: vcs lint: diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env.core b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env.core index 8103212c1975f..d410ad0c99312 100644 --- a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env.core +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env.core @@ -2,11 +2,12 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:alert_handler_env:0.1" +name: lowrisc:opentitan:top_darjeeling_alert_handler_env:0.1 description: "ALERT_HANDLER DV UVM environment" filesets: files_dv: depend: + - lowrisc:dv:ralgen - lowrisc:dv:cip_lib - lowrisc:ip:alert_handler_component # import alert_pkg - lowrisc:prim:mubi # import prim_mubi_pkg @@ -36,7 +37,17 @@ filesets: - seq_lib/alert_handler_alert_accum_saturation_vseq.sv: {is_include_file: true} file_type: systemVerilogSource +generate: + ral: + generator: ralgen + parameters: + name: alert_handler + ip_hjson: ../../data/alert_handler.hjson + position: prepend + targets: default: filesets: - files_dv + generate: + - ral diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/tb/alert_handler_tb.core b/hw/top_darjeeling/ip_autogen/alert_handler/dv/tb/alert_handler_tb.core index bbf6842a74308..7a352bba75c01 100644 --- a/hw/top_darjeeling/ip_autogen/alert_handler/dv/tb/alert_handler_tb.core +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/tb/alert_handler_tb.core @@ -2,12 +2,12 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:alert_handler_tb:0.1" +name: lowrisc:opentitan:top_darjeeling_alert_handler_tb:0.1 description: "ALERT_HANDLER UVM TB environment" filesets: files_dv: depend: - - lowrisc:dv:alert_handler_test:0.1 + - lowrisc:opentitan:top_darjeeling_alert_handler_test:0.1 files: - tb.sv file_type: systemVerilogSource diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/tests/alert_handler_test.core b/hw/top_darjeeling/ip_autogen/alert_handler/dv/tests/alert_handler_test.core index 767c0654f1c6d..3204367b6fa71 100644 --- a/hw/top_darjeeling/ip_autogen/alert_handler/dv/tests/alert_handler_test.core +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/tests/alert_handler_test.core @@ -2,12 +2,12 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:alert_handler_test:0.1" +name: lowrisc:opentitan:top_darjeeling_alert_handler_test:0.1 description: "ALERT_HANDLER DV UVM test" filesets: files_dv: depend: - - lowrisc:dv:alert_handler_env + - lowrisc:opentitan:top_darjeeling_alert_handler_env files: - alert_handler_test_pkg.sv - alert_handler_base_test.sv: {is_include_file: true} diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env.core b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env.core index 2fa8234336d2c..34fd79715f99b 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env.core +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env.core @@ -40,6 +40,7 @@ generate: parameters: name: clkmgr ip_hjson: ../../data/clkmgr.hjson + position: prepend targets: default: diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core index 731e28063b434..90c6919414578 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core @@ -46,6 +46,7 @@ generate: parameters: name: pwrmgr ip_hjson: ../../data/pwrmgr.hjson + position: prepend targets: default: diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim.core b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim.core index 5ece9db65645d..5d554fb8ebdd8 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim.core +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim.core @@ -13,6 +13,7 @@ filesets: - lowrisc:dv:pwrmgr_test - lowrisc:dv:pwrmgr_sva - lowrisc:dv:pwrmgr_unit_only_sva + - lowrisc:prim_generic:all files: - tb.sv - cov/pwrmgr_cov_bind.sv diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env.core b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env.core index a8d54568b804e..25504659e8c81 100644 --- a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env.core +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env.core @@ -43,6 +43,7 @@ generate: parameters: name: rstmgr ip_hjson: ../../data/rstmgr.hjson + position: prepend targets: default: diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core index 11c3cfc7e74fe..720433d592a5e 100644 --- a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core @@ -16,6 +16,7 @@ filesets: - lowrisc:dv:dv_utils - lowrisc:dv:dv_test_status - lowrisc:dv:common_ifs + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim.core b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim.core index c9d6ae318a74f..ef236226abaa2 100644 --- a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim.core +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim.core @@ -13,6 +13,7 @@ filesets: depend: - lowrisc:dv:rstmgr_test - lowrisc:dv:rstmgr_sva + - lowrisc:prim_generic:all files: - tb.sv - cov/rstmgr_cov_bind.sv diff --git a/hw/top_earlgrey/dv/chip_sim.core b/hw/top_earlgrey/dv/chip_sim.core index 5fbc9320503c7..c3d017292e851 100644 --- a/hw/top_earlgrey/dv/chip_sim.core +++ b/hw/top_earlgrey/dv/chip_sim.core @@ -39,6 +39,8 @@ filesets: - lowrisc:dv_dpi_c:usbdpi - lowrisc:dv_dpi_sv:usbdpi - lowrisc:dv:usb20_usbdpi + # It may make sense to put this generic behind a flag + - lowrisc:prim_generic:all files: - tb/chip_hier_macros.svh: {is_include_file: true} - autogen/tb__xbar_connect.sv: {is_include_file: true} diff --git a/hw/top_earlgrey/dv/verilator/chip_sim.core b/hw/top_earlgrey/dv/verilator/chip_sim.core index a5b58502a030f..b491a73602529 100644 --- a/hw/top_earlgrey/dv/verilator/chip_sim.core +++ b/hw/top_earlgrey/dv/verilator/chip_sim.core @@ -25,6 +25,7 @@ filesets: - lowrisc:dv:sw_test_status - lowrisc:dv:dv_test_status - lowrisc:systems:chip_earlgrey_verilator + - lowrisc:prim_generic:all files: - chip_sim_tb.sv: { file_type: systemVerilogSource } - chip_sim_tb.cc: { file_type: cppSource } diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core index 66ccd3d1ec3e5..8a2c40a7c64e8 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core @@ -18,6 +18,7 @@ filesets: - lowrisc:dv:flash_ctrl_test - lowrisc:dv:flash_ctrl_sva - lowrisc:dv:flash_ctrl_cov + - lowrisc:prim_generic:all files: - tb/tb.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core index 5ece9db65645d..5d554fb8ebdd8 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core @@ -13,6 +13,7 @@ filesets: - lowrisc:dv:pwrmgr_test - lowrisc:dv:pwrmgr_sva - lowrisc:dv:pwrmgr_unit_only_sva + - lowrisc:prim_generic:all files: - tb.sv - cov/pwrmgr_cov_bind.sv diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core b/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core index 11c3cfc7e74fe..720433d592a5e 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core +++ b/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core @@ -16,6 +16,7 @@ filesets: - lowrisc:dv:dv_utils - lowrisc:dv:dv_test_status - lowrisc:dv:common_ifs + - lowrisc:prim_generic:all files: - tb.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim.core b/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim.core index c9d6ae318a74f..ef236226abaa2 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim.core +++ b/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim.core @@ -13,6 +13,7 @@ filesets: depend: - lowrisc:dv:rstmgr_test - lowrisc:dv:rstmgr_sva + - lowrisc:prim_generic:all files: - tb.sv - cov/rstmgr_cov_bind.sv diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_sim.core b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_sim.core index 473007cf67a79..62ee146751510 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_sim.core +++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_sim.core @@ -14,6 +14,7 @@ filesets: - lowrisc:dv:ibex_icache_test - lowrisc:dv:ibex_icache_fcov - lowrisc:prim:ram_1p_scr + - lowrisc:prim_generic:all files: - tb/tb.sv file_type: systemVerilogSource diff --git a/hw/vendor/patches/lowrisc_ibex/dv/0001-dv-Added-concrete-prim-implementation-to-all-simulat.patch b/hw/vendor/patches/lowrisc_ibex/dv/0001-dv-Added-concrete-prim-implementation-to-all-simulat.patch new file mode 100644 index 0000000000000..585fa55788baf --- /dev/null +++ b/hw/vendor/patches/lowrisc_ibex/dv/0001-dv-Added-concrete-prim-implementation-to-all-simulat.patch @@ -0,0 +1,26 @@ +From 2cc68d159fab356d9462ad0b83714f6d5b5123d0 Mon Sep 17 00:00:00 2001 +From: Hugo McNally +Date: Tue, 10 Dec 2024 06:02:11 +0000 +Subject: [PATCH 1/2] [dv] Added concrete prim implementation to all simulation + top levels + +Signed-off-by: Hugo McNally +--- + uvm/icache/dv/ibex_icache_sim.core | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/uvm/icache/dv/ibex_icache_sim.core b/dv/uvm/icache/dv/ibex_icache_sim.core +index 473007cf67..62ee146751 100644 +--- a/uvm/icache/dv/ibex_icache_sim.core ++++ b/uvm/icache/dv/ibex_icache_sim.core +@@ -14,6 +14,7 @@ filesets: + - lowrisc:dv:ibex_icache_test + - lowrisc:dv:ibex_icache_fcov + - lowrisc:prim:ram_1p_scr ++ - lowrisc:prim_generic:all + files: + - tb/tb.sv + file_type: systemVerilogSource +-- +2.43.0 + From b5e6605c736c7ded786988094b5d5b9d46fb7fd3 Mon Sep 17 00:00:00 2001 From: Hugo McNally Date: Tue, 10 Dec 2024 06:03:14 +0000 Subject: [PATCH 15/24] [hw] Removed references to non virtual primitive cores. Signed-off-by: Hugo McNally --- hw/ip/usbdev/dv/usbdev_sim.core | 2 +- .../dv/prim_badbit/prim_badbit_ram_1p.core | 2 +- ...ences-to-non-virtual-primitive-cores.patch | 26 +++++++++++++++++++ 3 files changed, 28 insertions(+), 2 deletions(-) create mode 100644 hw/vendor/patches/lowrisc_ibex/dv/0002-hw-Removed-references-to-non-virtual-primitive-cores.patch diff --git a/hw/ip/usbdev/dv/usbdev_sim.core b/hw/ip/usbdev/dv/usbdev_sim.core index d54ecf53c6a5b..8e895be7d1477 100644 --- a/hw/ip/usbdev/dv/usbdev_sim.core +++ b/hw/ip/usbdev/dv/usbdev_sim.core @@ -16,7 +16,7 @@ filesets: - lowrisc:dv:usb20_usbdpi - lowrisc:dv_dpi_c:usbdpi - lowrisc:dv_dpi_sv:usbdpi - - lowrisc:prim_generic:usb_diff_rx + - lowrisc:prim:usb_diff_rx - lowrisc:prim_generic:all files: - tb/tb.sv diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/prim_badbit/prim_badbit_ram_1p.core b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/prim_badbit/prim_badbit_ram_1p.core index df81ec5dd3ca6..cf48598fe038c 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/prim_badbit/prim_badbit_ram_1p.core +++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/prim_badbit/prim_badbit_ram_1p.core @@ -8,7 +8,7 @@ description: "Single-port RAM which allows a bound interface to inject errors" filesets: files_rtl: depend: - - lowrisc:prim_generic:ram_1p + - lowrisc:prim:ram_1p - lowrisc:prim:assert files: - prim_badbit_ram_1p.sv diff --git a/hw/vendor/patches/lowrisc_ibex/dv/0002-hw-Removed-references-to-non-virtual-primitive-cores.patch b/hw/vendor/patches/lowrisc_ibex/dv/0002-hw-Removed-references-to-non-virtual-primitive-cores.patch new file mode 100644 index 0000000000000..1fc802b076179 --- /dev/null +++ b/hw/vendor/patches/lowrisc_ibex/dv/0002-hw-Removed-references-to-non-virtual-primitive-cores.patch @@ -0,0 +1,26 @@ +From a730b803e5182c1b1b95e11a966b2f5b44c942d9 Mon Sep 17 00:00:00 2001 +From: Hugo McNally +Date: Tue, 10 Dec 2024 06:03:14 +0000 +Subject: [PATCH 2/2] [hw] Removed references to non virtual primitive cores. + +Signed-off-by: Hugo McNally +--- + .../dv/uvm/icache/dv/prim_badbit/prim_badbit_ram_1p.core | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/uvm/icache/dv/prim_badbit/prim_badbit_ram_1p.core b/uvm/icache/dv/prim_badbit/prim_badbit_ram_1p.core +index df81ec5dd3..cf48598fe0 100644 +--- a/uvm/icache/dv/prim_badbit/prim_badbit_ram_1p.core ++++ b/uvm/icache/dv/prim_badbit/prim_badbit_ram_1p.core +@@ -8,7 +8,7 @@ description: "Single-port RAM which allows a bound interface to inject errors" + filesets: + files_rtl: + depend: +- - lowrisc:prim_generic:ram_1p ++ - lowrisc:prim:ram_1p + - lowrisc:prim:assert + files: + - prim_badbit_ram_1p.sv +-- +2.43.0 + From 3e911dc20c145ae8b1ea69ff89638c20eab2c3ba Mon Sep 17 00:00:00 2001 From: Hugo McNally Date: Tue, 17 Dec 2024 08:57:23 +0000 Subject: [PATCH 16/24] [prim/lint] Update file names ascent lint waivers Signed-off-by: Hugo McNally --- .../lint/prim_generic_clock_div.waiver | 16 ++++++++-------- .../lint/prim_generic_flop_2sync.waiver | 6 +++--- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/hw/ip/prim_generic/lint/prim_generic_clock_div.waiver b/hw/ip/prim_generic/lint/prim_generic_clock_div.waiver index c4210149639cf..39c024c2c1599 100644 --- a/hw/ip/prim_generic/lint/prim_generic_clock_div.waiver +++ b/hw/ip/prim_generic/lint/prim_generic_clock_div.waiver @@ -19,26 +19,26 @@ waive -rules CLOCK_USE -location {prim_clock_div.sv} -regexp {'clk_i' is connect waive -rules SAME_NAME_TYPE -location {prim_clock_div.sv} -regexp {'ResetValue' is used as a parameter here, and as an enumeration value at} \ -comment "Reused parameter name." -waive -rules CLOCK_DRIVER -location {prim_generic_clock_div.sv} -regexp {'gen_div2.q_p' is driven by instance 'gen_div2\^u_div2' of module 'prim_flop', and used as a clock 'clk_i'} \ +waive -rules CLOCK_DRIVER -location {prim_clock_div.sv} -regexp {'gen_div2.q_p' is driven by instance 'gen_div2\^u_div2' of module 'prim_flop', and used as a clock 'clk_i'} \ -comment "A 'prim_flop' is used together with a 'prim_clock_inv' to implement a division by 2" -waive -rules CLOCK_USE -location {prim_generic_clock_div.sv} -regexp {'gen_div2.q_n' is connected to 'prim_flop' port 'd_i\[0\]', and used as a clock 'clk_i'} \ +waive -rules CLOCK_USE -location {prim_clock_div.sv} -regexp {'gen_div2.q_n' is connected to 'prim_flop' port 'd_i\[0\]', and used as a clock 'clk_i'} \ -comment "A 'prim_flop' is used together with a 'prim_clock_inv' to implement a division by 2" -waive -rules INV_CLOCK -location {prim_generic_clock_div.sv} -regexp {'gen_div2.q_p' is inverted, used as clock 'clk_i'} \ +waive -rules INV_CLOCK -location {prim_clock_div.sv} -regexp {'gen_div2.q_p' is inverted, used as clock 'clk_i'} \ -comment "A 'prim_flop' is used together with a 'prim_clock_inv' to implement a division by 2" -waive -rules CLOCK_DRIVER -location {prim_generic_clock_div.sv} -regexp {'clk_int' is driven here, and used as a clock} \ +waive -rules CLOCK_DRIVER -location {prim_clock_div.sv} -regexp {'clk_int' is driven here, and used as a clock} \ -comment "The division by more than 2 is implemented using a behavioral toggle counter" -waive -rules CLOCK_MUX -location {prim_generic_clock_div.sv} -regexp {Clock 'clk_int' is driven by a multiplexer here, used as a clock 'clk_i'} \ +waive -rules CLOCK_MUX -location {prim_clock_div.sv} -regexp {Clock 'clk_int' is driven by a multiplexer here, used as a clock 'clk_i'} \ -comment "This clock mux usage is OK." -waive -rules CLOCK_MUX -location {prim_generic_clock_div.sv} -regexp {Clock 'clk_muxed' is driven by a multiplexer here, used as a clock} \ +waive -rules CLOCK_MUX -location {prim_clock_div.sv} -regexp {Clock 'clk_muxed' is driven by a multiplexer here, used as a clock} \ -comment "This clock mux usage is OK." -waive -rules CLOCK_USE -location {prim_generic_clock_div.sv} -regexp {'clk_muxed' is used for some other purpose, and as clock} \ +waive -rules CLOCK_USE -location {prim_clock_div.sv} -regexp {'clk_muxed' is used for some other purpose, and as clock} \ -comment "The division by more than 2 is implemented using a behavioral toggle counter driven by 'clk_muxed'" -waive -rules INV_CLOCK -location {prim_generic_clock_div.sv} -regexp {'clk_muxed' is inverted, used as clock} \ +waive -rules INV_CLOCK -location {prim_clock_div.sv} -regexp {'clk_muxed' is inverted, used as clock} \ -comment "The division by more than 2 is implemented using a behavioral toggle counter driven by 'clk_muxed'" diff --git a/hw/ip/prim_generic/lint/prim_generic_flop_2sync.waiver b/hw/ip/prim_generic/lint/prim_generic_flop_2sync.waiver index b5f9763b82542..9cb13fb9fe7f8 100644 --- a/hw/ip/prim_generic/lint/prim_generic_flop_2sync.waiver +++ b/hw/ip/prim_generic/lint/prim_generic_flop_2sync.waiver @@ -2,7 +2,7 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# waiver file for prim_generic_flop_2sync +# waiver file for prim_flop_2sync -waive -rules {IFDEF_CODE} -location {prim_generic_flop_2sync.sv} -regexp {.*contained within \`else block.*} \ - -comment "Ifdefs are required for prim_generic_flop_2sync since it is turned on only for simulation." +waive -rules {IFDEF_CODE} -location {prim_flop_2sync.sv} -regexp {.*contained within \`else block.*} \ + -comment "Ifdefs are required for prim_flop_2sync since it is turned on only for simulation." From cbc1846caf8b83a4ddaf5fe14c4e178f3c6c8275 Mon Sep 17 00:00:00 2001 From: Hugo McNally Date: Tue, 17 Dec 2024 09:07:49 +0000 Subject: [PATCH 17/24] [dvsim] Adjust search path for ascent lint parser Switched ascent lint over to use FuseSoC's `--work-root` as oppose to `--build-root`. Signed-off-by: Hugo McNally --- hw/lint/tools/dvsim/common_lint_cfg.hjson | 2 +- util/dvsim/ascentlint-report-parser.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/lint/tools/dvsim/common_lint_cfg.hjson b/hw/lint/tools/dvsim/common_lint_cfg.hjson index 9ec23bdf9bf48..5377c3087dda4 100644 --- a/hw/lint/tools/dvsim/common_lint_cfg.hjson +++ b/hw/lint/tools/dvsim/common_lint_cfg.hjson @@ -25,7 +25,7 @@ "--flag=fileset_{design_level}", "--target={flow}", "--tool={tool}", - "--build-root={build_dir}", + "--work-root={build_dir}/fusesoc-work", "{fusesoc_core}"] // Determines which message severities to print into report summaries. diff --git a/util/dvsim/ascentlint-report-parser.py b/util/dvsim/ascentlint-report-parser.py index 2edb2bf80c898..e032baea0e183 100755 --- a/util/dvsim/ascentlint-report-parser.py +++ b/util/dvsim/ascentlint-report-parser.py @@ -62,7 +62,7 @@ def main(): # Patterns for ascentlint.log parser_args.update({ - args.repdir.joinpath('lint-ascentlint/ascentlint.log'): [ + args.repdir.joinpath('fusesoc-work/ascentlint.log'): [ ("flow_error", r"^FlexNet Licensing error.*"), ("flow_error", r"^Error: .*"), ("flow_error", r"^ERROR.*"), @@ -77,7 +77,7 @@ def main(): # Patterns for ascentlint.rpt parser_args.update({ - args.repdir.joinpath('lint-ascentlint/ascentlint.rpt'): [ + args.repdir.joinpath('fusesoc-work/ascentlint.rpt'): [ ("lint_error", r"^E .*"), ("lint_warning", r"^W .*"), ("lint_info", r"^I .*") From c83bae9de6dba0010ef269da7b2629ea1b34216e Mon Sep 17 00:00:00 2001 From: Hugo McNally Date: Tue, 17 Dec 2024 14:10:27 +0000 Subject: [PATCH 18/24] [hw,lint] Specified concrete prim implementation for lints Signed-off-by: Hugo McNally --- hw/lint/common.core | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/lint/common.core b/hw/lint/common.core index 20338eaf11d62..6a5c19dbcfcc9 100644 --- a/hw/lint/common.core +++ b/hw/lint/common.core @@ -6,11 +6,15 @@ name: "lowrisc:lint:common:0.1" description: "Common waivers" filesets: files_verilator: + depend: + - lowrisc:prim_generic:all files: - tools/verilator/common.vlt file_type: vlt files_ascentlint: + depend: + - lowrisc:prim_generic:all files: - tools/ascentlint/common.waiver: {file_type: waiver} - tools/ascentlint/ascentlint-config.tcl: {file_type: tclSource} From 5808ba85ea4ddbae913f0f3db2310d9eb9fa7318 Mon Sep 17 00:00:00 2001 From: Hugo McNally Date: Tue, 17 Dec 2024 14:59:12 +0000 Subject: [PATCH 19/24] [hw,lint] Removed common lints from prims Because we introduce specify a concrete prim implementation in the common lint dependencies, we can't use common lint in this prim implementation or we'll have a circular dependency. Signed-off-by: Hugo McNally --- hw/ip/prim_generic/prim_generic_and2.core | 18 ------------------ hw/ip/prim_generic/prim_generic_buf.core | 18 ------------------ hw/ip/prim_generic/prim_generic_clock_buf.core | 12 ------------ hw/ip/prim_generic/prim_generic_clock_div.core | 4 ---- .../prim_generic_clock_gating.core | 12 ------------ hw/ip/prim_generic/prim_generic_clock_inv.core | 18 ------------------ .../prim_generic/prim_generic_clock_mux2.core | 12 ------------ hw/ip/prim_generic/prim_generic_flash.core | 12 ------------ hw/ip/prim_generic/prim_generic_flop.core | 18 ------------------ .../prim_generic/prim_generic_flop_2sync.core | 15 --------------- hw/ip/prim_generic/prim_generic_flop_en.core | 18 ------------------ hw/ip/prim_generic/prim_generic_otp.core | 8 -------- hw/ip/prim_generic/prim_generic_pad_attr.core | 18 ------------------ .../prim_generic/prim_generic_pad_wrapper.core | 12 ------------ hw/ip/prim_generic/prim_generic_ram_1p.core | 12 ------------ hw/ip/prim_generic/prim_generic_ram_1r1w.core | 12 ------------ hw/ip/prim_generic/prim_generic_ram_2p.core | 12 ------------ hw/ip/prim_generic/prim_generic_rom.core | 12 ------------ .../prim_generic/prim_generic_usb_diff_rx.core | 15 --------------- hw/ip/prim_generic/prim_generic_xnor2.core | 18 ------------------ hw/ip/prim_generic/prim_generic_xor2.core | 18 ------------------ 21 files changed, 294 deletions(-) diff --git a/hw/ip/prim_generic/prim_generic_and2.core b/hw/ip/prim_generic/prim_generic_and2.core index e18e8b48a2d65..f4047815b9797 100644 --- a/hw/ip/prim_generic/prim_generic_and2.core +++ b/hw/ip/prim_generic/prim_generic_and2.core @@ -14,25 +14,7 @@ filesets: - rtl/prim_and2.sv file_type: systemVerilogSource - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_buf.core b/hw/ip/prim_generic/prim_generic_buf.core index 9db9568d253eb..d92ef6fd56047 100644 --- a/hw/ip/prim_generic/prim_generic_buf.core +++ b/hw/ip/prim_generic/prim_generic_buf.core @@ -14,25 +14,7 @@ filesets: - rtl/prim_buf.sv file_type: systemVerilogSource - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_clock_buf.core b/hw/ip/prim_generic/prim_generic_clock_buf.core index d11883d9ea4f7..a8a478cb721f3 100644 --- a/hw/ip/prim_generic/prim_generic_clock_buf.core +++ b/hw/ip/prim_generic/prim_generic_clock_buf.core @@ -15,30 +15,18 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_clock_buf.vlt file_type: vlt files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_clock_buf.waiver file_type: waiver - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_clock_div.core b/hw/ip/prim_generic/prim_generic_clock_div.core index 0c33b7398f10d..26bddcc4f0d47 100644 --- a/hw/ip/prim_generic/prim_generic_clock_div.core +++ b/hw/ip/prim_generic/prim_generic_clock_div.core @@ -20,9 +20,6 @@ filesets: file_type: systemVerilogSource files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_clock_div.waiver file_type: waiver @@ -30,5 +27,4 @@ filesets: targets: default: filesets: - - tool_ascentlint ? (files_ascentlint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_clock_gating.core b/hw/ip/prim_generic/prim_generic_clock_gating.core index 9d79c9d540303..5277c92a8739d 100644 --- a/hw/ip/prim_generic/prim_generic_clock_gating.core +++ b/hw/ip/prim_generic/prim_generic_clock_gating.core @@ -15,30 +15,18 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_clock_gating.vlt file_type: vlt files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_clock_gating.waiver file_type: waiver - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_clock_inv.core b/hw/ip/prim_generic/prim_generic_clock_inv.core index 399b220bb6f44..9dbe2b94195d0 100644 --- a/hw/ip/prim_generic/prim_generic_clock_inv.core +++ b/hw/ip/prim_generic/prim_generic_clock_inv.core @@ -17,25 +17,7 @@ filesets: - rtl/prim_clock_inv.sv file_type: systemVerilogSource - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_clock_mux2.core b/hw/ip/prim_generic/prim_generic_clock_mux2.core index de600aea58b3d..7b524e31c08b0 100644 --- a/hw/ip/prim_generic/prim_generic_clock_mux2.core +++ b/hw/ip/prim_generic/prim_generic_clock_mux2.core @@ -17,30 +17,18 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_clock_mux2.vlt file_type: vlt files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_clock_mux2.waiver file_type: waiver - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_flash.core b/hw/ip/prim_generic/prim_generic_flash.core index 13035b8278b46..f620c63101565 100644 --- a/hw/ip/prim_generic/prim_generic_flash.core +++ b/hw/ip/prim_generic/prim_generic_flash.core @@ -23,30 +23,18 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_flash.vlt file_type: vlt files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_flash.waiver file_type: waiver - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_flop.core b/hw/ip/prim_generic/prim_generic_flop.core index e899f79042ee0..4b112de28a65b 100644 --- a/hw/ip/prim_generic/prim_generic_flop.core +++ b/hw/ip/prim_generic/prim_generic_flop.core @@ -14,25 +14,7 @@ filesets: - rtl/prim_flop.sv file_type: systemVerilogSource - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_flop_2sync.core b/hw/ip/prim_generic/prim_generic_flop_2sync.core index a67519a8696f9..1864e470f0db5 100644 --- a/hw/ip/prim_generic/prim_generic_flop_2sync.core +++ b/hw/ip/prim_generic/prim_generic_flop_2sync.core @@ -19,28 +19,13 @@ filesets: - rtl/prim_flop_2sync.sv file_type: systemVerilogSource - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_flop_2sync.waiver file_type: waiver - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_flop_en.core b/hw/ip/prim_generic/prim_generic_flop_en.core index e1c70ecfc605a..6212f98c6b27c 100644 --- a/hw/ip/prim_generic/prim_generic_flop_en.core +++ b/hw/ip/prim_generic/prim_generic_flop_en.core @@ -16,25 +16,7 @@ filesets: - rtl/prim_flop_en.sv file_type: systemVerilogSource - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_otp.core b/hw/ip/prim_generic/prim_generic_otp.core index 70e12ce53bdbc..87df633fc5029 100644 --- a/hw/ip/prim_generic/prim_generic_otp.core +++ b/hw/ip/prim_generic/prim_generic_otp.core @@ -23,17 +23,11 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_otp.vlt file_type: vlt files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_otp.waiver file_type: waiver @@ -42,6 +36,4 @@ filesets: targets: default: filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_pad_attr.core b/hw/ip/prim_generic/prim_generic_pad_attr.core index c80c59e00dbf3..c7107c8bbab88 100644 --- a/hw/ip/prim_generic/prim_generic_pad_attr.core +++ b/hw/ip/prim_generic/prim_generic_pad_attr.core @@ -17,25 +17,7 @@ filesets: - rtl/prim_pad_attr.sv file_type: systemVerilogSource - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_pad_wrapper.core b/hw/ip/prim_generic/prim_generic_pad_wrapper.core index 764cd45f89ce3..3806226aaca43 100644 --- a/hw/ip/prim_generic/prim_generic_pad_wrapper.core +++ b/hw/ip/prim_generic/prim_generic_pad_wrapper.core @@ -18,30 +18,18 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_pad_wrapper.vlt file_type: vlt files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_pad_wrapper.waiver file_type: waiver - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_ram_1p.core b/hw/ip/prim_generic/prim_generic_ram_1p.core index 661a96627b516..4ac9ed5db9fe1 100644 --- a/hw/ip/prim_generic/prim_generic_ram_1p.core +++ b/hw/ip/prim_generic/prim_generic_ram_1p.core @@ -19,30 +19,18 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_ram_1p.vlt file_type: vlt files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_ram_1p.waiver file_type: waiver - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_ram_1r1w.core b/hw/ip/prim_generic/prim_generic_ram_1r1w.core index efcbc802748bd..2bb70f45c20b6 100644 --- a/hw/ip/prim_generic/prim_generic_ram_1r1w.core +++ b/hw/ip/prim_generic/prim_generic_ram_1r1w.core @@ -19,30 +19,18 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_ram_1r1w.vlt file_type: vlt files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_ram_1r1w.waiver file_type: waiver - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_ram_2p.core b/hw/ip/prim_generic/prim_generic_ram_2p.core index b246ce1164f30..752ee36d62942 100644 --- a/hw/ip/prim_generic/prim_generic_ram_2p.core +++ b/hw/ip/prim_generic/prim_generic_ram_2p.core @@ -19,30 +19,18 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_ram_2p.vlt file_type: vlt files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_ram_2p.waiver file_type: waiver - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_rom.core b/hw/ip/prim_generic/prim_generic_rom.core index 41d76d4fb95e4..ce371cda6e834 100644 --- a/hw/ip/prim_generic/prim_generic_rom.core +++ b/hw/ip/prim_generic/prim_generic_rom.core @@ -19,30 +19,18 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_rom.vlt file_type: vlt files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_rom.waiver file_type: waiver - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_usb_diff_rx.core b/hw/ip/prim_generic/prim_generic_usb_diff_rx.core index f77bdeee10838..60279b061a57c 100644 --- a/hw/ip/prim_generic/prim_generic_usb_diff_rx.core +++ b/hw/ip/prim_generic/prim_generic_usb_diff_rx.core @@ -14,28 +14,13 @@ filesets: - rtl/prim_usb_diff_rx.sv file_type: systemVerilogSource - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common files: - lint/prim_generic_usb_diff_rx.waiver file_type: waiver - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_xnor2.core b/hw/ip/prim_generic/prim_generic_xnor2.core index 137af0183886b..e7229318007d5 100644 --- a/hw/ip/prim_generic/prim_generic_xnor2.core +++ b/hw/ip/prim_generic/prim_generic_xnor2.core @@ -14,25 +14,7 @@ filesets: - rtl/prim_xnor2.sv file_type: systemVerilogSource - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_xor2.core b/hw/ip/prim_generic/prim_generic_xor2.core index b77448326d5a9..ebc0022600162 100644 --- a/hw/ip/prim_generic/prim_generic_xor2.core +++ b/hw/ip/prim_generic/prim_generic_xor2.core @@ -14,25 +14,7 @@ filesets: - rtl/prim_xor2.sv file_type: systemVerilogSource - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - targets: default: filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl From 63f1dee9516b2117525d6402f8ce2b9f44e9b502 Mon Sep 17 00:00:00 2001 From: Alexander Williams Date: Wed, 18 Dec 2024 02:13:26 +0000 Subject: [PATCH 20/24] [lint] Add concrete implementation for lint targets Make many lint targets depend on the generic prims. Signed-off-by: Alexander Williams --- hw/ip/adc_ctrl/adc_ctrl.core | 6 ++++++ hw/ip/aes/aes.core | 6 ++++++ hw/ip/aes/aes_wrap.core | 6 ++++++ hw/ip/aon_timer/aon_timer.core | 6 ++++++ hw/ip/ascon/ascon.core | 6 ++++++ hw/ip/csrng/csrng.core | 5 +++++ hw/ip/dma/dma.core | 6 ++++++ hw/ip/edn/edn.core | 6 ++++++ hw/ip/entropy_src/entropy_src.core | 6 ++++++ hw/ip/gpio/gpio.core | 6 ++++++ hw/ip/hmac/hmac.core | 6 ++++++ hw/ip/i2c/i2c.core | 6 ++++++ hw/ip/keymgr/keymgr.core | 6 ++++++ hw/ip/keymgr_dpe/keymgr_dpe.core | 6 ++++++ hw/ip/kmac/kmac.core | 6 ++++++ hw/ip/kmac/kmac_reduced.core | 6 ++++++ hw/ip/kmac/sha3.core | 6 ++++++ hw/ip/lc_ctrl/lc_ctrl.core | 6 ++++++ hw/ip/lc_ctrl/lc_ctrl_pkg.core | 6 ++++++ hw/ip/mbx/mbx.core | 6 ++++++ hw/ip/otbn/otbn.core | 6 ++++++ hw/ip/otp_ctrl/otp_ctrl.core | 6 ++++++ hw/ip/otp_ctrl/otp_ctrl_pkg.core | 6 ++++++ hw/ip/pattgen/pattgen.core | 6 ++++++ hw/ip/pwm/pwm.core | 6 ++++++ hw/ip/rom_ctrl/rom_ctrl.core | 6 ++++++ hw/ip/rv_core_ibex/rv_core_ibex.core | 6 ++++++ hw/ip/rv_dm/rv_dm.core | 6 ++++++ hw/ip/rv_timer/rv_timer.core | 6 ++++++ hw/ip/soc_dbg_ctrl/soc_dbg_ctrl.core | 6 ++++++ hw/ip/soc_dbg_ctrl/soc_dbg_ctrl_decode.core | 6 ++++++ hw/ip/spi_device/spi_device.core | 6 ++++++ hw/ip/spi_host/spi_host.core | 6 ++++++ hw/ip/sram_ctrl/sram_ctrl.core | 6 ++++++ hw/ip/sysrst_ctrl/sysrst_ctrl.core | 6 ++++++ hw/ip/tlul/adapter_dmi.core | 6 ++++++ hw/ip/tlul/adapter_host.core | 6 ++++++ hw/ip/tlul/adapter_reg.core | 6 ++++++ hw/ip/tlul/adapter_sram.core | 6 ++++++ hw/ip/tlul/jtag_dtm.core | 6 ++++++ hw/ip/tlul/request_loopback.core | 6 ++++++ hw/ip/tlul/socket_1n.core | 6 ++++++ hw/ip/tlul/socket_m1.core | 6 ++++++ hw/ip/tlul/sram2tlul.core | 6 ++++++ hw/ip/tlul/tlul_lc_gate.core | 6 ++++++ hw/ip/tlul/trans_intg.core | 6 ++++++ hw/ip/uart/uart.core | 6 ++++++ hw/ip/usbdev/usb_fs_nb_pe.core | 6 ++++++ hw/ip/usbdev/usbdev.core | 6 ++++++ hw/ip_templates/alert_handler/alert_handler.core.tpl | 6 ++++++ hw/ip_templates/clkmgr/clkmgr.core.tpl | 6 ++++++ hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl | 6 ++++++ hw/ip_templates/pinmux/pinmux.core.tpl | 6 ++++++ hw/ip_templates/pwrmgr/pwrmgr.core.tpl | 6 ++++++ hw/ip_templates/pwrmgr/pwrmgr_components.core | 6 ++++++ hw/ip_templates/rstmgr/rstmgr.core.tpl | 6 ++++++ hw/ip_templates/rv_plic/rv_plic.core.tpl | 6 ++++++ hw/lint/common.core | 4 ---- hw/top_darjeeling/chip_darjeeling_asic.core | 6 ++++++ hw/top_darjeeling/ip/ast/ast.core | 6 ++++++ hw/top_darjeeling/ip/sensor_ctrl/sensor_ctrl.core | 6 ++++++ .../ip_autogen/alert_handler/alert_handler.core | 6 ++++++ hw/top_darjeeling/ip_autogen/clkmgr/clkmgr.core | 6 ++++++ hw/top_darjeeling/ip_autogen/pinmux/pinmux.core | 6 ++++++ hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core | 6 ++++++ hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_components.core | 6 ++++++ hw/top_darjeeling/ip_autogen/rstmgr/rstmgr.core | 6 ++++++ hw/top_darjeeling/ip_autogen/rv_plic/rv_plic.core | 6 ++++++ hw/top_darjeeling/top_darjeeling.core | 6 ++++++ hw/top_earlgrey/chip_earlgrey_asic.core | 6 ++++++ hw/top_earlgrey/chip_earlgrey_cw310.core | 6 ++++++ hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core | 6 ++++++ hw/top_earlgrey/chip_earlgrey_cw340.core | 6 ++++++ hw/top_earlgrey/chip_earlgrey_verilator.core | 6 ++++++ hw/top_earlgrey/dv/verilator/chip_sim.core | 6 ++++++ hw/top_earlgrey/ip/ast/ast.core | 6 ++++++ hw/top_earlgrey/ip/sensor_ctrl/sensor_ctrl.core | 6 ++++++ hw/top_earlgrey/ip_autogen/alert_handler/alert_handler.core | 6 ++++++ hw/top_earlgrey/ip_autogen/clkmgr/clkmgr.core | 6 ++++++ hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core | 6 ++++++ hw/top_earlgrey/ip_autogen/pinmux/pinmux.core | 6 ++++++ hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core | 6 ++++++ hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core | 6 ++++++ hw/top_earlgrey/ip_autogen/rstmgr/rstmgr.core | 6 ++++++ hw/top_earlgrey/ip_autogen/rv_plic/rv_plic.core | 6 ++++++ hw/top_earlgrey/top_earlgrey.core | 6 ++++++ 86 files changed, 509 insertions(+), 4 deletions(-) diff --git a/hw/ip/adc_ctrl/adc_ctrl.core b/hw/ip/adc_ctrl/adc_ctrl.core index a75aed73b7814..404a6c05f4825 100644 --- a/hw/ip/adc_ctrl/adc_ctrl.core +++ b/hw/ip/adc_ctrl/adc_ctrl.core @@ -41,6 +41,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -59,6 +63,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/aes/aes.core b/hw/ip/aes/aes.core index 5c19412af405f..1b12eb5115a90 100644 --- a/hw/ip/aes/aes.core +++ b/hw/ip/aes/aes.core @@ -79,6 +79,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -97,6 +101,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/aes/aes_wrap.core b/hw/ip/aes/aes_wrap.core index 70e1e807526d5..3f8e37f91a76a 100644 --- a/hw/ip/aes/aes_wrap.core +++ b/hw/ip/aes/aes_wrap.core @@ -36,6 +36,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -54,6 +58,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/aon_timer/aon_timer.core b/hw/ip/aon_timer/aon_timer.core index 9c2c8fa827c50..ae7ccb396a2ec 100644 --- a/hw/ip/aon_timer/aon_timer.core +++ b/hw/ip/aon_timer/aon_timer.core @@ -42,6 +42,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -59,6 +63,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/ascon/ascon.core b/hw/ip/ascon/ascon.core index 565a2c7579696..1f97ffa53b132 100644 --- a/hw/ip/ascon/ascon.core +++ b/hw/ip/ascon/ascon.core @@ -46,6 +46,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -64,6 +68,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/csrng/csrng.core b/hw/ip/csrng/csrng.core index 8d23ac97da87d..327c7344d7d7c 100644 --- a/hw/ip/csrng/csrng.core +++ b/hw/ip/csrng/csrng.core @@ -50,6 +50,9 @@ filesets: - lint/csrng.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all parameters: SYNTHESIS: @@ -68,6 +71,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/dma/dma.core b/hw/ip/dma/dma.core index c0f25a059080a..401cdc64cab27 100644 --- a/hw/ip/dma/dma.core +++ b/hw/ip/dma/dma.core @@ -42,6 +42,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -59,6 +63,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/edn/edn.core b/hw/ip/edn/edn.core index f67b0c75d68bc..52abcadacf7f9 100644 --- a/hw/ip/edn/edn.core +++ b/hw/ip/edn/edn.core @@ -41,6 +41,10 @@ filesets: - lint/edn.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: @@ -59,6 +63,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/entropy_src/entropy_src.core b/hw/ip/entropy_src/entropy_src.core index a00f592b9515a..0bd277a98ebf8 100644 --- a/hw/ip/entropy_src/entropy_src.core +++ b/hw/ip/entropy_src/entropy_src.core @@ -60,6 +60,10 @@ filesets: - lint/entropy_src.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: @@ -78,6 +82,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/gpio/gpio.core b/hw/ip/gpio/gpio.core index a05201aece722..d593bf3e4ca01 100644 --- a/hw/ip/gpio/gpio.core +++ b/hw/ip/gpio/gpio.core @@ -40,6 +40,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -58,6 +62,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/hmac/hmac.core b/hw/ip/hmac/hmac.core index 97d1c14899975..25b7928be226c 100644 --- a/hw/ip/hmac/hmac.core +++ b/hw/ip/hmac/hmac.core @@ -40,6 +40,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -57,6 +61,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/i2c/i2c.core b/hw/ip/i2c/i2c.core index 4ec62eb5fee07..0133df46ebaf2 100644 --- a/hw/ip/i2c/i2c.core +++ b/hw/ip/i2c/i2c.core @@ -49,6 +49,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -67,6 +71,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/keymgr/keymgr.core b/hw/ip/keymgr/keymgr.core index eb6a8a38ec66d..6e346d4bbf2b8 100644 --- a/hw/ip/keymgr/keymgr.core +++ b/hw/ip/keymgr/keymgr.core @@ -57,6 +57,10 @@ filesets: - lint/keymgr.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -74,6 +78,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/keymgr_dpe/keymgr_dpe.core b/hw/ip/keymgr_dpe/keymgr_dpe.core index 67c4f1f6e5f9a..1f8413253c3ec 100644 --- a/hw/ip/keymgr_dpe/keymgr_dpe.core +++ b/hw/ip/keymgr_dpe/keymgr_dpe.core @@ -49,6 +49,10 @@ filesets: - lint/keymgr_dpe.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -66,6 +70,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/kmac/kmac.core b/hw/ip/kmac/kmac.core index c4472c4e1ddea..6f12d0e880f07 100644 --- a/hw/ip/kmac/kmac.core +++ b/hw/ip/kmac/kmac.core @@ -60,6 +60,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -83,6 +87,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/kmac/kmac_reduced.core b/hw/ip/kmac/kmac_reduced.core index 85e69dde472c1..d3ebfa79fc671 100644 --- a/hw/ip/kmac/kmac_reduced.core +++ b/hw/ip/kmac/kmac_reduced.core @@ -36,6 +36,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -59,6 +63,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/kmac/sha3.core b/hw/ip/kmac/sha3.core index 6892a7cadd333..71fc23257c3ae 100644 --- a/hw/ip/kmac/sha3.core +++ b/hw/ip/kmac/sha3.core @@ -42,6 +42,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -65,6 +69,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/lc_ctrl/lc_ctrl.core b/hw/ip/lc_ctrl/lc_ctrl.core index 3b8837d4264e1..642a8ccfd231a 100644 --- a/hw/ip/lc_ctrl/lc_ctrl.core +++ b/hw/ip/lc_ctrl/lc_ctrl.core @@ -60,6 +60,10 @@ filesets: - lint/lc_ctrl.vbl file_type: veribleLintWaiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -78,6 +82,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/lc_ctrl/lc_ctrl_pkg.core b/hw/ip/lc_ctrl/lc_ctrl_pkg.core index 425b2c7baee30..006aac8189dca 100644 --- a/hw/ip/lc_ctrl/lc_ctrl_pkg.core +++ b/hw/ip/lc_ctrl/lc_ctrl_pkg.core @@ -39,6 +39,10 @@ filesets: - lint/lc_ctrl_pkg.vbl file_type: veribleLintWaiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -57,6 +61,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/mbx/mbx.core b/hw/ip/mbx/mbx.core index fa24ff79d1627..a6fb36b39495b 100644 --- a/hw/ip/mbx/mbx.core +++ b/hw/ip/mbx/mbx.core @@ -47,6 +47,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -64,6 +68,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/otbn/otbn.core b/hw/ip/otbn/otbn.core index 488fe1490b4b1..b9b51b9db4fa9 100644 --- a/hw/ip/otbn/otbn.core +++ b/hw/ip/otbn/otbn.core @@ -80,6 +80,10 @@ filesets: - lint/otbn.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -97,6 +101,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/otp_ctrl/otp_ctrl.core b/hw/ip/otp_ctrl/otp_ctrl.core index f94c950317da6..e5a86e7288117 100644 --- a/hw/ip/otp_ctrl/otp_ctrl.core +++ b/hw/ip/otp_ctrl/otp_ctrl.core @@ -69,6 +69,10 @@ filesets: - lint/otp_ctrl.vbl file_type: veribleLintWaiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -87,6 +91,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/otp_ctrl/otp_ctrl_pkg.core b/hw/ip/otp_ctrl/otp_ctrl_pkg.core index 12628f906ee2b..1da4ee1893dcd 100644 --- a/hw/ip/otp_ctrl/otp_ctrl_pkg.core +++ b/hw/ip/otp_ctrl/otp_ctrl_pkg.core @@ -44,6 +44,10 @@ filesets: - lint/otp_ctrl_pkg.vbl file_type: veribleLintWaiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -62,6 +66,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/pattgen/pattgen.core b/hw/ip/pattgen/pattgen.core index d4cb631fb86c2..b931704b15bd1 100644 --- a/hw/ip/pattgen/pattgen.core +++ b/hw/ip/pattgen/pattgen.core @@ -50,6 +50,10 @@ filesets: # - dv/tb/pattgen_bind.sv # file_type: systemVerilogSource + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -78,6 +82,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/pwm/pwm.core b/hw/ip/pwm/pwm.core index 3d18758715b80..d0d9a27e92b20 100644 --- a/hw/ip/pwm/pwm.core +++ b/hw/ip/pwm/pwm.core @@ -42,6 +42,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -60,6 +64,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/rom_ctrl/rom_ctrl.core b/hw/ip/rom_ctrl/rom_ctrl.core index 07aa0faf55983..66396509b2ac1 100644 --- a/hw/ip/rom_ctrl/rom_ctrl.core +++ b/hw/ip/rom_ctrl/rom_ctrl.core @@ -49,6 +49,10 @@ filesets: - lint/rom_ctrl.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -65,6 +69,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/rv_core_ibex/rv_core_ibex.core b/hw/ip/rv_core_ibex/rv_core_ibex.core index a67b0ba628079..20fef25861eb0 100644 --- a/hw/ip/rv_core_ibex/rv_core_ibex.core +++ b/hw/ip/rv_core_ibex/rv_core_ibex.core @@ -49,6 +49,10 @@ filesets: # common waivers - lowrisc:lint:common + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -67,6 +71,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/rv_dm/rv_dm.core b/hw/ip/rv_dm/rv_dm.core index eed11cb417f86..2b39db872d094 100644 --- a/hw/ip/rv_dm/rv_dm.core +++ b/hw/ip/rv_dm/rv_dm.core @@ -48,6 +48,10 @@ filesets: # common waivers - lowrisc:lint:common + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: NrHarts: datatype: int @@ -71,6 +75,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/rv_timer/rv_timer.core b/hw/ip/rv_timer/rv_timer.core index 59469652f8762..62025dbb773ae 100644 --- a/hw/ip/rv_timer/rv_timer.core +++ b/hw/ip/rv_timer/rv_timer.core @@ -40,6 +40,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -57,6 +61,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/soc_dbg_ctrl/soc_dbg_ctrl.core b/hw/ip/soc_dbg_ctrl/soc_dbg_ctrl.core index ad68307ca6ebb..653ef16c4aa98 100644 --- a/hw/ip/soc_dbg_ctrl/soc_dbg_ctrl.core +++ b/hw/ip/soc_dbg_ctrl/soc_dbg_ctrl.core @@ -43,6 +43,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -60,6 +64,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/soc_dbg_ctrl/soc_dbg_ctrl_decode.core b/hw/ip/soc_dbg_ctrl/soc_dbg_ctrl_decode.core index b49edc9406f60..9e0c1fed3f7d8 100644 --- a/hw/ip/soc_dbg_ctrl/soc_dbg_ctrl_decode.core +++ b/hw/ip/soc_dbg_ctrl/soc_dbg_ctrl_decode.core @@ -36,6 +36,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -53,6 +57,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/spi_device/spi_device.core b/hw/ip/spi_device/spi_device.core index 496373d2e525e..a7c988f1fe295 100644 --- a/hw/ip/spi_device/spi_device.core +++ b/hw/ip/spi_device/spi_device.core @@ -67,6 +67,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -85,6 +89,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/spi_host/spi_host.core b/hw/ip/spi_host/spi_host.core index db52aeb058a1c..f6e801cc5f22b 100644 --- a/hw/ip/spi_host/spi_host.core +++ b/hw/ip/spi_host/spi_host.core @@ -52,6 +52,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -70,6 +74,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/sram_ctrl/sram_ctrl.core b/hw/ip/sram_ctrl/sram_ctrl.core index e7b0950f83042..a786517f5acd4 100644 --- a/hw/ip/sram_ctrl/sram_ctrl.core +++ b/hw/ip/sram_ctrl/sram_ctrl.core @@ -41,6 +41,10 @@ filesets: - lint/sram_ctrl.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -58,6 +62,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/sysrst_ctrl/sysrst_ctrl.core b/hw/ip/sysrst_ctrl/sysrst_ctrl.core index 4ffa1d40587e9..884c8db164a30 100644 --- a/hw/ip/sysrst_ctrl/sysrst_ctrl.core +++ b/hw/ip/sysrst_ctrl/sysrst_ctrl.core @@ -40,6 +40,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -61,6 +65,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/tlul/adapter_dmi.core b/hw/ip/tlul/adapter_dmi.core index 60cc8475f2db2..1d7bf73c5d641 100644 --- a/hw/ip/tlul/adapter_dmi.core +++ b/hw/ip/tlul/adapter_dmi.core @@ -38,6 +38,10 @@ filesets: # common waivers - lowrisc:lint:common + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -56,6 +60,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/tlul/adapter_host.core b/hw/ip/tlul/adapter_host.core index d08ee136e20e6..4926a9192e046 100644 --- a/hw/ip/tlul/adapter_host.core +++ b/hw/ip/tlul/adapter_host.core @@ -37,6 +37,10 @@ filesets: # common waivers - lowrisc:lint:common + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -55,6 +59,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/tlul/adapter_reg.core b/hw/ip/tlul/adapter_reg.core index aab7657be11de..891bd79187d4a 100644 --- a/hw/ip/tlul/adapter_reg.core +++ b/hw/ip/tlul/adapter_reg.core @@ -37,6 +37,10 @@ filesets: # common waivers - lowrisc:lint:common + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -55,6 +59,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/tlul/adapter_sram.core b/hw/ip/tlul/adapter_sram.core index 7107a0075863c..32cbcdbc2f572 100644 --- a/hw/ip/tlul/adapter_sram.core +++ b/hw/ip/tlul/adapter_sram.core @@ -37,6 +37,10 @@ filesets: # common waivers - lowrisc:lint:common + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -55,6 +59,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/tlul/jtag_dtm.core b/hw/ip/tlul/jtag_dtm.core index 9341a80c47b4e..254dbd11ecb4a 100644 --- a/hw/ip/tlul/jtag_dtm.core +++ b/hw/ip/tlul/jtag_dtm.core @@ -37,6 +37,10 @@ filesets: # common waivers - lowrisc:lint:common + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -54,6 +58,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/tlul/request_loopback.core b/hw/ip/tlul/request_loopback.core index e06840d03e6d5..f2453bbb8702c 100644 --- a/hw/ip/tlul/request_loopback.core +++ b/hw/ip/tlul/request_loopback.core @@ -36,6 +36,10 @@ filesets: # common waivers - lowrisc:lint:common + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -54,6 +58,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/tlul/socket_1n.core b/hw/ip/tlul/socket_1n.core index a4c2e3853d390..f3dece51a3d1a 100644 --- a/hw/ip/tlul/socket_1n.core +++ b/hw/ip/tlul/socket_1n.core @@ -37,6 +37,10 @@ filesets: # common waivers - lowrisc:lint:common + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -55,6 +59,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/tlul/socket_m1.core b/hw/ip/tlul/socket_m1.core index e8e3af59acadc..1e6fa0ad1565b 100644 --- a/hw/ip/tlul/socket_m1.core +++ b/hw/ip/tlul/socket_m1.core @@ -37,6 +37,10 @@ filesets: # common waivers - lowrisc:lint:common + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -55,6 +59,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/tlul/sram2tlul.core b/hw/ip/tlul/sram2tlul.core index f4489900b2aa0..c0ce6772d195d 100644 --- a/hw/ip/tlul/sram2tlul.core +++ b/hw/ip/tlul/sram2tlul.core @@ -35,6 +35,10 @@ filesets: # common waivers - lowrisc:lint:common + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -53,6 +57,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/tlul/tlul_lc_gate.core b/hw/ip/tlul/tlul_lc_gate.core index efb0b1ec323ff..c8098b2306a5d 100644 --- a/hw/ip/tlul/tlul_lc_gate.core +++ b/hw/ip/tlul/tlul_lc_gate.core @@ -37,6 +37,10 @@ filesets: # common waivers - lowrisc:lint:common + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -55,6 +59,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/tlul/trans_intg.core b/hw/ip/tlul/trans_intg.core index 50b9dcd8b608e..dfae766d73e14 100644 --- a/hw/ip/tlul/trans_intg.core +++ b/hw/ip/tlul/trans_intg.core @@ -37,6 +37,10 @@ filesets: # common waivers - lowrisc:lint:common + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -55,6 +59,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/uart/uart.core b/hw/ip/uart/uart.core index 6f6c0773ce683..d2ae6608bc1b7 100644 --- a/hw/ip/uart/uart.core +++ b/hw/ip/uart/uart.core @@ -43,6 +43,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -61,6 +65,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/usbdev/usb_fs_nb_pe.core b/hw/ip/usbdev/usb_fs_nb_pe.core index db1405a3cc9fd..b2135f40c3485 100644 --- a/hw/ip/usbdev/usb_fs_nb_pe.core +++ b/hw/ip/usbdev/usb_fs_nb_pe.core @@ -40,6 +40,10 @@ filesets: # common waivers - lowrisc:lint:common + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -58,6 +62,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip/usbdev/usbdev.core b/hw/ip/usbdev/usbdev.core index caea1d69b3043..92aea0536d37d 100644 --- a/hw/ip/usbdev/usbdev.core +++ b/hw/ip/usbdev/usbdev.core @@ -49,6 +49,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -67,6 +71,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip_templates/alert_handler/alert_handler.core.tpl b/hw/ip_templates/alert_handler/alert_handler.core.tpl index 5085d5cb89418..79011ad87432e 100644 --- a/hw/ip_templates/alert_handler/alert_handler.core.tpl +++ b/hw/ip_templates/alert_handler/alert_handler.core.tpl @@ -14,6 +14,10 @@ filesets: - ${instance_vlnv("lowrisc:ip_interfaces:alert_handler_reg:0.1")} file_type: systemVerilogSource + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -29,6 +33,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip_templates/clkmgr/clkmgr.core.tpl b/hw/ip_templates/clkmgr/clkmgr.core.tpl index 2ae17f2b1c725..7221d490154ea 100644 --- a/hw/ip_templates/clkmgr/clkmgr.core.tpl +++ b/hw/ip_templates/clkmgr/clkmgr.core.tpl @@ -48,6 +48,10 @@ filesets: - lint/clkmgr.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -64,6 +68,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl b/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl index c1f23f6d2f90c..e7d4c1a75cf90 100644 --- a/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl +++ b/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl @@ -72,6 +72,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -90,6 +94,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip_templates/pinmux/pinmux.core.tpl b/hw/ip_templates/pinmux/pinmux.core.tpl index 1653720140fc4..a57089fd428cb 100644 --- a/hw/ip_templates/pinmux/pinmux.core.tpl +++ b/hw/ip_templates/pinmux/pinmux.core.tpl @@ -58,6 +58,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -75,6 +79,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip_templates/pwrmgr/pwrmgr.core.tpl b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl index ff456a51e7e09..b875b0dc7d6bc 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr.core.tpl +++ b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl @@ -40,6 +40,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -58,6 +62,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip_templates/pwrmgr/pwrmgr_components.core b/hw/ip_templates/pwrmgr/pwrmgr_components.core index bf144fe1c9b5d..477bd370dbe40 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr_components.core +++ b/hw/ip_templates/pwrmgr/pwrmgr_components.core @@ -53,6 +53,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -71,6 +75,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip_templates/rstmgr/rstmgr.core.tpl b/hw/ip_templates/rstmgr/rstmgr.core.tpl index 035ed729c703b..699616c17c655 100644 --- a/hw/ip_templates/rstmgr/rstmgr.core.tpl +++ b/hw/ip_templates/rstmgr/rstmgr.core.tpl @@ -45,6 +45,10 @@ filesets: - lint/rstmgr.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -62,6 +66,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/ip_templates/rv_plic/rv_plic.core.tpl b/hw/ip_templates/rv_plic/rv_plic.core.tpl index 0787cf300a53f..0f4dd5f581b42 100644 --- a/hw/ip_templates/rv_plic/rv_plic.core.tpl +++ b/hw/ip_templates/rv_plic/rv_plic.core.tpl @@ -20,6 +20,10 @@ filesets: - rtl/${module_instance_name}.sv file_type: systemVerilogSource + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -34,6 +38,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/lint/common.core b/hw/lint/common.core index 6a5c19dbcfcc9..20338eaf11d62 100644 --- a/hw/lint/common.core +++ b/hw/lint/common.core @@ -6,15 +6,11 @@ name: "lowrisc:lint:common:0.1" description: "Common waivers" filesets: files_verilator: - depend: - - lowrisc:prim_generic:all files: - tools/verilator/common.vlt file_type: vlt files_ascentlint: - depend: - - lowrisc:prim_generic:all files: - tools/ascentlint/common.waiver: {file_type: waiver} - tools/ascentlint/ascentlint-config.tcl: {file_type: tclSource} diff --git a/hw/top_darjeeling/chip_darjeeling_asic.core b/hw/top_darjeeling/chip_darjeeling_asic.core index b436ac378b93c..b4b23c717fceb 100644 --- a/hw/top_darjeeling/chip_darjeeling_asic.core +++ b/hw/top_darjeeling/chip_darjeeling_asic.core @@ -40,6 +40,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -61,6 +65,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_darjeeling/ip/ast/ast.core b/hw/top_darjeeling/ip/ast/ast.core index 06360ba9493b7..6dce79b7a6487 100644 --- a/hw/top_darjeeling/ip/ast/ast.core +++ b/hw/top_darjeeling/ip/ast/ast.core @@ -78,6 +78,10 @@ filesets: # common waivers - lowrisc:lint:common + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -107,6 +111,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_darjeeling/ip/sensor_ctrl/sensor_ctrl.core b/hw/top_darjeeling/ip/sensor_ctrl/sensor_ctrl.core index 5ec43c8f12e1e..124dc31e92102 100644 --- a/hw/top_darjeeling/ip/sensor_ctrl/sensor_ctrl.core +++ b/hw/top_darjeeling/ip/sensor_ctrl/sensor_ctrl.core @@ -32,6 +32,10 @@ filesets: - lint/sensor_ctrl.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -49,6 +53,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/alert_handler.core b/hw/top_darjeeling/ip_autogen/alert_handler/alert_handler.core index 0efc94e28679a..cbfeb5f374853 100644 --- a/hw/top_darjeeling/ip_autogen/alert_handler/alert_handler.core +++ b/hw/top_darjeeling/ip_autogen/alert_handler/alert_handler.core @@ -14,6 +14,10 @@ filesets: - lowrisc:opentitan:top_darjeeling_alert_handler_reg:0.1 file_type: systemVerilogSource + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -29,6 +33,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr.core b/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr.core index dbca598dc0dcb..8d8e35098e7e1 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr.core +++ b/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr.core @@ -48,6 +48,10 @@ filesets: - lint/clkmgr.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -64,6 +68,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_darjeeling/ip_autogen/pinmux/pinmux.core b/hw/top_darjeeling/ip_autogen/pinmux/pinmux.core index 6080281ea350e..a3399b8b6d5b7 100644 --- a/hw/top_darjeeling/ip_autogen/pinmux/pinmux.core +++ b/hw/top_darjeeling/ip_autogen/pinmux/pinmux.core @@ -55,6 +55,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -72,6 +76,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core index bd571df415d59..63feaef6ef482 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core @@ -40,6 +40,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -58,6 +62,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_components.core b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_components.core index bf144fe1c9b5d..477bd370dbe40 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_components.core +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_components.core @@ -53,6 +53,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -71,6 +75,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr.core b/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr.core index 3ae8bb48fa0e1..bd646d7e01840 100644 --- a/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr.core +++ b/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr.core @@ -45,6 +45,10 @@ filesets: - lint/rstmgr.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -62,6 +66,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/rv_plic.core b/hw/top_darjeeling/ip_autogen/rv_plic/rv_plic.core index ea68a50321017..714cbd73ebee4 100644 --- a/hw/top_darjeeling/ip_autogen/rv_plic/rv_plic.core +++ b/hw/top_darjeeling/ip_autogen/rv_plic/rv_plic.core @@ -17,6 +17,10 @@ filesets: - rtl/rv_plic.sv file_type: systemVerilogSource + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -31,6 +35,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_darjeeling/top_darjeeling.core b/hw/top_darjeeling/top_darjeeling.core index 108548bbcb529..dda689bd2a43f 100644 --- a/hw/top_darjeeling/top_darjeeling.core +++ b/hw/top_darjeeling/top_darjeeling.core @@ -93,6 +93,10 @@ filesets: file_type: veribleLintWaiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -116,6 +120,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_earlgrey/chip_earlgrey_asic.core b/hw/top_earlgrey/chip_earlgrey_asic.core index af1d800e7e987..a770000bf9977 100644 --- a/hw/top_earlgrey/chip_earlgrey_asic.core +++ b/hw/top_earlgrey/chip_earlgrey_asic.core @@ -42,6 +42,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -65,6 +69,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_earlgrey/chip_earlgrey_cw310.core b/hw/top_earlgrey/chip_earlgrey_cw310.core index 2422902ab102d..7c84b70e3b713 100644 --- a/hw/top_earlgrey/chip_earlgrey_cw310.core +++ b/hw/top_earlgrey/chip_earlgrey_cw310.core @@ -47,6 +47,10 @@ filesets: - lint/chip_earlgrey_cw310.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: # XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1 # directory. It's best to pass it as absolute path when invoking fusesoc, e.g. @@ -107,6 +111,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true - AST_BYPASS_CLK=true diff --git a/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core b/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core index 764370d85be36..effe28e7cb38e 100644 --- a/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core +++ b/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core @@ -49,6 +49,10 @@ filesets: - lint/chip_earlgrey_cw310.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: # XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1 # directory. It's best to pass it as absolute path when invoking fusesoc, e.g. @@ -109,6 +113,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true - AST_BYPASS_CLK=true diff --git a/hw/top_earlgrey/chip_earlgrey_cw340.core b/hw/top_earlgrey/chip_earlgrey_cw340.core index 9fbbf891d9ff2..471cb7cb307c0 100644 --- a/hw/top_earlgrey/chip_earlgrey_cw340.core +++ b/hw/top_earlgrey/chip_earlgrey_cw340.core @@ -44,6 +44,10 @@ filesets: - lowrisc:lint:comportable file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: # XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1 # directory. It's best to pass it as absolute path when invoking fusesoc, e.g. @@ -104,6 +108,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true - AST_BYPASS_CLK=true diff --git a/hw/top_earlgrey/chip_earlgrey_verilator.core b/hw/top_earlgrey/chip_earlgrey_verilator.core index 48d115e54412a..ff0f7f1c138b3 100644 --- a/hw/top_earlgrey/chip_earlgrey_verilator.core +++ b/hw/top_earlgrey/chip_earlgrey_verilator.core @@ -19,6 +19,10 @@ filesets: files: - rtl/chip_earlgrey_verilator.sv: { file_type: systemVerilogSource } + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: AST_BYPASS_CLK: datatype: bool @@ -41,6 +45,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint tools: verilator: mode: lint-only diff --git a/hw/top_earlgrey/dv/verilator/chip_sim.core b/hw/top_earlgrey/dv/verilator/chip_sim.core index b491a73602529..e3b89fac167ae 100644 --- a/hw/top_earlgrey/dv/verilator/chip_sim.core +++ b/hw/top_earlgrey/dv/verilator/chip_sim.core @@ -30,6 +30,10 @@ filesets: - chip_sim_tb.sv: { file_type: systemVerilogSource } - chip_sim_tb.cc: { file_type: cppSource } + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: # For value definition, please see ip/prim/rtl/prim_pkg.sv PRIM_DEFAULT_IMPL: @@ -126,6 +130,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint tools: verilator: mode: lint-only diff --git a/hw/top_earlgrey/ip/ast/ast.core b/hw/top_earlgrey/ip/ast/ast.core index d517b94fe62fe..60a56dd440154 100644 --- a/hw/top_earlgrey/ip/ast/ast.core +++ b/hw/top_earlgrey/ip/ast/ast.core @@ -82,6 +82,10 @@ filesets: - lint/ast.vbl file_type: veribleLintWaiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: @@ -112,6 +116,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_earlgrey/ip/sensor_ctrl/sensor_ctrl.core b/hw/top_earlgrey/ip/sensor_ctrl/sensor_ctrl.core index cc92505c31362..5ab0cde232596 100644 --- a/hw/top_earlgrey/ip/sensor_ctrl/sensor_ctrl.core +++ b/hw/top_earlgrey/ip/sensor_ctrl/sensor_ctrl.core @@ -33,6 +33,10 @@ filesets: - lint/sensor_ctrl.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -50,6 +54,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/alert_handler.core b/hw/top_earlgrey/ip_autogen/alert_handler/alert_handler.core index 853c597598cfc..c758e06aa55d4 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/alert_handler.core +++ b/hw/top_earlgrey/ip_autogen/alert_handler/alert_handler.core @@ -14,6 +14,10 @@ filesets: - lowrisc:opentitan:top_earlgrey_alert_handler_reg:0.1 file_type: systemVerilogSource + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -29,6 +33,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/clkmgr.core b/hw/top_earlgrey/ip_autogen/clkmgr/clkmgr.core index bbf3e7ff4bf82..8e5c8d7beea76 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/clkmgr.core +++ b/hw/top_earlgrey/ip_autogen/clkmgr/clkmgr.core @@ -48,6 +48,10 @@ filesets: - lint/clkmgr.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -64,6 +68,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core index 6e585c4dcccc8..76ef9d698daba 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core @@ -72,6 +72,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -90,6 +94,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_earlgrey/ip_autogen/pinmux/pinmux.core b/hw/top_earlgrey/ip_autogen/pinmux/pinmux.core index e20df06cd9210..a0a44d1d8ab67 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/pinmux.core +++ b/hw/top_earlgrey/ip_autogen/pinmux/pinmux.core @@ -56,6 +56,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -73,6 +77,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core index e02527dbc422d..d2203d22e3d9d 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core @@ -40,6 +40,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -58,6 +62,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core index bf144fe1c9b5d..477bd370dbe40 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core @@ -53,6 +53,10 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -71,6 +75,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/rstmgr.core b/hw/top_earlgrey/ip_autogen/rstmgr/rstmgr.core index f4335faedef8a..07a67dc1cc7d0 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/rstmgr.core +++ b/hw/top_earlgrey/ip_autogen/rstmgr/rstmgr.core @@ -45,6 +45,10 @@ filesets: - lint/rstmgr.waiver file_type: waiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -62,6 +66,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/rv_plic.core b/hw/top_earlgrey/ip_autogen/rv_plic/rv_plic.core index cabf830aa856d..434117ff25686 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/rv_plic.core +++ b/hw/top_earlgrey/ip_autogen/rv_plic/rv_plic.core @@ -17,6 +17,10 @@ filesets: - rtl/rv_plic.sv file_type: systemVerilogSource + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -31,6 +35,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core index 49a1a40993ccf..3afd584894b54 100644 --- a/hw/top_earlgrey/top_earlgrey.core +++ b/hw/top_earlgrey/top_earlgrey.core @@ -92,6 +92,10 @@ filesets: file_type: veribleLintWaiver + files_lint: + depend: + - lowrisc:prim_generic:all + parameters: SYNTHESIS: datatype: bool @@ -121,6 +125,8 @@ targets: lint: <<: *default_target default_tool: verilator + filesets_append: + - files_lint parameters: - SYNTHESIS=true tools: From 566b93ee55149b1aafa66000a2126027528173db Mon Sep 17 00:00:00 2001 From: Alexander Williams Date: Tue, 17 Dec 2024 19:49:01 -0800 Subject: [PATCH 21/24] Revert "[hw,lint] Removed common lints from prims" This reverts commit 5808ba85ea4ddbae913f0f3db2310d9eb9fa7318. Signed-off-by: Alexander Williams --- hw/ip/prim_generic/prim_generic_and2.core | 18 ++++++++++++++++++ hw/ip/prim_generic/prim_generic_buf.core | 18 ++++++++++++++++++ hw/ip/prim_generic/prim_generic_clock_buf.core | 12 ++++++++++++ hw/ip/prim_generic/prim_generic_clock_div.core | 4 ++++ .../prim_generic_clock_gating.core | 12 ++++++++++++ hw/ip/prim_generic/prim_generic_clock_inv.core | 18 ++++++++++++++++++ .../prim_generic/prim_generic_clock_mux2.core | 12 ++++++++++++ hw/ip/prim_generic/prim_generic_flash.core | 12 ++++++++++++ hw/ip/prim_generic/prim_generic_flop.core | 18 ++++++++++++++++++ .../prim_generic/prim_generic_flop_2sync.core | 15 +++++++++++++++ hw/ip/prim_generic/prim_generic_flop_en.core | 18 ++++++++++++++++++ hw/ip/prim_generic/prim_generic_otp.core | 8 ++++++++ hw/ip/prim_generic/prim_generic_pad_attr.core | 18 ++++++++++++++++++ .../prim_generic/prim_generic_pad_wrapper.core | 12 ++++++++++++ hw/ip/prim_generic/prim_generic_ram_1p.core | 12 ++++++++++++ hw/ip/prim_generic/prim_generic_ram_1r1w.core | 12 ++++++++++++ hw/ip/prim_generic/prim_generic_ram_2p.core | 12 ++++++++++++ hw/ip/prim_generic/prim_generic_rom.core | 12 ++++++++++++ .../prim_generic/prim_generic_usb_diff_rx.core | 15 +++++++++++++++ hw/ip/prim_generic/prim_generic_xnor2.core | 18 ++++++++++++++++++ hw/ip/prim_generic/prim_generic_xor2.core | 18 ++++++++++++++++++ 21 files changed, 294 insertions(+) diff --git a/hw/ip/prim_generic/prim_generic_and2.core b/hw/ip/prim_generic/prim_generic_and2.core index f4047815b9797..e18e8b48a2d65 100644 --- a/hw/ip/prim_generic/prim_generic_and2.core +++ b/hw/ip/prim_generic/prim_generic_and2.core @@ -14,7 +14,25 @@ filesets: - rtl/prim_and2.sv file_type: systemVerilogSource + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_buf.core b/hw/ip/prim_generic/prim_generic_buf.core index d92ef6fd56047..9db9568d253eb 100644 --- a/hw/ip/prim_generic/prim_generic_buf.core +++ b/hw/ip/prim_generic/prim_generic_buf.core @@ -14,7 +14,25 @@ filesets: - rtl/prim_buf.sv file_type: systemVerilogSource + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_clock_buf.core b/hw/ip/prim_generic/prim_generic_clock_buf.core index a8a478cb721f3..d11883d9ea4f7 100644 --- a/hw/ip/prim_generic/prim_generic_clock_buf.core +++ b/hw/ip/prim_generic/prim_generic_clock_buf.core @@ -15,18 +15,30 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_clock_buf.vlt file_type: vlt files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_clock_buf.waiver file_type: waiver + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_clock_div.core b/hw/ip/prim_generic/prim_generic_clock_div.core index 26bddcc4f0d47..0c33b7398f10d 100644 --- a/hw/ip/prim_generic/prim_generic_clock_div.core +++ b/hw/ip/prim_generic/prim_generic_clock_div.core @@ -20,6 +20,9 @@ filesets: file_type: systemVerilogSource files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_clock_div.waiver file_type: waiver @@ -27,4 +30,5 @@ filesets: targets: default: filesets: + - tool_ascentlint ? (files_ascentlint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_clock_gating.core b/hw/ip/prim_generic/prim_generic_clock_gating.core index 5277c92a8739d..9d79c9d540303 100644 --- a/hw/ip/prim_generic/prim_generic_clock_gating.core +++ b/hw/ip/prim_generic/prim_generic_clock_gating.core @@ -15,18 +15,30 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_clock_gating.vlt file_type: vlt files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_clock_gating.waiver file_type: waiver + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_clock_inv.core b/hw/ip/prim_generic/prim_generic_clock_inv.core index 9dbe2b94195d0..399b220bb6f44 100644 --- a/hw/ip/prim_generic/prim_generic_clock_inv.core +++ b/hw/ip/prim_generic/prim_generic_clock_inv.core @@ -17,7 +17,25 @@ filesets: - rtl/prim_clock_inv.sv file_type: systemVerilogSource + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_clock_mux2.core b/hw/ip/prim_generic/prim_generic_clock_mux2.core index 7b524e31c08b0..de600aea58b3d 100644 --- a/hw/ip/prim_generic/prim_generic_clock_mux2.core +++ b/hw/ip/prim_generic/prim_generic_clock_mux2.core @@ -17,18 +17,30 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_clock_mux2.vlt file_type: vlt files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_clock_mux2.waiver file_type: waiver + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_flash.core b/hw/ip/prim_generic/prim_generic_flash.core index f620c63101565..13035b8278b46 100644 --- a/hw/ip/prim_generic/prim_generic_flash.core +++ b/hw/ip/prim_generic/prim_generic_flash.core @@ -23,18 +23,30 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_flash.vlt file_type: vlt files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_flash.waiver file_type: waiver + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_flop.core b/hw/ip/prim_generic/prim_generic_flop.core index 4b112de28a65b..e899f79042ee0 100644 --- a/hw/ip/prim_generic/prim_generic_flop.core +++ b/hw/ip/prim_generic/prim_generic_flop.core @@ -14,7 +14,25 @@ filesets: - rtl/prim_flop.sv file_type: systemVerilogSource + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_flop_2sync.core b/hw/ip/prim_generic/prim_generic_flop_2sync.core index 1864e470f0db5..a67519a8696f9 100644 --- a/hw/ip/prim_generic/prim_generic_flop_2sync.core +++ b/hw/ip/prim_generic/prim_generic_flop_2sync.core @@ -19,13 +19,28 @@ filesets: - rtl/prim_flop_2sync.sv file_type: systemVerilogSource + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_flop_2sync.waiver file_type: waiver + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: + - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_flop_en.core b/hw/ip/prim_generic/prim_generic_flop_en.core index 6212f98c6b27c..e1c70ecfc605a 100644 --- a/hw/ip/prim_generic/prim_generic_flop_en.core +++ b/hw/ip/prim_generic/prim_generic_flop_en.core @@ -16,7 +16,25 @@ filesets: - rtl/prim_flop_en.sv file_type: systemVerilogSource + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_otp.core b/hw/ip/prim_generic/prim_generic_otp.core index 87df633fc5029..70e12ce53bdbc 100644 --- a/hw/ip/prim_generic/prim_generic_otp.core +++ b/hw/ip/prim_generic/prim_generic_otp.core @@ -23,11 +23,17 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_otp.vlt file_type: vlt files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_otp.waiver file_type: waiver @@ -36,4 +42,6 @@ filesets: targets: default: filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_pad_attr.core b/hw/ip/prim_generic/prim_generic_pad_attr.core index c7107c8bbab88..c80c59e00dbf3 100644 --- a/hw/ip/prim_generic/prim_generic_pad_attr.core +++ b/hw/ip/prim_generic/prim_generic_pad_attr.core @@ -17,7 +17,25 @@ filesets: - rtl/prim_pad_attr.sv file_type: systemVerilogSource + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_pad_wrapper.core b/hw/ip/prim_generic/prim_generic_pad_wrapper.core index 3806226aaca43..764cd45f89ce3 100644 --- a/hw/ip/prim_generic/prim_generic_pad_wrapper.core +++ b/hw/ip/prim_generic/prim_generic_pad_wrapper.core @@ -18,18 +18,30 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_pad_wrapper.vlt file_type: vlt files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_pad_wrapper.waiver file_type: waiver + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_ram_1p.core b/hw/ip/prim_generic/prim_generic_ram_1p.core index 4ac9ed5db9fe1..661a96627b516 100644 --- a/hw/ip/prim_generic/prim_generic_ram_1p.core +++ b/hw/ip/prim_generic/prim_generic_ram_1p.core @@ -19,18 +19,30 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_ram_1p.vlt file_type: vlt files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_ram_1p.waiver file_type: waiver + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_ram_1r1w.core b/hw/ip/prim_generic/prim_generic_ram_1r1w.core index 2bb70f45c20b6..efcbc802748bd 100644 --- a/hw/ip/prim_generic/prim_generic_ram_1r1w.core +++ b/hw/ip/prim_generic/prim_generic_ram_1r1w.core @@ -19,18 +19,30 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_ram_1r1w.vlt file_type: vlt files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_ram_1r1w.waiver file_type: waiver + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_ram_2p.core b/hw/ip/prim_generic/prim_generic_ram_2p.core index 752ee36d62942..b246ce1164f30 100644 --- a/hw/ip/prim_generic/prim_generic_ram_2p.core +++ b/hw/ip/prim_generic/prim_generic_ram_2p.core @@ -19,18 +19,30 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_ram_2p.vlt file_type: vlt files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_ram_2p.waiver file_type: waiver + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_rom.core b/hw/ip/prim_generic/prim_generic_rom.core index ce371cda6e834..41d76d4fb95e4 100644 --- a/hw/ip/prim_generic/prim_generic_rom.core +++ b/hw/ip/prim_generic/prim_generic_rom.core @@ -19,18 +19,30 @@ filesets: file_type: systemVerilogSource files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_rom.vlt file_type: vlt files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_rom.waiver file_type: waiver + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_usb_diff_rx.core b/hw/ip/prim_generic/prim_generic_usb_diff_rx.core index 60279b061a57c..f77bdeee10838 100644 --- a/hw/ip/prim_generic/prim_generic_usb_diff_rx.core +++ b/hw/ip/prim_generic/prim_generic_usb_diff_rx.core @@ -14,13 +14,28 @@ filesets: - rtl/prim_usb_diff_rx.sv file_type: systemVerilogSource + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common files: - lint/prim_generic_usb_diff_rx.waiver file_type: waiver + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: + - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_xnor2.core b/hw/ip/prim_generic/prim_generic_xnor2.core index e7229318007d5..137af0183886b 100644 --- a/hw/ip/prim_generic/prim_generic_xnor2.core +++ b/hw/ip/prim_generic/prim_generic_xnor2.core @@ -14,7 +14,25 @@ filesets: - rtl/prim_xnor2.sv file_type: systemVerilogSource + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_xor2.core b/hw/ip/prim_generic/prim_generic_xor2.core index ebc0022600162..b77448326d5a9 100644 --- a/hw/ip/prim_generic/prim_generic_xor2.core +++ b/hw/ip/prim_generic/prim_generic_xor2.core @@ -14,7 +14,25 @@ filesets: - rtl/prim_xor2.sv file_type: systemVerilogSource + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + targets: default: filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl From 32eedc977f5a9b626b7a83a7284b02fe61052313 Mon Sep 17 00:00:00 2001 From: Alexander Williams Date: Wed, 18 Dec 2024 00:44:38 -0800 Subject: [PATCH 22/24] [prim,pwrmgr] Fix depends hierarchy for pwrmgr Ensure packages with constants are at the leaves of the dependency tree, so other cores may depend on them without creating cycles. Adjust the pwrmgr_reg core to depend on the pwrmgr_pkg core, with pwrmgr_reg_pkg moved to the pwrmgr_pkg core. Also split the mubi RTL implementations from the package with declarations and standalone utility functions. Signed-off-by: Alexander Williams --- hw/ip/prim/prim_mubi.core | 2 +- hw/ip/prim/prim_mubi_pkg.core | 45 +++++++++++++++++++ hw/ip/prim_generic/prim_generic_flash.core | 2 +- hw/ip/tlul/headers.core | 2 +- hw/ip_templates/pwrmgr/pwrmgr.core.tpl | 1 + hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl | 4 +- hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl | 4 +- .../ip_autogen/pwrmgr/pwrmgr.core | 1 + .../ip_autogen/pwrmgr/pwrmgr_pkg.core | 2 +- .../ip_autogen/pwrmgr/pwrmgr_reg.core | 4 +- hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core | 1 + .../ip_autogen/pwrmgr/pwrmgr_pkg.core | 3 +- .../ip_autogen/pwrmgr/pwrmgr_reg.core | 4 +- util/design/data/prim_mubi.core.tpl | 2 +- util/design/data/prim_mubi_pkg.core.tpl | 45 +++++++++++++++++++ util/design/mubi/prim_mubi.py | 3 ++ 16 files changed, 110 insertions(+), 15 deletions(-) create mode 100644 hw/ip/prim/prim_mubi_pkg.core create mode 100644 util/design/data/prim_mubi_pkg.core.tpl diff --git a/hw/ip/prim/prim_mubi.core b/hw/ip/prim/prim_mubi.core index 45aa85f7aec6c..f8d8cdd0b604f 100644 --- a/hw/ip/prim/prim_mubi.core +++ b/hw/ip/prim/prim_mubi.core @@ -16,8 +16,8 @@ filesets: - lowrisc:prim:assert - lowrisc:prim:buf - lowrisc:prim:flop + - lowrisc:prim:mubi_pkg files: - - rtl/prim_mubi_pkg.sv - rtl/prim_mubi4_sender.sv - rtl/prim_mubi4_sync.sv - rtl/prim_mubi4_dec.sv diff --git a/hw/ip/prim/prim_mubi_pkg.core b/hw/ip/prim/prim_mubi_pkg.core new file mode 100644 index 0000000000000..57a1f61a2eebe --- /dev/null +++ b/hw/ip/prim/prim_mubi_pkg.core @@ -0,0 +1,45 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +# PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +# +# util/design/gen-mubi.py +# +name: "lowrisc:prim:mubi_pkg:0.1" +description: "Multibit types and functions" +filesets: + files_rtl: + depend: + - lowrisc:prim:assert + files: + - rtl/prim_mubi_pkg.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/prim_mubi.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_flash.core b/hw/ip/prim_generic/prim_generic_flash.core index 13035b8278b46..3120181d4b09f 100644 --- a/hw/ip/prim_generic/prim_generic_flash.core +++ b/hw/ip/prim_generic/prim_generic_flash.core @@ -11,7 +11,7 @@ virtual: filesets: files_rtl: depend: - - lowrisc:ip:tlul + - lowrisc:tlul:headers - lowrisc:prim:ram_1p - "fileset_partner ? (partner:systems:ast_pkg)" - "!fileset_partner ? (lowrisc:systems:ast_pkg)" diff --git a/hw/ip/tlul/headers.core b/hw/ip/tlul/headers.core index 3da0e1c75e2ef..2f2e722535b3f 100644 --- a/hw/ip/tlul/headers.core +++ b/hw/ip/tlul/headers.core @@ -10,7 +10,7 @@ filesets: depend: - lowrisc:constants:top_pkg - lowrisc:prim:secded - - lowrisc:prim:mubi + - lowrisc:prim:mubi_pkg files: - rtl/tlul_pkg.sv file_type: systemVerilogSource diff --git a/hw/ip_templates/pwrmgr/pwrmgr.core.tpl b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl index b875b0dc7d6bc..28f011e02168e 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr.core.tpl +++ b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl @@ -12,6 +12,7 @@ filesets: depend: - ${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1")} - ${instance_vlnv("lowrisc:ip:pwrmgr_reg:0.1")} + - lowrisc:ip:rom_ctrl_pkg - lowrisc:ip:rv_core_ibex_pkg - lowrisc:ip:pwrmgr_component file_type: systemVerilogSource diff --git a/hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl b/hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl index cdf252d74038f..8f848f9b665ff 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl +++ b/hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl @@ -9,12 +9,12 @@ virtual: filesets: files_rtl: - depend: - - ${instance_vlnv("lowrisc:ip:pwrmgr_reg")} % if wait_for_external_reset: + depend: - lowrisc:ip:rom_ctrl_pkg % endif files: + - rtl/pwrmgr_reg_pkg.sv - rtl/pwrmgr_pkg.sv file_type: systemVerilogSource diff --git a/hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl b/hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl index 886a9c9fc6fb6..e4de42ba0cad3 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl +++ b/hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl @@ -10,11 +10,11 @@ virtual: filesets: files_rtl: depend: - - lowrisc:tlul:headers - lowrisc:ip:tlul + - ${instance_vlnv("lowrisc:ip:pwrmgr_pkg")} - lowrisc:prim:subreg + - lowrisc:tlul:headers files: - - rtl/pwrmgr_reg_pkg.sv - rtl/pwrmgr_reg_top.sv file_type: systemVerilogSource diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core index 63feaef6ef482..2d3eac078b875 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core @@ -12,6 +12,7 @@ filesets: depend: - lowrisc:opentitan:top_darjeeling_pwrmgr_pkg:0.1 - lowrisc:opentitan:top_darjeeling_pwrmgr_reg:0.1 + - lowrisc:ip:rom_ctrl_pkg - lowrisc:ip:rv_core_ibex_pkg - lowrisc:ip:pwrmgr_component file_type: systemVerilogSource diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_pkg.core b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_pkg.core index 997acbf90f737..444c46d740435 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_pkg.core +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_pkg.core @@ -10,9 +10,9 @@ virtual: filesets: files_rtl: depend: - - lowrisc:opentitan:top_darjeeling_pwrmgr_reg - lowrisc:ip:rom_ctrl_pkg files: + - rtl/pwrmgr_reg_pkg.sv - rtl/pwrmgr_pkg.sv file_type: systemVerilogSource diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_reg.core b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_reg.core index 4734a823dc51e..aaa19bc65a59f 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_reg.core +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_reg.core @@ -10,11 +10,11 @@ virtual: filesets: files_rtl: depend: - - lowrisc:tlul:headers - lowrisc:ip:tlul + - lowrisc:opentitan:top_darjeeling_pwrmgr_pkg - lowrisc:prim:subreg + - lowrisc:tlul:headers files: - - rtl/pwrmgr_reg_pkg.sv - rtl/pwrmgr_reg_top.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core index d2203d22e3d9d..4ec1a24c610fa 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core @@ -12,6 +12,7 @@ filesets: depend: - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1 - lowrisc:opentitan:top_earlgrey_pwrmgr_reg:0.1 + - lowrisc:ip:rom_ctrl_pkg - lowrisc:ip:rv_core_ibex_pkg - lowrisc:ip:pwrmgr_component file_type: systemVerilogSource diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core index 443110c717e33..12116d09ff13f 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core @@ -9,9 +9,8 @@ virtual: filesets: files_rtl: - depend: - - lowrisc:opentitan:top_earlgrey_pwrmgr_reg files: + - rtl/pwrmgr_reg_pkg.sv - rtl/pwrmgr_pkg.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core index 37d80d19168bc..10aeb6362523d 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core @@ -10,11 +10,11 @@ virtual: filesets: files_rtl: depend: - - lowrisc:tlul:headers - lowrisc:ip:tlul + - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg - lowrisc:prim:subreg + - lowrisc:tlul:headers files: - - rtl/pwrmgr_reg_pkg.sv - rtl/pwrmgr_reg_top.sv file_type: systemVerilogSource diff --git a/util/design/data/prim_mubi.core.tpl b/util/design/data/prim_mubi.core.tpl index 29fd2528ebefb..b82d7edcf914f 100644 --- a/util/design/data/prim_mubi.core.tpl +++ b/util/design/data/prim_mubi.core.tpl @@ -16,8 +16,8 @@ filesets: - lowrisc:prim:assert - lowrisc:prim:buf - lowrisc:prim:flop + - lowrisc:prim:mubi_pkg files: - - rtl/prim_mubi_pkg.sv % for n in range(1, n_max_nibbles+1): - rtl/prim_mubi${4*n}_sender.sv - rtl/prim_mubi${4*n}_sync.sv diff --git a/util/design/data/prim_mubi_pkg.core.tpl b/util/design/data/prim_mubi_pkg.core.tpl new file mode 100644 index 0000000000000..57a1f61a2eebe --- /dev/null +++ b/util/design/data/prim_mubi_pkg.core.tpl @@ -0,0 +1,45 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +# PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +# +# util/design/gen-mubi.py +# +name: "lowrisc:prim:mubi_pkg:0.1" +description: "Multibit types and functions" +filesets: + files_rtl: + depend: + - lowrisc:prim:assert + files: + - rtl/prim_mubi_pkg.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/prim_mubi.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl diff --git a/util/design/mubi/prim_mubi.py b/util/design/mubi/prim_mubi.py index 3737a2a03bf27..d634f226c787d 100755 --- a/util/design/mubi/prim_mubi.py +++ b/util/design/mubi/prim_mubi.py @@ -7,6 +7,7 @@ from mako.template import Template # type: ignore MUBI_PKG_TPL_PATH = "util/design/data/prim_mubi_pkg.sv.tpl" +MUBI_PKG_CORE_TPL_PATH = "util/design/data/prim_mubi_pkg.core.tpl" MUBI_CORE_TPL_PATH = "util/design/data/prim_mubi.core.tpl" MUBI_SENDER_TPL_PATH = "util/design/data/prim_mubi_sender.sv.tpl" MUBI_SYNC_TPL_PATH = "util/design/data/prim_mubi_sync.sv.tpl" @@ -15,6 +16,7 @@ MUBI_SW_ASM_TPL_PATH = "util/design/data/multibits_asm.h.tpl" MUBI_PKG_OUT_PATH = "hw/ip/prim/rtl/prim_mubi_pkg.sv" +MUBI_PKG_CORE_OUT_PATH = "hw/ip/prim/prim_mubi_pkg.core" MUBI_CORE_OUT_PATH = "hw/ip/prim/prim_mubi.core" MUBI_SENDER_OUT_PATH = "hw/ip/prim/rtl/prim_mubi{}_sender.sv" MUBI_SYNC_OUT_PATH = "hw/ip/prim/rtl/prim_mubi{}_sync.sv" @@ -60,6 +62,7 @@ def gen() -> None: tpls = [ (MUBI_PKG_TPL_PATH, MUBI_PKG_OUT_PATH), + (MUBI_PKG_CORE_TPL_PATH, MUBI_PKG_CORE_OUT_PATH), (MUBI_CORE_TPL_PATH, MUBI_CORE_OUT_PATH), (MUBI_SW_TPL_PATH, MUBI_SW_OUT_PATH), (MUBI_SW_ASM_TPL_PATH, MUBI_SW_ASM_OUT_PATH), From 1e928c7e12b0c408957ac87d0f93741552ede56e Mon Sep 17 00:00:00 2001 From: Alexander Williams Date: Wed, 18 Dec 2024 00:54:33 -0800 Subject: [PATCH 23/24] [cw305] Export flash_ctrl info pages for CW305 Since englishbreakfast on the CW305 shares an MMI script with earlgrey, add the same memory breakdown so info pages may be spliced. Signed-off-by: Alexander Williams --- .../chip_englishbreakfast_cw305.core | 2 +- .../englishbreakfast_xilinx_prim_pkg.core | 19 ++++++++++++++++++ .../rtl/prim_xilinx_pkg.sv | 20 +++++++++++++++++++ 3 files changed, 40 insertions(+), 1 deletion(-) create mode 100644 hw/top_englishbreakfast/englishbreakfast_xilinx_prim_pkg.core create mode 100644 hw/top_englishbreakfast/rtl/prim_xilinx_pkg.sv diff --git a/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core b/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core index c8b442bfb808f..ac107276ec38c 100644 --- a/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core +++ b/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core @@ -8,7 +8,7 @@ description: "English Breakfast toplevel for the ChipWhisperer CW305 board" filesets: files_rtl_cw305: depend: - - lowrisc:prim_xilinx:prim_xilinx_default_pkg + - lowrisc:prim_xilinx:englishbreakfast_xilinx_prim_pkg - lowrisc:systems:top_englishbreakfast:0.1 - lowrisc:systems:ast - lowrisc:systems:topgen diff --git a/hw/top_englishbreakfast/englishbreakfast_xilinx_prim_pkg.core b/hw/top_englishbreakfast/englishbreakfast_xilinx_prim_pkg.core new file mode 100644 index 0000000000000..bbf1f824a5bca --- /dev/null +++ b/hw/top_englishbreakfast/englishbreakfast_xilinx_prim_pkg.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +name: "lowrisc:prim_xilinx:englishbreakfast_xilinx_prim_pkg" +description: "Prim configuration for englishbreakfast" +virtual: + - lowrisc:prim_xilinx:prim_xilinx_pkg +filesets: + files_rtl: + files: + - rtl/prim_xilinx_pkg.sv + file_type: systemVerilogSource + +targets: + default: &default_target + filesets: + - files_rtl diff --git a/hw/top_englishbreakfast/rtl/prim_xilinx_pkg.sv b/hw/top_englishbreakfast/rtl/prim_xilinx_pkg.sv new file mode 100644 index 0000000000000..aa1a2b0b8f6c4 --- /dev/null +++ b/hw/top_englishbreakfast/rtl/prim_xilinx_pkg.sv @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package prim_xilinx_pkg; + + // Accommodates updatemem by breaking up flash info arrays into data and + // metadata subarrays. The 76-bit width and 1 BRAM depth identifies these + // memories in earlgrey, and we limit the subarray size to 64 bits, which is + // the size of the data portion. The leftover 12 bits get placed into their + // own memory with a unique hierarchical path. See prim_xilinx_ram_1p.sv to + // see how this works. + function automatic int get_ram_max_width(int width, int depth); + if (width == 76 && depth < 4096) begin + return 64; + end + return 0; + endfunction + +endpackage : prim_xilinx_pkg From 6a5f87c698b4e82f665c04571a4e90155329fe3b Mon Sep 17 00:00:00 2001 From: Alexander Williams Date: Wed, 18 Dec 2024 01:11:10 -0800 Subject: [PATCH 24/24] [ipgen] Fix missing deps for various reg tops They were all missing prim_subreg_pkg in their dependencies. Signed-off-by: Alexander Williams --- hw/ip_templates/clkmgr/clkmgr_reg.core.tpl | 2 ++ hw/ip_templates/flash_ctrl/flash_ctrl_prim_reg_top.core | 1 + hw/ip_templates/flash_ctrl/flash_ctrl_reg.core.tpl | 1 + hw/ip_templates/pinmux/pinmux_reg.core.tpl | 1 + hw/ip_templates/rstmgr/rstmgr_reg.core.tpl | 1 + hw/top_darjeeling/ip_autogen/clkmgr/clkmgr_reg.core | 2 ++ hw/top_darjeeling/ip_autogen/pinmux/pinmux_reg.core | 1 + hw/top_darjeeling/ip_autogen/rstmgr/rstmgr_reg.core | 1 + hw/top_earlgrey/ip_autogen/clkmgr/clkmgr_reg.core | 2 ++ .../ip_autogen/flash_ctrl/flash_ctrl_prim_reg_top.core | 1 + hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl_reg.core | 1 + hw/top_earlgrey/ip_autogen/pinmux/pinmux_reg.core | 1 + hw/top_earlgrey/ip_autogen/rstmgr/rstmgr_reg.core | 1 + 13 files changed, 16 insertions(+) diff --git a/hw/ip_templates/clkmgr/clkmgr_reg.core.tpl b/hw/ip_templates/clkmgr/clkmgr_reg.core.tpl index 5603e3813894d..2c260e6bcf3e4 100644 --- a/hw/ip_templates/clkmgr/clkmgr_reg.core.tpl +++ b/hw/ip_templates/clkmgr/clkmgr_reg.core.tpl @@ -10,6 +10,8 @@ virtual: filesets: files_rtl: depend: + - lowrisc:ip:tlul + - lowrisc:prim:subreg - lowrisc:tlul:headers files: - rtl/clkmgr_reg_pkg.sv diff --git a/hw/ip_templates/flash_ctrl/flash_ctrl_prim_reg_top.core b/hw/ip_templates/flash_ctrl/flash_ctrl_prim_reg_top.core index 1b79f3c2c6765..64c14e2b682e8 100644 --- a/hw/ip_templates/flash_ctrl/flash_ctrl_prim_reg_top.core +++ b/hw/ip_templates/flash_ctrl/flash_ctrl_prim_reg_top.core @@ -8,6 +8,7 @@ filesets: files_rtl: depend: - lowrisc:ip_interfaces:flash_ctrl_pkg + - lowrisc:prim:subreg files: - rtl/flash_ctrl_prim_reg_top.sv file_type: systemVerilogSource diff --git a/hw/ip_templates/flash_ctrl/flash_ctrl_reg.core.tpl b/hw/ip_templates/flash_ctrl/flash_ctrl_reg.core.tpl index 63b5667d5432b..4e765f4020d53 100644 --- a/hw/ip_templates/flash_ctrl/flash_ctrl_reg.core.tpl +++ b/hw/ip_templates/flash_ctrl/flash_ctrl_reg.core.tpl @@ -10,6 +10,7 @@ virtual: filesets: files_rtl: depend: + - lowrisc:prim:subreg - lowrisc:tlul:headers files: - rtl/flash_ctrl_reg_pkg.sv diff --git a/hw/ip_templates/pinmux/pinmux_reg.core.tpl b/hw/ip_templates/pinmux/pinmux_reg.core.tpl index 0a4cde8cf448e..136906439a529 100644 --- a/hw/ip_templates/pinmux/pinmux_reg.core.tpl +++ b/hw/ip_templates/pinmux/pinmux_reg.core.tpl @@ -10,6 +10,7 @@ virtual: filesets: files_rtl: depend: + - lowrisc:prim:subreg - lowrisc:tlul:headers files: - rtl/pinmux_reg_pkg.sv diff --git a/hw/ip_templates/rstmgr/rstmgr_reg.core.tpl b/hw/ip_templates/rstmgr/rstmgr_reg.core.tpl index 98b3f8f489150..e8a4110decee7 100644 --- a/hw/ip_templates/rstmgr/rstmgr_reg.core.tpl +++ b/hw/ip_templates/rstmgr/rstmgr_reg.core.tpl @@ -10,6 +10,7 @@ virtual: filesets: files_rtl: depend: + - lowrisc:prim:subreg - lowrisc:tlul:headers files: - rtl/rstmgr_reg_pkg.sv diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr_reg.core b/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr_reg.core index fa2fe9daada45..6f4c133e57b19 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr_reg.core +++ b/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr_reg.core @@ -10,6 +10,8 @@ virtual: filesets: files_rtl: depend: + - lowrisc:ip:tlul + - lowrisc:prim:subreg - lowrisc:tlul:headers files: - rtl/clkmgr_reg_pkg.sv diff --git a/hw/top_darjeeling/ip_autogen/pinmux/pinmux_reg.core b/hw/top_darjeeling/ip_autogen/pinmux/pinmux_reg.core index 9882819e798fb..f6e22622f9102 100644 --- a/hw/top_darjeeling/ip_autogen/pinmux/pinmux_reg.core +++ b/hw/top_darjeeling/ip_autogen/pinmux/pinmux_reg.core @@ -10,6 +10,7 @@ virtual: filesets: files_rtl: depend: + - lowrisc:prim:subreg - lowrisc:tlul:headers files: - rtl/pinmux_reg_pkg.sv diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr_reg.core b/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr_reg.core index 2aa72a7e17024..12010cd14b27c 100644 --- a/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr_reg.core +++ b/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr_reg.core @@ -10,6 +10,7 @@ virtual: filesets: files_rtl: depend: + - lowrisc:prim:subreg - lowrisc:tlul:headers files: - rtl/rstmgr_reg_pkg.sv diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/clkmgr_reg.core b/hw/top_earlgrey/ip_autogen/clkmgr/clkmgr_reg.core index adda72df2f033..c7996d5deb6e7 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/clkmgr_reg.core +++ b/hw/top_earlgrey/ip_autogen/clkmgr/clkmgr_reg.core @@ -10,6 +10,8 @@ virtual: filesets: files_rtl: depend: + - lowrisc:ip:tlul + - lowrisc:prim:subreg - lowrisc:tlul:headers files: - rtl/clkmgr_reg_pkg.sv diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl_prim_reg_top.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl_prim_reg_top.core index 1b79f3c2c6765..64c14e2b682e8 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl_prim_reg_top.core +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl_prim_reg_top.core @@ -8,6 +8,7 @@ filesets: files_rtl: depend: - lowrisc:ip_interfaces:flash_ctrl_pkg + - lowrisc:prim:subreg files: - rtl/flash_ctrl_prim_reg_top.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl_reg.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl_reg.core index 6cf0dd131df90..88dd35c8cae70 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl_reg.core +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl_reg.core @@ -10,6 +10,7 @@ virtual: filesets: files_rtl: depend: + - lowrisc:prim:subreg - lowrisc:tlul:headers files: - rtl/flash_ctrl_reg_pkg.sv diff --git a/hw/top_earlgrey/ip_autogen/pinmux/pinmux_reg.core b/hw/top_earlgrey/ip_autogen/pinmux/pinmux_reg.core index 1ad5e2a5641d3..8e1832d2a73b1 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/pinmux_reg.core +++ b/hw/top_earlgrey/ip_autogen/pinmux/pinmux_reg.core @@ -10,6 +10,7 @@ virtual: filesets: files_rtl: depend: + - lowrisc:prim:subreg - lowrisc:tlul:headers files: - rtl/pinmux_reg_pkg.sv diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/rstmgr_reg.core b/hw/top_earlgrey/ip_autogen/rstmgr/rstmgr_reg.core index a46e660b8b450..320fb705583eb 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/rstmgr_reg.core +++ b/hw/top_earlgrey/ip_autogen/rstmgr/rstmgr_reg.core @@ -10,6 +10,7 @@ virtual: filesets: files_rtl: depend: + - lowrisc:prim:subreg - lowrisc:tlul:headers files: - rtl/rstmgr_reg_pkg.sv