From d6ed971750b936182aee70eefab92763d6956be7 Mon Sep 17 00:00:00 2001 From: Guillermo Maturana Date: Wed, 17 Jan 2024 06:39:57 +0000 Subject: [PATCH 1/2] [topgen] Pass topname key/value pair to ipgen This pair is uniformly added to all ipgen modules. Change topgen.py to adopt the convention that, for example, the variable topname is just earlgrey for example, while top_name is top_earlgrey. Signed-off-by: Guillermo Maturana --- .../data/alert_handler.tpldesc.hjson | 6 ++ hw/ip_templates/pwrmgr/README.md.tpl | 2 +- .../pwrmgr/data/pwrmgr.tpldesc.hjson | 2 +- hw/ip_templates/pwrmgr/doc/interfaces.md.tpl | 2 +- hw/ip_templates/pwrmgr/doc/registers.md.tpl | 2 +- hw/ip_templates/pwrmgr/dv/README.md.tpl | 22 ++--- .../seq_lib/pwrmgr_wakeup_reset_vseq.sv.tpl | 2 +- .../rv_plic/data/rv_plic.tpldesc.hjson | 6 ++ .../top_earlgrey_alert_handler.ipconfig.hjson | 1 + .../data/top_earlgrey_pwrmgr.ipconfig.hjson | 2 +- .../data/top_earlgrey_rv_plic.ipconfig.hjson | 1 + util/ipgen/lib.py | 1 - util/topgen.py | 85 ++++++++++--------- 13 files changed, 75 insertions(+), 59 deletions(-) diff --git a/hw/ip_templates/alert_handler/data/alert_handler.tpldesc.hjson b/hw/ip_templates/alert_handler/data/alert_handler.tpldesc.hjson index fc0b08906ac33..6266633d01848 100644 --- a/hw/ip_templates/alert_handler/data/alert_handler.tpldesc.hjson +++ b/hw/ip_templates/alert_handler/data/alert_handler.tpldesc.hjson @@ -3,6 +3,12 @@ // SPDX-License-Identifier: Apache-2.0 { template_param_list: [ + { + name: "topname" + desc: "Name of top-level design, e.g., 'darjeeling' or 'earlgrey'" + type: "string" + default: "" + } { name: "n_alerts" desc: "Number of alert sources" diff --git a/hw/ip_templates/pwrmgr/README.md.tpl b/hw/ip_templates/pwrmgr/README.md.tpl index fa8cc5e12f807..e3882098c6a15 100644 --- a/hw/ip_templates/pwrmgr/README.md.tpl +++ b/hw/ip_templates/pwrmgr/README.md.tpl @@ -1,5 +1,5 @@ # Power Manager HWIP Technical Specification -[`pwrmgr`](https://reports.opentitan.org/hw/top_${top_name}/ip_autogen/pwrmgr/dv/latest/report.html): +[`pwrmgr`](https://reports.opentitan.org/hw/top_${topname}/ip_autogen/pwrmgr/dv/latest/report.html): ![](https://dashboards.lowrisc.org/badges/dv/pwrmgr/test.svg) ![](https://dashboards.lowrisc.org/badges/dv/pwrmgr/passing.svg) ![](https://dashboards.lowrisc.org/badges/dv/pwrmgr/functional.svg) diff --git a/hw/ip_templates/pwrmgr/data/pwrmgr.tpldesc.hjson b/hw/ip_templates/pwrmgr/data/pwrmgr.tpldesc.hjson index a1ea7906727ff..7ae94a16ae2f0 100644 --- a/hw/ip_templates/pwrmgr/data/pwrmgr.tpldesc.hjson +++ b/hw/ip_templates/pwrmgr/data/pwrmgr.tpldesc.hjson @@ -4,7 +4,7 @@ { template_param_list: [ { - name: "top_name" + name: "topname" desc: "Name of top-level design, e.g., 'darjeeling' or 'earlgrey'" type: "string" default: "" diff --git a/hw/ip_templates/pwrmgr/doc/interfaces.md.tpl b/hw/ip_templates/pwrmgr/doc/interfaces.md.tpl index c3de8cc7c3786..34a228c54563e 100644 --- a/hw/ip_templates/pwrmgr/doc/interfaces.md.tpl +++ b/hw/ip_templates/pwrmgr/doc/interfaces.md.tpl @@ -1,6 +1,6 @@ # Hardware Interfaces - + Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`pwrmgr`** has the following hardware interfaces defined - Primary Clock: **`clk_i`** - Other Clocks: **`clk_slow_i`**, **`clk_lc_i`**, **`clk_esc_i`** diff --git a/hw/ip_templates/pwrmgr/doc/registers.md.tpl b/hw/ip_templates/pwrmgr/doc/registers.md.tpl index 1bda7a75f7b5e..3b252c7dffdaa 100644 --- a/hw/ip_templates/pwrmgr/doc/registers.md.tpl +++ b/hw/ip_templates/pwrmgr/doc/registers.md.tpl @@ -1,6 +1,6 @@ # Registers - + ${"##"} Summary | Name | Offset | Length | Description | diff --git a/hw/ip_templates/pwrmgr/dv/README.md.tpl b/hw/ip_templates/pwrmgr/dv/README.md.tpl index 08014bb9c4d55..17638fa1c3036 100644 --- a/hw/ip_templates/pwrmgr/dv/README.md.tpl +++ b/hw/ip_templates/pwrmgr/dv/README.md.tpl @@ -1,5 +1,5 @@ # PWRMGR DV document - +<% top_name = f"top_{topname}" %> ${"##"} Goals * **DV** * Verify all PWRMGR IP features by running dynamic simulations with a SV/UVM based testbench. @@ -10,7 +10,7 @@ ${"##"} Goals ${"##"} Current status * [Design & verification stage](../doc/checklist.md) * [HW development stages](../../../../../doc/project_governance/development_stages.md) -* [Simulation results](https://reports.opentitan.org/hw/top_${top_name}/ip_autogen/pwrmgr/dv/latest/report.html) +* [Simulation results](https://reports.opentitan.org/hw/${top_name}/ip_autogen/pwrmgr/dv/latest/report.html) ${"##"} Design features For detailed information on PWRMGR design features, please see the [PWRMGR HWIP technical specification](../README.md). @@ -22,12 +22,12 @@ ${"###"} Block diagram ![Block diagram](./doc/tb.svg) ${"###"} Top level testbench -Top level testbench is located at [`hw/top_${top_name}/ip_autogen/pwrmgr/dv/tb.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_${top_name}/ip_autogen/pwrmgr/dv/tb.sv). -It instantiates the PWRMGR DUT module [`hw/top_${top_name}/ip_autogen/pwrmgr/rtl/pwrmgr.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_${top_name}/ip_autogen/pwrmgr/rtl/pwrmgr.sv). +Top level testbench is located at [`hw/${top_name}/ip_autogen/pwrmgr/dv/tb.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/${top_name}/ip_autogen/pwrmgr/dv/tb.sv). +It instantiates the PWRMGR DUT module [`hw/${top_name}/ip_autogen/pwrmgr/rtl/pwrmgr.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/${top_name}/ip_autogen/pwrmgr/rtl/pwrmgr.sv). In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`: * [Clock and reset interface](../../../../dv/sv/common_ifs/README.md) * [TileLink host interface](../../../../dv/sv/tl_agent/README.md) -* PWRMGR interface [`hw/top_${top_name}/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_${top_name}/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv). +* PWRMGR interface [`hw/${top_name}/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/${top_name}/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv). * Interrupts ([`pins_if`](../../../../dv/sv/common_ifs/README.md)) * Alerts ([`alert_esc_if`](../../../../dv/sv/alert_esc_agent/README.md)) @@ -38,7 +38,7 @@ The following utilities provide generic helper tasks and functions to perform ac ${"###"} Global types & methods All common types and methods defined at the package level can be found in -[`pwrmgr_env_pkg`](https://github.com/lowRISC/opentitan/blob/master/hw/top_${top_name}/ip_autogen/pwrmgr/dv/env/pwrmgr_env_pkg.sv). +[`pwrmgr_env_pkg`](https://github.com/lowRISC/opentitan/blob/master/hw/${top_name}/ip_autogen/pwrmgr/dv/env/pwrmgr_env_pkg.sv). Some of them in use are: ```systemverilog typedef enum int { @@ -75,7 +75,7 @@ It can be created manually by invoking [`regtool`](../../../../../util/reggen/do ${"###"} Stimulus strategy The sequences are closely related to the testplan's testpoints. Testpoints and coverage are described in more detail in the [testplan](#testplan). -All test sequences reside in [`hw/top_${top_name}/ip_autogen/pwrmgr/dv/env/seq_lib`](https://github.com/lowRISC/opentitan/blob/master/hw/top_${top_name}/ip_autogen/pwrmgr/dv/env/seq_lib), and extend `pwrmgr_base_vseq`. +All test sequences reside in [`hw/${top_name}/ip_autogen/pwrmgr/dv/env/seq_lib`](https://github.com/lowRISC/opentitan/blob/master/hw/${top_name}/ip_autogen/pwrmgr/dv/env/seq_lib), and extend `pwrmgr_base_vseq`. The `pwrmgr_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point. It provides commonly used handles, variables, functions and tasks used by the test sequences. Some of the most commonly used tasks and functions are as follows: @@ -153,7 +153,7 @@ ${"#####"} AST - Outputs `core_clk_en`, `io_clk_en`, and `usb_clk_en` reset low, and go high prior to the slow fsm requesting the fast fsm to wakeup. Notice the usb clock can be programmed to stay low on wakeup via the `control` CSR. These clock enables are cleared on reset, and should match their corresponding enables in the `control` CSR on low power transitions. - These clock enables are checked via SVAs in [`hw/top_${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv). + These clock enables are checked via SVAs in [`hw/${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv). When slow fsm transitions to `SlowPwrStateReqPwrUp` the clock enables should be on (except usb should match `control.usb_clk_en_active`). When slow fsm transitions to `SlowPwrStatePwrClampOn` the clock enables should match their bits in the `control` CSR. - Inputs `core_clk_val`, `io_clk_val`, and `usb_clk_val` track the corresponding enables. @@ -161,7 +161,7 @@ ${"#####"} AST Slow fsm waits for them to go high prior to requesting fast fsm wakeup. Lack of a high transition when needed is detected via timeout. Such timeout would be due to the corresponding enables being set incorrectly. - These inputs are checked via SVAs in [`hw/top_${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv). + These inputs are checked via SVAs in [`hw/${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv). - Output `main_pd_n` should go high when slow fsm transitions to `SlowPwrStateMainPowerOn`, and should match `control.main_pd_n` CSR when slow fsm transitions to `SlowPwrStateMainPowerOff`. - Input `main_pok` should turn on for the slow fsm to start power up sequence. This is also driven by `slow_responder`, which turn this off in response to `main_pd_n` going low, and turn it back on after a few random slow clock cycles from `main_pd_n` going high. @@ -226,7 +226,7 @@ There are a number of wakeup and reset requests. They are driven by sequences as they need to. ${"####"} Assertions -The [`hw/top_${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv) module binds a few modules containing assertions to the IP as follows: +The [`hw/${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv) module binds a few modules containing assertions to the IP as follows: * TLUL assertions: the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) ensures TileLink interface protocol compliance. * Clock enables assertions: The `pwrmgr_clock_enables_sva_if` module contains assertions checking that the various clk_en outputs correspond to the settings in the `control` CSR. @@ -248,7 +248,7 @@ We are using our in-house developed [regression tool](../../../../../util/dvsim/ Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here's how to run a smoke test: ```console -$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/top_${top_name}/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson -i pwrmgr_smoke +$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/${top_name}/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson -i pwrmgr_smoke ``` ${"##"} Testplan diff --git a/hw/ip_templates/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_reset_vseq.sv.tpl b/hw/ip_templates/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_reset_vseq.sv.tpl index af599b0b95c92..9b4c361fbe16c 100644 --- a/hw/ip_templates/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_reset_vseq.sv.tpl +++ b/hw/ip_templates/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_reset_vseq.sv.tpl @@ -27,7 +27,7 @@ class pwrmgr_wakeup_reset_vseq extends pwrmgr_base_vseq; // transition to active state. // ICEBOX(lowrisc/opentitan#18236) Consider adding checks to monitor fast state transitions are // compliant with "ROM Integrity Checks" at - // https://opentitan.org/book/hw/top_${top_name}/ip_autogen/pwrmgr/doc/theory_of_operation.html#rom-integrity-checks + // https://opentitan.org/book/hw/top_${topname}/ip_autogen/pwrmgr/doc/theory_of_operation.html#rom-integrity-checks virtual task twirl_rom_response(); cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4False; cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4False; diff --git a/hw/ip_templates/rv_plic/data/rv_plic.tpldesc.hjson b/hw/ip_templates/rv_plic/data/rv_plic.tpldesc.hjson index 72de4b7ffe90b..15a72c2a30b2e 100644 --- a/hw/ip_templates/rv_plic/data/rv_plic.tpldesc.hjson +++ b/hw/ip_templates/rv_plic/data/rv_plic.tpldesc.hjson @@ -3,6 +3,12 @@ // SPDX-License-Identifier: Apache-2.0 { template_param_list: [ + { + name: "topname" + desc: "Name of top-level design, e.g., 'darjeeling' or 'earlgrey'" + type: "string" + default: "" + } { name: "src" desc: "Number of interrupt sources" diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson index 625058c06b70d..af5299672cfe5 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson @@ -146,5 +146,6 @@ 5'd17 5'd17 ] + topname: earlgrey } } diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/data/top_earlgrey_pwrmgr.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/pwrmgr/data/top_earlgrey_pwrmgr.ipconfig.hjson index 31d2caeddf7d5..ebc6021bb1459 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/data/top_earlgrey_pwrmgr.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/data/top_earlgrey_pwrmgr.ipconfig.hjson @@ -5,7 +5,6 @@ instance_name: top_earlgrey_pwrmgr param_values: { - top_name: earlgrey NumWkups: 6 Wkups: [ @@ -80,5 +79,6 @@ ] } NumRstReqs: 2 + topname: earlgrey } } diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/data/top_earlgrey_rv_plic.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/rv_plic/data/top_earlgrey_rv_plic.ipconfig.hjson index a522eb49154eb..e7abdec8a5258 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/data/top_earlgrey_rv_plic.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/rv_plic/data/top_earlgrey_rv_plic.ipconfig.hjson @@ -8,5 +8,6 @@ src: 185 target: 1 prio: 3 + topname: earlgrey } } diff --git a/util/ipgen/lib.py b/util/ipgen/lib.py index 4abf2703c03f8..866d78bf7c64d 100644 --- a/util/ipgen/lib.py +++ b/util/ipgen/lib.py @@ -191,7 +191,6 @@ def _check_object(obj: object, what: str) -> object: """Check that obj is a Hjson-serializable object. If not, raise a ValueError; the what argument names the object. - """ try: # Round-trip objects through the JSON encoder to get the diff --git a/util/topgen.py b/util/topgen.py index 4fbefe691d21a..c458cf70e8563 100755 --- a/util/topgen.py +++ b/util/topgen.py @@ -51,8 +51,8 @@ // SPDX-License-Identifier: Apache-2.0 """ + warnhdr -GENCMD = ("// util/topgen.py -t hw/top_{topname}/data/top_{topname}.hjson\n" - "// -o hw/top_{topname}") +GENCMD = ("// util/topgen.py -t hw/{top_name}/data/{top_name}.hjson\n" + "// -o hw/{top_name}") SRCTREE_TOP = Path(__file__).parents[1].resolve() @@ -69,10 +69,12 @@ def ipgen_render(template_name: str, topname: str, params: Dict[str, object], Aborts the program execution in case of an error. """ module_name = params.get("module_instance_name", template_name) - instance_name = f"top_{topname}_{module_name}" + top_name = f"top_{topname}" + instance_name = f"{top_name}_{module_name}" ip_template = IpTemplate.from_template_path(SRCTREE_TOP / "hw" / "ip_templates" / template_name) + params.update({"topname": topname}) try: ip_config = IpConfig(ip_template.params, instance_name, params) except ValueError as e: @@ -100,16 +102,16 @@ def generate_top(top: Dict[str, object], name_to_block: Dict[str, IpBlock], def generate_xbars(top: Dict[str, object], out_path: Path) -> None: - topname = top["name"] - gencmd = ("// util/topgen.py -t hw/top_{topname}/data/top_{topname}.hjson " - "-o hw/top_{topname}/\n\n".format(topname=topname)) + top_name = "top_" + top["name"] + gencmd = (f"// util/topgen.py -t hw/{top_name}/data/{top_name}.hjson " + f"-o hw/{top_name}/\n\n") for obj in top["xbar"]: objname = obj["name"] xbar_path = out_path / "ip" / f"xbar_{objname}" / "data" / "autogen" xbar_path.mkdir(parents=True, exist_ok=True) xbar = tlgen.validate(obj) - xbar.ip_path = "/".join(["hw", f"top_{topname}", "ip", "{dut}"]) + xbar.ip_path = "/".join(["hw", top_name, "ip", "{dut}"]) # Generate output of crossbar with complete fields xbar_hjson_path = xbar_path / f"xbar_{xbar.name}.gen.hjson" @@ -120,7 +122,7 @@ def generate_xbars(top: Dict[str, object], out_path: Path) -> None: log.error("Elaboration failed." + repr(xbar)) try: - results = tlgen.generate(xbar, f"top_{topname}") + results = tlgen.generate(xbar, top_name) except: # noqa: E722 log.error(exceptions.text_error_template().render()) @@ -136,7 +138,7 @@ def generate_xbars(top: Dict[str, object], out_path: Path) -> None: dv_path.mkdir(parents=True, exist_ok=True) # generate testbench for xbar - tlgen.generate_tb(xbar, dv_path, f"top_{topname}") + tlgen.generate_tb(xbar, dv_path, top_name) # Read back the comportable IP and amend to Xbar xbar_ipfile = ip_path / "data" / "autogen" / f"xbar_{objname}.hjson" @@ -331,9 +333,10 @@ def generate_pinmux(top: Dict[str, object], out_path: Path) -> None: original_rtl_path = orig_ip_path / "rtl" # Generate register package and RTLs + top_name = f"top_{topname}" gencmd = ( - f"// util/topgen.py -t hw/top_{topname}/data/top_{topname}.hjson " - f"-o hw/top_{topname}/\n\n") + f"// util/topgen.py -t hw/{top_name}/data/{top_name}.hjson " + f"-o hw/{top_name}/\n\n") hjson_gen_path = data_path / "pinmux.hjson" @@ -447,7 +450,6 @@ def generate_pwrmgr(top: Dict[str, object], out_path: Path) -> None: "Reset requests are not supported.") params = { - "top_name": topname, "NumWkups": n_wkups, "Wkups": top["wakeups"], "rst_reqs": top["reset_requests"], @@ -616,7 +618,7 @@ def generate_flash(topcfg: Dict[str, object], out_path: Path) -> None: def generate_top_only(top_only_dict: Dict[str, bool], out_path: Path, - topname: str, alt_hjson_path: str) -> None: + top_name: str, alt_hjson_path: str) -> None: log.info("Generating top only modules") for ip, reggen_only in top_only_dict.items(): @@ -624,7 +626,7 @@ def generate_top_only(top_only_dict: Dict[str, bool], out_path: Path, if reggen_only and alt_hjson_path is not None: hjson_dir = Path(alt_hjson_path) else: - hjson_dir = (SRCTREE_TOP / "hw" / f"top_{topname}" / "ip" / ip / + hjson_dir = (SRCTREE_TOP / "hw" / top_name / "ip" / ip / "data") hjson_path = hjson_dir / f"{ip}.hjson" @@ -795,13 +797,13 @@ def _process_top(topcfg: Dict[str, object], args: argparse.Namespace, } log.info("Filtered dict is {}".format(top_only_dict)) - topname = topcfg["name"] + top_name = f"top_{topcfg['name']}" # Sweep the IP directory and gather the config files ip_dir = Path(__file__).parents[1] / "hw/ip" ips = search_ips(ip_dir) - # exclude filtered IPs (to use top_${topname} one) and + # exclude filtered IPs (to use ${top_name} one) and exclude_list = generated_list + list(top_only_dict.keys()) ips = [x for x in ips if not x.parents[1].name in exclude_list] @@ -877,7 +879,7 @@ def _process_top(topcfg: Dict[str, object], args: argparse.Namespace, tpl_path = SRCTREE_TOP / "hw/ip_templates" / ip_name ip_template = IpTemplate.from_template_path(tpl_path) ip_config = IpConfig(ip_template.params, - f"top_{topname}_{ip_name}") + f"{top_name}_{ip_name}") try: ip_desc = IpDescriptionOnlyRenderer( @@ -974,7 +976,7 @@ def _process_top(topcfg: Dict[str, object], args: argparse.Namespace, # Generate top only modules # These modules are not templated, but are not in hw/ip - generate_top_only(top_only_dict, out_path, topname, args.hjson_path) + generate_top_only(top_only_dict, out_path, top_name, args.hjson_path) return completecfg, name_to_block @@ -1199,6 +1201,7 @@ def main(): out_path_gen, pass_idx) topname = topcfg["name"] + top_name = f"top_{topname}" # Create the chip-level RAL only if args.top_ral: @@ -1228,14 +1231,14 @@ def main(): # Generate top.gen.hjson right before rendering genhjson_dir = out_path / "data/autogen" genhjson_dir.mkdir(parents=True, exist_ok=True) - genhjson_path = genhjson_dir / ("top_%s.gen.hjson" % completecfg["name"]) + genhjson_path = genhjson_dir / f"{top_name}.gen.hjson" # Header for HJSON gencmd = """// -// util/topgen.py -t hw/top_{topname}/data/top_{topname}.hjson \\ -// -o hw/top_{topname}/ \\ +// util/topgen.py -t hw/{top_name}/data/{top_name}.hjson \\ +// -o hw/{top_name}/ \\ // --rnd_cnst_seed {seed} -""".format(topname=topname, seed=completecfg["rnd_cnst_seed"]) +""".format(top_name=top_name, seed=completecfg["rnd_cnst_seed"]) genhjson_path.write_text(genhdr + gencmd + hjson.dumps(completecfg, for_json=True) + '\n') @@ -1260,16 +1263,16 @@ def render_template(template_path: str, rendered_path: Path, # Header for SV files gencmd = warnhdr + """// -// util/topgen.py -t hw/top_{topname}/data/top_{topname}.hjson \\ -// -o hw/top_{topname}/ \\ +// util/topgen.py -t hw/{top_name}/data/{top_name}.hjson \\ +// -o hw/{top_name}/ \\ // --rnd_cnst_seed \\ // {seed} -""".format(topname=topname, seed=completecfg["rnd_cnst_seed"]) +""".format(top_name=top_name, seed=completecfg["rnd_cnst_seed"]) # SystemVerilog Top: - # "toplevel.sv.tpl" -> "rtl/autogen/top_{topname}.sv" + # "toplevel.sv.tpl" -> "rtl/autogen/{top_name}.sv" render_template(TOPGEN_TEMPLATE_PATH / "toplevel.sv.tpl", - out_path / f"rtl/autogen/top_{topname}.sv", + out_path / "rtl" / "autogen" / f"{top_name}.sv", gencmd=gencmd) # Multiple chip-levels (ASIC, FPGA, Verilator, etc) @@ -1285,16 +1288,16 @@ def render_template(template_path: str, rendered_path: Path, # object to store it. c_helper = TopGenCTest(completecfg, name_to_block) - # "toplevel_pkg.sv.tpl" -> "rtl/autogen/top_{topname}_pkg.sv" + # "toplevel_pkg.sv.tpl" -> "rtl/autogen/{top_name}_pkg.sv" render_template(TOPGEN_TEMPLATE_PATH / "toplevel_pkg.sv.tpl", - out_path / f"rtl/autogen/top_{topname}_pkg.sv", + out_path / "rtl" / "autogen" / f"{top_name}_pkg.sv", helper=c_helper, gencmd=gencmd) # compile-time random netlist constants render_template(TOPGEN_TEMPLATE_PATH / "toplevel_rnd_cnst_pkg.sv.tpl", out_path / - f"rtl/autogen/top_{topname}_rnd_cnst_pkg.sv", + f"rtl/autogen/{top_name}_rnd_cnst_pkg.sv", gencmd=gencmd) # Since SW does not use FuseSoC and instead expects those files always @@ -1305,14 +1308,14 @@ def render_template(template_path: str, rendered_path: Path, root_paths = [out_path.resolve(), SRCTREE_TOP] out_paths = [ out_path.resolve(), - (SRCTREE_TOP / "hw/top_{}/".format(topname)).resolve() + (SRCTREE_TOP / "hw" / top_name).resolve() ] for idx, path in enumerate(out_paths): # C Header + C File + Clang-format file # "clang-format" -> "sw/autogen/.clang-format" cformat_tplpath = TOPGEN_TEMPLATE_PATH / "clang-format" - cformat_dir = path / "sw/autogen" + cformat_dir = path / "sw" / "autogen" cformat_dir.mkdir(parents=True, exist_ok=True) cformat_path = cformat_dir / ".clang-format" cformat_path.write_text(cformat_tplpath.read_text()) @@ -1322,8 +1325,8 @@ def render_template(template_path: str, rendered_path: Path, c_helper.header_macro_prefix = ( "OPENTITAN_" + str(rel_header_dir).replace("/", "_").upper()) - # "top_{topname}.h.tpl" -> "sw/autogen/top_{topname}.h" - cheader_path = cformat_dir / f"top_{topname}.h" + # "{top_name}.h.tpl" -> "sw/autogen/{top_name}.h" + cheader_path = cformat_dir / f"{top_name}.h" render_template(TOPGEN_TEMPLATE_PATH / "toplevel.h.tpl", cheader_path, helper=c_helper) @@ -1332,17 +1335,17 @@ def render_template(template_path: str, rendered_path: Path, rel_header_path = cheader_path.relative_to(root_paths[idx]) c_helper.header_path = str(rel_header_path) - # "toplevel.c.tpl" -> "sw/autogen/top_{topname}.c" + # "toplevel.c.tpl" -> "sw/autogen/{top_name}.c" render_template(TOPGEN_TEMPLATE_PATH / "toplevel.c.tpl", - cformat_dir / f"top_{topname}.c", + cformat_dir / f"{top_name}.c", helper=c_helper) - # "toplevel_memory.ld.tpl" -> "sw/autogen/top_{topname}_memory.ld" + # "toplevel_memory.ld.tpl" -> "sw/autogen/{top_name}_memory.ld" render_template(TOPGEN_TEMPLATE_PATH / "toplevel_memory.ld.tpl", - cformat_dir / f"top_{topname}_memory.ld") + cformat_dir / f"{top_name}_memory.ld") - # "toplevel_memory.h.tpl" -> "sw/autogen/top_{topname}_memory.h" - memory_cheader_path = cformat_dir / f"top_{topname}_memory.h" + # "toplevel_memory.h.tpl" -> "sw/autogen/{top_name}_memory.h" + memory_cheader_path = cformat_dir / f"{top_name}_memory.h" render_template(TOPGEN_TEMPLATE_PATH / "toplevel_memory.h.tpl", memory_cheader_path, helper=c_helper) @@ -1385,7 +1388,7 @@ def render_template(template_path: str, rendered_path: Path, gen_top_docs(completecfg, c_helper, out_path) # Auto-generate tests in "sw/device/tests/autogen" area. - gencmd = warnhdr + GENCMD.format(topname=topname) + gencmd = warnhdr + GENCMD.format(top_name=top_name) for fname in ["plic_all_irqs_test.c", "alert_test.c", "BUILD"]: outfile = SRCTREE_TOP / "sw/device/tests/autogen" / fname render_template(TOPGEN_TEMPLATE_PATH / f"{fname}.tpl", From abf0b609b520fc39722815cf62626c6854e9e00b Mon Sep 17 00:00:00 2001 From: Guillermo Maturana Date: Thu, 18 Jan 2024 19:10:27 +0000 Subject: [PATCH 2/2] [ipgen.pwrmgr] Change core files to vlnv naming and label as virtual The core files affected are the pwrmgr cores that are templetized. All other core files referring to the the files above need to depend on the virtual name instead. Remove the redundant files for which there is a corresponding template under ip_templates. Signed-off-by: Guillermo Maturana --- hw/ip/clkmgr/dv/env/clkmgr_env.core | 2 +- hw/ip/flash_ctrl/flash_ctrl_pkg.core | 2 +- hw/ip/lc_ctrl/lc_ctrl.core | 2 +- hw/ip/otp_ctrl/otp_ctrl.core | 2 +- hw/ip/rstmgr/dv/sva/rstmgr_sva_ifs.core | 2 +- hw/ip/rstmgr/rstmgr_pkg.core | 2 +- hw/ip/rv_core_ibex/rv_core_ibex.core | 2 +- hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core | 2 +- hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core | 2 +- .../pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core | 2 +- hw/ip_templates/pwrmgr/dv/sva/pwrmgr_sva.core | 4 +- hw/ip_templates/pwrmgr/pwrmgr.core.tpl | 66 ++ .../{pwrmgr.core => pwrmgr_components.core} | 5 +- .../{pwrmgr_pkg.core => pwrmgr_pkg.core.tpl} | 6 +- .../{pwrmgr_reg.core => pwrmgr_reg.core.tpl} | 4 +- hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_pkg.sv | 215 ---- hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_top.sv | 947 ------------------ hw/top_earlgrey/dv/chip_sim.core | 3 + hw/top_earlgrey/dv/env/chip_env.core | 2 +- hw/top_earlgrey/dv/sva/top_earlgrey_sva.core | 2 +- hw/top_earlgrey/ip/clkmgr/clkmgr.core | 2 +- hw/top_earlgrey/ip/clkmgr/clkmgr_pkg.core | 2 +- .../ip/rstmgr/system_rstmgr_pkg.core | 2 +- .../ip_autogen/pwrmgr/dv/env/pwrmgr_env.core | 2 +- .../ip_autogen/pwrmgr/dv/pwrmgr_sim.core | 2 +- .../pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core | 2 +- .../ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core | 4 +- hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core | 27 +- .../ip_autogen/pwrmgr/pwrmgr_components.core | 80 ++ .../ip_autogen/pwrmgr/pwrmgr_pkg.core | 6 +- .../ip_autogen/pwrmgr/pwrmgr_reg.core | 4 +- .../lint/top_earlgrey_lint_cfgs.hjson | 2 +- hw/top_earlgrey/top_earlgrey.core | 5 +- .../lint/top_englishbreakfast_lint_cfgs.hjson | 2 +- .../top_englishbreakfast.core | 2 +- util/topgen-fusesoc.py | 2 +- 36 files changed, 201 insertions(+), 1219 deletions(-) create mode 100644 hw/ip_templates/pwrmgr/pwrmgr.core.tpl rename hw/ip_templates/pwrmgr/{pwrmgr.core => pwrmgr_components.core} (95%) rename hw/ip_templates/pwrmgr/{pwrmgr_pkg.core => pwrmgr_pkg.core.tpl} (79%) rename hw/ip_templates/pwrmgr/{pwrmgr_reg.core => pwrmgr_reg.core.tpl} (82%) delete mode 100644 hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_pkg.sv delete mode 100644 hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_top.sv create mode 100644 hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core diff --git a/hw/ip/clkmgr/dv/env/clkmgr_env.core b/hw/ip/clkmgr/dv/env/clkmgr_env.core index 446d07e8ac1c3..f4b76088b71fc 100644 --- a/hw/ip/clkmgr/dv/env/clkmgr_env.core +++ b/hw/ip/clkmgr/dv/env/clkmgr_env.core @@ -9,7 +9,7 @@ filesets: depend: - lowrisc:dv:ralgen - lowrisc:dv:cip_lib - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:systems:clkmgr_pkg files: - clkmgr_csrs_if.sv diff --git a/hw/ip/flash_ctrl/flash_ctrl_pkg.core b/hw/ip/flash_ctrl/flash_ctrl_pkg.core index 05ec6743f249f..461ba7f711247 100644 --- a/hw/ip/flash_ctrl/flash_ctrl_pkg.core +++ b/hw/ip/flash_ctrl/flash_ctrl_pkg.core @@ -11,7 +11,7 @@ filesets: - lowrisc:constants:top_pkg - lowrisc:prim:util - lowrisc:ip:lc_ctrl_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:jtag_pkg - lowrisc:ip:edn_pkg - "fileset_partner ? (partner:systems:ast_pkg)" diff --git a/hw/ip/lc_ctrl/lc_ctrl.core b/hw/ip/lc_ctrl/lc_ctrl.core index 4dd46ccd9b487..c1efa3b8984df 100644 --- a/hw/ip/lc_ctrl/lc_ctrl.core +++ b/hw/ip/lc_ctrl/lc_ctrl.core @@ -17,7 +17,7 @@ filesets: - lowrisc:prim:sparse_fsm - lowrisc:ip:lc_ctrl_pkg - lowrisc:ip:tlul - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:otp_ctrl_pkg - lowrisc:ip:kmac_pkg - lowrisc:ip:rv_dm diff --git a/hw/ip/otp_ctrl/otp_ctrl.core b/hw/ip/otp_ctrl/otp_ctrl.core index 9f18a1a1a4414..10971dd549c4c 100644 --- a/hw/ip/otp_ctrl/otp_ctrl.core +++ b/hw/ip/otp_ctrl/otp_ctrl.core @@ -22,7 +22,7 @@ filesets: - lowrisc:prim:secded - lowrisc:ip:edn_requester - lowrisc:prim:sec_anchor - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:edn_pkg - lowrisc:prim:sparse_fsm - "fileset_partner ? (partner:systems:ast_pkg)" diff --git a/hw/ip/rstmgr/dv/sva/rstmgr_sva_ifs.core b/hw/ip/rstmgr/dv/sva/rstmgr_sva_ifs.core index bdedf685562ff..eff742449cc7c 100644 --- a/hw/ip/rstmgr/dv/sva/rstmgr_sva_ifs.core +++ b/hw/ip/rstmgr/dv/sva/rstmgr_sva_ifs.core @@ -8,7 +8,7 @@ filesets: files_dv: depend: - lowrisc:ip:lc_ctrl_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:rstmgr files: diff --git a/hw/ip/rstmgr/rstmgr_pkg.core b/hw/ip/rstmgr/rstmgr_pkg.core index 97511dfb561ae..6aa6f66e784e2 100644 --- a/hw/ip/rstmgr/rstmgr_pkg.core +++ b/hw/ip/rstmgr/rstmgr_pkg.core @@ -9,7 +9,7 @@ filesets: files_rtl: depend: - lowrisc:ip:alert_handler_component - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:rstmgr_reg - lowrisc:ip_interfaces:alert_handler_reg - "fileset_top ? (lowrisc:systems:rstmgr_pkg)" diff --git a/hw/ip/rv_core_ibex/rv_core_ibex.core b/hw/ip/rv_core_ibex/rv_core_ibex.core index bd14e14a936b8..4b0c539c83a00 100644 --- a/hw/ip/rv_core_ibex/rv_core_ibex.core +++ b/hw/ip/rv_core_ibex/rv_core_ibex.core @@ -11,7 +11,7 @@ filesets: - lowrisc:ip:edn_requester - lowrisc:ip:lc_ctrl_pkg - lowrisc:ip:otp_ctrl_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:rv_core_ibex_pkg - lowrisc:ip:tlul - lowrisc:ip_interfaces:alert_handler_reg diff --git a/hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core b/hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core index d71a35180c277..b19f07c362390 100644 --- a/hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core +++ b/hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core @@ -9,7 +9,7 @@ filesets: depend: - lowrisc:dv:ralgen - lowrisc:dv:cip_lib - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg files: - pwrmgr_env_pkg.sv - pwrmgr_env_cfg.sv: {is_include_file: true} diff --git a/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core b/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core index 9eaa8fd0db4d5..d35cbce65b7b7 100644 --- a/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core +++ b/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core @@ -7,7 +7,7 @@ description: "PWRMGR DV sim target" filesets: files_rtl: depend: - - lowrisc:ip:pwrmgr + - lowrisc:ip_interfaces:pwrmgr files_dv: depend: - lowrisc:dv:pwrmgr_test diff --git a/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core b/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core index 79631950495e2..8adac26d23551 100644 --- a/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core +++ b/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core @@ -7,7 +7,7 @@ description: "PWRMGR to RSTMGR assertion interface." filesets: files_dv: depend: - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:prim:assert files: - pwrmgr_rstmgr_sva_if.sv diff --git a/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_sva.core b/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_sva.core index b71c2dede28a4..4d606bf4e3522 100644 --- a/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_sva.core +++ b/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_sva.core @@ -9,7 +9,7 @@ filesets: depend: - lowrisc:tlul:headers - lowrisc:fpv:csr_assert_gen - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:dv:clkmgr_pwrmgr_sva_if - lowrisc:dv:pwrmgr_rstmgr_sva_if files: @@ -21,7 +21,7 @@ filesets: files_formal: depend: - - lowrisc:ip:pwrmgr + - lowrisc:ip_interfaces:pwrmgr generate: csr_assert_gen: diff --git a/hw/ip_templates/pwrmgr/pwrmgr.core.tpl b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl new file mode 100644 index 0000000000000..3b83fcde96d92 --- /dev/null +++ b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl @@ -0,0 +1,66 @@ +CAPI=2: +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: ${instance_vlnv("lowrisc:ip:pwrmgr:0.1")} +description: "Power manager RTL" +virtual: + - lowrisc:ip_interfaces:pwrmgr + +filesets: + files_rtl: + depend: + - ${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1")} + - ${instance_vlnv("lowrisc:ip:pwrmgr_reg:0.1")} + - lowrisc:ip:pwrmgr_component + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: pwrmgr + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/ip_templates/pwrmgr/pwrmgr.core b/hw/ip_templates/pwrmgr/pwrmgr_components.core similarity index 95% rename from hw/ip_templates/pwrmgr/pwrmgr.core rename to hw/ip_templates/pwrmgr/pwrmgr_components.core index c384dae955aab..2069107cadb6b 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr.core +++ b/hw/ip_templates/pwrmgr/pwrmgr_components.core @@ -2,7 +2,7 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr:0.1" +name: "lowrisc:ip:pwrmgr_component:0.1" description: "Power manager RTL" filesets: @@ -20,8 +20,7 @@ filesets: - lowrisc:prim:clock_buf - lowrisc:prim:measure - lowrisc:ip_interfaces:alert_handler_reg - - lowrisc:ip:pwrmgr_pkg - - lowrisc:ip:pwrmgr_reg + - lowrisc:ip_interfaces:pwrmgr_pkg files: - rtl/pwrmgr_cdc.sv - rtl/pwrmgr_slow_fsm.sv diff --git a/hw/ip_templates/pwrmgr/pwrmgr_pkg.core b/hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl similarity index 79% rename from hw/ip_templates/pwrmgr/pwrmgr_pkg.core rename to hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl index 3e83cde44fd12..f2d8b0995aaf5 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr_pkg.core +++ b/hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl @@ -2,13 +2,15 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr_pkg:0.1" +name: ${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1")} description: "Power manager package" +virtual: + - lowrisc:ip_interfaces:pwrmgr_pkg filesets: files_rtl: depend: - - lowrisc:ip:pwrmgr_reg + - ${instance_vlnv("lowrisc:ip:pwrmgr_reg")} files: - rtl/pwrmgr_pkg.sv file_type: systemVerilogSource diff --git a/hw/ip_templates/pwrmgr/pwrmgr_reg.core b/hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl similarity index 82% rename from hw/ip_templates/pwrmgr/pwrmgr_reg.core rename to hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl index c20cd917273d8..b2b8124fd5d04 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr_reg.core +++ b/hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl @@ -2,8 +2,10 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr_reg:0.1" +name: ${instance_vlnv("lowrisc:ip:pwrmgr_reg:0.1")} description: "Power manager registers" +virtual: + - lowrisc:ip_interfaces:pwrmgr_reg filesets: files_rtl: diff --git a/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_pkg.sv b/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_pkg.sv deleted file mode 100644 index f55eaaf7a32b4..0000000000000 --- a/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_pkg.sv +++ /dev/null @@ -1,215 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Package auto-generated by `reggen` containing data structure - -package pwrmgr_reg_pkg; - - // Param list - parameter int NumWkups = 1; - parameter int NumRstReqs = 1; - - // Address widths within the block - parameter int BlockAw = 6; - - //////////////////////////// - // Typedefs for registers // - //////////////////////////// - - typedef struct packed { - logic q; - } pwrmgr_reg2hw_intr_state_reg_t; - - typedef struct packed { - logic q; - } pwrmgr_reg2hw_intr_enable_reg_t; - - typedef struct packed { - logic q; - logic qe; - } pwrmgr_reg2hw_intr_test_reg_t; - - typedef struct packed { - struct packed { - logic q; - } low_power_hint; - struct packed { - logic q; - } core_clk_en; - struct packed { - logic q; - } io_clk_en; - struct packed { - logic q; - } usb_clk_en_lp; - struct packed { - logic q; - } usb_clk_en_active; - struct packed { - logic q; - } main_pd_n; - } pwrmgr_reg2hw_control_reg_t; - - typedef struct packed { - logic q; - logic qe; - } pwrmgr_reg2hw_cfg_cdc_sync_reg_t; - - typedef struct packed { - logic q; - } pwrmgr_reg2hw_wakeup_en_mreg_t; - - typedef struct packed { - logic q; - } pwrmgr_reg2hw_reset_en_mreg_t; - - typedef struct packed { - logic q; - } pwrmgr_reg2hw_wake_info_capture_dis_reg_t; - - typedef struct packed { - struct packed { - logic q; - logic qe; - } reasons; - struct packed { - logic q; - logic qe; - } fall_through; - struct packed { - logic q; - logic qe; - } abort; - } pwrmgr_reg2hw_wake_info_reg_t; - - typedef struct packed { - logic d; - logic de; - } pwrmgr_hw2reg_intr_state_reg_t; - - typedef struct packed { - logic d; - } pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t; - - typedef struct packed { - struct packed { - logic d; - logic de; - } low_power_hint; - } pwrmgr_hw2reg_control_reg_t; - - typedef struct packed { - logic d; - logic de; - } pwrmgr_hw2reg_cfg_cdc_sync_reg_t; - - typedef struct packed { - logic d; - logic de; - } pwrmgr_hw2reg_wake_status_mreg_t; - - typedef struct packed { - logic d; - logic de; - } pwrmgr_hw2reg_reset_status_mreg_t; - - typedef struct packed { - struct packed { - logic d; - } reasons; - struct packed { - logic d; - } fall_through; - struct packed { - logic d; - } abort; - } pwrmgr_hw2reg_wake_info_reg_t; - - // Register -> HW type - typedef struct packed { - pwrmgr_reg2hw_intr_state_reg_t intr_state; // [20:20] - pwrmgr_reg2hw_intr_enable_reg_t intr_enable; // [19:19] - pwrmgr_reg2hw_intr_test_reg_t intr_test; // [18:17] - pwrmgr_reg2hw_control_reg_t control; // [16:11] - pwrmgr_reg2hw_cfg_cdc_sync_reg_t cfg_cdc_sync; // [10:9] - pwrmgr_reg2hw_wakeup_en_mreg_t [0:0] wakeup_en; // [8:8] - pwrmgr_reg2hw_reset_en_mreg_t [0:0] reset_en; // [7:7] - pwrmgr_reg2hw_wake_info_capture_dis_reg_t wake_info_capture_dis; // [6:6] - pwrmgr_reg2hw_wake_info_reg_t wake_info; // [5:0] - } pwrmgr_reg2hw_t; - - // HW -> register type - typedef struct packed { - pwrmgr_hw2reg_intr_state_reg_t intr_state; // [13:12] - pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t ctrl_cfg_regwen; // [11:11] - pwrmgr_hw2reg_control_reg_t control; // [10:9] - pwrmgr_hw2reg_cfg_cdc_sync_reg_t cfg_cdc_sync; // [8:7] - pwrmgr_hw2reg_wake_status_mreg_t [0:0] wake_status; // [6:5] - pwrmgr_hw2reg_reset_status_mreg_t [0:0] reset_status; // [4:3] - pwrmgr_hw2reg_wake_info_reg_t wake_info; // [2:0] - } pwrmgr_hw2reg_t; - - // Register offsets - parameter logic [BlockAw-1:0] PWRMGR_INTR_STATE_OFFSET = 6'h 0; - parameter logic [BlockAw-1:0] PWRMGR_INTR_ENABLE_OFFSET = 6'h 4; - parameter logic [BlockAw-1:0] PWRMGR_INTR_TEST_OFFSET = 6'h 8; - parameter logic [BlockAw-1:0] PWRMGR_CTRL_CFG_REGWEN_OFFSET = 6'h c; - parameter logic [BlockAw-1:0] PWRMGR_CONTROL_OFFSET = 6'h 10; - parameter logic [BlockAw-1:0] PWRMGR_CFG_CDC_SYNC_OFFSET = 6'h 14; - parameter logic [BlockAw-1:0] PWRMGR_WAKEUP_EN_REGWEN_OFFSET = 6'h 18; - parameter logic [BlockAw-1:0] PWRMGR_WAKEUP_EN_OFFSET = 6'h 1c; - parameter logic [BlockAw-1:0] PWRMGR_WAKE_STATUS_OFFSET = 6'h 20; - parameter logic [BlockAw-1:0] PWRMGR_RESET_EN_REGWEN_OFFSET = 6'h 24; - parameter logic [BlockAw-1:0] PWRMGR_RESET_EN_OFFSET = 6'h 28; - parameter logic [BlockAw-1:0] PWRMGR_RESET_STATUS_OFFSET = 6'h 2c; - parameter logic [BlockAw-1:0] PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET = 6'h 30; - parameter logic [BlockAw-1:0] PWRMGR_WAKE_INFO_OFFSET = 6'h 34; - - // Reset values for hwext registers and their fields - parameter logic [0:0] PWRMGR_INTR_TEST_RESVAL = 1'h 0; - parameter logic [0:0] PWRMGR_INTR_TEST_WAKEUP_RESVAL = 1'h 0; - parameter logic [0:0] PWRMGR_CTRL_CFG_REGWEN_RESVAL = 1'h 1; - parameter logic [0:0] PWRMGR_CTRL_CFG_REGWEN_EN_RESVAL = 1'h 1; - parameter logic [2:0] PWRMGR_WAKE_INFO_RESVAL = 3'h 0; - parameter logic [0:0] PWRMGR_WAKE_INFO_REASONS_RESVAL = 1'h 0; - parameter logic [0:0] PWRMGR_WAKE_INFO_FALL_THROUGH_RESVAL = 1'h 0; - parameter logic [0:0] PWRMGR_WAKE_INFO_ABORT_RESVAL = 1'h 0; - - // Register index - typedef enum int { - PWRMGR_INTR_STATE, - PWRMGR_INTR_ENABLE, - PWRMGR_INTR_TEST, - PWRMGR_CTRL_CFG_REGWEN, - PWRMGR_CONTROL, - PWRMGR_CFG_CDC_SYNC, - PWRMGR_WAKEUP_EN_REGWEN, - PWRMGR_WAKEUP_EN, - PWRMGR_WAKE_STATUS, - PWRMGR_RESET_EN_REGWEN, - PWRMGR_RESET_EN, - PWRMGR_RESET_STATUS, - PWRMGR_WAKE_INFO_CAPTURE_DIS, - PWRMGR_WAKE_INFO - } pwrmgr_id_e; - - // Register width information to check illegal writes - parameter logic [3:0] PWRMGR_PERMIT [14] = '{ - 4'b 0001, // index[ 0] PWRMGR_INTR_STATE - 4'b 0001, // index[ 1] PWRMGR_INTR_ENABLE - 4'b 0001, // index[ 2] PWRMGR_INTR_TEST - 4'b 0001, // index[ 3] PWRMGR_CTRL_CFG_REGWEN - 4'b 0011, // index[ 4] PWRMGR_CONTROL - 4'b 0001, // index[ 5] PWRMGR_CFG_CDC_SYNC - 4'b 0001, // index[ 6] PWRMGR_WAKEUP_EN_REGWEN - 4'b 0001, // index[ 7] PWRMGR_WAKEUP_EN - 4'b 0001, // index[ 8] PWRMGR_WAKE_STATUS - 4'b 0001, // index[ 9] PWRMGR_RESET_EN_REGWEN - 4'b 0001, // index[10] PWRMGR_RESET_EN - 4'b 0001, // index[11] PWRMGR_RESET_STATUS - 4'b 0001, // index[12] PWRMGR_WAKE_INFO_CAPTURE_DIS - 4'b 0001 // index[13] PWRMGR_WAKE_INFO - }; - -endpackage diff --git a/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_top.sv b/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_top.sv deleted file mode 100644 index 3c9198dc73624..0000000000000 --- a/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_top.sv +++ /dev/null @@ -1,947 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Top module auto-generated by `reggen` - -`include "prim_assert.sv" - -module pwrmgr_reg_top ( - input clk_i, - input rst_ni, - input tlul_pkg::tl_h2d_t tl_i, - output tlul_pkg::tl_d2h_t tl_o, - // To HW - output pwrmgr_reg_pkg::pwrmgr_reg2hw_t reg2hw, // Write - input pwrmgr_reg_pkg::pwrmgr_hw2reg_t hw2reg, // Read - - // Integrity check errors - output logic intg_err_o -); - - import pwrmgr_reg_pkg::* ; - - localparam int AW = 6; - localparam int DW = 32; - localparam int DBW = DW/8; // Byte Width - - // register signals - logic reg_we; - logic reg_re; - logic [AW-1:0] reg_addr; - logic [DW-1:0] reg_wdata; - logic [DBW-1:0] reg_be; - logic [DW-1:0] reg_rdata; - logic reg_error; - - logic addrmiss, wr_err; - - logic [DW-1:0] reg_rdata_next; - logic reg_busy; - - tlul_pkg::tl_h2d_t tl_reg_h2d; - tlul_pkg::tl_d2h_t tl_reg_d2h; - - - // incoming payload check - logic intg_err; - tlul_cmd_intg_chk u_chk ( - .tl_i(tl_i), - .err_o(intg_err) - ); - - // also check for spurious write enables - logic reg_we_err; - logic [13:0] reg_we_check; - prim_reg_we_check #( - .OneHotWidth(14) - ) u_prim_reg_we_check ( - .clk_i(clk_i), - .rst_ni(rst_ni), - .oh_i (reg_we_check), - .en_i (reg_we && !addrmiss), - .err_o (reg_we_err) - ); - - logic err_q; - always_ff @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - err_q <= '0; - end else if (intg_err || reg_we_err) begin - err_q <= 1'b1; - end - end - - // integrity error output is permanent and should be used for alert generation - // register errors are transactional - assign intg_err_o = err_q | intg_err | reg_we_err; - - // outgoing integrity generation - tlul_pkg::tl_d2h_t tl_o_pre; - tlul_rsp_intg_gen #( - .EnableRspIntgGen(1), - .EnableDataIntgGen(1) - ) u_rsp_intg_gen ( - .tl_i(tl_o_pre), - .tl_o(tl_o) - ); - - assign tl_reg_h2d = tl_i; - assign tl_o_pre = tl_reg_d2h; - - tlul_adapter_reg #( - .RegAw(AW), - .RegDw(DW), - .EnableDataIntgGen(0) - ) u_reg_if ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - .tl_i (tl_reg_h2d), - .tl_o (tl_reg_d2h), - - .en_ifetch_i(prim_mubi_pkg::MuBi4False), - .intg_error_o(), - - .we_o (reg_we), - .re_o (reg_re), - .addr_o (reg_addr), - .wdata_o (reg_wdata), - .be_o (reg_be), - .busy_i (reg_busy), - .rdata_i (reg_rdata), - .error_i (reg_error) - ); - - // cdc oversampling signals - - assign reg_rdata = reg_rdata_next ; - assign reg_error = addrmiss | wr_err | intg_err; - - // Define SW related signals - // Format: __{wd|we|qs} - // or _{wd|we|qs} if field == 1 or 0 - logic intr_state_we; - logic intr_state_qs; - logic intr_state_wd; - logic intr_enable_we; - logic intr_enable_qs; - logic intr_enable_wd; - logic intr_test_we; - logic intr_test_wd; - logic ctrl_cfg_regwen_re; - logic ctrl_cfg_regwen_qs; - logic control_we; - logic control_low_power_hint_qs; - logic control_low_power_hint_wd; - logic control_core_clk_en_qs; - logic control_core_clk_en_wd; - logic control_io_clk_en_qs; - logic control_io_clk_en_wd; - logic control_usb_clk_en_lp_qs; - logic control_usb_clk_en_lp_wd; - logic control_usb_clk_en_active_qs; - logic control_usb_clk_en_active_wd; - logic control_main_pd_n_qs; - logic control_main_pd_n_wd; - logic cfg_cdc_sync_we; - logic cfg_cdc_sync_qs; - logic cfg_cdc_sync_wd; - logic wakeup_en_regwen_we; - logic wakeup_en_regwen_qs; - logic wakeup_en_regwen_wd; - logic wakeup_en_we; - logic wakeup_en_qs; - logic wakeup_en_wd; - logic wake_status_qs; - logic reset_en_regwen_we; - logic reset_en_regwen_qs; - logic reset_en_regwen_wd; - logic reset_en_we; - logic reset_en_qs; - logic reset_en_wd; - logic reset_status_qs; - logic wake_info_capture_dis_we; - logic wake_info_capture_dis_qs; - logic wake_info_capture_dis_wd; - logic wake_info_re; - logic wake_info_we; - logic wake_info_reasons_qs; - logic wake_info_reasons_wd; - logic wake_info_fall_through_qs; - logic wake_info_fall_through_wd; - logic wake_info_abort_qs; - logic wake_info_abort_wd; - - // Register instances - // R[intr_state]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW1C), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_intr_state ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (intr_state_we), - .wd (intr_state_wd), - - // from internal hardware - .de (hw2reg.intr_state.de), - .d (hw2reg.intr_state.d), - - // to internal hardware - .qe (), - .q (reg2hw.intr_state.q), - .ds (), - - // to register interface (read) - .qs (intr_state_qs) - ); - - - // R[intr_enable]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_intr_enable ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (intr_enable_we), - .wd (intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.intr_enable.q), - .ds (), - - // to register interface (read) - .qs (intr_enable_qs) - ); - - - // R[intr_test]: V(True) - logic intr_test_qe; - logic [0:0] intr_test_flds_we; - assign intr_test_qe = &intr_test_flds_we; - prim_subreg_ext #( - .DW (1) - ) u_intr_test ( - .re (1'b0), - .we (intr_test_we), - .wd (intr_test_wd), - .d ('0), - .qre (), - .qe (intr_test_flds_we[0]), - .q (reg2hw.intr_test.q), - .ds (), - .qs () - ); - assign reg2hw.intr_test.qe = intr_test_qe; - - - // R[ctrl_cfg_regwen]: V(True) - prim_subreg_ext #( - .DW (1) - ) u_ctrl_cfg_regwen ( - .re (ctrl_cfg_regwen_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.ctrl_cfg_regwen.d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (ctrl_cfg_regwen_qs) - ); - - - // R[control]: V(False) - // Create REGWEN-gated WE signal - logic control_gated_we; - assign control_gated_we = control_we & ctrl_cfg_regwen_qs; - // F[low_power_hint]: 0:0 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_control_low_power_hint ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_low_power_hint_wd), - - // from internal hardware - .de (hw2reg.control.low_power_hint.de), - .d (hw2reg.control.low_power_hint.d), - - // to internal hardware - .qe (), - .q (reg2hw.control.low_power_hint.q), - .ds (), - - // to register interface (read) - .qs (control_low_power_hint_qs) - ); - - // F[core_clk_en]: 4:4 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_control_core_clk_en ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_core_clk_en_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.control.core_clk_en.q), - .ds (), - - // to register interface (read) - .qs (control_core_clk_en_qs) - ); - - // F[io_clk_en]: 5:5 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_control_io_clk_en ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_io_clk_en_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.control.io_clk_en.q), - .ds (), - - // to register interface (read) - .qs (control_io_clk_en_qs) - ); - - // F[usb_clk_en_lp]: 6:6 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_control_usb_clk_en_lp ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_usb_clk_en_lp_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.control.usb_clk_en_lp.q), - .ds (), - - // to register interface (read) - .qs (control_usb_clk_en_lp_qs) - ); - - // F[usb_clk_en_active]: 7:7 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_control_usb_clk_en_active ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_usb_clk_en_active_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.control.usb_clk_en_active.q), - .ds (), - - // to register interface (read) - .qs (control_usb_clk_en_active_qs) - ); - - // F[main_pd_n]: 8:8 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_control_main_pd_n ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_main_pd_n_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.control.main_pd_n.q), - .ds (), - - // to register interface (read) - .qs (control_main_pd_n_qs) - ); - - - // R[cfg_cdc_sync]: V(False) - logic cfg_cdc_sync_qe; - logic [0:0] cfg_cdc_sync_flds_we; - prim_flop #( - .Width(1), - .ResetValue(0) - ) u_cfg_cdc_sync0_qe ( - .clk_i(clk_i), - .rst_ni(rst_ni), - .d_i(&cfg_cdc_sync_flds_we), - .q_o(cfg_cdc_sync_qe) - ); - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_cfg_cdc_sync ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (cfg_cdc_sync_we), - .wd (cfg_cdc_sync_wd), - - // from internal hardware - .de (hw2reg.cfg_cdc_sync.de), - .d (hw2reg.cfg_cdc_sync.d), - - // to internal hardware - .qe (cfg_cdc_sync_flds_we[0]), - .q (reg2hw.cfg_cdc_sync.q), - .ds (), - - // to register interface (read) - .qs (cfg_cdc_sync_qs) - ); - assign reg2hw.cfg_cdc_sync.qe = cfg_cdc_sync_qe; - - - // R[wakeup_en_regwen]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_wakeup_en_regwen ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (wakeup_en_regwen_we), - .wd (wakeup_en_regwen_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (wakeup_en_regwen_qs) - ); - - - // Subregister 0 of Multireg wakeup_en - // R[wakeup_en]: V(False) - // Create REGWEN-gated WE signal - logic wakeup_en_gated_we; - assign wakeup_en_gated_we = wakeup_en_we & wakeup_en_regwen_qs; - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_wakeup_en ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (wakeup_en_gated_we), - .wd (wakeup_en_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.wakeup_en[0].q), - .ds (), - - // to register interface (read) - .qs (wakeup_en_qs) - ); - - - // Subregister 0 of Multireg wake_status - // R[wake_status]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_wake_status ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.wake_status[0].de), - .d (hw2reg.wake_status[0].d), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (wake_status_qs) - ); - - - // R[reset_en_regwen]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_reset_en_regwen ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (reset_en_regwen_we), - .wd (reset_en_regwen_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (reset_en_regwen_qs) - ); - - - // Subregister 0 of Multireg reset_en - // R[reset_en]: V(False) - // Create REGWEN-gated WE signal - logic reset_en_gated_we; - assign reset_en_gated_we = reset_en_we & reset_en_regwen_qs; - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_reset_en ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (reset_en_gated_we), - .wd (reset_en_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.reset_en[0].q), - .ds (), - - // to register interface (read) - .qs (reset_en_qs) - ); - - - // Subregister 0 of Multireg reset_status - // R[reset_status]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_reset_status ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.reset_status[0].de), - .d (hw2reg.reset_status[0].d), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (reset_status_qs) - ); - - - // R[wake_info_capture_dis]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_wake_info_capture_dis ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (wake_info_capture_dis_we), - .wd (wake_info_capture_dis_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.wake_info_capture_dis.q), - .ds (), - - // to register interface (read) - .qs (wake_info_capture_dis_qs) - ); - - - // R[wake_info]: V(True) - logic wake_info_qe; - logic [2:0] wake_info_flds_we; - assign wake_info_qe = &wake_info_flds_we; - // F[reasons]: 0:0 - prim_subreg_ext #( - .DW (1) - ) u_wake_info_reasons ( - .re (wake_info_re), - .we (wake_info_we), - .wd (wake_info_reasons_wd), - .d (hw2reg.wake_info.reasons.d), - .qre (), - .qe (wake_info_flds_we[0]), - .q (reg2hw.wake_info.reasons.q), - .ds (), - .qs (wake_info_reasons_qs) - ); - assign reg2hw.wake_info.reasons.qe = wake_info_qe; - - // F[fall_through]: 1:1 - prim_subreg_ext #( - .DW (1) - ) u_wake_info_fall_through ( - .re (wake_info_re), - .we (wake_info_we), - .wd (wake_info_fall_through_wd), - .d (hw2reg.wake_info.fall_through.d), - .qre (), - .qe (wake_info_flds_we[1]), - .q (reg2hw.wake_info.fall_through.q), - .ds (), - .qs (wake_info_fall_through_qs) - ); - assign reg2hw.wake_info.fall_through.qe = wake_info_qe; - - // F[abort]: 2:2 - prim_subreg_ext #( - .DW (1) - ) u_wake_info_abort ( - .re (wake_info_re), - .we (wake_info_we), - .wd (wake_info_abort_wd), - .d (hw2reg.wake_info.abort.d), - .qre (), - .qe (wake_info_flds_we[2]), - .q (reg2hw.wake_info.abort.q), - .ds (), - .qs (wake_info_abort_qs) - ); - assign reg2hw.wake_info.abort.qe = wake_info_qe; - - - - logic [13:0] addr_hit; - always_comb begin - addr_hit = '0; - addr_hit[ 0] = (reg_addr == PWRMGR_INTR_STATE_OFFSET); - addr_hit[ 1] = (reg_addr == PWRMGR_INTR_ENABLE_OFFSET); - addr_hit[ 2] = (reg_addr == PWRMGR_INTR_TEST_OFFSET); - addr_hit[ 3] = (reg_addr == PWRMGR_CTRL_CFG_REGWEN_OFFSET); - addr_hit[ 4] = (reg_addr == PWRMGR_CONTROL_OFFSET); - addr_hit[ 5] = (reg_addr == PWRMGR_CFG_CDC_SYNC_OFFSET); - addr_hit[ 6] = (reg_addr == PWRMGR_WAKEUP_EN_REGWEN_OFFSET); - addr_hit[ 7] = (reg_addr == PWRMGR_WAKEUP_EN_OFFSET); - addr_hit[ 8] = (reg_addr == PWRMGR_WAKE_STATUS_OFFSET); - addr_hit[ 9] = (reg_addr == PWRMGR_RESET_EN_REGWEN_OFFSET); - addr_hit[10] = (reg_addr == PWRMGR_RESET_EN_OFFSET); - addr_hit[11] = (reg_addr == PWRMGR_RESET_STATUS_OFFSET); - addr_hit[12] = (reg_addr == PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET); - addr_hit[13] = (reg_addr == PWRMGR_WAKE_INFO_OFFSET); - end - - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; - - // Check sub-word write is permitted - always_comb begin - wr_err = (reg_we & - ((addr_hit[ 0] & (|(PWRMGR_PERMIT[ 0] & ~reg_be))) | - (addr_hit[ 1] & (|(PWRMGR_PERMIT[ 1] & ~reg_be))) | - (addr_hit[ 2] & (|(PWRMGR_PERMIT[ 2] & ~reg_be))) | - (addr_hit[ 3] & (|(PWRMGR_PERMIT[ 3] & ~reg_be))) | - (addr_hit[ 4] & (|(PWRMGR_PERMIT[ 4] & ~reg_be))) | - (addr_hit[ 5] & (|(PWRMGR_PERMIT[ 5] & ~reg_be))) | - (addr_hit[ 6] & (|(PWRMGR_PERMIT[ 6] & ~reg_be))) | - (addr_hit[ 7] & (|(PWRMGR_PERMIT[ 7] & ~reg_be))) | - (addr_hit[ 8] & (|(PWRMGR_PERMIT[ 8] & ~reg_be))) | - (addr_hit[ 9] & (|(PWRMGR_PERMIT[ 9] & ~reg_be))) | - (addr_hit[10] & (|(PWRMGR_PERMIT[10] & ~reg_be))) | - (addr_hit[11] & (|(PWRMGR_PERMIT[11] & ~reg_be))) | - (addr_hit[12] & (|(PWRMGR_PERMIT[12] & ~reg_be))) | - (addr_hit[13] & (|(PWRMGR_PERMIT[13] & ~reg_be))))); - end - - // Generate write-enables - assign intr_state_we = addr_hit[0] & reg_we & !reg_error; - - assign intr_state_wd = reg_wdata[0]; - assign intr_enable_we = addr_hit[1] & reg_we & !reg_error; - - assign intr_enable_wd = reg_wdata[0]; - assign intr_test_we = addr_hit[2] & reg_we & !reg_error; - - assign intr_test_wd = reg_wdata[0]; - assign ctrl_cfg_regwen_re = addr_hit[3] & reg_re & !reg_error; - assign control_we = addr_hit[4] & reg_we & !reg_error; - - assign control_low_power_hint_wd = reg_wdata[0]; - - assign control_core_clk_en_wd = reg_wdata[4]; - - assign control_io_clk_en_wd = reg_wdata[5]; - - assign control_usb_clk_en_lp_wd = reg_wdata[6]; - - assign control_usb_clk_en_active_wd = reg_wdata[7]; - - assign control_main_pd_n_wd = reg_wdata[8]; - assign cfg_cdc_sync_we = addr_hit[5] & reg_we & !reg_error; - - assign cfg_cdc_sync_wd = reg_wdata[0]; - assign wakeup_en_regwen_we = addr_hit[6] & reg_we & !reg_error; - - assign wakeup_en_regwen_wd = reg_wdata[0]; - assign wakeup_en_we = addr_hit[7] & reg_we & !reg_error; - - assign wakeup_en_wd = reg_wdata[0]; - assign reset_en_regwen_we = addr_hit[9] & reg_we & !reg_error; - - assign reset_en_regwen_wd = reg_wdata[0]; - assign reset_en_we = addr_hit[10] & reg_we & !reg_error; - - assign reset_en_wd = reg_wdata[0]; - assign wake_info_capture_dis_we = addr_hit[12] & reg_we & !reg_error; - - assign wake_info_capture_dis_wd = reg_wdata[0]; - assign wake_info_re = addr_hit[13] & reg_re & !reg_error; - assign wake_info_we = addr_hit[13] & reg_we & !reg_error; - - assign wake_info_reasons_wd = reg_wdata[0]; - - assign wake_info_fall_through_wd = reg_wdata[1]; - - assign wake_info_abort_wd = reg_wdata[2]; - - // Assign write-enables to checker logic vector. - always_comb begin - reg_we_check = '0; - reg_we_check[0] = intr_state_we; - reg_we_check[1] = intr_enable_we; - reg_we_check[2] = intr_test_we; - reg_we_check[3] = 1'b0; - reg_we_check[4] = control_gated_we; - reg_we_check[5] = cfg_cdc_sync_we; - reg_we_check[6] = wakeup_en_regwen_we; - reg_we_check[7] = wakeup_en_gated_we; - reg_we_check[8] = 1'b0; - reg_we_check[9] = reset_en_regwen_we; - reg_we_check[10] = reset_en_gated_we; - reg_we_check[11] = 1'b0; - reg_we_check[12] = wake_info_capture_dis_we; - reg_we_check[13] = wake_info_we; - end - - // Read data return - always_comb begin - reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin - reg_rdata_next[0] = intr_state_qs; - end - - addr_hit[1]: begin - reg_rdata_next[0] = intr_enable_qs; - end - - addr_hit[2]: begin - reg_rdata_next[0] = '0; - end - - addr_hit[3]: begin - reg_rdata_next[0] = ctrl_cfg_regwen_qs; - end - - addr_hit[4]: begin - reg_rdata_next[0] = control_low_power_hint_qs; - reg_rdata_next[4] = control_core_clk_en_qs; - reg_rdata_next[5] = control_io_clk_en_qs; - reg_rdata_next[6] = control_usb_clk_en_lp_qs; - reg_rdata_next[7] = control_usb_clk_en_active_qs; - reg_rdata_next[8] = control_main_pd_n_qs; - end - - addr_hit[5]: begin - reg_rdata_next[0] = cfg_cdc_sync_qs; - end - - addr_hit[6]: begin - reg_rdata_next[0] = wakeup_en_regwen_qs; - end - - addr_hit[7]: begin - reg_rdata_next[0] = wakeup_en_qs; - end - - addr_hit[8]: begin - reg_rdata_next[0] = wake_status_qs; - end - - addr_hit[9]: begin - reg_rdata_next[0] = reset_en_regwen_qs; - end - - addr_hit[10]: begin - reg_rdata_next[0] = reset_en_qs; - end - - addr_hit[11]: begin - reg_rdata_next[0] = reset_status_qs; - end - - addr_hit[12]: begin - reg_rdata_next[0] = wake_info_capture_dis_qs; - end - - addr_hit[13]: begin - reg_rdata_next[0] = wake_info_reasons_qs; - reg_rdata_next[1] = wake_info_fall_through_qs; - reg_rdata_next[2] = wake_info_abort_qs; - end - - default: begin - reg_rdata_next = '1; - end - endcase - end - - // shadow busy - logic shadow_busy; - assign shadow_busy = 1'b0; - - // register busy - assign reg_busy = shadow_busy; - - // Unused signal tieoff - - // wdata / byte enable are not always fully used - // add a blanket unused statement to handle lint waivers - logic unused_wdata; - logic unused_be; - assign unused_wdata = ^reg_wdata; - assign unused_be = ^reg_be; - - // Assertions for Register Interface - `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) - `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) - - `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) - - `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) - - // this is formulated as an assumption such that the FPV testbenches do disprove this - // property by mistake - //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) - -endmodule diff --git a/hw/top_earlgrey/dv/chip_sim.core b/hw/top_earlgrey/dv/chip_sim.core index c79fe5592d1a6..c8732a52a3b1c 100644 --- a/hw/top_earlgrey/dv/chip_sim.core +++ b/hw/top_earlgrey/dv/chip_sim.core @@ -16,6 +16,9 @@ filesets: files_dv: depend: + # Place the autogen packages first to avoid conflicts + - lowrisc:opentitan:top_earlgrey_alert_handler_reg + - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg - lowrisc:ip:tlul - lowrisc:dv:chip_test - lowrisc:dv:clkmgr_sva diff --git a/hw/top_earlgrey/dv/env/chip_env.core b/hw/top_earlgrey/dv/env/chip_env.core index b7cf1059cbd30..a35712a9091a3 100644 --- a/hw/top_earlgrey/dv/env/chip_env.core +++ b/hw/top_earlgrey/dv/env/chip_env.core @@ -31,7 +31,7 @@ filesets: - lowrisc:dv:i2c_agent - lowrisc:dv:pattgen_agent - lowrisc:ip:otp_ctrl_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:dv:lc_ctrl_dv_utils - "!fileset_partner ? (lowrisc:systems:ast_pkg)" - "fileset_partner ? (partner:systems:ast_pkg)" diff --git a/hw/top_earlgrey/dv/sva/top_earlgrey_sva.core b/hw/top_earlgrey/dv/sva/top_earlgrey_sva.core index d429f609e9db8..e86c330f155ea 100644 --- a/hw/top_earlgrey/dv/sva/top_earlgrey_sva.core +++ b/hw/top_earlgrey/dv/sva/top_earlgrey_sva.core @@ -7,7 +7,7 @@ description: "TOP_EARLGREY assertion modules and bind file." filesets: files_dv: depend: - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:prim:assert - lowrisc:systems:top_earlgrey files: diff --git a/hw/top_earlgrey/ip/clkmgr/clkmgr.core b/hw/top_earlgrey/ip/clkmgr/clkmgr.core index b146e9cd3305b..06422de232a83 100644 --- a/hw/top_earlgrey/ip/clkmgr/clkmgr.core +++ b/hw/top_earlgrey/ip/clkmgr/clkmgr.core @@ -9,7 +9,7 @@ filesets: files_rtl: depend: - lowrisc:ip:lc_ctrl_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:tlul - lowrisc:prim:all - lowrisc:prim:buf diff --git a/hw/top_earlgrey/ip/clkmgr/clkmgr_pkg.core b/hw/top_earlgrey/ip/clkmgr/clkmgr_pkg.core index c8c3b25229ae0..c47cf27c055fd 100644 --- a/hw/top_earlgrey/ip/clkmgr/clkmgr_pkg.core +++ b/hw/top_earlgrey/ip/clkmgr/clkmgr_pkg.core @@ -9,7 +9,7 @@ filesets: files_rtl: depend: - lowrisc:constants:top_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg files: - rtl/autogen/clkmgr_pkg.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/ip/rstmgr/system_rstmgr_pkg.core b/hw/top_earlgrey/ip/rstmgr/system_rstmgr_pkg.core index aaf4e9d5e052d..ec08c5d8b2714 100644 --- a/hw/top_earlgrey/ip/rstmgr/system_rstmgr_pkg.core +++ b/hw/top_earlgrey/ip/rstmgr/system_rstmgr_pkg.core @@ -8,7 +8,7 @@ description: "Auto-generated reset manager package for top_earlgrey" filesets: files_rtl: depend: - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:rstmgr_reg - lowrisc:ip_interfaces:alert_handler_reg - lowrisc:ip:alert_handler_component diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core index d71a35180c277..b19f07c362390 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core @@ -9,7 +9,7 @@ filesets: depend: - lowrisc:dv:ralgen - lowrisc:dv:cip_lib - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg files: - pwrmgr_env_pkg.sv - pwrmgr_env_cfg.sv: {is_include_file: true} diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core index 9eaa8fd0db4d5..d35cbce65b7b7 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core @@ -7,7 +7,7 @@ description: "PWRMGR DV sim target" filesets: files_rtl: depend: - - lowrisc:ip:pwrmgr + - lowrisc:ip_interfaces:pwrmgr files_dv: depend: - lowrisc:dv:pwrmgr_test diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core index 79631950495e2..8adac26d23551 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core @@ -7,7 +7,7 @@ description: "PWRMGR to RSTMGR assertion interface." filesets: files_dv: depend: - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:prim:assert files: - pwrmgr_rstmgr_sva_if.sv diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core index b71c2dede28a4..4d606bf4e3522 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core @@ -9,7 +9,7 @@ filesets: depend: - lowrisc:tlul:headers - lowrisc:fpv:csr_assert_gen - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:dv:clkmgr_pwrmgr_sva_if - lowrisc:dv:pwrmgr_rstmgr_sva_if files: @@ -21,7 +21,7 @@ filesets: files_formal: depend: - - lowrisc:ip:pwrmgr + - lowrisc:ip_interfaces:pwrmgr generate: csr_assert_gen: diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core index c384dae955aab..a12e1d70b1393 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core @@ -2,32 +2,17 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr:0.1" +name: lowrisc:opentitan:top_earlgrey_pwrmgr:0.1 description: "Power manager RTL" +virtual: + - lowrisc:ip_interfaces:pwrmgr filesets: files_rtl: depend: - - lowrisc:ip:tlul - - lowrisc:prim:esc - - lowrisc:prim:lc_sync - - lowrisc:prim:lc_sender - - lowrisc:prim:all - - lowrisc:ip:rom_ctrl_pkg - - lowrisc:ip:lc_ctrl_pkg - - lowrisc:prim:sparse_fsm - - lowrisc:prim:mubi - - lowrisc:prim:clock_buf - - lowrisc:prim:measure - - lowrisc:ip_interfaces:alert_handler_reg - - lowrisc:ip:pwrmgr_pkg - - lowrisc:ip:pwrmgr_reg - files: - - rtl/pwrmgr_cdc.sv - - rtl/pwrmgr_slow_fsm.sv - - rtl/pwrmgr_fsm.sv - - rtl/pwrmgr_wake_info.sv - - rtl/pwrmgr.sv + - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1 + - lowrisc:opentitan:top_earlgrey_pwrmgr_reg:0.1 + - lowrisc:ip:pwrmgr_component file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core new file mode 100644 index 0000000000000..2069107cadb6b --- /dev/null +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core @@ -0,0 +1,80 @@ +CAPI=2: +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:ip:pwrmgr_component:0.1" +description: "Power manager RTL" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:esc + - lowrisc:prim:lc_sync + - lowrisc:prim:lc_sender + - lowrisc:prim:all + - lowrisc:ip:rom_ctrl_pkg + - lowrisc:ip:lc_ctrl_pkg + - lowrisc:prim:sparse_fsm + - lowrisc:prim:mubi + - lowrisc:prim:clock_buf + - lowrisc:prim:measure + - lowrisc:ip_interfaces:alert_handler_reg + - lowrisc:ip_interfaces:pwrmgr_pkg + files: + - rtl/pwrmgr_cdc.sv + - rtl/pwrmgr_slow_fsm.sv + - rtl/pwrmgr_fsm.sv + - rtl/pwrmgr_wake_info.sv + - rtl/pwrmgr.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: pwrmgr + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core index 3e83cde44fd12..71d3abdcafc86 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core @@ -2,13 +2,15 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr_pkg:0.1" +name: lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1 description: "Power manager package" +virtual: + - lowrisc:ip_interfaces:pwrmgr_pkg filesets: files_rtl: depend: - - lowrisc:ip:pwrmgr_reg + - lowrisc:opentitan:top_earlgrey_pwrmgr_reg files: - rtl/pwrmgr_pkg.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core index c20cd917273d8..75361f737b0b8 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core @@ -2,8 +2,10 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr_reg:0.1" +name: lowrisc:opentitan:top_earlgrey_pwrmgr_reg:0.1 description: "Power manager registers" +virtual: + - lowrisc:ip_interfaces:pwrmgr_reg filesets: files_rtl: diff --git a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson index 1bb7e093dbd68..be8ef48fe87e2 100644 --- a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson +++ b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson @@ -175,7 +175,7 @@ ] }, { name: pwrmgr - fusesoc_core: lowrisc:ip:pwrmgr + fusesoc_core: lowrisc:ip_interfaces:pwrmgr import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], rel_path: "hw/top_earlgrey/ip_autogen/pwrmgr/lint/{tool}", overrides: [ diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core index e2e3536fcfaac..4dd99a51b247c 100644 --- a/hw/top_earlgrey/top_earlgrey.core +++ b/hw/top_earlgrey/top_earlgrey.core @@ -7,6 +7,9 @@ description: "Technology-independent Earl Grey toplevel" filesets: files_rtl_generic: depend: + # Place the autogen packages first to avoid conflicts + - lowrisc:opentitan:top_earlgrey_alert_handler_reg + - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg - lowrisc:ip:uart:0.1 - lowrisc:opentitan:top_earlgrey_alert_handler - lowrisc:ip:gpio @@ -41,7 +44,7 @@ filesets: - lowrisc:top_earlgrey:xbar_main - lowrisc:top_earlgrey:xbar_peri - lowrisc:ip:rstmgr - - lowrisc:ip:pwrmgr + - lowrisc:opentitan:top_earlgrey_pwrmgr - lowrisc:ip:aon_timer - lowrisc:ip:adc_ctrl - lowrisc:ip:sysrst_ctrl diff --git a/hw/top_englishbreakfast/lint/top_englishbreakfast_lint_cfgs.hjson b/hw/top_englishbreakfast/lint/top_englishbreakfast_lint_cfgs.hjson index 76975e3855fba..7e5090d6f52a3 100644 --- a/hw/top_englishbreakfast/lint/top_englishbreakfast_lint_cfgs.hjson +++ b/hw/top_englishbreakfast/lint/top_englishbreakfast_lint_cfgs.hjson @@ -41,7 +41,7 @@ ] }, { name: pwrmgr - fusesoc_core: lowrisc:ip:pwrmgr + fusesoc_core: lowrisc:ip_interfaces:pwrmgr import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], rel_path: "hw/ip/pwrmgr/lint/{tool}", overrides: [ diff --git a/hw/top_englishbreakfast/top_englishbreakfast.core b/hw/top_englishbreakfast/top_englishbreakfast.core index 981cc42037b68..969a2b0130c4d 100644 --- a/hw/top_englishbreakfast/top_englishbreakfast.core +++ b/hw/top_englishbreakfast/top_englishbreakfast.core @@ -39,7 +39,7 @@ filesets: - lowrisc:top_englishbreakfast:xbar_main - lowrisc:top_englishbreakfast:xbar_peri - lowrisc:ip:rstmgr - - lowrisc:ip:pwrmgr + - lowrisc:opentitan:top_englishbreakfast_pwrmgr - lowrisc:ip:rom_ctrl - lowrisc:ip:aon_timer diff --git a/util/topgen-fusesoc.py b/util/topgen-fusesoc.py index 61114341d8104..a74482c973ec3 100755 --- a/util/topgen-fusesoc.py +++ b/util/topgen-fusesoc.py @@ -125,7 +125,7 @@ def main(): 'lowrisc:constants:top_pkg', 'lowrisc:prim:util', 'lowrisc:ip:lc_ctrl_pkg', - 'lowrisc:ip:pwrmgr_pkg', + 'lowrisc:ip_interfaces:pwrmgr_pkg', # rstmgr 'lowrisc:prim:clock_mux2', # clkmgr