[sival,flash_ctrl] complete flash_ctrl sival

hw/top_earlgrey/data/ip/chip_flash_ctrl_testplan.hjson

@@ -18,6 +18,7 @@
               different seed values.
 
             - This test needs to execute as a boot rom image.
+            - In sival, this will be covered by manuf_ft_provision_rma_token_and_personalization.
             '''
       features: ["FLASH_CTRL.INIT.SCRAMBLING_KEYS", "FLASH_CTRL.INIT.ROOT_SEEDS",
                  "FLASH_CTRL.INFO.CREATOR_PARTITION", "FLASH_CTRL.INFO.OWNER_PARTITION"]
@@ -38,6 +39,7 @@
       lc_states: ["DEV", "PROD", "PROD_END", "RMA"]
       tests: ["chip_sw_flash_ctrl_access",
               "chip_sw_flash_ctrl_access_jitter_en"]
+      bazel: ["//sw/device/tests:flash_ctrl_ops_test"]
     }
     {
       name: chip_sw_flash_ctrl_ops
@@ -52,6 +54,7 @@
       si_stage: SV3
       lc_states: ["DEV", "PROD", "PROD_END", "RMA"]
       tests: ["chip_sw_flash_ctrl_ops", "chip_sw_flash_ctrl_ops_jitter_en"]
+      bazel: ["//sw/device/tests:flash_ctrl_ops_test"]
     }
     {
       name: chip_sw_flash_memory_protection
@@ -66,7 +69,8 @@
       stage: V3
       si_stage: SV3
       lc_states: ["DEV", "PROD", "PROD_END", "RMA"]
-      tests: []
+      tests: ["chip_sw_flash_ctrl_mem_protection"]
+      bazel: ["//sw/device/tests:flash_ctrl_mem_protection_test"]
     }
     {
       name: chip_sw_flash_rma_unlocked
@@ -121,6 +125,7 @@
       si_stage: SV3
       lc_states: ["DEV", "PROD", "PROD_END", "RMA"]
       tests: ["chip_sw_flash_ctrl_idle_low_power"]
+      bazel: ["//sw/device/tests:flash_ctrl_idle_low_power_test"]
     }
     {
       name: chip_sw_flash_keymgr_seeds
@@ -148,6 +153,9 @@
       si_stage: SV3
       lc_states: ["DEV", "PROD", "PROD_END", "RMA"]
       tests: ["chip_sw_flash_ctrl_lc_rw_en"]
+      bazel: ["//sw/device/tests:flash_ctrl_info_access_lc_states",
+              "//sw/device/tests:flash_ctrl_info_access_lc_states_personalized"]
+
     }
     {
       name: chip_sw_flash_creator_seed_wipe_on_rma
@@ -158,6 +166,7 @@
       si_stage: SV3
       lc_states: ["DEV", "PROD", "PROD_END", "RMA"]
       tests: ["chip_sw_flash_rma_unlocked"]
+      bazel: ["//sw/device/tests:flash_ctrl_rma_test"]
     }
     {
       name: chip_sw_flash_lc_owner_seed_sw_rw_en
@@ -172,6 +181,7 @@
       si_stage: SV3
       lc_states: ["DEV", "PROD", "PROD_END", "RMA"]
       tests: ["chip_sw_flash_ctrl_lc_rw_en"]
+      bazel: ["//sw/device/tests:flash_ctrl_info_access_lc_states"]
     }
     {
       name: chip_sw_flash_lc_iso_part_sw_rd_en
@@ -186,6 +196,7 @@
       si_stage: SV3
       lc_states: ["PROD", "PROD_END", "RMA"]
       tests: ["chip_sw_flash_ctrl_lc_rw_en"]
+      bazel: ["//sw/device/tests:flash_ctrl_info_access_lc_states"]
     }
     {
       name: chip_sw_flash_lc_iso_part_sw_wr_en
@@ -200,6 +211,7 @@
       si_stage: SV3
       lc_states: ["TEST_UNLOCKED", "DEV", "PROD", "PROD_END", "RMA"]
       tests: ["chip_sw_flash_ctrl_lc_rw_en"]
+      bazel: ["//sw/device/tests:flash_ctrl_info_access_lc_states"]
     }
     {
       name: chip_sw_flash_lc_seed_hw_rd_en
@@ -209,6 +221,7 @@
               that this LC signal transitions from 0 to 1 and back to 0. Verify that the flash ctrl
               does (or does not) read the creator and owner partitions to fetch the seeds for the
               keymgr.
+            - In sival, this will be covered by manuf_ft_provision_rma_token_and_personalization.
             '''
       features: ["FLASH_CTRL.INIT.ROOT_SEEDS"]
       stage: V2
@@ -230,8 +243,7 @@
             '''
       features: ["FLASH_CTRL.ESCALATION"]
       stage: V2
-      si_stage: SV3
-      lc_states: []
+      si_stage: None
       tests: ["chip_sw_all_escalation_resets"]
     }
     {
@@ -255,8 +267,9 @@
             - This sets the test for closed source where the flash access timing matters.
             '''
       stage: V2
-      si_stage: None
+      si_stage: SV3
       tests: ["chip_sw_flash_ctrl_clock_freqs"]
+      bazel: ["//sw/device/tests:flash_ctrl_clock_freqs_test"]
     }
     {
       name: chip_sw_flash_ctrl_escalation_reset

sw/device/tests/BUILD

@@ -1433,15 +1433,11 @@ opentitan_test(
     srcs = ["flash_ctrl_idle_low_power_test.c"],
     exec_env = {
         "//hw/top_earlgrey:fpga_cw310_test_rom": None,
-        "//hw/top_earlgrey:silicon_creator": None,
-        "//hw/top_earlgrey:silicon_owner_sival_rom_ext": "silicon_owner",
-        "//hw/top_earlgrey:silicon_owner_prodc_rom_ext": "silicon_owner",
+        "//hw/top_earlgrey:silicon_owner_sival_rom_ext": None,
+        "//hw/top_earlgrey:silicon_owner_prodc_rom_ext": None,
         "//hw/top_earlgrey:sim_dv": None,
         "//hw/top_earlgrey:sim_verilator": None,
     },
-    silicon_owner = silicon_params(
-        tags = ["broken"],
-    ),
     deps = [
         "//hw/top_earlgrey/sw/autogen:top_earlgrey",
         "//sw/device/lib/base:mmio",
@@ -1469,11 +1465,11 @@ opentitan_test(
         EARLGREY_TEST_ENVS,
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
         {
-            "//hw/top_earlgrey:silicon_creator": None,
+            "//hw/top_earlgrey:silicon_owner_sival_rom_ext": None,
         },
     ),
-    silicon = silicon_params(tags = ["broken"]),
     deps = [
+        "//hw/ip/otp_ctrl/data:otp_ctrl_regs",
         "//hw/top_earlgrey/sw/autogen:top_earlgrey",
         "//sw/device/lib/base:abs_mmio",
         "//sw/device/lib/base:mmio",
@@ -1607,18 +1603,17 @@ test_suite(
 opentitan_test(
     name = "flash_ctrl_clock_freqs_test",
     srcs = ["flash_ctrl_clock_freqs_test.c"],
-    # TODO(#12486): [bazel] targets in sw/device/tests failing on cw310 and verilator when built by bazel
-    cw310 = new_cw310_params(tags = ["broken"]),
     exec_env = dicts.add(
         EARLGREY_TEST_ENVS,
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
         {
-            "//hw/top_earlgrey:silicon_creator": None,
+            "//hw/top_earlgrey:silicon_owner_sival_rom_ext": None,
         },
     ),
-    silicon = silicon_params(tags = ["broken"]),
     verilator = new_verilator_params(timeout = "long"),
     deps = [
+        "//hw/ip/otp_ctrl/data:otp_ctrl_regs",
+        "//sw/device/lib/base:abs_mmio",
         "//sw/device/lib/base:mmio",
         "//sw/device/lib/dif:clkmgr",
         "//sw/device/lib/dif:flash_ctrl",
@@ -1660,11 +1655,9 @@ opentitan_test(
     exec_env = dicts.add(
         EARLGREY_TEST_ENVS,
         {
-            "//hw/top_earlgrey:silicon_creator": None,
             "//hw/top_earlgrey:silicon_owner_sival_rom_ext": None,
         },
     ),
-    silicon = silicon_params(tags = ["broken"]),
     verilator = new_verilator_params(timeout = "long"),
     deps = [
         "//hw/top_earlgrey/ip/flash_ctrl/data/autogen:flash_ctrl_regs",

sw/device/tests/flash_ctrl_clock_freqs_test.c

@@ -2,6 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
+#include "sw/device/lib/base/abs_mmio.h"
 #include "sw/device/lib/base/mmio.h"
 #include "sw/device/lib/dif/dif_clkmgr.h"
 #include "sw/device/lib/dif/dif_flash_ctrl.h"
@@ -12,6 +13,20 @@
 #include "sw/device/lib/testing/test_framework/ottf_main.h"
 
 #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
+#include "otp_ctrl_regs.h"
+
+/**
+ * Bitfields for `CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG` and
+ * `CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG` OTP items.
+ *
+ * Defined here to be able to use in tests.
+ */
+#define FLASH_CTRL_OTP_FIELD_SCRAMBLING \
+  (bitfield_field32_t) { .mask = UINT8_MAX, .index = CHAR_BIT * 0 }
+#define FLASH_CTRL_OTP_FIELD_ECC \
+  (bitfield_field32_t) { .mask = UINT8_MAX, .index = CHAR_BIT * 1 }
+#define FLASH_CTRL_OTP_FIELD_HE \
+  (bitfield_field32_t) { .mask = UINT8_MAX, .index = CHAR_BIT * 2 }
 
 OTTF_DEFINE_TEST_CONFIG();
 
@@ -89,9 +104,24 @@ static void do_data_partition_test(uint32_t bank_number) {
     // Bank 0 contains the program data so can only be read and checked
     // against the host interface read.
     uint32_t address = 0;
-    CHECK_STATUS_OK(flash_ctrl_testutils_data_region_setup(
+    uint32_t otp_val = abs_mmio_read32(
+        TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR +
+        OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET +
+        OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG_OFFSET);
+
+    dif_flash_ctrl_region_properties_t region_properties = {
+        .ecc_en = bitfield_field32_read(otp_val, FLASH_CTRL_OTP_FIELD_ECC),
+        .high_endurance_en =
+            bitfield_field32_read(otp_val, FLASH_CTRL_OTP_FIELD_HE),
+        .scramble_en =
+            bitfield_field32_read(otp_val, FLASH_CTRL_OTP_FIELD_SCRAMBLING),
+        .erase_en = kMultiBitBool4True,
+        .prog_en = kMultiBitBool4True,
+        .rd_en = kMultiBitBool4True};
+
+    CHECK_STATUS_OK(flash_ctrl_testutils_data_region_setup_properties(
         &flash_state, kRegionBaseBank0Page0Index, kFlashBank0DataRegion,
-        kRegionSize, &address));
+        kRegionSize, region_properties, &address));
 
     uint32_t readback_data[kDataSize];
     CHECK_STATUS_OK(flash_ctrl_testutils_read(
@@ -140,10 +170,12 @@ bool test_main(void) {
       mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR)));
 
   for (int i = 0; i < kNumLoops; ++i) {
-    do_info_partition_test(kFlashInfoPageIdCreatorSecret);
-    do_info_partition_test(kFlashInfoPageIdOwnerSecret);
-    do_info_partition_test(kFlashInfoPageIdIsoPart);
-    do_data_partition_test(kFlashDataBank0);
+    if (kDeviceType != kDeviceSilicon) {
+      do_info_partition_test(kFlashInfoPageIdCreatorSecret);
+      do_info_partition_test(kFlashInfoPageIdOwnerSecret);
+      do_info_partition_test(kFlashInfoPageIdIsoPart);
+      do_data_partition_test(kFlashDataBank0);
+    }
     do_data_partition_test(kFlashDataBank1);
   }
 

sw/device/tests/flash_ctrl_idle_low_power_test.c

@@ -25,6 +25,7 @@ OTTF_DEFINE_TEST_CONFIG();
 
 static dif_rv_plic_t plic;
 static dif_aon_timer_t aon;
+static dif_rv_core_ibex_t rv_core_ibex;
 
 static plic_isr_ctx_t plic_ctx = {
     .rv_plic = &plic,
@@ -59,6 +60,27 @@ void ottf_external_isr(uint32_t *exc_info) {
                               &irq_serviced);
 }
 
+/**
+ * OTTF external NMI internal IRQ handler.
+ * The ROM configures the watchdog to generates a NMI at bark, so we clean the
+ * NMI and wait the external irq handler next.
+ */
+void ottf_external_nmi_handler(void) {
+  bool is_pending;
+  // The watchdog bark external interrupt is also connected to the NMI input
+  // of rv_core_ibex. We therefore expect the interrupt to be pending on the
+  // peripheral side (the check is done later in the test function).
+  CHECK_DIF_OK(dif_aon_timer_irq_is_pending(&aon, kDifAonTimerIrqWdogTimerBark,
+                                            &is_pending));
+  // In order to handle the NMI we need to acknowledge the interrupt status
+  // bit it at the peripheral side.
+  CHECK_DIF_OK(
+      dif_aon_timer_irq_acknowledge(&aon, kDifAonTimerIrqWdogTimerBark));
+
+  CHECK_DIF_OK(dif_rv_core_ibex_clear_nmi_state(&rv_core_ibex,
+                                                kDifRvCoreIbexNmiSourceAll));
+}
+
 static void enable_irqs(void) {
   // Enable the AON bark interrupt.
   CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
@@ -89,7 +111,9 @@ bool test_main(void) {
       mmio_region_from_addr(TOP_EARLGREY_RSTMGR_AON_BASE_ADDR), &rstmgr));
   CHECK_DIF_OK(dif_aon_timer_init(
       mmio_region_from_addr(TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR), &aon));
-
+  CHECK_DIF_OK(dif_rv_core_ibex_init(
+      mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR),
+      &rv_core_ibex));
   enable_irqs();
 
   CHECK_DIF_OK(dif_aon_timer_watchdog_stop(&aon));
@@ -130,9 +154,18 @@ bool test_main(void) {
         &pwrmgr, kDifPwrmgrWakeupRequestSourceTwo, 0));
 
     CHECK_DIF_OK(dif_aon_timer_watchdog_stop(&aon));
+
+    uint32_t bark_th = kAONBarkTh;
+    uint32_t bite_th = kAONBiteTh;
+
+    // Update bark and bite threshold in case of silicon test
+    if (kDeviceType == kDeviceSilicon) {
+      bark_th = 4000;
+      bite_th = 4 * bark_th;
+    }
     CHECK_DIF_OK(dif_aon_timer_watchdog_start(
-        &aon /* aon */, kAONBarkTh /* bark_threshold */,
-        kAONBiteTh /* bite_threshold */, false /* pause_in_sleep */,
+        &aon /* aon */, bark_th /* bark_threshold */,
+        bite_th /* bite_threshold */, false /* pause_in_sleep */,
         false /* lock */));
 
     dif_flash_ctrl_transaction_t transaction = {
@@ -143,6 +176,8 @@ bool test_main(void) {
         .word_count = 0x0};
 
     CHECK_DIF_OK(dif_flash_ctrl_start(&flash, transaction));
+    // Do not put any print here.
+    // That will cause interrupt miss and spurious test failure
     wait_for_interrupt();
 
     // Return from interrupt. Stop the watchdog. Check the reset info

sw/device/tests/flash_ctrl_mem_protection_test.c

@@ -196,10 +196,13 @@ bool test_main(void) {
       &flash, mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR)));
 
   // Set up default access for data partitions.
-  CHECK_STATUS_OK(flash_ctrl_testutils_default_region_access(
-      &flash, /*rd_en=*/true, /*prog_en=*/true, /*erase_en=*/true,
-      /*scramble_en=*/false, /*ecc_en=*/false, /*high_endurance_en=*/false));
-
+  // In silicon, rom_ext will set default region access.
+  // After that, it cannot be updated.
+  if (kDeviceType != kDeviceSilicon) {
+    CHECK_STATUS_OK(flash_ctrl_testutils_default_region_access(
+        &flash, /*rd_en=*/true, /*prog_en=*/true, /*erase_en=*/true,
+        /*scramble_en=*/false, /*ecc_en=*/false, /*high_endurance_en=*/false));
+  }
   // Program starts from kRegion[2], kRegion[1], and kRegion[0] in order.
   for (int i = 2; i >= 0; i--) {
     CHECK_DIF_OK(dif_flash_ctrl_set_data_region_properties(

sw/device/tests/flash_ctrl_ops_test.c

@@ -383,10 +383,12 @@ bool test_main(void) {
   irq_global_ctrl(true);
   irq_external_ctrl(true);
 
-  do_info_partition_test(kFlashInfoPageIdCreatorSecret, kRandomData1);
-  do_info_partition_test(kFlashInfoPageIdOwnerSecret, kRandomData2);
-  do_info_partition_test(kFlashInfoPageIdIsoPart, kRandomData3);
-  do_bank0_data_partition_test();
+  if (kDeviceType != kDeviceSilicon) {
+    do_info_partition_test(kFlashInfoPageIdCreatorSecret, kRandomData1);
+    do_info_partition_test(kFlashInfoPageIdOwnerSecret, kRandomData2);
+    do_info_partition_test(kFlashInfoPageIdIsoPart, kRandomData3);
+    do_bank0_data_partition_test();
+  }
   do_bank1_data_partition_test();
 
   return true;