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The connectivity test (triggered using util/dvsim/dvsim.py hw/top_earlgrey/formal/chip_conn_cfg.hjson) is currently broken on master, earlgrey_1.0.0 and earlgrey_1.0.0._presilicon. The root cause is the following commit 1194ca4 which enabled the pull-up setting for the power-on reset signal. The change itself is not controversial at all and was requested by the PD team but the FPV flow / connectivity test needs to be aligned accordingly.
I don't have sufficient expertise to take care of this on my own. I might be able with some help from an expert like @matutem and I am happy to collaborate.
If in the meantime someone wants to run the connectivity test, the mentioned commit above needs to be reverted to make things pass again.
The text was updated successfully, but these errors were encountered:
Description
The connectivity test (triggered using
util/dvsim/dvsim.py hw/top_earlgrey/formal/chip_conn_cfg.hjson
) is currently broken onmaster
,earlgrey_1.0.0
andearlgrey_1.0.0._presilicon
. The root cause is the following commit 1194ca4 which enabled the pull-up setting for the power-on reset signal. The change itself is not controversial at all and was requested by the PD team but the FPV flow / connectivity test needs to be aligned accordingly.I don't have sufficient expertise to take care of this on my own. I might be able with some help from an expert like @matutem and I am happy to collaborate.
If in the meantime someone wants to run the connectivity test, the mentioned commit above needs to be reverted to make things pass again.
The text was updated successfully, but these errors were encountered: