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[chip-test] chip_sw_spi_device_tpm #20636

Closed
1 of 10 tasks
engdoreis opened this issue Dec 12, 2023 · 1 comment
Closed
1 of 10 tasks

[chip-test] chip_sw_spi_device_tpm #20636

engdoreis opened this issue Dec 12, 2023 · 1 comment
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@engdoreis
Labels
Component:ChipLevelTest Used to filter the chip-level test backlog
Milestone
Earlgrey ES SV3

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@engdoreis
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Test point name

chip_sw_spi_device_tpm

Host side component

Rust

OpenTitanTool infrastructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation Targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

No response

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • HJSON test plan updated with test name (so it shows up in the dashboard)
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression
@engdoreis engdoreis added the Component:ChipLevelTest Used to filter the chip-level test backlog label Dec 12, 2023
@engdoreis engdoreis added this to the Earlgrey ES SV3 milestone Dec 12, 2023
@engdoreis engdoreis self-assigned this Dec 12, 2023
@engdoreis
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Fixed by #20679

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@engdoreis engdoreis

Labels
Component:ChipLevelTest Used to filter the chip-level test backlog
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Milestone
Earlgrey ES SV3
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@engdoreis