diff --git a/hw/ip/rv_dm/rtl/rv_dm.sv b/hw/ip/rv_dm/rtl/rv_dm.sv index be55e166d9a67..ba46ded1c26be 100644 --- a/hw/ip/rv_dm/rtl/rv_dm.sv +++ b/hw/ip/rv_dm/rtl/rv_dm.sv @@ -290,8 +290,6 @@ module rv_dm end assign debug_req_o = debug_req & debug_req_en; - // Bound-in DPI module replaces the TAP and TL-UL DMI -`ifndef DMIDirectTAP tlul_pkg::tl_h2d_t dbg_tl_h2d_win; tlul_pkg::tl_d2h_t dbg_tl_d2h_win; rv_dm_dbg_reg_top u_rv_dm_dbg_reg_top ( @@ -332,11 +330,6 @@ module rv_dm // Since the JTAG DTM used in this system can always drain this FIFO, // no additional reset request should be needed in order to clear it. assign dmi_rst_n = rst_ni; -`else - assign dbg_intg_error = 1'b0; - assign dmi_intg_error = 1'b0; - assign dbg_tl_d_o = tlul_pkg::TL_D2H_DEFAULT; -`endif // SEC_CM: DM_EN.CTRL.LC_GATED // SEC_CM: MEM_TL_LC_GATE.FSM.SPARSE diff --git a/hw/top_darjeeling/dv/verilator/chip_sim_tb.sv b/hw/top_darjeeling/dv/verilator/chip_sim_tb.sv index a28944c498714..2458211a44bb3 100644 --- a/hw/top_darjeeling/dv/verilator/chip_sim_tb.sv +++ b/hw/top_darjeeling/dv/verilator/chip_sim_tb.sv @@ -16,6 +16,12 @@ module chip_sim_tb ( logic cio_spi_device_sdi_p2d; logic cio_spi_device_sdo_d2p, cio_spi_device_sdo_en_d2p; + logic cio_jtag_tck; + logic cio_jtag_tms; + logic cio_jtag_trst_n; + logic cio_jtag_tdi; + logic cio_jtag_tdo; + chip_darjeeling_verilator u_dut ( .clk_i, .rst_ni, @@ -36,7 +42,14 @@ module chip_sim_tb ( .cio_spi_device_csb_p2d_i(cio_spi_device_csb_p2d), .cio_spi_device_sdi_p2d_i(cio_spi_device_sdi_p2d), .cio_spi_device_sdo_d2p_o(cio_spi_device_sdo_d2p), - .cio_spi_device_sdo_en_d2p_o(cio_spi_device_sdo_en_d2p) + .cio_spi_device_sdo_en_d2p_o(cio_spi_device_sdo_en_d2p), + + // communication with JTAG + .cio_jtag_tck_i(cio_jtag_tck), + .cio_jtag_tms_i(cio_jtag_tms), + .cio_jtag_trst_ni(cio_jtag_trst_n), + .cio_jtag_tdi_i(cio_jtag_tdi), + .cio_jtag_tdo_o(cio_jtag_tdo) ); // GPIO DPI @@ -64,40 +77,18 @@ module chip_sim_tb ( .rx_i (cio_uart_tx_d2p) ); -`ifdef DMIDirectTAP - // OpenOCD direct DMI TAP - bind rv_dm dmidpi u_dmidpi ( + // OpenOCD JTAG DPI (to rv_dm and lc_ctrl) + jtagdpi u_jtagdpi ( .clk_i, .rst_ni, - .dmi_req_valid, - .dmi_req_ready, - .dmi_req_addr (dmi_req.addr), - .dmi_req_op (dmi_req.op), - .dmi_req_data (dmi_req.data), - .dmi_rsp_valid, - .dmi_rsp_ready, - .dmi_rsp_data (dmi_rsp.data), - .dmi_rsp_resp (dmi_rsp.resp), - .dmi_rst_n (dmi_rst_n) + + .jtag_tck (cio_jtag_tck), + .jtag_tms (cio_jtag_tms), + .jtag_tdi (cio_jtag_tdi), + .jtag_tdo (cio_jtag_tdo), + .jtag_trst_n (cio_jtag_trst_n), + .jtag_srst_n () ); -`else - // TODO: this is currently not supported. - // connect this to the correct pins once pinout is final and once the - // verilator testbench supports DFT/Debug strap sampling. - // See also #5221. - // - // jtagdpi u_jtagdpi ( - // .clk_i, - // .rst_ni, - - // .jtag_tck (cio_jtag_tck), - // .jtag_tms (cio_jtag_tms), - // .jtag_tdi (cio_jtag_tdi), - // .jtag_tdo (cio_jtag_tdo), - // .jtag_trst_n (cio_jtag_trst_n), - // .jtag_srst_n (cio_jtag_srst_n) - // ); -`endif // SPI DPI spidpi u_spi ( diff --git a/hw/top_darjeeling/rtl/chip_darjeeling_verilator.sv b/hw/top_darjeeling/rtl/chip_darjeeling_verilator.sv index 2779497f29f35..eab62ca23345d 100644 --- a/hw/top_darjeeling/rtl/chip_darjeeling_verilator.sv +++ b/hw/top_darjeeling/rtl/chip_darjeeling_verilator.sv @@ -25,12 +25,47 @@ module chip_darjeeling_verilator ( input cio_spi_device_sdi_p2d_i, output logic cio_spi_device_sdo_d2p_o, output logic cio_spi_device_sdo_en_d2p_o, + + // communication with JTAG + input logic cio_jtag_tck_i, + input logic cio_jtag_tms_i, + input logic cio_jtag_tdi_i, + input logic cio_jtag_trst_ni, + output logic cio_jtag_tdo_o ); import top_darjeeling_pkg::*; - logic IO_JTCK, IO_JTMS, IO_JTRST_N, IO_JTDI, IO_JTDO; + // JTAG + jtag_pkg::jtag_req_t jtag_req; + jtag_pkg::jtag_rsp_t jtag_rsp; + tlul_pkg::tl_h2d_t dbg_tl_h2d; + tlul_pkg::tl_d2h_t dbg_tl_d2h; + assign jtag_req.tck = cio_jtag_tck_i; + assign jtag_req.tms = cio_jtag_tms_i; + assign jtag_req.trst_n = cio_jtag_trst_ni; + assign jtag_req.tdi = cio_jtag_tdi_i; + assign cio_jtag_tdo_o = jtag_rsp.tdo; + + tlul_jtag_dtm #( + .IdcodeValue(jtag_id_pkg::LC_DM_COMBINED_JTAG_IDCODE), + // Notes: + // - one RV_DM instance uses 9bits + // - our crossbar tooling expects individual IPs to be spaced apart by 12bits at the moment + // - the DMI address shifted through jtag is a word address and hence 2bits smaller than this + // - setting this to 18bits effectively gives us 2^6 = 64 addressable 12bit ranges + .NumDmiByteAbits(18) + ) u_tlul_jtag_dtm ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]), + .jtag_i (jtag_req), + .jtag_o (jtag_rsp), + .scan_rst_ni(scan_rst_n), + .scanmode_i (scanmode), + .tl_h2d_o (dbg_tl_h2d), + .tl_d2h_i (dbg_tl_d2h) + ); // TODO: instantiate padring and route these signals through that module logic [pinmux_reg_pkg::NDioPads-1:0] dio_in; @@ -610,10 +645,9 @@ module chip_darjeeling_verilator ( .calib_rdy_i ( ast_init_done ), .ast_init_done_i ( ast_init_done ), - // DMI into rv_dm - // TODO: instantiate TAP at this level and connect these ports - .dbg_tl_req_i ( tlul_pkg::TL_H2D_DEFAULT ), - .dbg_tl_rsp_o ( ), + // DMI into rv_dm and lc_ctrl + .dbg_tl_req_i ( dbg_tl_h2d ), + .dbg_tl_rsp_o ( dbg_tl_d2h ), // ingress / egress ports and soc proxy signals .ctn_tl_h2d_o ( ctn_egress_tl_h2d ), diff --git a/util/openocd/interface/sim-jtagdpi.cfg b/util/openocd/interface/sim-jtagdpi.cfg index d22929248bd08..946cd6dc88753 100644 --- a/util/openocd/interface/sim-jtagdpi.cfg +++ b/util/openocd/interface/sim-jtagdpi.cfg @@ -7,5 +7,5 @@ # SystemVerilog DPI module. adapter driver remote_bitbang -remote_bitbang_port 44853 -remote_bitbang_host localhost +remote_bitbang port 44853 +remote_bitbang host localhost diff --git a/util/openocd/target/lowrisc-darjeeling.cfg b/util/openocd/target/lowrisc-darjeeling.cfg index a294b1b3d42f8..337f49be2d1f2 100644 --- a/util/openocd/target/lowrisc-darjeeling.cfg +++ b/util/openocd/target/lowrisc-darjeeling.cfg @@ -14,7 +14,7 @@ if { [info exists CPUTAPID ] } { set _CPUTAPID $CPUTAPID } else { # Defined in `hw/top_darjeeling/rtl/jtag_id_pkg.sv`. - set _CPUTAPID 0x10001cdf + set _CPUTAPID 0x10003cdf } jtag newtap $_CHIPNAME tap -irlen 5 -expected-id $_CPUTAPID