diff --git a/hw/ip/gpio/rtl/gpio.sv b/hw/ip/gpio/rtl/gpio.sv
index 3809c652cd96a..8af320247d01f 100644
--- a/hw/ip/gpio/rtl/gpio.sv
+++ b/hw/ip/gpio/rtl/gpio.sv
@@ -69,14 +69,13 @@ module gpio
   if (GpioAsHwStrapsEn) begin : gen_strap_sample
     // sample at gpio inputs at strap_en_i signal pulse.
     logic strap_en;
-    prim_flop_2sync #(
-      .Width(1)
-    ) u_prim_flop_2sync (
-      .clk_i,
-      .rst_ni,
-      .d_i(strap_en_i),
-      .q_o(strap_en)
-    );
+
+    // The strap_en_i is a single cycle pulse generated by the pwrmgr
+    // Both sender (pwrmgr) and receiver (gpio controller) are in the same clock domain (io_div4)
+    // A cdc synchronizer is not required
+    //
+    assign strap_en = strap_en_i;
+
     // we guarantee here by design that this will always be done exactly once per reset cycle.
     logic sample_trigger;
     assign sample_trigger                    = strap_en && !reg2hw.hw_straps_data_in_valid.q;