diff --git a/hw/ip/clkmgr/dv/env/clkmgr_env.core b/hw/ip/clkmgr/dv/env/clkmgr_env.core index 446d07e8ac1c38..f4b76088b71fca 100644 --- a/hw/ip/clkmgr/dv/env/clkmgr_env.core +++ b/hw/ip/clkmgr/dv/env/clkmgr_env.core @@ -9,7 +9,7 @@ filesets: depend: - lowrisc:dv:ralgen - lowrisc:dv:cip_lib - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:systems:clkmgr_pkg files: - clkmgr_csrs_if.sv diff --git a/hw/ip/flash_ctrl/flash_ctrl_pkg.core b/hw/ip/flash_ctrl/flash_ctrl_pkg.core index 05ec6743f249fd..461ba7f7112473 100644 --- a/hw/ip/flash_ctrl/flash_ctrl_pkg.core +++ b/hw/ip/flash_ctrl/flash_ctrl_pkg.core @@ -11,7 +11,7 @@ filesets: - lowrisc:constants:top_pkg - lowrisc:prim:util - lowrisc:ip:lc_ctrl_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:jtag_pkg - lowrisc:ip:edn_pkg - "fileset_partner ? (partner:systems:ast_pkg)" diff --git a/hw/ip/lc_ctrl/lc_ctrl.core b/hw/ip/lc_ctrl/lc_ctrl.core index 4dd46ccd9b4879..c1efa3b8984df2 100644 --- a/hw/ip/lc_ctrl/lc_ctrl.core +++ b/hw/ip/lc_ctrl/lc_ctrl.core @@ -17,7 +17,7 @@ filesets: - lowrisc:prim:sparse_fsm - lowrisc:ip:lc_ctrl_pkg - lowrisc:ip:tlul - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:otp_ctrl_pkg - lowrisc:ip:kmac_pkg - lowrisc:ip:rv_dm diff --git a/hw/ip/otp_ctrl/otp_ctrl.core b/hw/ip/otp_ctrl/otp_ctrl.core index 9f18a1a1a4414b..10971dd549c4c8 100644 --- a/hw/ip/otp_ctrl/otp_ctrl.core +++ b/hw/ip/otp_ctrl/otp_ctrl.core @@ -22,7 +22,7 @@ filesets: - lowrisc:prim:secded - lowrisc:ip:edn_requester - lowrisc:prim:sec_anchor - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:edn_pkg - lowrisc:prim:sparse_fsm - "fileset_partner ? (partner:systems:ast_pkg)" diff --git a/hw/ip/rstmgr/dv/sva/rstmgr_sva_ifs.core b/hw/ip/rstmgr/dv/sva/rstmgr_sva_ifs.core index bdedf685562ffe..eff742449cc7cd 100644 --- a/hw/ip/rstmgr/dv/sva/rstmgr_sva_ifs.core +++ b/hw/ip/rstmgr/dv/sva/rstmgr_sva_ifs.core @@ -8,7 +8,7 @@ filesets: files_dv: depend: - lowrisc:ip:lc_ctrl_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:rstmgr files: diff --git a/hw/ip/rstmgr/rstmgr_pkg.core b/hw/ip/rstmgr/rstmgr_pkg.core index 97511dfb561aea..6aa6f66e784e2d 100644 --- a/hw/ip/rstmgr/rstmgr_pkg.core +++ b/hw/ip/rstmgr/rstmgr_pkg.core @@ -9,7 +9,7 @@ filesets: files_rtl: depend: - lowrisc:ip:alert_handler_component - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:rstmgr_reg - lowrisc:ip_interfaces:alert_handler_reg - "fileset_top ? (lowrisc:systems:rstmgr_pkg)" diff --git a/hw/ip/rv_core_ibex/rv_core_ibex.core b/hw/ip/rv_core_ibex/rv_core_ibex.core index bd14e14a936b80..4b0c539c83a003 100644 --- a/hw/ip/rv_core_ibex/rv_core_ibex.core +++ b/hw/ip/rv_core_ibex/rv_core_ibex.core @@ -11,7 +11,7 @@ filesets: - lowrisc:ip:edn_requester - lowrisc:ip:lc_ctrl_pkg - lowrisc:ip:otp_ctrl_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:rv_core_ibex_pkg - lowrisc:ip:tlul - lowrisc:ip_interfaces:alert_handler_reg diff --git a/hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core b/hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core index d71a35180c2772..b19f07c3623908 100644 --- a/hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core +++ b/hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core @@ -9,7 +9,7 @@ filesets: depend: - lowrisc:dv:ralgen - lowrisc:dv:cip_lib - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg files: - pwrmgr_env_pkg.sv - pwrmgr_env_cfg.sv: {is_include_file: true} diff --git a/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core b/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core index 9eaa8fd0db4d5a..d35cbce65b7b7a 100644 --- a/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core +++ b/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core @@ -7,7 +7,7 @@ description: "PWRMGR DV sim target" filesets: files_rtl: depend: - - lowrisc:ip:pwrmgr + - lowrisc:ip_interfaces:pwrmgr files_dv: depend: - lowrisc:dv:pwrmgr_test diff --git a/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core b/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core index 79631950495e26..8adac26d23551f 100644 --- a/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core +++ b/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core @@ -7,7 +7,7 @@ description: "PWRMGR to RSTMGR assertion interface." filesets: files_dv: depend: - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:prim:assert files: - pwrmgr_rstmgr_sva_if.sv diff --git a/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_sva.core b/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_sva.core index b71c2dede28a47..4d606bf4e35228 100644 --- a/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_sva.core +++ b/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_sva.core @@ -9,7 +9,7 @@ filesets: depend: - lowrisc:tlul:headers - lowrisc:fpv:csr_assert_gen - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:dv:clkmgr_pwrmgr_sva_if - lowrisc:dv:pwrmgr_rstmgr_sva_if files: @@ -21,7 +21,7 @@ filesets: files_formal: depend: - - lowrisc:ip:pwrmgr + - lowrisc:ip_interfaces:pwrmgr generate: csr_assert_gen: diff --git a/hw/ip_templates/pwrmgr/pwrmgr.core.tpl b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl new file mode 100644 index 00000000000000..3b83fcde96d924 --- /dev/null +++ b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl @@ -0,0 +1,66 @@ +CAPI=2: +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: ${instance_vlnv("lowrisc:ip:pwrmgr:0.1")} +description: "Power manager RTL" +virtual: + - lowrisc:ip_interfaces:pwrmgr + +filesets: + files_rtl: + depend: + - ${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1")} + - ${instance_vlnv("lowrisc:ip:pwrmgr_reg:0.1")} + - lowrisc:ip:pwrmgr_component + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: pwrmgr + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/ip_templates/pwrmgr/pwrmgr.core b/hw/ip_templates/pwrmgr/pwrmgr_components.core similarity index 95% rename from hw/ip_templates/pwrmgr/pwrmgr.core rename to hw/ip_templates/pwrmgr/pwrmgr_components.core index c384dae955aaba..2069107cadb6b0 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr.core +++ b/hw/ip_templates/pwrmgr/pwrmgr_components.core @@ -2,7 +2,7 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr:0.1" +name: "lowrisc:ip:pwrmgr_component:0.1" description: "Power manager RTL" filesets: @@ -20,8 +20,7 @@ filesets: - lowrisc:prim:clock_buf - lowrisc:prim:measure - lowrisc:ip_interfaces:alert_handler_reg - - lowrisc:ip:pwrmgr_pkg - - lowrisc:ip:pwrmgr_reg + - lowrisc:ip_interfaces:pwrmgr_pkg files: - rtl/pwrmgr_cdc.sv - rtl/pwrmgr_slow_fsm.sv diff --git a/hw/ip_templates/pwrmgr/pwrmgr_pkg.core b/hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl similarity index 79% rename from hw/ip_templates/pwrmgr/pwrmgr_pkg.core rename to hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl index 3e83cde44fd128..f2d8b0995aaf57 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr_pkg.core +++ b/hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl @@ -2,13 +2,15 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr_pkg:0.1" +name: ${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1")} description: "Power manager package" +virtual: + - lowrisc:ip_interfaces:pwrmgr_pkg filesets: files_rtl: depend: - - lowrisc:ip:pwrmgr_reg + - ${instance_vlnv("lowrisc:ip:pwrmgr_reg")} files: - rtl/pwrmgr_pkg.sv file_type: systemVerilogSource diff --git a/hw/ip_templates/pwrmgr/pwrmgr_reg.core b/hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl similarity index 82% rename from hw/ip_templates/pwrmgr/pwrmgr_reg.core rename to hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl index c20cd917273d83..b2b8124fd5d04f 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr_reg.core +++ b/hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl @@ -2,8 +2,10 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr_reg:0.1" +name: ${instance_vlnv("lowrisc:ip:pwrmgr_reg:0.1")} description: "Power manager registers" +virtual: + - lowrisc:ip_interfaces:pwrmgr_reg filesets: files_rtl: diff --git a/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_pkg.sv b/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_pkg.sv deleted file mode 100644 index f55eaaf7a32b44..00000000000000 --- a/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_pkg.sv +++ /dev/null @@ -1,215 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Package auto-generated by `reggen` containing data structure - -package pwrmgr_reg_pkg; - - // Param list - parameter int NumWkups = 1; - parameter int NumRstReqs = 1; - - // Address widths within the block - parameter int BlockAw = 6; - - //////////////////////////// - // Typedefs for registers // - //////////////////////////// - - typedef struct packed { - logic q; - } pwrmgr_reg2hw_intr_state_reg_t; - - typedef struct packed { - logic q; - } pwrmgr_reg2hw_intr_enable_reg_t; - - typedef struct packed { - logic q; - logic qe; - } pwrmgr_reg2hw_intr_test_reg_t; - - typedef struct packed { - struct packed { - logic q; - } low_power_hint; - struct packed { - logic q; - } core_clk_en; - struct packed { - logic q; - } io_clk_en; - struct packed { - logic q; - } usb_clk_en_lp; - struct packed { - logic q; - } usb_clk_en_active; - struct packed { - logic q; - } main_pd_n; - } pwrmgr_reg2hw_control_reg_t; - - typedef struct packed { - logic q; - logic qe; - } pwrmgr_reg2hw_cfg_cdc_sync_reg_t; - - typedef struct packed { - logic q; - } pwrmgr_reg2hw_wakeup_en_mreg_t; - - typedef struct packed { - logic q; - } pwrmgr_reg2hw_reset_en_mreg_t; - - typedef struct packed { - logic q; - } pwrmgr_reg2hw_wake_info_capture_dis_reg_t; - - typedef struct packed { - struct packed { - logic q; - logic qe; - } reasons; - struct packed { - logic q; - logic qe; - } fall_through; - struct packed { - logic q; - logic qe; - } abort; - } pwrmgr_reg2hw_wake_info_reg_t; - - typedef struct packed { - logic d; - logic de; - } pwrmgr_hw2reg_intr_state_reg_t; - - typedef struct packed { - logic d; - } pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t; - - typedef struct packed { - struct packed { - logic d; - logic de; - } low_power_hint; - } pwrmgr_hw2reg_control_reg_t; - - typedef struct packed { - logic d; - logic de; - } pwrmgr_hw2reg_cfg_cdc_sync_reg_t; - - typedef struct packed { - logic d; - logic de; - } pwrmgr_hw2reg_wake_status_mreg_t; - - typedef struct packed { - logic d; - logic de; - } pwrmgr_hw2reg_reset_status_mreg_t; - - typedef struct packed { - struct packed { - logic d; - } reasons; - struct packed { - logic d; - } fall_through; - struct packed { - logic d; - } abort; - } pwrmgr_hw2reg_wake_info_reg_t; - - // Register -> HW type - typedef struct packed { - pwrmgr_reg2hw_intr_state_reg_t intr_state; // [20:20] - pwrmgr_reg2hw_intr_enable_reg_t intr_enable; // [19:19] - pwrmgr_reg2hw_intr_test_reg_t intr_test; // [18:17] - pwrmgr_reg2hw_control_reg_t control; // [16:11] - pwrmgr_reg2hw_cfg_cdc_sync_reg_t cfg_cdc_sync; // [10:9] - pwrmgr_reg2hw_wakeup_en_mreg_t [0:0] wakeup_en; // [8:8] - pwrmgr_reg2hw_reset_en_mreg_t [0:0] reset_en; // [7:7] - pwrmgr_reg2hw_wake_info_capture_dis_reg_t wake_info_capture_dis; // [6:6] - pwrmgr_reg2hw_wake_info_reg_t wake_info; // [5:0] - } pwrmgr_reg2hw_t; - - // HW -> register type - typedef struct packed { - pwrmgr_hw2reg_intr_state_reg_t intr_state; // [13:12] - pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t ctrl_cfg_regwen; // [11:11] - pwrmgr_hw2reg_control_reg_t control; // [10:9] - pwrmgr_hw2reg_cfg_cdc_sync_reg_t cfg_cdc_sync; // [8:7] - pwrmgr_hw2reg_wake_status_mreg_t [0:0] wake_status; // [6:5] - pwrmgr_hw2reg_reset_status_mreg_t [0:0] reset_status; // [4:3] - pwrmgr_hw2reg_wake_info_reg_t wake_info; // [2:0] - } pwrmgr_hw2reg_t; - - // Register offsets - parameter logic [BlockAw-1:0] PWRMGR_INTR_STATE_OFFSET = 6'h 0; - parameter logic [BlockAw-1:0] PWRMGR_INTR_ENABLE_OFFSET = 6'h 4; - parameter logic [BlockAw-1:0] PWRMGR_INTR_TEST_OFFSET = 6'h 8; - parameter logic [BlockAw-1:0] PWRMGR_CTRL_CFG_REGWEN_OFFSET = 6'h c; - parameter logic [BlockAw-1:0] PWRMGR_CONTROL_OFFSET = 6'h 10; - parameter logic [BlockAw-1:0] PWRMGR_CFG_CDC_SYNC_OFFSET = 6'h 14; - parameter logic [BlockAw-1:0] PWRMGR_WAKEUP_EN_REGWEN_OFFSET = 6'h 18; - parameter logic [BlockAw-1:0] PWRMGR_WAKEUP_EN_OFFSET = 6'h 1c; - parameter logic [BlockAw-1:0] PWRMGR_WAKE_STATUS_OFFSET = 6'h 20; - parameter logic [BlockAw-1:0] PWRMGR_RESET_EN_REGWEN_OFFSET = 6'h 24; - parameter logic [BlockAw-1:0] PWRMGR_RESET_EN_OFFSET = 6'h 28; - parameter logic [BlockAw-1:0] PWRMGR_RESET_STATUS_OFFSET = 6'h 2c; - parameter logic [BlockAw-1:0] PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET = 6'h 30; - parameter logic [BlockAw-1:0] PWRMGR_WAKE_INFO_OFFSET = 6'h 34; - - // Reset values for hwext registers and their fields - parameter logic [0:0] PWRMGR_INTR_TEST_RESVAL = 1'h 0; - parameter logic [0:0] PWRMGR_INTR_TEST_WAKEUP_RESVAL = 1'h 0; - parameter logic [0:0] PWRMGR_CTRL_CFG_REGWEN_RESVAL = 1'h 1; - parameter logic [0:0] PWRMGR_CTRL_CFG_REGWEN_EN_RESVAL = 1'h 1; - parameter logic [2:0] PWRMGR_WAKE_INFO_RESVAL = 3'h 0; - parameter logic [0:0] PWRMGR_WAKE_INFO_REASONS_RESVAL = 1'h 0; - parameter logic [0:0] PWRMGR_WAKE_INFO_FALL_THROUGH_RESVAL = 1'h 0; - parameter logic [0:0] PWRMGR_WAKE_INFO_ABORT_RESVAL = 1'h 0; - - // Register index - typedef enum int { - PWRMGR_INTR_STATE, - PWRMGR_INTR_ENABLE, - PWRMGR_INTR_TEST, - PWRMGR_CTRL_CFG_REGWEN, - PWRMGR_CONTROL, - PWRMGR_CFG_CDC_SYNC, - PWRMGR_WAKEUP_EN_REGWEN, - PWRMGR_WAKEUP_EN, - PWRMGR_WAKE_STATUS, - PWRMGR_RESET_EN_REGWEN, - PWRMGR_RESET_EN, - PWRMGR_RESET_STATUS, - PWRMGR_WAKE_INFO_CAPTURE_DIS, - PWRMGR_WAKE_INFO - } pwrmgr_id_e; - - // Register width information to check illegal writes - parameter logic [3:0] PWRMGR_PERMIT [14] = '{ - 4'b 0001, // index[ 0] PWRMGR_INTR_STATE - 4'b 0001, // index[ 1] PWRMGR_INTR_ENABLE - 4'b 0001, // index[ 2] PWRMGR_INTR_TEST - 4'b 0001, // index[ 3] PWRMGR_CTRL_CFG_REGWEN - 4'b 0011, // index[ 4] PWRMGR_CONTROL - 4'b 0001, // index[ 5] PWRMGR_CFG_CDC_SYNC - 4'b 0001, // index[ 6] PWRMGR_WAKEUP_EN_REGWEN - 4'b 0001, // index[ 7] PWRMGR_WAKEUP_EN - 4'b 0001, // index[ 8] PWRMGR_WAKE_STATUS - 4'b 0001, // index[ 9] PWRMGR_RESET_EN_REGWEN - 4'b 0001, // index[10] PWRMGR_RESET_EN - 4'b 0001, // index[11] PWRMGR_RESET_STATUS - 4'b 0001, // index[12] PWRMGR_WAKE_INFO_CAPTURE_DIS - 4'b 0001 // index[13] PWRMGR_WAKE_INFO - }; - -endpackage diff --git a/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_top.sv b/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_top.sv deleted file mode 100644 index 3c9198dc73624e..00000000000000 --- a/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_top.sv +++ /dev/null @@ -1,947 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Top module auto-generated by `reggen` - -`include "prim_assert.sv" - -module pwrmgr_reg_top ( - input clk_i, - input rst_ni, - input tlul_pkg::tl_h2d_t tl_i, - output tlul_pkg::tl_d2h_t tl_o, - // To HW - output pwrmgr_reg_pkg::pwrmgr_reg2hw_t reg2hw, // Write - input pwrmgr_reg_pkg::pwrmgr_hw2reg_t hw2reg, // Read - - // Integrity check errors - output logic intg_err_o -); - - import pwrmgr_reg_pkg::* ; - - localparam int AW = 6; - localparam int DW = 32; - localparam int DBW = DW/8; // Byte Width - - // register signals - logic reg_we; - logic reg_re; - logic [AW-1:0] reg_addr; - logic [DW-1:0] reg_wdata; - logic [DBW-1:0] reg_be; - logic [DW-1:0] reg_rdata; - logic reg_error; - - logic addrmiss, wr_err; - - logic [DW-1:0] reg_rdata_next; - logic reg_busy; - - tlul_pkg::tl_h2d_t tl_reg_h2d; - tlul_pkg::tl_d2h_t tl_reg_d2h; - - - // incoming payload check - logic intg_err; - tlul_cmd_intg_chk u_chk ( - .tl_i(tl_i), - .err_o(intg_err) - ); - - // also check for spurious write enables - logic reg_we_err; - logic [13:0] reg_we_check; - prim_reg_we_check #( - .OneHotWidth(14) - ) u_prim_reg_we_check ( - .clk_i(clk_i), - .rst_ni(rst_ni), - .oh_i (reg_we_check), - .en_i (reg_we && !addrmiss), - .err_o (reg_we_err) - ); - - logic err_q; - always_ff @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - err_q <= '0; - end else if (intg_err || reg_we_err) begin - err_q <= 1'b1; - end - end - - // integrity error output is permanent and should be used for alert generation - // register errors are transactional - assign intg_err_o = err_q | intg_err | reg_we_err; - - // outgoing integrity generation - tlul_pkg::tl_d2h_t tl_o_pre; - tlul_rsp_intg_gen #( - .EnableRspIntgGen(1), - .EnableDataIntgGen(1) - ) u_rsp_intg_gen ( - .tl_i(tl_o_pre), - .tl_o(tl_o) - ); - - assign tl_reg_h2d = tl_i; - assign tl_o_pre = tl_reg_d2h; - - tlul_adapter_reg #( - .RegAw(AW), - .RegDw(DW), - .EnableDataIntgGen(0) - ) u_reg_if ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - .tl_i (tl_reg_h2d), - .tl_o (tl_reg_d2h), - - .en_ifetch_i(prim_mubi_pkg::MuBi4False), - .intg_error_o(), - - .we_o (reg_we), - .re_o (reg_re), - .addr_o (reg_addr), - .wdata_o (reg_wdata), - .be_o (reg_be), - .busy_i (reg_busy), - .rdata_i (reg_rdata), - .error_i (reg_error) - ); - - // cdc oversampling signals - - assign reg_rdata = reg_rdata_next ; - assign reg_error = addrmiss | wr_err | intg_err; - - // Define SW related signals - // Format: __{wd|we|qs} - // or _{wd|we|qs} if field == 1 or 0 - logic intr_state_we; - logic intr_state_qs; - logic intr_state_wd; - logic intr_enable_we; - logic intr_enable_qs; - logic intr_enable_wd; - logic intr_test_we; - logic intr_test_wd; - logic ctrl_cfg_regwen_re; - logic ctrl_cfg_regwen_qs; - logic control_we; - logic control_low_power_hint_qs; - logic control_low_power_hint_wd; - logic control_core_clk_en_qs; - logic control_core_clk_en_wd; - logic control_io_clk_en_qs; - logic control_io_clk_en_wd; - logic control_usb_clk_en_lp_qs; - logic control_usb_clk_en_lp_wd; - logic control_usb_clk_en_active_qs; - logic control_usb_clk_en_active_wd; - logic control_main_pd_n_qs; - logic control_main_pd_n_wd; - logic cfg_cdc_sync_we; - logic cfg_cdc_sync_qs; - logic cfg_cdc_sync_wd; - logic wakeup_en_regwen_we; - logic wakeup_en_regwen_qs; - logic wakeup_en_regwen_wd; - logic wakeup_en_we; - logic wakeup_en_qs; - logic wakeup_en_wd; - logic wake_status_qs; - logic reset_en_regwen_we; - logic reset_en_regwen_qs; - logic reset_en_regwen_wd; - logic reset_en_we; - logic reset_en_qs; - logic reset_en_wd; - logic reset_status_qs; - logic wake_info_capture_dis_we; - logic wake_info_capture_dis_qs; - logic wake_info_capture_dis_wd; - logic wake_info_re; - logic wake_info_we; - logic wake_info_reasons_qs; - logic wake_info_reasons_wd; - logic wake_info_fall_through_qs; - logic wake_info_fall_through_wd; - logic wake_info_abort_qs; - logic wake_info_abort_wd; - - // Register instances - // R[intr_state]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW1C), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_intr_state ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (intr_state_we), - .wd (intr_state_wd), - - // from internal hardware - .de (hw2reg.intr_state.de), - .d (hw2reg.intr_state.d), - - // to internal hardware - .qe (), - .q (reg2hw.intr_state.q), - .ds (), - - // to register interface (read) - .qs (intr_state_qs) - ); - - - // R[intr_enable]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_intr_enable ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (intr_enable_we), - .wd (intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.intr_enable.q), - .ds (), - - // to register interface (read) - .qs (intr_enable_qs) - ); - - - // R[intr_test]: V(True) - logic intr_test_qe; - logic [0:0] intr_test_flds_we; - assign intr_test_qe = &intr_test_flds_we; - prim_subreg_ext #( - .DW (1) - ) u_intr_test ( - .re (1'b0), - .we (intr_test_we), - .wd (intr_test_wd), - .d ('0), - .qre (), - .qe (intr_test_flds_we[0]), - .q (reg2hw.intr_test.q), - .ds (), - .qs () - ); - assign reg2hw.intr_test.qe = intr_test_qe; - - - // R[ctrl_cfg_regwen]: V(True) - prim_subreg_ext #( - .DW (1) - ) u_ctrl_cfg_regwen ( - .re (ctrl_cfg_regwen_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.ctrl_cfg_regwen.d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (ctrl_cfg_regwen_qs) - ); - - - // R[control]: V(False) - // Create REGWEN-gated WE signal - logic control_gated_we; - assign control_gated_we = control_we & ctrl_cfg_regwen_qs; - // F[low_power_hint]: 0:0 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_control_low_power_hint ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_low_power_hint_wd), - - // from internal hardware - .de (hw2reg.control.low_power_hint.de), - .d (hw2reg.control.low_power_hint.d), - - // to internal hardware - .qe (), - .q (reg2hw.control.low_power_hint.q), - .ds (), - - // to register interface (read) - .qs (control_low_power_hint_qs) - ); - - // F[core_clk_en]: 4:4 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_control_core_clk_en ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_core_clk_en_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.control.core_clk_en.q), - .ds (), - - // to register interface (read) - .qs (control_core_clk_en_qs) - ); - - // F[io_clk_en]: 5:5 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_control_io_clk_en ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_io_clk_en_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.control.io_clk_en.q), - .ds (), - - // to register interface (read) - .qs (control_io_clk_en_qs) - ); - - // F[usb_clk_en_lp]: 6:6 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_control_usb_clk_en_lp ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_usb_clk_en_lp_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.control.usb_clk_en_lp.q), - .ds (), - - // to register interface (read) - .qs (control_usb_clk_en_lp_qs) - ); - - // F[usb_clk_en_active]: 7:7 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_control_usb_clk_en_active ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_usb_clk_en_active_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.control.usb_clk_en_active.q), - .ds (), - - // to register interface (read) - .qs (control_usb_clk_en_active_qs) - ); - - // F[main_pd_n]: 8:8 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_control_main_pd_n ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_main_pd_n_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.control.main_pd_n.q), - .ds (), - - // to register interface (read) - .qs (control_main_pd_n_qs) - ); - - - // R[cfg_cdc_sync]: V(False) - logic cfg_cdc_sync_qe; - logic [0:0] cfg_cdc_sync_flds_we; - prim_flop #( - .Width(1), - .ResetValue(0) - ) u_cfg_cdc_sync0_qe ( - .clk_i(clk_i), - .rst_ni(rst_ni), - .d_i(&cfg_cdc_sync_flds_we), - .q_o(cfg_cdc_sync_qe) - ); - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_cfg_cdc_sync ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (cfg_cdc_sync_we), - .wd (cfg_cdc_sync_wd), - - // from internal hardware - .de (hw2reg.cfg_cdc_sync.de), - .d (hw2reg.cfg_cdc_sync.d), - - // to internal hardware - .qe (cfg_cdc_sync_flds_we[0]), - .q (reg2hw.cfg_cdc_sync.q), - .ds (), - - // to register interface (read) - .qs (cfg_cdc_sync_qs) - ); - assign reg2hw.cfg_cdc_sync.qe = cfg_cdc_sync_qe; - - - // R[wakeup_en_regwen]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_wakeup_en_regwen ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (wakeup_en_regwen_we), - .wd (wakeup_en_regwen_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (wakeup_en_regwen_qs) - ); - - - // Subregister 0 of Multireg wakeup_en - // R[wakeup_en]: V(False) - // Create REGWEN-gated WE signal - logic wakeup_en_gated_we; - assign wakeup_en_gated_we = wakeup_en_we & wakeup_en_regwen_qs; - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_wakeup_en ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (wakeup_en_gated_we), - .wd (wakeup_en_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.wakeup_en[0].q), - .ds (), - - // to register interface (read) - .qs (wakeup_en_qs) - ); - - - // Subregister 0 of Multireg wake_status - // R[wake_status]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_wake_status ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.wake_status[0].de), - .d (hw2reg.wake_status[0].d), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (wake_status_qs) - ); - - - // R[reset_en_regwen]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_reset_en_regwen ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (reset_en_regwen_we), - .wd (reset_en_regwen_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (reset_en_regwen_qs) - ); - - - // Subregister 0 of Multireg reset_en - // R[reset_en]: V(False) - // Create REGWEN-gated WE signal - logic reset_en_gated_we; - assign reset_en_gated_we = reset_en_we & reset_en_regwen_qs; - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_reset_en ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (reset_en_gated_we), - .wd (reset_en_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.reset_en[0].q), - .ds (), - - // to register interface (read) - .qs (reset_en_qs) - ); - - - // Subregister 0 of Multireg reset_status - // R[reset_status]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_reset_status ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.reset_status[0].de), - .d (hw2reg.reset_status[0].d), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (reset_status_qs) - ); - - - // R[wake_info_capture_dis]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_wake_info_capture_dis ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (wake_info_capture_dis_we), - .wd (wake_info_capture_dis_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.wake_info_capture_dis.q), - .ds (), - - // to register interface (read) - .qs (wake_info_capture_dis_qs) - ); - - - // R[wake_info]: V(True) - logic wake_info_qe; - logic [2:0] wake_info_flds_we; - assign wake_info_qe = &wake_info_flds_we; - // F[reasons]: 0:0 - prim_subreg_ext #( - .DW (1) - ) u_wake_info_reasons ( - .re (wake_info_re), - .we (wake_info_we), - .wd (wake_info_reasons_wd), - .d (hw2reg.wake_info.reasons.d), - .qre (), - .qe (wake_info_flds_we[0]), - .q (reg2hw.wake_info.reasons.q), - .ds (), - .qs (wake_info_reasons_qs) - ); - assign reg2hw.wake_info.reasons.qe = wake_info_qe; - - // F[fall_through]: 1:1 - prim_subreg_ext #( - .DW (1) - ) u_wake_info_fall_through ( - .re (wake_info_re), - .we (wake_info_we), - .wd (wake_info_fall_through_wd), - .d (hw2reg.wake_info.fall_through.d), - .qre (), - .qe (wake_info_flds_we[1]), - .q (reg2hw.wake_info.fall_through.q), - .ds (), - .qs (wake_info_fall_through_qs) - ); - assign reg2hw.wake_info.fall_through.qe = wake_info_qe; - - // F[abort]: 2:2 - prim_subreg_ext #( - .DW (1) - ) u_wake_info_abort ( - .re (wake_info_re), - .we (wake_info_we), - .wd (wake_info_abort_wd), - .d (hw2reg.wake_info.abort.d), - .qre (), - .qe (wake_info_flds_we[2]), - .q (reg2hw.wake_info.abort.q), - .ds (), - .qs (wake_info_abort_qs) - ); - assign reg2hw.wake_info.abort.qe = wake_info_qe; - - - - logic [13:0] addr_hit; - always_comb begin - addr_hit = '0; - addr_hit[ 0] = (reg_addr == PWRMGR_INTR_STATE_OFFSET); - addr_hit[ 1] = (reg_addr == PWRMGR_INTR_ENABLE_OFFSET); - addr_hit[ 2] = (reg_addr == PWRMGR_INTR_TEST_OFFSET); - addr_hit[ 3] = (reg_addr == PWRMGR_CTRL_CFG_REGWEN_OFFSET); - addr_hit[ 4] = (reg_addr == PWRMGR_CONTROL_OFFSET); - addr_hit[ 5] = (reg_addr == PWRMGR_CFG_CDC_SYNC_OFFSET); - addr_hit[ 6] = (reg_addr == PWRMGR_WAKEUP_EN_REGWEN_OFFSET); - addr_hit[ 7] = (reg_addr == PWRMGR_WAKEUP_EN_OFFSET); - addr_hit[ 8] = (reg_addr == PWRMGR_WAKE_STATUS_OFFSET); - addr_hit[ 9] = (reg_addr == PWRMGR_RESET_EN_REGWEN_OFFSET); - addr_hit[10] = (reg_addr == PWRMGR_RESET_EN_OFFSET); - addr_hit[11] = (reg_addr == PWRMGR_RESET_STATUS_OFFSET); - addr_hit[12] = (reg_addr == PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET); - addr_hit[13] = (reg_addr == PWRMGR_WAKE_INFO_OFFSET); - end - - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; - - // Check sub-word write is permitted - always_comb begin - wr_err = (reg_we & - ((addr_hit[ 0] & (|(PWRMGR_PERMIT[ 0] & ~reg_be))) | - (addr_hit[ 1] & (|(PWRMGR_PERMIT[ 1] & ~reg_be))) | - (addr_hit[ 2] & (|(PWRMGR_PERMIT[ 2] & ~reg_be))) | - (addr_hit[ 3] & (|(PWRMGR_PERMIT[ 3] & ~reg_be))) | - (addr_hit[ 4] & (|(PWRMGR_PERMIT[ 4] & ~reg_be))) | - (addr_hit[ 5] & (|(PWRMGR_PERMIT[ 5] & ~reg_be))) | - (addr_hit[ 6] & (|(PWRMGR_PERMIT[ 6] & ~reg_be))) | - (addr_hit[ 7] & (|(PWRMGR_PERMIT[ 7] & ~reg_be))) | - (addr_hit[ 8] & (|(PWRMGR_PERMIT[ 8] & ~reg_be))) | - (addr_hit[ 9] & (|(PWRMGR_PERMIT[ 9] & ~reg_be))) | - (addr_hit[10] & (|(PWRMGR_PERMIT[10] & ~reg_be))) | - (addr_hit[11] & (|(PWRMGR_PERMIT[11] & ~reg_be))) | - (addr_hit[12] & (|(PWRMGR_PERMIT[12] & ~reg_be))) | - (addr_hit[13] & (|(PWRMGR_PERMIT[13] & ~reg_be))))); - end - - // Generate write-enables - assign intr_state_we = addr_hit[0] & reg_we & !reg_error; - - assign intr_state_wd = reg_wdata[0]; - assign intr_enable_we = addr_hit[1] & reg_we & !reg_error; - - assign intr_enable_wd = reg_wdata[0]; - assign intr_test_we = addr_hit[2] & reg_we & !reg_error; - - assign intr_test_wd = reg_wdata[0]; - assign ctrl_cfg_regwen_re = addr_hit[3] & reg_re & !reg_error; - assign control_we = addr_hit[4] & reg_we & !reg_error; - - assign control_low_power_hint_wd = reg_wdata[0]; - - assign control_core_clk_en_wd = reg_wdata[4]; - - assign control_io_clk_en_wd = reg_wdata[5]; - - assign control_usb_clk_en_lp_wd = reg_wdata[6]; - - assign control_usb_clk_en_active_wd = reg_wdata[7]; - - assign control_main_pd_n_wd = reg_wdata[8]; - assign cfg_cdc_sync_we = addr_hit[5] & reg_we & !reg_error; - - assign cfg_cdc_sync_wd = reg_wdata[0]; - assign wakeup_en_regwen_we = addr_hit[6] & reg_we & !reg_error; - - assign wakeup_en_regwen_wd = reg_wdata[0]; - assign wakeup_en_we = addr_hit[7] & reg_we & !reg_error; - - assign wakeup_en_wd = reg_wdata[0]; - assign reset_en_regwen_we = addr_hit[9] & reg_we & !reg_error; - - assign reset_en_regwen_wd = reg_wdata[0]; - assign reset_en_we = addr_hit[10] & reg_we & !reg_error; - - assign reset_en_wd = reg_wdata[0]; - assign wake_info_capture_dis_we = addr_hit[12] & reg_we & !reg_error; - - assign wake_info_capture_dis_wd = reg_wdata[0]; - assign wake_info_re = addr_hit[13] & reg_re & !reg_error; - assign wake_info_we = addr_hit[13] & reg_we & !reg_error; - - assign wake_info_reasons_wd = reg_wdata[0]; - - assign wake_info_fall_through_wd = reg_wdata[1]; - - assign wake_info_abort_wd = reg_wdata[2]; - - // Assign write-enables to checker logic vector. - always_comb begin - reg_we_check = '0; - reg_we_check[0] = intr_state_we; - reg_we_check[1] = intr_enable_we; - reg_we_check[2] = intr_test_we; - reg_we_check[3] = 1'b0; - reg_we_check[4] = control_gated_we; - reg_we_check[5] = cfg_cdc_sync_we; - reg_we_check[6] = wakeup_en_regwen_we; - reg_we_check[7] = wakeup_en_gated_we; - reg_we_check[8] = 1'b0; - reg_we_check[9] = reset_en_regwen_we; - reg_we_check[10] = reset_en_gated_we; - reg_we_check[11] = 1'b0; - reg_we_check[12] = wake_info_capture_dis_we; - reg_we_check[13] = wake_info_we; - end - - // Read data return - always_comb begin - reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin - reg_rdata_next[0] = intr_state_qs; - end - - addr_hit[1]: begin - reg_rdata_next[0] = intr_enable_qs; - end - - addr_hit[2]: begin - reg_rdata_next[0] = '0; - end - - addr_hit[3]: begin - reg_rdata_next[0] = ctrl_cfg_regwen_qs; - end - - addr_hit[4]: begin - reg_rdata_next[0] = control_low_power_hint_qs; - reg_rdata_next[4] = control_core_clk_en_qs; - reg_rdata_next[5] = control_io_clk_en_qs; - reg_rdata_next[6] = control_usb_clk_en_lp_qs; - reg_rdata_next[7] = control_usb_clk_en_active_qs; - reg_rdata_next[8] = control_main_pd_n_qs; - end - - addr_hit[5]: begin - reg_rdata_next[0] = cfg_cdc_sync_qs; - end - - addr_hit[6]: begin - reg_rdata_next[0] = wakeup_en_regwen_qs; - end - - addr_hit[7]: begin - reg_rdata_next[0] = wakeup_en_qs; - end - - addr_hit[8]: begin - reg_rdata_next[0] = wake_status_qs; - end - - addr_hit[9]: begin - reg_rdata_next[0] = reset_en_regwen_qs; - end - - addr_hit[10]: begin - reg_rdata_next[0] = reset_en_qs; - end - - addr_hit[11]: begin - reg_rdata_next[0] = reset_status_qs; - end - - addr_hit[12]: begin - reg_rdata_next[0] = wake_info_capture_dis_qs; - end - - addr_hit[13]: begin - reg_rdata_next[0] = wake_info_reasons_qs; - reg_rdata_next[1] = wake_info_fall_through_qs; - reg_rdata_next[2] = wake_info_abort_qs; - end - - default: begin - reg_rdata_next = '1; - end - endcase - end - - // shadow busy - logic shadow_busy; - assign shadow_busy = 1'b0; - - // register busy - assign reg_busy = shadow_busy; - - // Unused signal tieoff - - // wdata / byte enable are not always fully used - // add a blanket unused statement to handle lint waivers - logic unused_wdata; - logic unused_be; - assign unused_wdata = ^reg_wdata; - assign unused_be = ^reg_be; - - // Assertions for Register Interface - `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) - `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) - - `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) - - `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) - - // this is formulated as an assumption such that the FPV testbenches do disprove this - // property by mistake - //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) - -endmodule diff --git a/hw/top_earlgrey/dv/chip_sim.core b/hw/top_earlgrey/dv/chip_sim.core index c79fe5592d1a63..c8732a52a3b1c8 100644 --- a/hw/top_earlgrey/dv/chip_sim.core +++ b/hw/top_earlgrey/dv/chip_sim.core @@ -16,6 +16,9 @@ filesets: files_dv: depend: + # Place the autogen packages first to avoid conflicts + - lowrisc:opentitan:top_earlgrey_alert_handler_reg + - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg - lowrisc:ip:tlul - lowrisc:dv:chip_test - lowrisc:dv:clkmgr_sva diff --git a/hw/top_earlgrey/dv/env/chip_env.core b/hw/top_earlgrey/dv/env/chip_env.core index b7cf1059cbd300..a35712a9091a33 100644 --- a/hw/top_earlgrey/dv/env/chip_env.core +++ b/hw/top_earlgrey/dv/env/chip_env.core @@ -31,7 +31,7 @@ filesets: - lowrisc:dv:i2c_agent - lowrisc:dv:pattgen_agent - lowrisc:ip:otp_ctrl_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:dv:lc_ctrl_dv_utils - "!fileset_partner ? (lowrisc:systems:ast_pkg)" - "fileset_partner ? (partner:systems:ast_pkg)" diff --git a/hw/top_earlgrey/dv/sva/top_earlgrey_sva.core b/hw/top_earlgrey/dv/sva/top_earlgrey_sva.core index d429f609e9db8f..e86c330f155ea1 100644 --- a/hw/top_earlgrey/dv/sva/top_earlgrey_sva.core +++ b/hw/top_earlgrey/dv/sva/top_earlgrey_sva.core @@ -7,7 +7,7 @@ description: "TOP_EARLGREY assertion modules and bind file." filesets: files_dv: depend: - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:prim:assert - lowrisc:systems:top_earlgrey files: diff --git a/hw/top_earlgrey/ip/clkmgr/clkmgr.core b/hw/top_earlgrey/ip/clkmgr/clkmgr.core index b146e9cd3305b3..06422de232a83c 100644 --- a/hw/top_earlgrey/ip/clkmgr/clkmgr.core +++ b/hw/top_earlgrey/ip/clkmgr/clkmgr.core @@ -9,7 +9,7 @@ filesets: files_rtl: depend: - lowrisc:ip:lc_ctrl_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:tlul - lowrisc:prim:all - lowrisc:prim:buf diff --git a/hw/top_earlgrey/ip/clkmgr/clkmgr_pkg.core b/hw/top_earlgrey/ip/clkmgr/clkmgr_pkg.core index c8c3b25229ae08..c47cf27c055fd5 100644 --- a/hw/top_earlgrey/ip/clkmgr/clkmgr_pkg.core +++ b/hw/top_earlgrey/ip/clkmgr/clkmgr_pkg.core @@ -9,7 +9,7 @@ filesets: files_rtl: depend: - lowrisc:constants:top_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg files: - rtl/autogen/clkmgr_pkg.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/ip/rstmgr/system_rstmgr_pkg.core b/hw/top_earlgrey/ip/rstmgr/system_rstmgr_pkg.core index aaf4e9d5e052dc..ec08c5d8b2714c 100644 --- a/hw/top_earlgrey/ip/rstmgr/system_rstmgr_pkg.core +++ b/hw/top_earlgrey/ip/rstmgr/system_rstmgr_pkg.core @@ -8,7 +8,7 @@ description: "Auto-generated reset manager package for top_earlgrey" filesets: files_rtl: depend: - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:rstmgr_reg - lowrisc:ip_interfaces:alert_handler_reg - lowrisc:ip:alert_handler_component diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core index d71a35180c2772..b19f07c3623908 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core @@ -9,7 +9,7 @@ filesets: depend: - lowrisc:dv:ralgen - lowrisc:dv:cip_lib - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg files: - pwrmgr_env_pkg.sv - pwrmgr_env_cfg.sv: {is_include_file: true} diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core index 9eaa8fd0db4d5a..d35cbce65b7b7a 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core @@ -7,7 +7,7 @@ description: "PWRMGR DV sim target" filesets: files_rtl: depend: - - lowrisc:ip:pwrmgr + - lowrisc:ip_interfaces:pwrmgr files_dv: depend: - lowrisc:dv:pwrmgr_test diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core index 79631950495e26..8adac26d23551f 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core @@ -7,7 +7,7 @@ description: "PWRMGR to RSTMGR assertion interface." filesets: files_dv: depend: - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:prim:assert files: - pwrmgr_rstmgr_sva_if.sv diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core index b71c2dede28a47..4d606bf4e35228 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core @@ -9,7 +9,7 @@ filesets: depend: - lowrisc:tlul:headers - lowrisc:fpv:csr_assert_gen - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:dv:clkmgr_pwrmgr_sva_if - lowrisc:dv:pwrmgr_rstmgr_sva_if files: @@ -21,7 +21,7 @@ filesets: files_formal: depend: - - lowrisc:ip:pwrmgr + - lowrisc:ip_interfaces:pwrmgr generate: csr_assert_gen: diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core index c384dae955aaba..a12e1d70b13931 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core @@ -2,32 +2,17 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr:0.1" +name: lowrisc:opentitan:top_earlgrey_pwrmgr:0.1 description: "Power manager RTL" +virtual: + - lowrisc:ip_interfaces:pwrmgr filesets: files_rtl: depend: - - lowrisc:ip:tlul - - lowrisc:prim:esc - - lowrisc:prim:lc_sync - - lowrisc:prim:lc_sender - - lowrisc:prim:all - - lowrisc:ip:rom_ctrl_pkg - - lowrisc:ip:lc_ctrl_pkg - - lowrisc:prim:sparse_fsm - - lowrisc:prim:mubi - - lowrisc:prim:clock_buf - - lowrisc:prim:measure - - lowrisc:ip_interfaces:alert_handler_reg - - lowrisc:ip:pwrmgr_pkg - - lowrisc:ip:pwrmgr_reg - files: - - rtl/pwrmgr_cdc.sv - - rtl/pwrmgr_slow_fsm.sv - - rtl/pwrmgr_fsm.sv - - rtl/pwrmgr_wake_info.sv - - rtl/pwrmgr.sv + - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1 + - lowrisc:opentitan:top_earlgrey_pwrmgr_reg:0.1 + - lowrisc:ip:pwrmgr_component file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core new file mode 100644 index 00000000000000..2069107cadb6b0 --- /dev/null +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core @@ -0,0 +1,80 @@ +CAPI=2: +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:ip:pwrmgr_component:0.1" +description: "Power manager RTL" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:esc + - lowrisc:prim:lc_sync + - lowrisc:prim:lc_sender + - lowrisc:prim:all + - lowrisc:ip:rom_ctrl_pkg + - lowrisc:ip:lc_ctrl_pkg + - lowrisc:prim:sparse_fsm + - lowrisc:prim:mubi + - lowrisc:prim:clock_buf + - lowrisc:prim:measure + - lowrisc:ip_interfaces:alert_handler_reg + - lowrisc:ip_interfaces:pwrmgr_pkg + files: + - rtl/pwrmgr_cdc.sv + - rtl/pwrmgr_slow_fsm.sv + - rtl/pwrmgr_fsm.sv + - rtl/pwrmgr_wake_info.sv + - rtl/pwrmgr.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: pwrmgr + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core index 3e83cde44fd128..71d3abdcafc86f 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core @@ -2,13 +2,15 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr_pkg:0.1" +name: lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1 description: "Power manager package" +virtual: + - lowrisc:ip_interfaces:pwrmgr_pkg filesets: files_rtl: depend: - - lowrisc:ip:pwrmgr_reg + - lowrisc:opentitan:top_earlgrey_pwrmgr_reg files: - rtl/pwrmgr_pkg.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core index c20cd917273d83..75361f737b0b80 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core @@ -2,8 +2,10 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr_reg:0.1" +name: lowrisc:opentitan:top_earlgrey_pwrmgr_reg:0.1 description: "Power manager registers" +virtual: + - lowrisc:ip_interfaces:pwrmgr_reg filesets: files_rtl: diff --git a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson index 1bb7e093dbd686..be8ef48fe87e2c 100644 --- a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson +++ b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson @@ -175,7 +175,7 @@ ] }, { name: pwrmgr - fusesoc_core: lowrisc:ip:pwrmgr + fusesoc_core: lowrisc:ip_interfaces:pwrmgr import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], rel_path: "hw/top_earlgrey/ip_autogen/pwrmgr/lint/{tool}", overrides: [ diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core index e2e3536fcfaac4..4dd99a51b247c3 100644 --- a/hw/top_earlgrey/top_earlgrey.core +++ b/hw/top_earlgrey/top_earlgrey.core @@ -7,6 +7,9 @@ description: "Technology-independent Earl Grey toplevel" filesets: files_rtl_generic: depend: + # Place the autogen packages first to avoid conflicts + - lowrisc:opentitan:top_earlgrey_alert_handler_reg + - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg - lowrisc:ip:uart:0.1 - lowrisc:opentitan:top_earlgrey_alert_handler - lowrisc:ip:gpio @@ -41,7 +44,7 @@ filesets: - lowrisc:top_earlgrey:xbar_main - lowrisc:top_earlgrey:xbar_peri - lowrisc:ip:rstmgr - - lowrisc:ip:pwrmgr + - lowrisc:opentitan:top_earlgrey_pwrmgr - lowrisc:ip:aon_timer - lowrisc:ip:adc_ctrl - lowrisc:ip:sysrst_ctrl diff --git a/hw/top_englishbreakfast/lint/top_englishbreakfast_lint_cfgs.hjson b/hw/top_englishbreakfast/lint/top_englishbreakfast_lint_cfgs.hjson index 76975e3855fbab..7e5090d6f52a33 100644 --- a/hw/top_englishbreakfast/lint/top_englishbreakfast_lint_cfgs.hjson +++ b/hw/top_englishbreakfast/lint/top_englishbreakfast_lint_cfgs.hjson @@ -41,7 +41,7 @@ ] }, { name: pwrmgr - fusesoc_core: lowrisc:ip:pwrmgr + fusesoc_core: lowrisc:ip_interfaces:pwrmgr import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], rel_path: "hw/ip/pwrmgr/lint/{tool}", overrides: [ diff --git a/hw/top_englishbreakfast/top_englishbreakfast.core b/hw/top_englishbreakfast/top_englishbreakfast.core index 981cc42037b68d..969a2b0130c4db 100644 --- a/hw/top_englishbreakfast/top_englishbreakfast.core +++ b/hw/top_englishbreakfast/top_englishbreakfast.core @@ -39,7 +39,7 @@ filesets: - lowrisc:top_englishbreakfast:xbar_main - lowrisc:top_englishbreakfast:xbar_peri - lowrisc:ip:rstmgr - - lowrisc:ip:pwrmgr + - lowrisc:opentitan:top_englishbreakfast_pwrmgr - lowrisc:ip:rom_ctrl - lowrisc:ip:aon_timer diff --git a/sw/device/tests/autogen/BUILD b/sw/device/tests/autogen/BUILD index 85838f05ae191a..6a9c8db93a3f43 100644 --- a/sw/device/tests/autogen/BUILD +++ b/sw/device/tests/autogen/BUILD @@ -4,8 +4,8 @@ # # ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------# # PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: -# util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -# -o hw/top_earlgrey +# util/topgen.py -t hw/top_englishbreakfast/data/top_englishbreakfast.hjson +# -o hw/top_englishbreakfast load( "//rules/opentitan:defs.bzl", @@ -42,28 +42,13 @@ package(default_visibility = ["//visibility:public"]) "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/arch:boot_stage", "//sw/device/lib/base:mmio", - "//sw/device/lib/dif:adc_ctrl", - "//sw/device/lib/dif:alert_handler", "//sw/device/lib/dif:aon_timer", - "//sw/device/lib/dif:csrng", - "//sw/device/lib/dif:edn", - "//sw/device/lib/dif:entropy_src", "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:gpio", - "//sw/device/lib/dif:hmac", - "//sw/device/lib/dif:i2c", - "//sw/device/lib/dif:keymgr", - "//sw/device/lib/dif:kmac", - "//sw/device/lib/dif:otbn", - "//sw/device/lib/dif:otp_ctrl", - "//sw/device/lib/dif:pattgen", "//sw/device/lib/dif:pwrmgr", "//sw/device/lib/dif:rv_plic", - "//sw/device/lib/dif:rv_timer", - "//sw/device/lib/dif:sensor_ctrl", "//sw/device/lib/dif:spi_device", "//sw/device/lib/dif:spi_host", - "//sw/device/lib/dif:sysrst_ctrl", "//sw/device/lib/dif:uart", "//sw/device/lib/dif:usbdev", "//sw/device/lib/runtime:irq", @@ -72,15 +57,13 @@ package(default_visibility = ["//visibility:public"]) "//sw/device/lib/testing/test_framework:ottf_main", ], ) - for min in range(0, 23, 10) + for min in range(0, 8, 10) ] test_suite( name = "plic_all_irqs_test", tests = [ "plic_all_irqs_test_0", - "plic_all_irqs_test_10", - "plic_all_irqs_test_20", ], ) @@ -101,37 +84,22 @@ opentitan_test( "//sw/device/lib/arch:boot_stage", "//sw/device/lib/base:memory", "//sw/device/lib/base:mmio", - "//sw/device/lib/dif:adc_ctrl", "//sw/device/lib/dif:aes", "//sw/device/lib/dif:alert_handler", "//sw/device/lib/dif:aon_timer", "//sw/device/lib/dif:clkmgr", - "//sw/device/lib/dif:csrng", - "//sw/device/lib/dif:edn", - "//sw/device/lib/dif:entropy_src", "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:gpio", - "//sw/device/lib/dif:hmac", - "//sw/device/lib/dif:i2c", - "//sw/device/lib/dif:keymgr", - "//sw/device/lib/dif:kmac", - "//sw/device/lib/dif:lc_ctrl", - "//sw/device/lib/dif:otbn", - "//sw/device/lib/dif:otp_ctrl", - "//sw/device/lib/dif:pattgen", "//sw/device/lib/dif:pinmux", - "//sw/device/lib/dif:pwm", "//sw/device/lib/dif:pwrmgr", "//sw/device/lib/dif:rom_ctrl", "//sw/device/lib/dif:rstmgr", "//sw/device/lib/dif:rv_core_ibex", "//sw/device/lib/dif:rv_plic", "//sw/device/lib/dif:rv_timer", - "//sw/device/lib/dif:sensor_ctrl", "//sw/device/lib/dif:spi_device", "//sw/device/lib/dif:spi_host", "//sw/device/lib/dif:sram_ctrl", - "//sw/device/lib/dif:sysrst_ctrl", "//sw/device/lib/dif:uart", "//sw/device/lib/dif:usbdev", "//sw/device/lib/runtime:log", diff --git a/sw/device/tests/autogen/alert_test.c b/sw/device/tests/autogen/alert_test.c index f68c8aa5d35b13..2b14951821d4da 100644 --- a/sw/device/tests/autogen/alert_test.c +++ b/sw/device/tests/autogen/alert_test.c @@ -6,41 +6,26 @@ // // ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// // PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: -// util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -// -o hw/top_earlgrey +// util/topgen.py -t hw/top_englishbreakfast/data/top_englishbreakfast.hjson +// -o hw/top_englishbreakfast #include "sw/device/lib/arch/boot_stage.h" #include "sw/device/lib/base/mmio.h" -#include "sw/device/lib/dif/dif_adc_ctrl.h" #include "sw/device/lib/dif/dif_aes.h" #include "sw/device/lib/dif/dif_alert_handler.h" #include "sw/device/lib/dif/dif_aon_timer.h" #include "sw/device/lib/dif/dif_clkmgr.h" -#include "sw/device/lib/dif/dif_csrng.h" -#include "sw/device/lib/dif/dif_edn.h" -#include "sw/device/lib/dif/dif_entropy_src.h" #include "sw/device/lib/dif/dif_flash_ctrl.h" #include "sw/device/lib/dif/dif_gpio.h" -#include "sw/device/lib/dif/dif_hmac.h" -#include "sw/device/lib/dif/dif_i2c.h" -#include "sw/device/lib/dif/dif_keymgr.h" -#include "sw/device/lib/dif/dif_kmac.h" -#include "sw/device/lib/dif/dif_lc_ctrl.h" -#include "sw/device/lib/dif/dif_otbn.h" -#include "sw/device/lib/dif/dif_otp_ctrl.h" -#include "sw/device/lib/dif/dif_pattgen.h" #include "sw/device/lib/dif/dif_pinmux.h" -#include "sw/device/lib/dif/dif_pwm.h" #include "sw/device/lib/dif/dif_pwrmgr.h" #include "sw/device/lib/dif/dif_rom_ctrl.h" #include "sw/device/lib/dif/dif_rstmgr.h" #include "sw/device/lib/dif/dif_rv_core_ibex.h" #include "sw/device/lib/dif/dif_rv_plic.h" #include "sw/device/lib/dif/dif_rv_timer.h" -#include "sw/device/lib/dif/dif_sensor_ctrl.h" #include "sw/device/lib/dif/dif_spi_device.h" #include "sw/device/lib/dif/dif_spi_host.h" #include "sw/device/lib/dif/dif_sram_ctrl.h" -#include "sw/device/lib/dif/dif_sysrst_ctrl.h" #include "sw/device/lib/dif/dif_uart.h" #include "sw/device/lib/dif/dif_usbdev.h" #include "sw/device/lib/testing/alert_handler_testutils.h" @@ -54,45 +39,22 @@ OTTF_DEFINE_TEST_CONFIG(); static dif_alert_handler_t alert_handler; -static dif_adc_ctrl_t adc_ctrl_aon; static dif_aes_t aes; static dif_aon_timer_t aon_timer_aon; static dif_clkmgr_t clkmgr_aon; -static dif_csrng_t csrng; -static dif_edn_t edn0; -static dif_edn_t edn1; -static dif_entropy_src_t entropy_src; static dif_flash_ctrl_t flash_ctrl; static dif_gpio_t gpio; -static dif_hmac_t hmac; -static dif_i2c_t i2c0; -static dif_i2c_t i2c1; -static dif_i2c_t i2c2; -static dif_keymgr_t keymgr; -static dif_kmac_t kmac; -static dif_lc_ctrl_t lc_ctrl; -static dif_otbn_t otbn; -static dif_otp_ctrl_t otp_ctrl; -static dif_pattgen_t pattgen; static dif_pinmux_t pinmux_aon; -static dif_pwm_t pwm_aon; static dif_pwrmgr_t pwrmgr_aon; static dif_rom_ctrl_t rom_ctrl; static dif_rstmgr_t rstmgr_aon; static dif_rv_core_ibex_t rv_core_ibex; static dif_rv_plic_t rv_plic; static dif_rv_timer_t rv_timer; -static dif_sensor_ctrl_t sensor_ctrl_aon; static dif_spi_device_t spi_device; static dif_spi_host_t spi_host0; -static dif_spi_host_t spi_host1; static dif_sram_ctrl_t sram_ctrl_main; -static dif_sram_ctrl_t sram_ctrl_ret_aon; -static dif_sysrst_ctrl_t sysrst_ctrl_aon; static dif_uart_t uart0; -static dif_uart_t uart1; -static dif_uart_t uart2; -static dif_uart_t uart3; static dif_usbdev_t usbdev; /** @@ -103,124 +65,55 @@ static void init_peripherals(void) { base_addr = mmio_region_from_addr(TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR); CHECK_DIF_OK(dif_alert_handler_init(base_addr, &alert_handler)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR); - CHECK_DIF_OK(dif_adc_ctrl_init(base_addr, &adc_ctrl_aon)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_AES_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_AES_BASE_ADDR); CHECK_DIF_OK(dif_aes_init(base_addr, &aes)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_AON_TIMER_AON_BASE_ADDR); CHECK_DIF_OK(dif_aon_timer_init(base_addr, &aon_timer_aon)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_CLKMGR_AON_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_CLKMGR_AON_BASE_ADDR); CHECK_DIF_OK(dif_clkmgr_init(base_addr, &clkmgr_aon)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_CSRNG_BASE_ADDR); - CHECK_DIF_OK(dif_csrng_init(base_addr, &csrng)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_EDN0_BASE_ADDR); - CHECK_DIF_OK(dif_edn_init(base_addr, &edn0)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_EDN1_BASE_ADDR); - CHECK_DIF_OK(dif_edn_init(base_addr, &edn1)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR); - CHECK_DIF_OK(dif_entropy_src_init(base_addr, &entropy_src)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_BASE_ADDR); CHECK_DIF_OK(dif_flash_ctrl_init(base_addr, &flash_ctrl)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_GPIO_BASE_ADDR); CHECK_DIF_OK(dif_gpio_init(base_addr, &gpio)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_HMAC_BASE_ADDR); - CHECK_DIF_OK(dif_hmac_init(base_addr, &hmac)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C0_BASE_ADDR); - CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c0)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C1_BASE_ADDR); - CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c1)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C2_BASE_ADDR); - CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c2)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_KEYMGR_BASE_ADDR); - CHECK_DIF_OK(dif_keymgr_init(base_addr, &keymgr)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_KMAC_BASE_ADDR); - CHECK_DIF_OK(dif_kmac_init(base_addr, &kmac)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_LC_CTRL_BASE_ADDR); - CHECK_DIF_OK(dif_lc_ctrl_init(base_addr, &lc_ctrl)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR); - CHECK_DIF_OK(dif_otbn_init(base_addr, &otbn)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR); - CHECK_DIF_OK(dif_otp_ctrl_init(base_addr, &otp_ctrl)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_PATTGEN_BASE_ADDR); - CHECK_DIF_OK(dif_pattgen_init(base_addr, &pattgen)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_PINMUX_AON_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_PINMUX_AON_BASE_ADDR); CHECK_DIF_OK(dif_pinmux_init(base_addr, &pinmux_aon)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_PWM_AON_BASE_ADDR); - CHECK_DIF_OK(dif_pwm_init(base_addr, &pwm_aon)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_PWRMGR_AON_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_PWRMGR_AON_BASE_ADDR); CHECK_DIF_OK(dif_pwrmgr_init(base_addr, &pwrmgr_aon)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_BASE_ADDR); CHECK_DIF_OK(dif_rom_ctrl_init(base_addr, &rom_ctrl)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_RSTMGR_AON_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_RSTMGR_AON_BASE_ADDR); CHECK_DIF_OK(dif_rstmgr_init(base_addr, &rstmgr_aon)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_BASE_ADDR); CHECK_DIF_OK(dif_rv_core_ibex_init(base_addr, &rv_core_ibex)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_RV_PLIC_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_RV_PLIC_BASE_ADDR); CHECK_DIF_OK(dif_rv_plic_init(base_addr, &rv_plic)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_RV_TIMER_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_RV_TIMER_BASE_ADDR); CHECK_DIF_OK(dif_rv_timer_init(base_addr, &rv_timer)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR); - CHECK_DIF_OK(dif_sensor_ctrl_init(base_addr, &sensor_ctrl_aon)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_SPI_DEVICE_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_SPI_DEVICE_BASE_ADDR); CHECK_DIF_OK(dif_spi_device_init(base_addr, &spi_device)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_SPI_HOST0_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_SPI_HOST0_BASE_ADDR); CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host0)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_SPI_HOST1_BASE_ADDR); - CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host1)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_BASE_ADDR); CHECK_DIF_OK(dif_sram_ctrl_init(base_addr, &sram_ctrl_main)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR); - CHECK_DIF_OK(dif_sram_ctrl_init(base_addr, &sram_ctrl_ret_aon)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR); - CHECK_DIF_OK(dif_sysrst_ctrl_init(base_addr, &sysrst_ctrl_aon)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_UART0_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_UART0_BASE_ADDR); CHECK_DIF_OK(dif_uart_init(base_addr, &uart0)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_UART1_BASE_ADDR); - CHECK_DIF_OK(dif_uart_init(base_addr, &uart1)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_UART2_BASE_ADDR); - CHECK_DIF_OK(dif_uart_init(base_addr, &uart2)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_UART3_BASE_ADDR); - CHECK_DIF_OK(dif_uart_init(base_addr, &uart3)); - - base_addr = mmio_region_from_addr(TOP_EARLGREY_USBDEV_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_USBDEV_BASE_ADDR); CHECK_DIF_OK(dif_usbdev_init(base_addr, &usbdev)); } @@ -281,27 +174,12 @@ static void trigger_alert_test(void) { bool is_cause; dif_alert_handler_alert_t exp_alert; - // Write adc_ctrl's alert_test reg and check alert_cause. - for (dif_adc_ctrl_alert_t i = 0; i < 1; ++i) { - CHECK_DIF_OK(dif_adc_ctrl_alert_force(&adc_ctrl_aon, kDifAdcCtrlAlertFatalFault + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdAdcCtrlAonFatalFault + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - // Write aes's alert_test reg and check alert_cause. for (dif_aes_alert_t i = 0; i < 2; ++i) { CHECK_DIF_OK(dif_aes_alert_force(&aes, kDifAesAlertRecovCtrlUpdateErr + i)); // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdAesRecovCtrlUpdateErr + i; + exp_alert = kTopEnglishbreakfastAlertIdAesRecovCtrlUpdateErr + i; CHECK_DIF_OK(dif_alert_handler_alert_is_cause( &alert_handler, exp_alert, &is_cause)); CHECK(is_cause, "Expect alert %d!", exp_alert); @@ -316,7 +194,7 @@ static void trigger_alert_test(void) { CHECK_DIF_OK(dif_aon_timer_alert_force(&aon_timer_aon, kDifAonTimerAlertFatalFault + i)); // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdAonTimerAonFatalFault + i; + exp_alert = kTopEnglishbreakfastAlertIdAonTimerAonFatalFault + i; CHECK_DIF_OK(dif_alert_handler_alert_is_cause( &alert_handler, exp_alert, &is_cause)); CHECK(is_cause, "Expect alert %d!", exp_alert); @@ -331,67 +209,7 @@ static void trigger_alert_test(void) { CHECK_DIF_OK(dif_clkmgr_alert_force(&clkmgr_aon, kDifClkmgrAlertRecovFault + i)); // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdClkmgrAonRecovFault + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write csrng's alert_test reg and check alert_cause. - for (dif_csrng_alert_t i = 0; i < 2; ++i) { - CHECK_DIF_OK(dif_csrng_alert_force(&csrng, kDifCsrngAlertRecovAlert + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdCsrngRecovAlert + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write edn's alert_test reg and check alert_cause. - for (dif_edn_alert_t i = 0; i < 2; ++i) { - CHECK_DIF_OK(dif_edn_alert_force(&edn0, kDifEdnAlertRecovAlert + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdEdn0RecovAlert + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write edn's alert_test reg and check alert_cause. - for (dif_edn_alert_t i = 0; i < 2; ++i) { - CHECK_DIF_OK(dif_edn_alert_force(&edn1, kDifEdnAlertRecovAlert + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdEdn1RecovAlert + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write entropy_src's alert_test reg and check alert_cause. - for (dif_entropy_src_alert_t i = 0; i < 2; ++i) { - CHECK_DIF_OK(dif_entropy_src_alert_force(&entropy_src, kDifEntropySrcAlertRecovAlert + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdEntropySrcRecovAlert + i; + exp_alert = kTopEnglishbreakfastAlertIdClkmgrAonRecovFault + i; CHECK_DIF_OK(dif_alert_handler_alert_is_cause( &alert_handler, exp_alert, &is_cause)); CHECK(is_cause, "Expect alert %d!", exp_alert); @@ -406,7 +224,7 @@ static void trigger_alert_test(void) { CHECK_DIF_OK(dif_flash_ctrl_alert_force(&flash_ctrl, kDifFlashCtrlAlertRecovErr + i)); // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdFlashCtrlRecovErr + i; + exp_alert = kTopEnglishbreakfastAlertIdFlashCtrlRecovErr + i; CHECK_DIF_OK(dif_alert_handler_alert_is_cause( &alert_handler, exp_alert, &is_cause)); CHECK(is_cause, "Expect alert %d!", exp_alert); @@ -421,160 +239,7 @@ static void trigger_alert_test(void) { CHECK_DIF_OK(dif_gpio_alert_force(&gpio, kDifGpioAlertFatalFault + i)); // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdGpioFatalFault + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write hmac's alert_test reg and check alert_cause. - for (dif_hmac_alert_t i = 0; i < 1; ++i) { - CHECK_DIF_OK(dif_hmac_alert_force(&hmac, kDifHmacAlertFatalFault + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdHmacFatalFault + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write i2c's alert_test reg and check alert_cause. - for (dif_i2c_alert_t i = 0; i < 1; ++i) { - CHECK_DIF_OK(dif_i2c_alert_force(&i2c0, kDifI2cAlertFatalFault + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdI2c0FatalFault + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write i2c's alert_test reg and check alert_cause. - for (dif_i2c_alert_t i = 0; i < 1; ++i) { - CHECK_DIF_OK(dif_i2c_alert_force(&i2c1, kDifI2cAlertFatalFault + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdI2c1FatalFault + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write i2c's alert_test reg and check alert_cause. - for (dif_i2c_alert_t i = 0; i < 1; ++i) { - CHECK_DIF_OK(dif_i2c_alert_force(&i2c2, kDifI2cAlertFatalFault + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdI2c2FatalFault + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write keymgr's alert_test reg and check alert_cause. - for (dif_keymgr_alert_t i = 0; i < 2; ++i) { - CHECK_DIF_OK(dif_keymgr_alert_force(&keymgr, kDifKeymgrAlertRecovOperationErr + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdKeymgrRecovOperationErr + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write kmac's alert_test reg and check alert_cause. - for (dif_kmac_alert_t i = 0; i < 2; ++i) { - CHECK_DIF_OK(dif_kmac_alert_force(&kmac, kDifKmacAlertRecovOperationErr + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdKmacRecovOperationErr + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write lc_ctrl's alert_test reg and check alert_cause. - for (dif_lc_ctrl_alert_t i = 0; i < 3; ++i) { - CHECK_DIF_OK(dif_lc_ctrl_alert_force(&lc_ctrl, kDifLcCtrlAlertFatalProgError + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdLcCtrlFatalProgError + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write otbn's alert_test reg and check alert_cause. - for (dif_otbn_alert_t i = 0; i < 2; ++i) { - CHECK_DIF_OK(dif_otbn_alert_force(&otbn, kDifOtbnAlertFatal + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdOtbnFatal + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // TODO(lowrisc/opentitan#20348): Enable otp_ctrl when this is fixed. - if (kBootStage != kBootStageOwner) { - // Write otp_ctrl's alert_test reg and check alert_cause. - for (dif_otp_ctrl_alert_t i = 0; i < 5; ++i) { - CHECK_DIF_OK(dif_otp_ctrl_alert_force(&otp_ctrl, kDifOtpCtrlAlertFatalMacroError + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdOtpCtrlFatalMacroError + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - } - - // Write pattgen's alert_test reg and check alert_cause. - for (dif_pattgen_alert_t i = 0; i < 1; ++i) { - CHECK_DIF_OK(dif_pattgen_alert_force(&pattgen, kDifPattgenAlertFatalFault + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdPattgenFatalFault + i; + exp_alert = kTopEnglishbreakfastAlertIdGpioFatalFault + i; CHECK_DIF_OK(dif_alert_handler_alert_is_cause( &alert_handler, exp_alert, &is_cause)); CHECK(is_cause, "Expect alert %d!", exp_alert); @@ -589,22 +254,7 @@ static void trigger_alert_test(void) { CHECK_DIF_OK(dif_pinmux_alert_force(&pinmux_aon, kDifPinmuxAlertFatalFault + i)); // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdPinmuxAonFatalFault + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write pwm's alert_test reg and check alert_cause. - for (dif_pwm_alert_t i = 0; i < 1; ++i) { - CHECK_DIF_OK(dif_pwm_alert_force(&pwm_aon, kDifPwmAlertFatalFault + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdPwmAonFatalFault + i; + exp_alert = kTopEnglishbreakfastAlertIdPinmuxAonFatalFault + i; CHECK_DIF_OK(dif_alert_handler_alert_is_cause( &alert_handler, exp_alert, &is_cause)); CHECK(is_cause, "Expect alert %d!", exp_alert); @@ -619,7 +269,7 @@ static void trigger_alert_test(void) { CHECK_DIF_OK(dif_pwrmgr_alert_force(&pwrmgr_aon, kDifPwrmgrAlertFatalFault + i)); // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdPwrmgrAonFatalFault + i; + exp_alert = kTopEnglishbreakfastAlertIdPwrmgrAonFatalFault + i; CHECK_DIF_OK(dif_alert_handler_alert_is_cause( &alert_handler, exp_alert, &is_cause)); CHECK(is_cause, "Expect alert %d!", exp_alert); @@ -634,7 +284,7 @@ static void trigger_alert_test(void) { CHECK_DIF_OK(dif_rom_ctrl_alert_force(&rom_ctrl, kDifRomCtrlAlertFatal + i)); // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdRomCtrlFatal + i; + exp_alert = kTopEnglishbreakfastAlertIdRomCtrlFatal + i; CHECK_DIF_OK(dif_alert_handler_alert_is_cause( &alert_handler, exp_alert, &is_cause)); CHECK(is_cause, "Expect alert %d!", exp_alert); @@ -649,7 +299,7 @@ static void trigger_alert_test(void) { CHECK_DIF_OK(dif_rstmgr_alert_force(&rstmgr_aon, kDifRstmgrAlertFatalFault + i)); // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdRstmgrAonFatalFault + i; + exp_alert = kTopEnglishbreakfastAlertIdRstmgrAonFatalFault + i; CHECK_DIF_OK(dif_alert_handler_alert_is_cause( &alert_handler, exp_alert, &is_cause)); CHECK(is_cause, "Expect alert %d!", exp_alert); @@ -664,7 +314,7 @@ static void trigger_alert_test(void) { CHECK_DIF_OK(dif_rv_core_ibex_alert_force(&rv_core_ibex, kDifRvCoreIbexAlertFatalSwErr + i)); // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdRvCoreIbexFatalSwErr + i; + exp_alert = kTopEnglishbreakfastAlertIdRvCoreIbexFatalSwErr + i; CHECK_DIF_OK(dif_alert_handler_alert_is_cause( &alert_handler, exp_alert, &is_cause)); CHECK(is_cause, "Expect alert %d!", exp_alert); @@ -679,7 +329,7 @@ static void trigger_alert_test(void) { CHECK_DIF_OK(dif_rv_plic_alert_force(&rv_plic, kDifRvPlicAlertFatalFault + i)); // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdRvPlicFatalFault + i; + exp_alert = kTopEnglishbreakfastAlertIdRvPlicFatalFault + i; CHECK_DIF_OK(dif_alert_handler_alert_is_cause( &alert_handler, exp_alert, &is_cause)); CHECK(is_cause, "Expect alert %d!", exp_alert); @@ -694,22 +344,7 @@ static void trigger_alert_test(void) { CHECK_DIF_OK(dif_rv_timer_alert_force(&rv_timer, kDifRvTimerAlertFatalFault + i)); // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdRvTimerFatalFault + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write sensor_ctrl's alert_test reg and check alert_cause. - for (dif_sensor_ctrl_alert_t i = 0; i < 2; ++i) { - CHECK_DIF_OK(dif_sensor_ctrl_alert_force(&sensor_ctrl_aon, kDifSensorCtrlAlertRecovAlert + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdSensorCtrlAonRecovAlert + i; + exp_alert = kTopEnglishbreakfastAlertIdRvTimerFatalFault + i; CHECK_DIF_OK(dif_alert_handler_alert_is_cause( &alert_handler, exp_alert, &is_cause)); CHECK(is_cause, "Expect alert %d!", exp_alert); @@ -724,7 +359,7 @@ static void trigger_alert_test(void) { CHECK_DIF_OK(dif_spi_device_alert_force(&spi_device, kDifSpiDeviceAlertFatalFault + i)); // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdSpiDeviceFatalFault + i; + exp_alert = kTopEnglishbreakfastAlertIdSpiDeviceFatalFault + i; CHECK_DIF_OK(dif_alert_handler_alert_is_cause( &alert_handler, exp_alert, &is_cause)); CHECK(is_cause, "Expect alert %d!", exp_alert); @@ -739,22 +374,7 @@ static void trigger_alert_test(void) { CHECK_DIF_OK(dif_spi_host_alert_force(&spi_host0, kDifSpiHostAlertFatalFault + i)); // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdSpiHost0FatalFault + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write spi_host's alert_test reg and check alert_cause. - for (dif_spi_host_alert_t i = 0; i < 1; ++i) { - CHECK_DIF_OK(dif_spi_host_alert_force(&spi_host1, kDifSpiHostAlertFatalFault + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdSpiHost1FatalFault + i; + exp_alert = kTopEnglishbreakfastAlertIdSpiHost0FatalFault + i; CHECK_DIF_OK(dif_alert_handler_alert_is_cause( &alert_handler, exp_alert, &is_cause)); CHECK(is_cause, "Expect alert %d!", exp_alert); @@ -769,37 +389,7 @@ static void trigger_alert_test(void) { CHECK_DIF_OK(dif_sram_ctrl_alert_force(&sram_ctrl_main, kDifSramCtrlAlertFatalError + i)); // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdSramCtrlMainFatalError + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write sram_ctrl's alert_test reg and check alert_cause. - for (dif_sram_ctrl_alert_t i = 0; i < 1; ++i) { - CHECK_DIF_OK(dif_sram_ctrl_alert_force(&sram_ctrl_ret_aon, kDifSramCtrlAlertFatalError + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdSramCtrlRetAonFatalError + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write sysrst_ctrl's alert_test reg and check alert_cause. - for (dif_sysrst_ctrl_alert_t i = 0; i < 1; ++i) { - CHECK_DIF_OK(dif_sysrst_ctrl_alert_force(&sysrst_ctrl_aon, kDifSysrstCtrlAlertFatalFault + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdSysrstCtrlAonFatalFault + i; + exp_alert = kTopEnglishbreakfastAlertIdSramCtrlMainFatalError + i; CHECK_DIF_OK(dif_alert_handler_alert_is_cause( &alert_handler, exp_alert, &is_cause)); CHECK(is_cause, "Expect alert %d!", exp_alert); @@ -814,52 +404,7 @@ static void trigger_alert_test(void) { CHECK_DIF_OK(dif_uart_alert_force(&uart0, kDifUartAlertFatalFault + i)); // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdUart0FatalFault + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write uart's alert_test reg and check alert_cause. - for (dif_uart_alert_t i = 0; i < 1; ++i) { - CHECK_DIF_OK(dif_uart_alert_force(&uart1, kDifUartAlertFatalFault + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdUart1FatalFault + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write uart's alert_test reg and check alert_cause. - for (dif_uart_alert_t i = 0; i < 1; ++i) { - CHECK_DIF_OK(dif_uart_alert_force(&uart2, kDifUartAlertFatalFault + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdUart2FatalFault + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - - // Write uart's alert_test reg and check alert_cause. - for (dif_uart_alert_t i = 0; i < 1; ++i) { - CHECK_DIF_OK(dif_uart_alert_force(&uart3, kDifUartAlertFatalFault + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdUart3FatalFault + i; + exp_alert = kTopEnglishbreakfastAlertIdUart0FatalFault + i; CHECK_DIF_OK(dif_alert_handler_alert_is_cause( &alert_handler, exp_alert, &is_cause)); CHECK(is_cause, "Expect alert %d!", exp_alert); @@ -874,7 +419,7 @@ static void trigger_alert_test(void) { CHECK_DIF_OK(dif_usbdev_alert_force(&usbdev, kDifUsbdevAlertFatalFault + i)); // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdUsbdevFatalFault + i; + exp_alert = kTopEnglishbreakfastAlertIdUsbdevFatalFault + i; CHECK_DIF_OK(dif_alert_handler_alert_is_cause( &alert_handler, exp_alert, &is_cause)); CHECK(is_cause, "Expect alert %d!", exp_alert); diff --git a/sw/device/tests/autogen/plic_all_irqs_test.c b/sw/device/tests/autogen/plic_all_irqs_test.c index cd6c4fe69e64e0..242ba5ed49c825 100644 --- a/sw/device/tests/autogen/plic_all_irqs_test.c +++ b/sw/device/tests/autogen/plic_all_irqs_test.c @@ -5,8 +5,8 @@ // // ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// // PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: -// util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -// -o hw/top_earlgrey +// util/topgen.py -t hw/top_englishbreakfast/data/top_englishbreakfast.hjson +// -o hw/top_englishbreakfast #include // This test should avoid otp_ctrl interrupts in rom_ext, since the rom @@ -22,34 +22,19 @@ #endif #ifndef TEST_MAX_IRQ_PERIPHERAL -#define TEST_MAX_IRQ_PERIPHERAL 23 +#define TEST_MAX_IRQ_PERIPHERAL 8 #endif #include "sw/device/lib/arch/boot_stage.h" #include "sw/device/lib/base/csr.h" #include "sw/device/lib/base/mmio.h" -#include "sw/device/lib/dif/dif_adc_ctrl.h" -#include "sw/device/lib/dif/dif_alert_handler.h" #include "sw/device/lib/dif/dif_aon_timer.h" -#include "sw/device/lib/dif/dif_csrng.h" -#include "sw/device/lib/dif/dif_edn.h" -#include "sw/device/lib/dif/dif_entropy_src.h" #include "sw/device/lib/dif/dif_flash_ctrl.h" #include "sw/device/lib/dif/dif_gpio.h" -#include "sw/device/lib/dif/dif_hmac.h" -#include "sw/device/lib/dif/dif_i2c.h" -#include "sw/device/lib/dif/dif_keymgr.h" -#include "sw/device/lib/dif/dif_kmac.h" -#include "sw/device/lib/dif/dif_otbn.h" -#include "sw/device/lib/dif/dif_otp_ctrl.h" -#include "sw/device/lib/dif/dif_pattgen.h" #include "sw/device/lib/dif/dif_pwrmgr.h" #include "sw/device/lib/dif/dif_rv_plic.h" -#include "sw/device/lib/dif/dif_rv_timer.h" -#include "sw/device/lib/dif/dif_sensor_ctrl.h" #include "sw/device/lib/dif/dif_spi_device.h" #include "sw/device/lib/dif/dif_spi_host.h" -#include "sw/device/lib/dif/dif_sysrst_ctrl.h" #include "sw/device/lib/dif/dif_uart.h" #include "sw/device/lib/dif/dif_usbdev.h" #include "sw/device/lib/runtime/ibex.h" @@ -59,130 +44,42 @@ #include "sw/device/lib/testing/rv_plic_testutils.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" #include "sw/device/lib/testing/test_framework/status.h" -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" +#include "hw/top_englishbreakfast/sw/autogen/top_englishbreakfast.h" #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL -static dif_adc_ctrl_t adc_ctrl_aon; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL -static dif_alert_handler_t alert_handler; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL static dif_aon_timer_t aon_timer_aon; #endif -// TODO(lowrisc/opentitan#20747) Adjust csrng special handling once this is -// fixed. -static dif_csrng_t csrng; - -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL -static dif_edn_t edn0; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL -static dif_edn_t edn1; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL -static dif_entropy_src_t entropy_src; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL static dif_flash_ctrl_t flash_ctrl; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL static dif_gpio_t gpio; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL -static dif_hmac_t hmac; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL -static dif_i2c_t i2c0; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL -static dif_i2c_t i2c1; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL -static dif_i2c_t i2c2; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL -static dif_keymgr_t keymgr; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL -static dif_kmac_t kmac; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL -static dif_otbn_t otbn; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL -static dif_otp_ctrl_t otp_ctrl; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL -static dif_pattgen_t pattgen; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL static dif_pwrmgr_t pwrmgr_aon; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL -static dif_rv_timer_t rv_timer; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL -static dif_sensor_ctrl_t sensor_ctrl_aon; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL static dif_spi_device_t spi_device; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL static dif_spi_host_t spi_host0; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL -static dif_spi_host_t spi_host1; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL -static dif_sysrst_ctrl_t sysrst_ctrl_aon; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL static dif_uart_t uart0; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL -static dif_uart_t uart1; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL -static dif_uart_t uart2; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL -static dif_uart_t uart3; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL static dif_usbdev_t usbdev; #endif static dif_rv_plic_t plic; -static const top_earlgrey_plic_target_t kHart = kTopEarlgreyPlicTargetIbex0; +static const top_englishbreakfast_plic_target_t kHart = kTopEnglishbreakfastPlicTargetIbex0; /** * Flag indicating which peripheral is under test. @@ -190,7 +87,7 @@ static const top_earlgrey_plic_target_t kHart = kTopEarlgreyPlicTargetIbex0; * Declared volatile because it is referenced in the main program flow as well * as the ISR. */ -static volatile top_earlgrey_plic_peripheral_t peripheral_expected; +static volatile top_englishbreakfast_plic_peripheral_t peripheral_expected; /** * Flags indicating the IRQ expected to have triggered and serviced within the @@ -201,126 +98,46 @@ static volatile top_earlgrey_plic_peripheral_t peripheral_expected; */ #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_adc_ctrl_irq_t adc_ctrl_irq_expected; -static volatile dif_adc_ctrl_irq_t adc_ctrl_irq_serviced; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_alert_handler_irq_t alert_handler_irq_expected; -static volatile dif_alert_handler_irq_t alert_handler_irq_serviced; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_aon_timer_irq_t aon_timer_irq_expected; static volatile dif_aon_timer_irq_t aon_timer_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_csrng_irq_t csrng_irq_expected; -static volatile dif_csrng_irq_t csrng_irq_serviced; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_edn_irq_t edn_irq_expected; -static volatile dif_edn_irq_t edn_irq_serviced; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_entropy_src_irq_t entropy_src_irq_expected; -static volatile dif_entropy_src_irq_t entropy_src_irq_serviced; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_flash_ctrl_irq_t flash_ctrl_irq_expected; static volatile dif_flash_ctrl_irq_t flash_ctrl_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_gpio_irq_t gpio_irq_expected; static volatile dif_gpio_irq_t gpio_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_hmac_irq_t hmac_irq_expected; -static volatile dif_hmac_irq_t hmac_irq_serviced; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_i2c_irq_t i2c_irq_expected; -static volatile dif_i2c_irq_t i2c_irq_serviced; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_keymgr_irq_t keymgr_irq_expected; -static volatile dif_keymgr_irq_t keymgr_irq_serviced; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_kmac_irq_t kmac_irq_expected; -static volatile dif_kmac_irq_t kmac_irq_serviced; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_otbn_irq_t otbn_irq_expected; -static volatile dif_otbn_irq_t otbn_irq_serviced; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_otp_ctrl_irq_t otp_ctrl_irq_expected; -static volatile dif_otp_ctrl_irq_t otp_ctrl_irq_serviced; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_pattgen_irq_t pattgen_irq_expected; -static volatile dif_pattgen_irq_t pattgen_irq_serviced; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_pwrmgr_irq_t pwrmgr_irq_expected; static volatile dif_pwrmgr_irq_t pwrmgr_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_rv_timer_irq_t rv_timer_irq_expected; -static volatile dif_rv_timer_irq_t rv_timer_irq_serviced; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_sensor_ctrl_irq_t sensor_ctrl_irq_expected; -static volatile dif_sensor_ctrl_irq_t sensor_ctrl_irq_serviced; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_spi_device_irq_t spi_device_irq_expected; static volatile dif_spi_device_irq_t spi_device_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_spi_host_irq_t spi_host_irq_expected; static volatile dif_spi_host_irq_t spi_host_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_sysrst_ctrl_irq_t sysrst_ctrl_irq_expected; -static volatile dif_sysrst_ctrl_irq_t sysrst_ctrl_irq_serviced; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_uart_irq_t uart_irq_expected; static volatile dif_uart_irq_t uart_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_usbdev_irq_t usbdev_irq_expected; static volatile dif_usbdev_irq_t usbdev_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 < TEST_MAX_IRQ_PERIPHERAL -static volatile bool allow_csrng_irq = true; -#else -static volatile bool allow_csrng_irq = false; -#endif /** * Provides external IRQ handling for this test. @@ -339,25 +156,9 @@ void ottf_external_isr(uint32_t *exc_info) { dif_rv_plic_irq_id_t plic_irq_id; CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic, kHart, &plic_irq_id)); - top_earlgrey_plic_peripheral_t peripheral = (top_earlgrey_plic_peripheral_t) - top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id]; - // TODO(lowrisc/opentitan#20747) Adjust code once this issue is fixed. - if (allow_csrng_irq && kBootStage == kBootStageOwner && - peripheral != peripheral_expected && - peripheral == kTopEarlgreyPlicPeripheralCsrng) { - dif_csrng_irq_t irq = (dif_csrng_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone); - - dif_csrng_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_csrng_irq_get_state(&csrng, &snapshot)); - CHECK(snapshot == (dif_csrng_irq_state_snapshot_t)(1 << irq), - "Only csrng IRQ %d expected to fire. Actual interrupt status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_csrng_irq_force(&csrng, irq, false)); - CHECK_DIF_OK(dif_csrng_irq_acknowledge(&csrng, irq)); + top_englishbreakfast_plic_peripheral_t peripheral = (top_englishbreakfast_plic_peripheral_t) + top_englishbreakfast_plic_interrupt_for_peripheral[plic_irq_id]; + if (false) { } else { CHECK(peripheral == peripheral_expected, "Interrupt from incorrect peripheral: exp = %d, obs = %d", @@ -365,58 +166,10 @@ void ottf_external_isr(uint32_t *exc_info) { switch (peripheral) { #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralAdcCtrlAon: { - dif_adc_ctrl_irq_t irq = (dif_adc_ctrl_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdAdcCtrlAonMatchDone); - CHECK(irq == adc_ctrl_irq_expected, - "Incorrect adc_ctrl_aon IRQ triggered: exp = %d, obs = %d", - adc_ctrl_irq_expected, irq); - adc_ctrl_irq_serviced = irq; - - dif_adc_ctrl_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_adc_ctrl_irq_get_state(&adc_ctrl_aon, &snapshot)); - CHECK(snapshot == (dif_adc_ctrl_irq_state_snapshot_t)(1 << irq), - "Only adc_ctrl_aon IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_adc_ctrl_irq_force(&adc_ctrl_aon, irq, false)); - CHECK_DIF_OK(dif_adc_ctrl_irq_acknowledge(&adc_ctrl_aon, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralAlertHandler: { - dif_alert_handler_irq_t irq = (dif_alert_handler_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdAlertHandlerClassa); - CHECK(irq == alert_handler_irq_expected, - "Incorrect alert_handler IRQ triggered: exp = %d, obs = %d", - alert_handler_irq_expected, irq); - alert_handler_irq_serviced = irq; - - dif_alert_handler_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_alert_handler_irq_get_state(&alert_handler, &snapshot)); - CHECK(snapshot == (dif_alert_handler_irq_state_snapshot_t)(1 << irq), - "Only alert_handler IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_alert_handler_irq_force(&alert_handler, irq, false)); - CHECK_DIF_OK(dif_alert_handler_irq_acknowledge(&alert_handler, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralAonTimerAon: { + case kTopEnglishbreakfastPlicPeripheralAonTimerAon: { dif_aon_timer_irq_t irq = (dif_aon_timer_irq_t)( plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdAonTimerAonWkupTimerExpired); + (dif_rv_plic_irq_id_t)kTopEnglishbreakfastPlicIrqIdAonTimerAonWkupTimerExpired); CHECK(irq == aon_timer_irq_expected, "Incorrect aon_timer_aon IRQ triggered: exp = %d, obs = %d", aon_timer_irq_expected, irq); @@ -436,113 +189,11 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralCsrng: { - dif_csrng_irq_t irq = (dif_csrng_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone); - // This special handling of CSRNG is because it is configured - // to constantly generate interrupts. There may be better ways - // to configure the entropy complex so it is less noisy. - // TODO(lowrisc/opentitan#20747) Adjust code once this is fixed. - if (kBootStage != kBootStageOwner) { - CHECK(irq == csrng_irq_expected, - "Incorrect csrng IRQ triggered: exp = %d, obs = %d", - csrng_irq_expected, irq); - } - csrng_irq_serviced = irq; - - dif_csrng_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_csrng_irq_get_state(&csrng, &snapshot)); - CHECK(snapshot == (dif_csrng_irq_state_snapshot_t)(1 << irq), - "Only csrng IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_csrng_irq_force(&csrng, irq, false)); - CHECK_DIF_OK(dif_csrng_irq_acknowledge(&csrng, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralEdn0: { - dif_edn_irq_t irq = (dif_edn_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone); - CHECK(irq == edn_irq_expected, - "Incorrect edn0 IRQ triggered: exp = %d, obs = %d", - edn_irq_expected, irq); - edn_irq_serviced = irq; - - dif_edn_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_edn_irq_get_state(&edn0, &snapshot)); - CHECK(snapshot == (dif_edn_irq_state_snapshot_t)(1 << irq), - "Only edn0 IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_edn_irq_force(&edn0, irq, false)); - CHECK_DIF_OK(dif_edn_irq_acknowledge(&edn0, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralEdn1: { - dif_edn_irq_t irq = (dif_edn_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone); - CHECK(irq == edn_irq_expected, - "Incorrect edn1 IRQ triggered: exp = %d, obs = %d", - edn_irq_expected, irq); - edn_irq_serviced = irq; - - dif_edn_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_edn_irq_get_state(&edn1, &snapshot)); - CHECK(snapshot == (dif_edn_irq_state_snapshot_t)(1 << irq), - "Only edn1 IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_edn_irq_force(&edn1, irq, false)); - CHECK_DIF_OK(dif_edn_irq_acknowledge(&edn1, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralEntropySrc: { - dif_entropy_src_irq_t irq = (dif_entropy_src_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid); - CHECK(irq == entropy_src_irq_expected, - "Incorrect entropy_src IRQ triggered: exp = %d, obs = %d", - entropy_src_irq_expected, irq); - entropy_src_irq_serviced = irq; - - dif_entropy_src_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_entropy_src_irq_get_state(&entropy_src, &snapshot)); - CHECK(snapshot == (dif_entropy_src_irq_state_snapshot_t)(1 << irq), - "Only entropy_src IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_entropy_src_irq_force(&entropy_src, irq, false)); - CHECK_DIF_OK(dif_entropy_src_irq_acknowledge(&entropy_src, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralFlashCtrl: { +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL + case kTopEnglishbreakfastPlicPeripheralFlashCtrl: { dif_flash_ctrl_irq_t irq = (dif_flash_ctrl_irq_t)( plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty); + (dif_rv_plic_irq_id_t)kTopEnglishbreakfastPlicIrqIdFlashCtrlProgEmpty); CHECK(irq == flash_ctrl_irq_expected, "Incorrect flash_ctrl IRQ triggered: exp = %d, obs = %d", flash_ctrl_irq_expected, irq); @@ -562,11 +213,11 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralGpio: { +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL + case kTopEnglishbreakfastPlicPeripheralGpio: { dif_gpio_irq_t irq = (dif_gpio_irq_t)( plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdGpioGpio0); + (dif_rv_plic_irq_id_t)kTopEnglishbreakfastPlicIrqIdGpioGpio0); CHECK(irq == gpio_irq_expected, "Incorrect gpio IRQ triggered: exp = %d, obs = %d", gpio_irq_expected, irq); @@ -586,506 +237,122 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralHmac: { - dif_hmac_irq_t irq = (dif_hmac_irq_t)( +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL + case kTopEnglishbreakfastPlicPeripheralPwrmgrAon: { + dif_pwrmgr_irq_t irq = (dif_pwrmgr_irq_t)( plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdHmacHmacDone); - CHECK(irq == hmac_irq_expected, - "Incorrect hmac IRQ triggered: exp = %d, obs = %d", - hmac_irq_expected, irq); - hmac_irq_serviced = irq; - - dif_hmac_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_hmac_irq_get_state(&hmac, &snapshot)); - CHECK(snapshot == (dif_hmac_irq_state_snapshot_t)(1 << irq), - "Only hmac IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_hmac_irq_force(&hmac, irq, false)); - CHECK_DIF_OK(dif_hmac_irq_acknowledge(&hmac, irq)); - break; - } -#endif + (dif_rv_plic_irq_id_t)kTopEnglishbreakfastPlicIrqIdPwrmgrAonWakeup); + CHECK(irq == pwrmgr_irq_expected, + "Incorrect pwrmgr_aon IRQ triggered: exp = %d, obs = %d", + pwrmgr_irq_expected, irq); + pwrmgr_irq_serviced = irq; -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralI2c0: { - dif_i2c_irq_t irq = (dif_i2c_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdI2c0FmtThreshold); - CHECK(irq == i2c_irq_expected, - "Incorrect i2c0 IRQ triggered: exp = %d, obs = %d", - i2c_irq_expected, irq); - i2c_irq_serviced = irq; - - dif_i2c_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_i2c_irq_get_state(&i2c0, &snapshot)); - CHECK(snapshot == (dif_i2c_irq_state_snapshot_t)(1 << irq), - "Only i2c0 IRQ %d expected to fire. Actual interrupt " + dif_pwrmgr_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_pwrmgr_irq_get_state(&pwrmgr_aon, &snapshot)); + CHECK(snapshot == (dif_pwrmgr_irq_state_snapshot_t)(1 << irq), + "Only pwrmgr_aon IRQ %d expected to fire. Actual interrupt " "status = %x", irq, snapshot); // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_i2c_irq_force(&i2c0, irq, false)); - CHECK_DIF_OK(dif_i2c_irq_acknowledge(&i2c0, irq)); + CHECK_DIF_OK(dif_pwrmgr_irq_force(&pwrmgr_aon, irq, false)); + CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge(&pwrmgr_aon, irq)); break; } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralI2c1: { - dif_i2c_irq_t irq = (dif_i2c_irq_t)( +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL + case kTopEnglishbreakfastPlicPeripheralSpiDevice: { + dif_spi_device_irq_t irq = (dif_spi_device_irq_t)( plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdI2c1FmtThreshold); - CHECK(irq == i2c_irq_expected, - "Incorrect i2c1 IRQ triggered: exp = %d, obs = %d", - i2c_irq_expected, irq); - i2c_irq_serviced = irq; - - dif_i2c_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_i2c_irq_get_state(&i2c1, &snapshot)); - CHECK(snapshot == (dif_i2c_irq_state_snapshot_t)(1 << irq), - "Only i2c1 IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_i2c_irq_force(&i2c1, irq, false)); - CHECK_DIF_OK(dif_i2c_irq_acknowledge(&i2c1, irq)); - break; - } -#endif + (dif_rv_plic_irq_id_t)kTopEnglishbreakfastPlicIrqIdSpiDeviceGenericRxFull); + CHECK(irq == spi_device_irq_expected, + "Incorrect spi_device IRQ triggered: exp = %d, obs = %d", + spi_device_irq_expected, irq); + spi_device_irq_serviced = irq; -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralI2c2: { - dif_i2c_irq_t irq = (dif_i2c_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdI2c2FmtThreshold); - CHECK(irq == i2c_irq_expected, - "Incorrect i2c2 IRQ triggered: exp = %d, obs = %d", - i2c_irq_expected, irq); - i2c_irq_serviced = irq; - - dif_i2c_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_i2c_irq_get_state(&i2c2, &snapshot)); - CHECK(snapshot == (dif_i2c_irq_state_snapshot_t)(1 << irq), - "Only i2c2 IRQ %d expected to fire. Actual interrupt " + dif_spi_device_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_spi_device_irq_get_state(&spi_device, &snapshot)); + CHECK(snapshot == (dif_spi_device_irq_state_snapshot_t)(1 << irq), + "Only spi_device IRQ %d expected to fire. Actual interrupt " "status = %x", irq, snapshot); // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_i2c_irq_force(&i2c2, irq, false)); - CHECK_DIF_OK(dif_i2c_irq_acknowledge(&i2c2, irq)); + CHECK_DIF_OK(dif_spi_device_irq_force(&spi_device, irq, false)); + CHECK_DIF_OK(dif_spi_device_irq_acknowledge(&spi_device, irq)); break; } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralKeymgr: { - dif_keymgr_irq_t irq = (dif_keymgr_irq_t)( +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL + case kTopEnglishbreakfastPlicPeripheralSpiHost0: { + dif_spi_host_irq_t irq = (dif_spi_host_irq_t)( plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdKeymgrOpDone); - CHECK(irq == keymgr_irq_expected, - "Incorrect keymgr IRQ triggered: exp = %d, obs = %d", - keymgr_irq_expected, irq); - keymgr_irq_serviced = irq; - - dif_keymgr_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_keymgr_irq_get_state(&keymgr, &snapshot)); - CHECK(snapshot == (dif_keymgr_irq_state_snapshot_t)(1 << irq), - "Only keymgr IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_keymgr_irq_force(&keymgr, irq, false)); - CHECK_DIF_OK(dif_keymgr_irq_acknowledge(&keymgr, irq)); - break; - } -#endif + (dif_rv_plic_irq_id_t)kTopEnglishbreakfastPlicIrqIdSpiHost0Error); + CHECK(irq == spi_host_irq_expected, + "Incorrect spi_host0 IRQ triggered: exp = %d, obs = %d", + spi_host_irq_expected, irq); + spi_host_irq_serviced = irq; -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralKmac: { - dif_kmac_irq_t irq = (dif_kmac_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdKmacKmacDone); - CHECK(irq == kmac_irq_expected, - "Incorrect kmac IRQ triggered: exp = %d, obs = %d", - kmac_irq_expected, irq); - kmac_irq_serviced = irq; - - dif_kmac_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_kmac_irq_get_state(&kmac, &snapshot)); - CHECK(snapshot == (dif_kmac_irq_state_snapshot_t)(1 << irq), - "Only kmac IRQ %d expected to fire. Actual interrupt " + dif_spi_host_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_spi_host_irq_get_state(&spi_host0, &snapshot)); + CHECK(snapshot == (dif_spi_host_irq_state_snapshot_t)(1 << irq), + "Only spi_host0 IRQ %d expected to fire. Actual interrupt " "status = %x", irq, snapshot); // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_kmac_irq_force(&kmac, irq, false)); - CHECK_DIF_OK(dif_kmac_irq_acknowledge(&kmac, irq)); + CHECK_DIF_OK(dif_spi_host_irq_force(&spi_host0, irq, false)); + CHECK_DIF_OK(dif_spi_host_irq_acknowledge(&spi_host0, irq)); break; } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralOtbn: { - dif_otbn_irq_t irq = (dif_otbn_irq_t)( +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL + case kTopEnglishbreakfastPlicPeripheralUart0: { + dif_uart_irq_t irq = (dif_uart_irq_t)( plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdOtbnDone); - CHECK(irq == otbn_irq_expected, - "Incorrect otbn IRQ triggered: exp = %d, obs = %d", - otbn_irq_expected, irq); - otbn_irq_serviced = irq; - - dif_otbn_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_otbn_irq_get_state(&otbn, &snapshot)); - CHECK(snapshot == (dif_otbn_irq_state_snapshot_t)(1 << irq), - "Only otbn IRQ %d expected to fire. Actual interrupt " + (dif_rv_plic_irq_id_t)kTopEnglishbreakfastPlicIrqIdUart0TxWatermark); + CHECK(irq == uart_irq_expected, + "Incorrect uart0 IRQ triggered: exp = %d, obs = %d", + uart_irq_expected, irq); + uart_irq_serviced = irq; + + dif_uart_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_uart_irq_get_state(&uart0, &snapshot)); + CHECK(snapshot == (dif_uart_irq_state_snapshot_t)(1 << irq), + "Only uart0 IRQ %d expected to fire. Actual interrupt " "status = %x", irq, snapshot); // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_otbn_irq_force(&otbn, irq, false)); - CHECK_DIF_OK(dif_otbn_irq_acknowledge(&otbn, irq)); + CHECK_DIF_OK(dif_uart_irq_force(&uart0, irq, false)); + CHECK_DIF_OK(dif_uart_irq_acknowledge(&uart0, irq)); break; } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralOtpCtrl: { - dif_otp_ctrl_irq_t irq = (dif_otp_ctrl_irq_t)( +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL + case kTopEnglishbreakfastPlicPeripheralUsbdev: { + dif_usbdev_irq_t irq = (dif_usbdev_irq_t)( plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone); - CHECK(irq == otp_ctrl_irq_expected, - "Incorrect otp_ctrl IRQ triggered: exp = %d, obs = %d", - otp_ctrl_irq_expected, irq); - otp_ctrl_irq_serviced = irq; - - dif_otp_ctrl_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_otp_ctrl_irq_get_state(&otp_ctrl, &snapshot)); - CHECK(snapshot == (dif_otp_ctrl_irq_state_snapshot_t)(1 << irq), - "Only otp_ctrl IRQ %d expected to fire. Actual interrupt " + (dif_rv_plic_irq_id_t)kTopEnglishbreakfastPlicIrqIdUsbdevPktReceived); + CHECK(irq == usbdev_irq_expected, + "Incorrect usbdev IRQ triggered: exp = %d, obs = %d", + usbdev_irq_expected, irq); + usbdev_irq_serviced = irq; + + dif_usbdev_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_usbdev_irq_get_state(&usbdev, &snapshot)); + CHECK(snapshot == (dif_usbdev_irq_state_snapshot_t)(1 << irq), + "Only usbdev IRQ %d expected to fire. Actual interrupt " "status = %x", irq, snapshot); // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_otp_ctrl_irq_force(&otp_ctrl, irq, false)); - CHECK_DIF_OK(dif_otp_ctrl_irq_acknowledge(&otp_ctrl, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralPattgen: { - dif_pattgen_irq_t irq = (dif_pattgen_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdPattgenDoneCh0); - CHECK(irq == pattgen_irq_expected, - "Incorrect pattgen IRQ triggered: exp = %d, obs = %d", - pattgen_irq_expected, irq); - pattgen_irq_serviced = irq; - - dif_pattgen_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_pattgen_irq_get_state(&pattgen, &snapshot)); - CHECK(snapshot == (dif_pattgen_irq_state_snapshot_t)(1 << irq), - "Only pattgen IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_pattgen_irq_force(&pattgen, irq, false)); - CHECK_DIF_OK(dif_pattgen_irq_acknowledge(&pattgen, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralPwrmgrAon: { - dif_pwrmgr_irq_t irq = (dif_pwrmgr_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdPwrmgrAonWakeup); - CHECK(irq == pwrmgr_irq_expected, - "Incorrect pwrmgr_aon IRQ triggered: exp = %d, obs = %d", - pwrmgr_irq_expected, irq); - pwrmgr_irq_serviced = irq; - - dif_pwrmgr_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_pwrmgr_irq_get_state(&pwrmgr_aon, &snapshot)); - CHECK(snapshot == (dif_pwrmgr_irq_state_snapshot_t)(1 << irq), - "Only pwrmgr_aon IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_pwrmgr_irq_force(&pwrmgr_aon, irq, false)); - CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge(&pwrmgr_aon, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralRvTimer: { - dif_rv_timer_irq_t irq = (dif_rv_timer_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdRvTimerTimerExpiredHart0Timer0); - CHECK(irq == rv_timer_irq_expected, - "Incorrect rv_timer IRQ triggered: exp = %d, obs = %d", - rv_timer_irq_expected, irq); - rv_timer_irq_serviced = irq; - - dif_rv_timer_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_rv_timer_irq_get_state(&rv_timer, kHart, &snapshot)); - CHECK(snapshot == (dif_rv_timer_irq_state_snapshot_t)(1 << irq), - "Only rv_timer IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_rv_timer_irq_force(&rv_timer, irq, false)); - CHECK_DIF_OK(dif_rv_timer_irq_acknowledge(&rv_timer, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralSensorCtrlAon: { - dif_sensor_ctrl_irq_t irq = (dif_sensor_ctrl_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdSensorCtrlAonIoStatusChange); - CHECK(irq == sensor_ctrl_irq_expected, - "Incorrect sensor_ctrl_aon IRQ triggered: exp = %d, obs = %d", - sensor_ctrl_irq_expected, irq); - sensor_ctrl_irq_serviced = irq; - - dif_sensor_ctrl_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_sensor_ctrl_irq_get_state(&sensor_ctrl_aon, &snapshot)); - CHECK(snapshot == (dif_sensor_ctrl_irq_state_snapshot_t)(1 << irq), - "Only sensor_ctrl_aon IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_sensor_ctrl_irq_force(&sensor_ctrl_aon, irq, false)); - CHECK_DIF_OK(dif_sensor_ctrl_irq_acknowledge(&sensor_ctrl_aon, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralSpiDevice: { - dif_spi_device_irq_t irq = (dif_spi_device_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdSpiDeviceGenericRxFull); - CHECK(irq == spi_device_irq_expected, - "Incorrect spi_device IRQ triggered: exp = %d, obs = %d", - spi_device_irq_expected, irq); - spi_device_irq_serviced = irq; - - dif_spi_device_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_spi_device_irq_get_state(&spi_device, &snapshot)); - CHECK(snapshot == (dif_spi_device_irq_state_snapshot_t)(1 << irq), - "Only spi_device IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_spi_device_irq_force(&spi_device, irq, false)); - CHECK_DIF_OK(dif_spi_device_irq_acknowledge(&spi_device, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralSpiHost0: { - dif_spi_host_irq_t irq = (dif_spi_host_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdSpiHost0Error); - CHECK(irq == spi_host_irq_expected, - "Incorrect spi_host0 IRQ triggered: exp = %d, obs = %d", - spi_host_irq_expected, irq); - spi_host_irq_serviced = irq; - - dif_spi_host_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_spi_host_irq_get_state(&spi_host0, &snapshot)); - CHECK(snapshot == (dif_spi_host_irq_state_snapshot_t)(1 << irq), - "Only spi_host0 IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_spi_host_irq_force(&spi_host0, irq, false)); - CHECK_DIF_OK(dif_spi_host_irq_acknowledge(&spi_host0, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralSpiHost1: { - dif_spi_host_irq_t irq = (dif_spi_host_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdSpiHost1Error); - CHECK(irq == spi_host_irq_expected, - "Incorrect spi_host1 IRQ triggered: exp = %d, obs = %d", - spi_host_irq_expected, irq); - spi_host_irq_serviced = irq; - - dif_spi_host_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_spi_host_irq_get_state(&spi_host1, &snapshot)); - CHECK(snapshot == (dif_spi_host_irq_state_snapshot_t)(1 << irq), - "Only spi_host1 IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_spi_host_irq_force(&spi_host1, irq, false)); - CHECK_DIF_OK(dif_spi_host_irq_acknowledge(&spi_host1, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralSysrstCtrlAon: { - dif_sysrst_ctrl_irq_t irq = (dif_sysrst_ctrl_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdSysrstCtrlAonEventDetected); - CHECK(irq == sysrst_ctrl_irq_expected, - "Incorrect sysrst_ctrl_aon IRQ triggered: exp = %d, obs = %d", - sysrst_ctrl_irq_expected, irq); - sysrst_ctrl_irq_serviced = irq; - - dif_sysrst_ctrl_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_sysrst_ctrl_irq_get_state(&sysrst_ctrl_aon, &snapshot)); - CHECK(snapshot == (dif_sysrst_ctrl_irq_state_snapshot_t)(1 << irq), - "Only sysrst_ctrl_aon IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_sysrst_ctrl_irq_force(&sysrst_ctrl_aon, irq, false)); - CHECK_DIF_OK(dif_sysrst_ctrl_irq_acknowledge(&sysrst_ctrl_aon, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralUart0: { - dif_uart_irq_t irq = (dif_uart_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdUart0TxWatermark); - CHECK(irq == uart_irq_expected, - "Incorrect uart0 IRQ triggered: exp = %d, obs = %d", - uart_irq_expected, irq); - uart_irq_serviced = irq; - - dif_uart_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_uart_irq_get_state(&uart0, &snapshot)); - CHECK(snapshot == (dif_uart_irq_state_snapshot_t)(1 << irq), - "Only uart0 IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_uart_irq_force(&uart0, irq, false)); - CHECK_DIF_OK(dif_uart_irq_acknowledge(&uart0, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralUart1: { - dif_uart_irq_t irq = (dif_uart_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdUart1TxWatermark); - CHECK(irq == uart_irq_expected, - "Incorrect uart1 IRQ triggered: exp = %d, obs = %d", - uart_irq_expected, irq); - uart_irq_serviced = irq; - - dif_uart_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_uart_irq_get_state(&uart1, &snapshot)); - CHECK(snapshot == (dif_uart_irq_state_snapshot_t)(1 << irq), - "Only uart1 IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_uart_irq_force(&uart1, irq, false)); - CHECK_DIF_OK(dif_uart_irq_acknowledge(&uart1, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralUart2: { - dif_uart_irq_t irq = (dif_uart_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdUart2TxWatermark); - CHECK(irq == uart_irq_expected, - "Incorrect uart2 IRQ triggered: exp = %d, obs = %d", - uart_irq_expected, irq); - uart_irq_serviced = irq; - - dif_uart_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_uart_irq_get_state(&uart2, &snapshot)); - CHECK(snapshot == (dif_uart_irq_state_snapshot_t)(1 << irq), - "Only uart2 IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_uart_irq_force(&uart2, irq, false)); - CHECK_DIF_OK(dif_uart_irq_acknowledge(&uart2, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralUart3: { - dif_uart_irq_t irq = (dif_uart_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdUart3TxWatermark); - CHECK(irq == uart_irq_expected, - "Incorrect uart3 IRQ triggered: exp = %d, obs = %d", - uart_irq_expected, irq); - uart_irq_serviced = irq; - - dif_uart_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_uart_irq_get_state(&uart3, &snapshot)); - CHECK(snapshot == (dif_uart_irq_state_snapshot_t)(1 << irq), - "Only uart3 IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_uart_irq_force(&uart3, irq, false)); - CHECK_DIF_OK(dif_uart_irq_acknowledge(&uart3, irq)); - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralUsbdev: { - dif_usbdev_irq_t irq = (dif_usbdev_irq_t)( - plic_irq_id - - (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdUsbdevPktReceived); - CHECK(irq == usbdev_irq_expected, - "Incorrect usbdev IRQ triggered: exp = %d, obs = %d", - usbdev_irq_expected, irq); - usbdev_irq_serviced = irq; - - dif_usbdev_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_usbdev_irq_get_state(&usbdev, &snapshot)); - CHECK(snapshot == (dif_usbdev_irq_state_snapshot_t)(1 << irq), - "Only usbdev IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - // TODO: Check Interrupt type then clear INTR_TEST if needed. - CHECK_DIF_OK(dif_usbdev_irq_force(&usbdev, irq, false)); - CHECK_DIF_OK(dif_usbdev_irq_acknowledge(&usbdev, irq)); + CHECK_DIF_OK(dif_usbdev_irq_force(&usbdev, irq, false)); + CHECK_DIF_OK(dif_usbdev_irq_acknowledge(&usbdev, irq)); break; } #endif @@ -1106,523 +373,151 @@ static void peripherals_init(void) { mmio_region_t base_addr; #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR); - CHECK_DIF_OK(dif_adc_ctrl_init(base_addr, &adc_ctrl_aon)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR); - CHECK_DIF_OK(dif_alert_handler_init(base_addr, &alert_handler)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_AON_TIMER_AON_BASE_ADDR); CHECK_DIF_OK(dif_aon_timer_init(base_addr, &aon_timer_aon)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_CSRNG_BASE_ADDR); - CHECK_DIF_OK(dif_csrng_init(base_addr, &csrng)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_EDN0_BASE_ADDR); - CHECK_DIF_OK(dif_edn_init(base_addr, &edn0)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_EDN1_BASE_ADDR); - CHECK_DIF_OK(dif_edn_init(base_addr, &edn1)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR); - CHECK_DIF_OK(dif_entropy_src_init(base_addr, &entropy_src)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR); - CHECK_DIF_OK(dif_flash_ctrl_init(base_addr, &flash_ctrl)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR); - CHECK_DIF_OK(dif_gpio_init(base_addr, &gpio)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_HMAC_BASE_ADDR); - CHECK_DIF_OK(dif_hmac_init(base_addr, &hmac)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C0_BASE_ADDR); - CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c0)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C1_BASE_ADDR); - CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c1)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C2_BASE_ADDR); - CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c2)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_KEYMGR_BASE_ADDR); - CHECK_DIF_OK(dif_keymgr_init(base_addr, &keymgr)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_KMAC_BASE_ADDR); - CHECK_DIF_OK(dif_kmac_init(base_addr, &kmac)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR); - CHECK_DIF_OK(dif_otbn_init(base_addr, &otbn)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR); - CHECK_DIF_OK(dif_otp_ctrl_init(base_addr, &otp_ctrl)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_PATTGEN_BASE_ADDR); - CHECK_DIF_OK(dif_pattgen_init(base_addr, &pattgen)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_PWRMGR_AON_BASE_ADDR); - CHECK_DIF_OK(dif_pwrmgr_init(base_addr, &pwrmgr_aon)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_RV_TIMER_BASE_ADDR); - CHECK_DIF_OK(dif_rv_timer_init(base_addr, &rv_timer)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR); - CHECK_DIF_OK(dif_sensor_ctrl_init(base_addr, &sensor_ctrl_aon)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_SPI_DEVICE_BASE_ADDR); - CHECK_DIF_OK(dif_spi_device_init(base_addr, &spi_device)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_SPI_HOST0_BASE_ADDR); - CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host0)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_SPI_HOST1_BASE_ADDR); - CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host1)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR); - CHECK_DIF_OK(dif_sysrst_ctrl_init(base_addr, &sysrst_ctrl_aon)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_UART0_BASE_ADDR); - CHECK_DIF_OK(dif_uart_init(base_addr, &uart0)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_UART1_BASE_ADDR); - CHECK_DIF_OK(dif_uart_init(base_addr, &uart1)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_UART2_BASE_ADDR); - CHECK_DIF_OK(dif_uart_init(base_addr, &uart2)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_UART3_BASE_ADDR); - CHECK_DIF_OK(dif_uart_init(base_addr, &uart3)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_USBDEV_BASE_ADDR); - CHECK_DIF_OK(dif_usbdev_init(base_addr, &usbdev)); -#endif - - base_addr = mmio_region_from_addr(TOP_EARLGREY_RV_PLIC_BASE_ADDR); - CHECK_DIF_OK(dif_rv_plic_init(base_addr, &plic)); -} - -/** - * Clears pending IRQs in all peripherals. - */ -static void peripheral_irqs_clear(void) { -#if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_adc_ctrl_irq_acknowledge_all(&adc_ctrl_aon)); -#endif - #if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_alert_handler_irq_acknowledge_all(&alert_handler)); + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_flash_ctrl_init(base_addr, &flash_ctrl)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_aon_timer_irq_acknowledge_all(&aon_timer_aon)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_csrng_irq_acknowledge_all(&csrng)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_edn_irq_acknowledge_all(&edn0)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_edn_irq_acknowledge_all(&edn1)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_entropy_src_irq_acknowledge_all(&entropy_src)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_flash_ctrl_irq_acknowledge_all(&flash_ctrl)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_gpio_irq_acknowledge_all(&gpio)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_hmac_irq_acknowledge_all(&hmac)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c0)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c1)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c2)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_keymgr_irq_acknowledge_all(&keymgr)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_kmac_irq_acknowledge_all(&kmac)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_otbn_irq_acknowledge_all(&otbn)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL - if (kBootStage != kBootStageOwner) { - CHECK_DIF_OK(dif_otp_ctrl_irq_acknowledge_all(&otp_ctrl)); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_pattgen_irq_acknowledge_all(&pattgen)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge_all(&pwrmgr_aon)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_rv_timer_irq_acknowledge_all(&rv_timer, kHart)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_sensor_ctrl_irq_acknowledge_all(&sensor_ctrl_aon)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_spi_device_irq_acknowledge_all(&spi_device)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_spi_host_irq_acknowledge_all(&spi_host0)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_spi_host_irq_acknowledge_all(&spi_host1)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_sysrst_ctrl_irq_acknowledge_all(&sysrst_ctrl_aon)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart0)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart1)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart2)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart3)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_usbdev_irq_acknowledge_all(&usbdev)); -#endif -} - -/** - * Enables all IRQs in all peripherals. - */ -static void peripheral_irqs_enable(void) { -#if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL - dif_adc_ctrl_irq_state_snapshot_t adc_ctrl_irqs = - (dif_adc_ctrl_irq_state_snapshot_t)UINT_MAX; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL - dif_alert_handler_irq_state_snapshot_t alert_handler_irqs = - (dif_alert_handler_irq_state_snapshot_t)UINT_MAX; + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_GPIO_BASE_ADDR); + CHECK_DIF_OK(dif_gpio_init(base_addr, &gpio)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL - dif_csrng_irq_state_snapshot_t csrng_irqs = - (dif_csrng_irq_state_snapshot_t)UINT_MAX; + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_PWRMGR_AON_BASE_ADDR); + CHECK_DIF_OK(dif_pwrmgr_init(base_addr, &pwrmgr_aon)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL - dif_edn_irq_state_snapshot_t edn_irqs = - (dif_edn_irq_state_snapshot_t)UINT_MAX; + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_SPI_DEVICE_BASE_ADDR); + CHECK_DIF_OK(dif_spi_device_init(base_addr, &spi_device)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL - dif_entropy_src_irq_state_snapshot_t entropy_src_irqs = - (dif_entropy_src_irq_state_snapshot_t)UINT_MAX; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL - dif_flash_ctrl_irq_state_snapshot_t flash_ctrl_irqs = - (dif_flash_ctrl_irq_state_snapshot_t)UINT_MAX; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL - dif_gpio_irq_state_snapshot_t gpio_irqs = - (dif_gpio_irq_state_snapshot_t)UINT_MAX; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL - dif_hmac_irq_state_snapshot_t hmac_irqs = - (dif_hmac_irq_state_snapshot_t)UINT_MAX; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - dif_i2c_irq_state_snapshot_t i2c_irqs = - (dif_i2c_irq_state_snapshot_t)UINT_MAX; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL - dif_keymgr_irq_state_snapshot_t keymgr_irqs = - (dif_keymgr_irq_state_snapshot_t)UINT_MAX; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL - dif_kmac_irq_state_snapshot_t kmac_irqs = - (dif_kmac_irq_state_snapshot_t)UINT_MAX; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - dif_otbn_irq_state_snapshot_t otbn_irqs = - (dif_otbn_irq_state_snapshot_t)UINT_MAX; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL - dif_otp_ctrl_irq_state_snapshot_t otp_ctrl_irqs = - (dif_otp_ctrl_irq_state_snapshot_t)UINT_MAX; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL - dif_pattgen_irq_state_snapshot_t pattgen_irqs = - (dif_pattgen_irq_state_snapshot_t)UINT_MAX; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL - dif_pwrmgr_irq_state_snapshot_t pwrmgr_irqs = - (dif_pwrmgr_irq_state_snapshot_t)UINT_MAX; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL - dif_rv_timer_irq_state_snapshot_t rv_timer_irqs = - (dif_rv_timer_irq_state_snapshot_t)UINT_MAX; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL - dif_sensor_ctrl_irq_state_snapshot_t sensor_ctrl_irqs = - (dif_sensor_ctrl_irq_state_snapshot_t)UINT_MAX; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL - dif_spi_device_irq_state_snapshot_t spi_device_irqs = - (dif_spi_device_irq_state_snapshot_t)UINT_MAX; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL - dif_spi_host_irq_state_snapshot_t spi_host_irqs = - (dif_spi_host_irq_state_snapshot_t)UINT_MAX; + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_SPI_HOST0_BASE_ADDR); + CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL - dif_sysrst_ctrl_irq_state_snapshot_t sysrst_ctrl_irqs = - (dif_sysrst_ctrl_irq_state_snapshot_t)UINT_MAX; +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_UART0_BASE_ADDR); + CHECK_DIF_OK(dif_uart_init(base_addr, &uart0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - dif_uart_irq_state_snapshot_t uart_irqs = - (dif_uart_irq_state_snapshot_t)UINT_MAX; +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_USBDEV_BASE_ADDR); + CHECK_DIF_OK(dif_usbdev_init(base_addr, &usbdev)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL - dif_usbdev_irq_state_snapshot_t usbdev_irqs = - (dif_usbdev_irq_state_snapshot_t)UINT_MAX; -#endif + base_addr = mmio_region_from_addr(TOP_ENGLISHBREAKFAST_RV_PLIC_BASE_ADDR); + CHECK_DIF_OK(dif_rv_plic_init(base_addr, &plic)); +} +/** + * Clears pending IRQs in all peripherals. + */ +static void peripheral_irqs_clear(void) { #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_adc_ctrl_irq_restore_all(&adc_ctrl_aon, &adc_ctrl_irqs)); + CHECK_DIF_OK(dif_aon_timer_irq_acknowledge_all(&aon_timer_aon)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_alert_handler_irq_restore_all(&alert_handler, &alert_handler_irqs)); + CHECK_DIF_OK(dif_flash_ctrl_irq_acknowledge_all(&flash_ctrl)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_csrng_irq_restore_all(&csrng, &csrng_irqs)); +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_gpio_irq_acknowledge_all(&gpio)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_edn_irq_restore_all(&edn0, &edn_irqs)); +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge_all(&pwrmgr_aon)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_edn_irq_restore_all(&edn1, &edn_irqs)); + CHECK_DIF_OK(dif_spi_device_irq_acknowledge_all(&spi_device)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_entropy_src_irq_restore_all(&entropy_src, &entropy_src_irqs)); + CHECK_DIF_OK(dif_spi_host_irq_acknowledge_all(&spi_host0)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_flash_ctrl_irq_restore_all(&flash_ctrl, &flash_ctrl_irqs)); + CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart0)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_gpio_irq_restore_all(&gpio, &gpio_irqs)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_hmac_irq_restore_all(&hmac, &hmac_irqs)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_i2c_irq_restore_all(&i2c0, &i2c_irqs)); + CHECK_DIF_OK(dif_usbdev_irq_acknowledge_all(&usbdev)); #endif +} -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_i2c_irq_restore_all(&i2c1, &i2c_irqs)); +/** + * Enables all IRQs in all peripherals. + */ +static void peripheral_irqs_enable(void) { +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL + dif_flash_ctrl_irq_state_snapshot_t flash_ctrl_irqs = + (dif_flash_ctrl_irq_state_snapshot_t)UINT_MAX; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_i2c_irq_restore_all(&i2c2, &i2c_irqs)); +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL + dif_gpio_irq_state_snapshot_t gpio_irqs = + (dif_gpio_irq_state_snapshot_t)UINT_MAX; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_keymgr_irq_restore_all(&keymgr, &keymgr_irqs)); +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL + dif_pwrmgr_irq_state_snapshot_t pwrmgr_irqs = + (dif_pwrmgr_irq_state_snapshot_t)UINT_MAX; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_kmac_irq_restore_all(&kmac, &kmac_irqs)); +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL + dif_spi_device_irq_state_snapshot_t spi_device_irqs = + (dif_spi_device_irq_state_snapshot_t)UINT_MAX; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_otbn_irq_restore_all(&otbn, &otbn_irqs)); +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL + dif_spi_host_irq_state_snapshot_t spi_host_irqs = + (dif_spi_host_irq_state_snapshot_t)UINT_MAX; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL - if (kBootStage != kBootStageOwner) { - CHECK_DIF_OK( - dif_otp_ctrl_irq_restore_all(&otp_ctrl, &otp_ctrl_irqs)); - } +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL + dif_uart_irq_state_snapshot_t uart_irqs = + (dif_uart_irq_state_snapshot_t)UINT_MAX; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_pattgen_irq_restore_all(&pattgen, &pattgen_irqs)); +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL + dif_usbdev_irq_state_snapshot_t usbdev_irqs = + (dif_usbdev_irq_state_snapshot_t)UINT_MAX; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK( - dif_pwrmgr_irq_restore_all(&pwrmgr_aon, &pwrmgr_irqs)); + dif_flash_ctrl_irq_restore_all(&flash_ctrl, &flash_ctrl_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK( - dif_rv_timer_irq_restore_all(&rv_timer, kHart, &rv_timer_irqs)); + dif_gpio_irq_restore_all(&gpio, &gpio_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK( - dif_sensor_ctrl_irq_restore_all(&sensor_ctrl_aon, &sensor_ctrl_irqs)); + dif_pwrmgr_irq_restore_all(&pwrmgr_aon, &pwrmgr_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK( dif_spi_device_irq_restore_all(&spi_device, &spi_device_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK( dif_spi_host_irq_restore_all(&spi_host0, &spi_host_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_spi_host_irq_restore_all(&spi_host1, &spi_host_irqs)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_sysrst_ctrl_irq_restore_all(&sysrst_ctrl_aon, &sysrst_ctrl_irqs)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL // lowrisc/opentitan#8656: Skip UART0 in non-DV setups due to interference // from the logging facility. if (kDeviceType == kDeviceSimDV) { @@ -1631,22 +526,7 @@ static void peripheral_irqs_enable(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_uart_irq_restore_all(&uart1, &uart_irqs)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_uart_irq_restore_all(&uart2, &uart_irqs)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK( - dif_uart_irq_restore_all(&uart3, &uart_irqs)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK( dif_usbdev_irq_restore_all(&usbdev, &usbdev_irqs)); #endif @@ -1663,43 +543,13 @@ static void peripheral_irqs_enable(void) { */ static void peripheral_irqs_trigger(void) { #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralAdcCtrlAon; - for (dif_adc_ctrl_irq_t irq = kDifAdcCtrlIrqMatchDone; - irq <= kDifAdcCtrlIrqMatchDone; ++irq) { - adc_ctrl_irq_expected = irq; - LOG_INFO("Triggering adc_ctrl_aon IRQ %d.", irq); - CHECK_DIF_OK(dif_adc_ctrl_irq_force(&adc_ctrl_aon, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(adc_ctrl_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from adc_ctrl_aon is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralAlertHandler; - for (dif_alert_handler_irq_t irq = kDifAlertHandlerIrqClassa; - irq <= kDifAlertHandlerIrqClassd; ++irq) { - alert_handler_irq_expected = irq; - LOG_INFO("Triggering alert_handler IRQ %d.", irq); - CHECK_DIF_OK(dif_alert_handler_irq_force(&alert_handler, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(alert_handler_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from alert_handler is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL // lowrisc/opentitan#8656: Skip UART0 in non-DV setups due to interference // from the logging facility. // aon_timer may generate a NMI instead of a PLIC IRQ depending on the ROM. // Since there are other tests covering this already, we just skip this for // non-DV setups. if (kDeviceType == kDeviceSimDV) { - peripheral_expected = kTopEarlgreyPlicPeripheralAonTimerAon; + peripheral_expected = kTopEnglishbreakfastPlicPeripheralAonTimerAon; for (dif_aon_timer_irq_t irq = kDifAonTimerIrqWkupTimerExpired; irq <= kDifAonTimerIrqWdogTimerBark; ++irq) { aon_timer_irq_expected = irq; @@ -1714,68 +564,8 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralCsrng; - for (dif_csrng_irq_t irq = kDifCsrngIrqCsCmdReqDone; - irq <= kDifCsrngIrqCsFatalErr; ++irq) { - csrng_irq_expected = irq; - LOG_INFO("Triggering csrng IRQ %d.", irq); - CHECK_DIF_OK(dif_csrng_irq_force(&csrng, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(csrng_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from csrng is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralEdn0; - for (dif_edn_irq_t irq = kDifEdnIrqEdnCmdReqDone; - irq <= kDifEdnIrqEdnFatalErr; ++irq) { - edn_irq_expected = irq; - LOG_INFO("Triggering edn0 IRQ %d.", irq); - CHECK_DIF_OK(dif_edn_irq_force(&edn0, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(edn_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from edn0 is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralEdn1; - for (dif_edn_irq_t irq = kDifEdnIrqEdnCmdReqDone; - irq <= kDifEdnIrqEdnFatalErr; ++irq) { - edn_irq_expected = irq; - LOG_INFO("Triggering edn1 IRQ %d.", irq); - CHECK_DIF_OK(dif_edn_irq_force(&edn1, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(edn_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from edn1 is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralEntropySrc; - for (dif_entropy_src_irq_t irq = kDifEntropySrcIrqEsEntropyValid; - irq <= kDifEntropySrcIrqEsFatalErr; ++irq) { - entropy_src_irq_expected = irq; - LOG_INFO("Triggering entropy_src IRQ %d.", irq); - CHECK_DIF_OK(dif_entropy_src_irq_force(&entropy_src, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(entropy_src_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from entropy_src is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralFlashCtrl; +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopEnglishbreakfastPlicPeripheralFlashCtrl; for (dif_flash_ctrl_irq_t irq = kDifFlashCtrlIrqProgEmpty; irq <= kDifFlashCtrlIrqCorrErr; ++irq) { flash_ctrl_irq_expected = irq; @@ -1789,8 +579,8 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralGpio; +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopEnglishbreakfastPlicPeripheralGpio; for (dif_gpio_irq_t irq = kDifGpioIrqGpio0; irq <= kDifGpioIrqGpio31; ++irq) { gpio_irq_expected = irq; @@ -1804,147 +594,8 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralHmac; - for (dif_hmac_irq_t irq = kDifHmacIrqHmacDone; - irq <= kDifHmacIrqHmacErr; ++irq) { - hmac_irq_expected = irq; - LOG_INFO("Triggering hmac IRQ %d.", irq); - CHECK_DIF_OK(dif_hmac_irq_force(&hmac, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(hmac_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from hmac is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralI2c0; - for (dif_i2c_irq_t irq = kDifI2cIrqFmtThreshold; - irq <= kDifI2cIrqHostTimeout; ++irq) { - i2c_irq_expected = irq; - LOG_INFO("Triggering i2c0 IRQ %d.", irq); - CHECK_DIF_OK(dif_i2c_irq_force(&i2c0, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(i2c_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from i2c0 is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralI2c1; - for (dif_i2c_irq_t irq = kDifI2cIrqFmtThreshold; - irq <= kDifI2cIrqHostTimeout; ++irq) { - i2c_irq_expected = irq; - LOG_INFO("Triggering i2c1 IRQ %d.", irq); - CHECK_DIF_OK(dif_i2c_irq_force(&i2c1, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(i2c_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from i2c1 is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralI2c2; - for (dif_i2c_irq_t irq = kDifI2cIrqFmtThreshold; - irq <= kDifI2cIrqHostTimeout; ++irq) { - i2c_irq_expected = irq; - LOG_INFO("Triggering i2c2 IRQ %d.", irq); - CHECK_DIF_OK(dif_i2c_irq_force(&i2c2, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(i2c_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from i2c2 is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralKeymgr; - for (dif_keymgr_irq_t irq = kDifKeymgrIrqOpDone; - irq <= kDifKeymgrIrqOpDone; ++irq) { - keymgr_irq_expected = irq; - LOG_INFO("Triggering keymgr IRQ %d.", irq); - CHECK_DIF_OK(dif_keymgr_irq_force(&keymgr, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(keymgr_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from keymgr is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralKmac; - for (dif_kmac_irq_t irq = kDifKmacIrqKmacDone; - irq <= kDifKmacIrqKmacErr; ++irq) { - kmac_irq_expected = irq; - LOG_INFO("Triggering kmac IRQ %d.", irq); - CHECK_DIF_OK(dif_kmac_irq_force(&kmac, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(kmac_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from kmac is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralOtbn; - for (dif_otbn_irq_t irq = kDifOtbnIrqDone; - irq <= kDifOtbnIrqDone; ++irq) { - otbn_irq_expected = irq; - LOG_INFO("Triggering otbn IRQ %d.", irq); - CHECK_DIF_OK(dif_otbn_irq_force(&otbn, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(otbn_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from otbn is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL - // Skip OTP_CTRL in boot stage owner since ROM_EXT configures all accesses - // to OTP_CTRL and AST to be illegal. - if (kBootStage != kBootStageOwner) { - peripheral_expected = kTopEarlgreyPlicPeripheralOtpCtrl; - for (dif_otp_ctrl_irq_t irq = kDifOtpCtrlIrqOtpOperationDone; - irq <= kDifOtpCtrlIrqOtpError; ++irq) { - otp_ctrl_irq_expected = irq; - LOG_INFO("Triggering otp_ctrl IRQ %d.", irq); - CHECK_DIF_OK(dif_otp_ctrl_irq_force(&otp_ctrl, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(otp_ctrl_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from otp_ctrl is serviced.", irq); - } - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralPattgen; - for (dif_pattgen_irq_t irq = kDifPattgenIrqDoneCh0; - irq <= kDifPattgenIrqDoneCh1; ++irq) { - pattgen_irq_expected = irq; - LOG_INFO("Triggering pattgen IRQ %d.", irq); - CHECK_DIF_OK(dif_pattgen_irq_force(&pattgen, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(pattgen_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from pattgen is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralPwrmgrAon; +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopEnglishbreakfastPlicPeripheralPwrmgrAon; for (dif_pwrmgr_irq_t irq = kDifPwrmgrIrqWakeup; irq <= kDifPwrmgrIrqWakeup; ++irq) { pwrmgr_irq_expected = irq; @@ -1958,38 +609,8 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralRvTimer; - for (dif_rv_timer_irq_t irq = kDifRvTimerIrqTimerExpiredHart0Timer0; - irq <= kDifRvTimerIrqTimerExpiredHart0Timer0; ++irq) { - rv_timer_irq_expected = irq; - LOG_INFO("Triggering rv_timer IRQ %d.", irq); - CHECK_DIF_OK(dif_rv_timer_irq_force(&rv_timer, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(rv_timer_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from rv_timer is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralSensorCtrlAon; - for (dif_sensor_ctrl_irq_t irq = kDifSensorCtrlIrqIoStatusChange; - irq <= kDifSensorCtrlIrqInitStatusChange; ++irq) { - sensor_ctrl_irq_expected = irq; - LOG_INFO("Triggering sensor_ctrl_aon IRQ %d.", irq); - CHECK_DIF_OK(dif_sensor_ctrl_irq_force(&sensor_ctrl_aon, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(sensor_ctrl_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from sensor_ctrl_aon is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralSpiDevice; +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopEnglishbreakfastPlicPeripheralSpiDevice; for (dif_spi_device_irq_t irq = kDifSpiDeviceIrqGenericRxFull; irq <= kDifSpiDeviceIrqTpmHeaderNotEmpty; ++irq) { spi_device_irq_expected = irq; @@ -2003,8 +624,8 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralSpiHost0; +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopEnglishbreakfastPlicPeripheralSpiHost0; for (dif_spi_host_irq_t irq = kDifSpiHostIrqError; irq <= kDifSpiHostIrqSpiEvent; ++irq) { spi_host_irq_expected = irq; @@ -2018,44 +639,14 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralSpiHost1; - for (dif_spi_host_irq_t irq = kDifSpiHostIrqError; - irq <= kDifSpiHostIrqSpiEvent; ++irq) { - spi_host_irq_expected = irq; - LOG_INFO("Triggering spi_host1 IRQ %d.", irq); - CHECK_DIF_OK(dif_spi_host_irq_force(&spi_host1, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(spi_host_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from spi_host1 is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralSysrstCtrlAon; - for (dif_sysrst_ctrl_irq_t irq = kDifSysrstCtrlIrqEventDetected; - irq <= kDifSysrstCtrlIrqEventDetected; ++irq) { - sysrst_ctrl_irq_expected = irq; - LOG_INFO("Triggering sysrst_ctrl_aon IRQ %d.", irq); - CHECK_DIF_OK(dif_sysrst_ctrl_irq_force(&sysrst_ctrl_aon, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(sysrst_ctrl_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from sysrst_ctrl_aon is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL // lowrisc/opentitan#8656: Skip UART0 in non-DV setups due to interference // from the logging facility. // aon_timer may generate a NMI instead of a PLIC IRQ depending on the ROM. // Since there are other tests covering this already, we just skip this for // non-DV setups. if (kDeviceType == kDeviceSimDV) { - peripheral_expected = kTopEarlgreyPlicPeripheralUart0; + peripheral_expected = kTopEnglishbreakfastPlicPeripheralUart0; for (dif_uart_irq_t irq = kDifUartIrqTxWatermark; irq <= kDifUartIrqRxParityErr; ++irq) { uart_irq_expected = irq; @@ -2070,53 +661,8 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralUart1; - for (dif_uart_irq_t irq = kDifUartIrqTxWatermark; - irq <= kDifUartIrqRxParityErr; ++irq) { - uart_irq_expected = irq; - LOG_INFO("Triggering uart1 IRQ %d.", irq); - CHECK_DIF_OK(dif_uart_irq_force(&uart1, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(uart_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from uart1 is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralUart2; - for (dif_uart_irq_t irq = kDifUartIrqTxWatermark; - irq <= kDifUartIrqRxParityErr; ++irq) { - uart_irq_expected = irq; - LOG_INFO("Triggering uart2 IRQ %d.", irq); - CHECK_DIF_OK(dif_uart_irq_force(&uart2, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(uart_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from uart2 is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralUart3; - for (dif_uart_irq_t irq = kDifUartIrqTxWatermark; - irq <= kDifUartIrqRxParityErr; ++irq) { - uart_irq_expected = irq; - LOG_INFO("Triggering uart3 IRQ %d.", irq); - CHECK_DIF_OK(dif_uart_irq_force(&uart3, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(uart_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from uart3 is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralUsbdev; +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopEnglishbreakfastPlicPeripheralUsbdev; for (dif_usbdev_irq_t irq = kDifUsbdevIrqPktReceived; irq <= kDifUsbdevIrqLinkOutErr; ++irq) { usbdev_irq_expected = irq; @@ -2150,7 +696,7 @@ bool test_main(void) { peripherals_init(); check_hart_id((uint32_t)kHart); rv_plic_testutils_irq_range_enable( - &plic, kHart, kTopEarlgreyPlicIrqIdNone + 1, kTopEarlgreyPlicIrqIdLast); + &plic, kHart, kTopEnglishbreakfastPlicIrqIdNone + 1, kTopEnglishbreakfastPlicIrqIdLast); peripheral_irqs_clear(); peripheral_irqs_enable(); peripheral_irqs_trigger(); diff --git a/util/topgen-fusesoc.py b/util/topgen-fusesoc.py index 61114341d8104e..a74482c973ec3d 100755 --- a/util/topgen-fusesoc.py +++ b/util/topgen-fusesoc.py @@ -125,7 +125,7 @@ def main(): 'lowrisc:constants:top_pkg', 'lowrisc:prim:util', 'lowrisc:ip:lc_ctrl_pkg', - 'lowrisc:ip:pwrmgr_pkg', + 'lowrisc:ip_interfaces:pwrmgr_pkg', # rstmgr 'lowrisc:prim:clock_mux2', # clkmgr