diff --git a/hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson b/hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson
index eaa6914aa799a3..111538b1ed4775 100644
--- a/hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson
+++ b/hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson
@@ -75,6 +75,7 @@
       features: ["I2C.MODE.HOST", "I2C.MODE.TARGET", "I2C.SPEED.STANDARD", "I2C.SPEED.FAST", "I2C.SPEED.FASTPLUS"]
       stage: V3
       si_stage: SV3
+      bazel: ["//sw/device/tests/pmod:i2c_host_fram_test"]
       tests: []
     }
     {
diff --git a/sw/device/tests/pmod/BUILD b/sw/device/tests/pmod/BUILD
index e9bed9626bf0e3..359ed11155bc53 100644
--- a/sw/device/tests/pmod/BUILD
+++ b/sw/device/tests/pmod/BUILD
@@ -4,8 +4,10 @@
 
 load(
     "//rules/opentitan:defs.bzl",
+    "EARLGREY_SILICON_OWNER_ROM_EXT_ENVS",
     "cw310_params",
     "opentitan_test",
+    "silicon_params",
 )
 
 package(default_visibility = ["//visibility:public"])
@@ -315,8 +317,14 @@ opentitan_test(
     ),
     exec_env = {
         "//hw/top_earlgrey:fpga_cw310_sival": None,
+        "//hw/top_earlgrey:silicon_owner_sival_rom_ext": "silicon_owner",
         "//hw/top_earlgrey:fpga_cw310_test_rom": None,
     },
+    silicon_owner = silicon_params(
+        tags = [
+            "pmod",
+        ],  # Requires the PMOD::BoB.
+    ),
     deps = [
         "//hw/top_earlgrey/sw/autogen:top_earlgrey",
         "//sw/device/lib/arch:device",
diff --git a/sw/device/tests/sival/BUILD b/sw/device/tests/sival/BUILD
index bd0d9872fa1c0f..66d8c14b7e4773 100644
--- a/sw/device/tests/sival/BUILD
+++ b/sw/device/tests/sival/BUILD
@@ -144,5 +144,6 @@ test_suite(
         "//sw/device/tests:sram_ctrl_sleep_sram_ret_contents_no_scramble_test",
         "//sw/device/tests:sram_ctrl_subword_access_test",
         "//sw/device/tests/autogen:alert_test",
+        "//sw/device/tests/pmod:i2c_host_fram_test",
     ],
 )