diff --git a/sw/device/tests/rstmgr_sw_rst_ctrl_test.c b/sw/device/tests/rstmgr_sw_rst_ctrl_test.c
index b2445aef47ee9c..afb3969f10f0d0 100644
--- a/sw/device/tests/rstmgr_sw_rst_ctrl_test.c
+++ b/sw/device/tests/rstmgr_sw_rst_ctrl_test.c
@@ -27,8 +27,9 @@ OTTF_DEFINE_TEST_CONFIG();
  *  RSTMGR SW_RST_CTRL Test
  *
  *  This test checks RSTMGR.SW_RST_CTRL_N[index] with peripheral devices.
- *  There are 7 RSTMGR.SW_RST_CTRL_N registers and each register
- *  controls peripheral reset as follows:
+ *  There are 8 RSTMGR.SW_RST_CTRL_N registers, one of which corresponds
+ *  to USB_AON, which has no software writeable CSRs, so it is not amenable
+ *  to this test. The other registers controls peripheral reset as follows:
  *
  * // index | device     |  test register |  reset value |  prgm value |
  * // ------------------------------------------------------------------
@@ -36,9 +37,10 @@ OTTF_DEFINE_TEST_CONFIG();
  * // 1     | SPI_HOST0  |  CONFIGOPTS    |  0x0         |  0x3210000
  * // 2     | SPI_HOST1  |  CONFIGOPTS    |  0x0         |  0x6540000
  * // 3     | USB        |  EP_OUT_ENABLE |  0x0         |  0xc3
- * // 4     | I2C0       |  TIMING0       |  0x0         |  0x8b00cfe
- * // 5     | I2C1       |  TIMING1       |  0x0         |  0x114010d8
- * // 6     | I2C2       |  TIMING2       |  0x0         |  0x19ec1595
+ * // 4     | USB_AON    |                |              |
+ * // 5     | I2C0       |  TIMING0       |  0x0         |  0x8b00cfe
+ * // 6     | I2C1       |  TIMING1       |  0x0         |  0x114010d8
+ * // 7     | I2C2       |  TIMING2       |  0x0         |  0x19ec1595
  *
  * 'test register' is a rw type register under each peripheral device.
  * During the test, these registers are programmed with arbitrary values. ('prgm