From c1835b676ca6f5c5526ba9fab303f36541c22230 Mon Sep 17 00:00:00 2001 From: Neeraj Upasani Date: Mon, 15 Apr 2024 15:41:52 -0700 Subject: [PATCH] [pwrmgr] Insert Interlock between External SoC Reset and Pwrmgr FSM 1. Internally generated reset request passed to SoC. 2. Create a sticky assertion internally to log request. Sticky flag cleared only upon external reset deassertion 3. SoC transfer this request to platform to assert external reset 4. External SoC reset deasserts after some time 5. Pwrmgr stays in FastPwrStateRstWait state until the external SoC reset deasserts. 6. Boot / reset sequence continues 7. Also fixes the external reset signal glitch filter to use the por reset, This is required to make sure that the external reset state does not self-reset once asserted & faithfully forwards that state to pwrmgr 8. Added some debug visibility signals for pwrmgr 9. Added temporary reset loop back path in pwrmgr tb to translate internal reset req from OT --> ext reset from SoC to OT. Needs a proper fix in testbench [extrst] Fixed chiplevel template for external reset loopback Signed-off-by: Neeraj Upasani --- hw/ip/pwrmgr/data/pwrmgr.hjson.tpl | 6 ++ hw/ip/pwrmgr/dv/tb.sv | 4 +- hw/ip/pwrmgr/rtl/pwrmgr.sv | 40 +++++++++++-- hw/ip/pwrmgr/rtl/pwrmgr_fsm.sv | 39 ++++++++++-- hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv | 10 ++++ .../data/autogen/top_darjeeling.gen.hjson | 47 ++++++++++++++- hw/top_darjeeling/data/top_darjeeling.hjson | 8 ++- .../dv/autogen/rstmgr_tgl_excl.cfg | 2 +- .../ip/pwrmgr/data/autogen/pwrmgr.hjson | 6 ++ .../rstmgr/dv/env/autogen/rstmgr_env_pkg.sv | 2 +- .../ip/rstmgr/rtl/autogen/rstmgr.sv | 60 +++++++++---------- .../ip/soc_proxy/data/soc_proxy.hjson | 2 +- .../ip/soc_proxy/rtl/soc_proxy.sv | 8 +-- .../rtl/autogen/chip_darjeeling_asic.sv | 4 +- .../rtl/autogen/chip_darjeeling_cw310.sv | 1 + .../rtl/autogen/top_darjeeling.sv | 4 +- .../data/autogen/top_earlgrey.gen.hjson | 20 +++++++ .../ip/pwrmgr/data/autogen/pwrmgr.hjson | 6 ++ .../rtl/autogen/chip_earlgrey_asic.sv | 1 + .../rtl/autogen/chip_earlgrey_cw310.sv | 1 + hw/top_earlgrey/rtl/autogen/top_earlgrey.sv | 1 + util/topgen/templates/chiplevel.sv.tpl | 4 +- 22 files changed, 221 insertions(+), 55 deletions(-) diff --git a/hw/ip/pwrmgr/data/pwrmgr.hjson.tpl b/hw/ip/pwrmgr/data/pwrmgr.hjson.tpl index 627be2cd9471ff..f66e8b108896a1 100644 --- a/hw/ip/pwrmgr/data/pwrmgr.hjson.tpl +++ b/hw/ip/pwrmgr/data/pwrmgr.hjson.tpl @@ -68,6 +68,12 @@ ], inter_signal_list: [ + { struct: "pwr_boot_status", + type: "uni", + name: "boot_status", + act: "req", + package: "pwrmgr_pkg", + }, { struct: "pwr_ast", type: "req_rsp", name: "pwr_ast", diff --git a/hw/ip/pwrmgr/dv/tb.sv b/hw/ip/pwrmgr/dv/tb.sv index 9fb11d5a7329c4..4eb9b7d85e0fc0 100644 --- a/hw/ip/pwrmgr/dv/tb.sv +++ b/hw/ip/pwrmgr/dv/tb.sv @@ -19,6 +19,7 @@ module tb; wire clk_slow, rst_slow_n; wire devmode; wire [NUM_MAX_INTERRUPTS-1:0] interrupts; + wire int_reset_req; // interfaces clk_rst_if clk_rst_if ( @@ -49,6 +50,7 @@ module tb; ); assign interrupts[0] = pwrmgr_if.intr_wakeup; + assign int_reset_req = tb.dut.light_reset_req ; pwrmgr_if pwrmgr_if ( .clk, @@ -97,7 +99,7 @@ module tb; .fetch_en_o(pwrmgr_if.fetch_en), .wakeups_i (pwrmgr_if.wakeups_i), - .rstreqs_i (pwrmgr_if.rstreqs_i), + .rstreqs_i ({int_reset_req,pwrmgr_if.rstreqs_i[0]}), .ndmreset_req_i(pwrmgr_if.cpu_i.ndmreset_req), .lc_dft_en_i (pwrmgr_if.lc_dft_en), diff --git a/hw/ip/pwrmgr/rtl/pwrmgr.sv b/hw/ip/pwrmgr/rtl/pwrmgr.sv index 2ff4b2c52d6c28..39af3bee3ea8fd 100644 --- a/hw/ip/pwrmgr/rtl/pwrmgr.sv +++ b/hw/ip/pwrmgr/rtl/pwrmgr.sv @@ -59,12 +59,13 @@ module pwrmgr input pwr_cpu_t pwr_cpu_i, // SEC_CM: LC_CTRL.INTERSIG.MUBI output lc_ctrl_pkg::lc_tx_t fetch_en_o, - input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, - input lc_ctrl_pkg::lc_tx_t lc_dft_en_i, + input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, + input lc_ctrl_pkg::lc_tx_t lc_dft_en_i, + output pwr_boot_status_t boot_status_o, // peripherals wakeup and reset requests - input [NumWkups-1:0] wakeups_i, - input [NumRstReqs-1:0] rstreqs_i, + input [NumWkups-1:0] wakeups_i, + input [NumRstReqs-1:0] rstreqs_i, // cpu related inputs input ndmreset_req_i, @@ -88,6 +89,11 @@ module pwrmgr output intr_wakeup_o ); + + logic internal_reset_req; + logic strap_sampled; + logic ext_reset_req; + //////////////////////////////////////////////////// // Input handling // //////////////////////////////////////////////////// @@ -504,6 +510,19 @@ module pwrmgr {NumIntRstReqs{1'b1}}, slow_reset_en}; + assign internal_reset_req =|( + slow_peri_reqs.rstreqs & + {{NumSwRstReq{1'b1}}, // SW driven reset + {NumDebugRstReqs{1'b1}}, // debugger reset + {NumIntRstReqs{1'b1}}, // {ESC reset, slow_fsm} + // exclude the external async reset + {1'b0,slow_reset_en[0]} + } + ); + assign ext_reset_req = slow_peri_reqs.rstreqs[NumRstReqs-1] ; // bit1 is ext rst + // Do not mask. + // Always want to propagate + for (genvar i = 0; i < NumWkups; i++) begin : gen_wakeup_status assign hw2reg.wake_status[i].de = 1'b1; assign hw2reg.wake_status[i].d = peri_reqs_masked.wakeups[i]; @@ -602,6 +621,8 @@ module pwrmgr .fall_through_o (low_power_fall_through), .abort_o (low_power_abort), .clr_hint_o (clr_hint), + .light_rst_req_i (internal_reset_req), + .ext_reset_req_i (ext_reset_req), // rstmgr .pwr_rst_o (pwr_rst_o), @@ -635,6 +656,7 @@ module pwrmgr // pinmux and other peripherals .strap_o, + .strap_sampled_o (strap_sampled), // to debug monitoring logic .low_power_o ); @@ -685,6 +707,16 @@ module pwrmgr .intr_o (intr_wakeup_o) ); + //////////////////////////////////////////////////// + // Routing sstaus signal outputs for monitoring + //////////////////////////////////////////////////// + assign boot_status_o.cpu_fetch_en = fetch_en_o; + assign boot_status_o.rom_ctrl_status = rom_ctrl_i; + assign boot_status_o.lc_done = pwr_lc_i.lc_done; + assign boot_status_o.otp_done = otp_rsp.otp_done; + assign boot_status_o.clk_status = pwr_clk_i; + assign boot_status_o.light_reset_req = internal_reset_req; + assign boot_status_o.strapSampled = strap_sampled; //////////////////////////// /// Assertions diff --git a/hw/ip/pwrmgr/rtl/pwrmgr_fsm.sv b/hw/ip/pwrmgr/rtl/pwrmgr_fsm.sv index 2bbc5bb975eb6f..e91f32f786fb19 100644 --- a/hw/ip/pwrmgr/rtl/pwrmgr_fsm.sv +++ b/hw/ip/pwrmgr/rtl/pwrmgr_fsm.sv @@ -33,6 +33,9 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( output logic abort_o, output logic clr_hint_o, output logic clr_cfg_lock_o, + input logic light_rst_req_i, // internally generated reset request. + // Send to platform to assert reset + input logic ext_reset_req_i, // Internal Req held until ext reset deasserts // rstmgr output pwr_rst_req_t pwr_rst_o, @@ -63,6 +66,7 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( // pinmux output logic strap_o, + output logic strap_sampled_o, output logic low_power_o, // processing elements @@ -103,7 +107,7 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( // strap sample should only happen on cold boot or when the // the system goes through a reset cycle - logic strap_sampled; + // [output] logic strap_sampled; // disable processing element fetching lc_ctrl_pkg::lc_tx_t fetch_en_q, fetch_en_d; @@ -118,6 +122,8 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( logic otp_init; logic lc_init; logic low_power_q, low_power_d; + logic ext_rst_req_d, ext_rst_req_q; + logic light_rst_req_q; assign pd_n_rsts_asserted = pwr_rst_i.rst_lc_src_n[PowerDomains-1:OffDomainSelStart] == '0 & pwr_rst_i.rst_sys_src_n[PowerDomains-1:OffDomainSelStart] == '0; @@ -153,6 +159,24 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( assign reset_valid = reset_cause_q == LowPwrEntry ? main_pd_ni | pd_n_rsts_asserted : reset_cause_q == HwReq ? all_rsts_asserted : 1'b0; + assign ext_rst_req_d = ext_reset_req_i; + + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + light_rst_req_q <= 0; + ext_rst_req_q <= 0; + end else begin + ext_rst_req_q <= ext_rst_req_d; + if(light_rst_req_q && !ext_rst_req_d && ext_rst_req_q) begin + light_rst_req_q <= '0; + end else if (light_rst_req_i) begin + light_rst_req_q <= 1'b1; + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin ack_pwrup_q <= 1'b0; @@ -180,11 +204,11 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin - strap_sampled <= 1'b0; + strap_sampled_o <= 1'b0; end else if (&rst_sys_req_q) begin - strap_sampled <= 1'b0; + strap_sampled_o <= 1'b0; end else if (strap_o) begin - strap_sampled <= 1'b1; + strap_sampled_o <= 1'b1; end end @@ -338,7 +362,7 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( end FastPwrStateStrap: begin - strap_o = ~strap_sampled; + strap_o = ~strap_sampled_o; state_d = FastPwrStateRomCheckDone; end @@ -471,7 +495,10 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( // cleared before proceeding. This also implies if the system is under a persistent // glitch, or if someone just turned off the power before pwrmgr turns it off itself, // we will stay stuck here and perpetually hold the system in reset. - if (reset_valid && !reset_reqs_i[ResetMainPwrIdx]) begin + // NumRstReqs-1 is the External SoC reset request. + // Need to hold in reset until external reset deasserts (i.e. light_rst_req_q goes low) + if (reset_valid && !reset_reqs_i[ResetMainPwrIdx] + && !light_rst_req_q ) begin state_d = FastPwrStateLowPower; end end diff --git a/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv b/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv index c86e8fb4959da3..0c4597d856f112 100644 --- a/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv +++ b/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv @@ -155,6 +155,16 @@ package pwrmgr_pkg; logic ndmreset_req; } pwrmgr_cpu_t; + typedef struct packed { + lc_ctrl_pkg::lc_tx_t cpu_fetch_en; + rom_ctrl_pkg::pwrmgr_data_t [pwrmgr_reg_pkg::NumRomInputs-1:0] rom_ctrl_status; + logic lc_done; + logic otp_done; + logic strapSampled; + logic light_reset_req; + pwr_clk_rsp_t clk_status; + } pwr_boot_status_t; + // exported resets // default value for pwrmgr_ast_rsp_t (for dangling ports) diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson index 16728c62de0d87..2b1a57508edeee 100644 --- a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson @@ -266,6 +266,7 @@ domains: [ Aon + "0" ] shadowed: false sw: false @@ -310,7 +311,6 @@ domains: [ Aon - "0" ] shadowed: false sw: false @@ -2112,6 +2112,20 @@ param_list: [] inter_signal_list: [ + { + name: boot_status + struct: pwr_boot_status + package: pwrmgr_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + external: true + top_signame: pwrmgr_boot_status + conn_type: false + index: -1 + } { name: pwr_ast struct: pwr_ast @@ -3687,9 +3701,9 @@ name: lc domain: "0" } - rst_aon_ni: + rst_por_ni: { - name: lc_aon + name: por_io_div4 domain: "0" } } @@ -9604,6 +9618,7 @@ ast.ram_1p_cfg: ram_1p_cfg ast.spi_ram_2p_cfg: spi_ram_2p_cfg ast.rom_cfg: rom_cfg + pwrmgr_aon.boot_status: pwrmgr_boot_status clkmgr_aon.jitter_en: clk_main_jitter_en clkmgr_aon.io_clk_byp_req: io_clk_byp_req clkmgr_aon.io_clk_byp_ack: io_clk_byp_ack @@ -18416,6 +18431,20 @@ top_signame: spi_host0_tl index: -1 } + { + name: boot_status + struct: pwr_boot_status + package: pwrmgr_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + external: true + top_signame: pwrmgr_boot_status + conn_type: false + index: -1 + } { name: pwr_ast struct: pwr_ast @@ -23530,6 +23559,18 @@ index: -1 netname: ast_rom_cfg } + { + package: pwrmgr_pkg + struct: pwr_boot_status + signame: pwrmgr_boot_status_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: pwrmgr_boot_status + } { package: prim_mubi_pkg struct: mubi4 diff --git a/hw/top_darjeeling/data/top_darjeeling.hjson b/hw/top_darjeeling/data/top_darjeeling.hjson index 3893f223720971..454b95f05d86de 100644 --- a/hw/top_darjeeling/data/top_darjeeling.hjson +++ b/hw/top_darjeeling/data/top_darjeeling.hjson @@ -510,7 +510,12 @@ type: "soc_proxy", clock_srcs: {clk_i: "main", clk_aon_i: "aon"}, clock_group: "infra", - reset_connections: {rst_ni: "lc", rst_aon_ni: "lc_aon"}, + reset_connections: { + rst_ni: "lc", + rst_por_ni: "por_io_div4" //{ + // name: "por_io_div4" + // }, + } base_addrs: { core: {hart: "0x22030000"}, ctn: {hart: "0x40000000"}, @@ -1214,6 +1219,7 @@ 'ast.ram_1p_cfg' : 'ram_1p_cfg', 'ast.spi_ram_2p_cfg' : 'spi_ram_2p_cfg', 'ast.rom_cfg' : 'rom_cfg', + 'pwrmgr_aon.boot_status' : 'pwrmgr_boot_status', 'clkmgr_aon.jitter_en' : 'clk_main_jitter_en', 'clkmgr_aon.io_clk_byp_req' : 'io_clk_byp_req', 'clkmgr_aon.io_clk_byp_ack' : 'io_clk_byp_ack', diff --git a/hw/top_darjeeling/dv/autogen/rstmgr_tgl_excl.cfg b/hw/top_darjeeling/dv/autogen/rstmgr_tgl_excl.cfg index d4763e5384aa21..95062639e48a88 100644 --- a/hw/top_darjeeling/dv/autogen/rstmgr_tgl_excl.cfg +++ b/hw/top_darjeeling/dv/autogen/rstmgr_tgl_excl.cfg @@ -18,7 +18,7 @@ -node tb.dut*.u_rstmgr_aon.resets_o.rst_por_n[1] -node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_n[1] -node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_div2_n[1] --node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_div4_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_aon_n[1] -node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_io_div2_n[1] -node tb.dut*.u_rstmgr_aon.resets_o.rst_sys_n[0] -node tb.dut*.u_rstmgr_aon.resets_o.rst_sys_io_div4_n[1] diff --git a/hw/top_darjeeling/ip/pwrmgr/data/autogen/pwrmgr.hjson b/hw/top_darjeeling/ip/pwrmgr/data/autogen/pwrmgr.hjson index cf513b52497143..97f2b3ad1c39a7 100644 --- a/hw/top_darjeeling/ip/pwrmgr/data/autogen/pwrmgr.hjson +++ b/hw/top_darjeeling/ip/pwrmgr/data/autogen/pwrmgr.hjson @@ -69,6 +69,12 @@ ], inter_signal_list: [ + { struct: "pwr_boot_status", + type: "uni", + name: "boot_status", + act: "req", + package: "pwrmgr_pkg", + }, { struct: "pwr_ast", type: "req_rsp", name: "pwr_ast", diff --git a/hw/top_darjeeling/ip/rstmgr/dv/env/autogen/rstmgr_env_pkg.sv b/hw/top_darjeeling/ip/rstmgr/dv/env/autogen/rstmgr_env_pkg.sv index 6923aeceddde00..85212d0e7e9f5b 100644 --- a/hw/top_darjeeling/ip/rstmgr/dv/env/autogen/rstmgr_env_pkg.sv +++ b/hw/top_darjeeling/ip/rstmgr/dv/env/autogen/rstmgr_env_pkg.sv @@ -40,6 +40,7 @@ package rstmgr_env_pkg; "u_daon_por_io", "u_daon_por_io_div2", "u_daon_por_io_div4", + "u_d0_por_io_div4", "u_daon_por_usb", "u_d0_por_usb", "u_d0_lc", @@ -47,7 +48,6 @@ package rstmgr_env_pkg; "u_daon_lc", "u_daon_lc_shadowed", "u_daon_lc_aon", - "u_d0_lc_aon", "u_daon_lc_io", "u_d0_lc_io", "u_daon_lc_io_div2", diff --git a/hw/top_darjeeling/ip/rstmgr/rtl/autogen/rstmgr.sv b/hw/top_darjeeling/ip/rstmgr/rtl/autogen/rstmgr.sv index d4ea11bcef2ab8..345f3ebca8f89e 100644 --- a/hw/top_darjeeling/ip/rstmgr/rtl/autogen/rstmgr.sv +++ b/hw/top_darjeeling/ip/rstmgr/rtl/autogen/rstmgr.sv @@ -397,7 +397,7 @@ module rstmgr assign shadow_fsm_errs[2] = '0; // Generating resets for por_io_div4 - // Power Domains: ['Aon'] + // Power Domains: ['Aon', '0'] // Shadowed: False rstmgr_leaf_rst #( .SecCheck(SecCheck), @@ -423,10 +423,30 @@ module rstmgr u_daon_por_io_div4.gen_rst_chk.u_rst_chk.u_state_regs, alert_tx_o[0]) end - assign resets_o.rst_por_io_div4_n[Domain0Sel] = '0; - assign cnsty_chk_errs[3][Domain0Sel] = '0; - assign fsm_errs[3][Domain0Sel] = '0; - assign rst_en_o.por_io_div4[Domain0Sel] = MuBi4True; + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_d0_por_io_div4 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_por_aon_n[Domain0Sel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.por_io_div4[Domain0Sel]), + .leaf_rst_o(resets_o.rst_por_io_div4_n[Domain0Sel]), + .err_o(cnsty_chk_errs[3][Domain0Sel]), + .fsm_err_o(fsm_errs[3][Domain0Sel]) + ); + + if (SecCheck) begin : gen_d0_por_io_div4_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + D0PorIoDiv4FsmCheck_A, + u_d0_por_io_div4.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end assign shadow_cnsty_chk_errs[3] = '0; assign shadow_fsm_errs[3] = '0; @@ -585,7 +605,7 @@ module rstmgr end // Generating resets for lc_aon - // Power Domains: ['Aon', '0'] + // Power Domains: ['Aon'] // Shadowed: False rstmgr_leaf_rst #( .SecCheck(SecCheck), @@ -611,30 +631,10 @@ module rstmgr u_daon_lc_aon.gen_rst_chk.u_rst_chk.u_state_regs, alert_tx_o[0]) end - rstmgr_leaf_rst #( - .SecCheck(SecCheck), - .SecMaxSyncDelay(SecMaxSyncDelay), - .SwRstReq(1'b0) - ) u_d0_lc_aon ( - .clk_i, - .rst_ni, - .leaf_clk_i(clk_aon_i), - .parent_rst_ni(rst_lc_src_n[Domain0Sel]), - .sw_rst_req_ni(1'b1), - .scan_rst_ni, - .scanmode_i, - .rst_en_o(rst_en_o.lc_aon[Domain0Sel]), - .leaf_rst_o(resets_o.rst_lc_aon_n[Domain0Sel]), - .err_o(cnsty_chk_errs[6][Domain0Sel]), - .fsm_err_o(fsm_errs[6][Domain0Sel]) - ); - - if (SecCheck) begin : gen_d0_lc_aon_assert - `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( - D0LcAonFsmCheck_A, - u_d0_lc_aon.gen_rst_chk.u_rst_chk.u_state_regs, - alert_tx_o[0]) - end + assign resets_o.rst_lc_aon_n[Domain0Sel] = '0; + assign cnsty_chk_errs[6][Domain0Sel] = '0; + assign fsm_errs[6][Domain0Sel] = '0; + assign rst_en_o.lc_aon[Domain0Sel] = MuBi4True; assign shadow_cnsty_chk_errs[6] = '0; assign shadow_fsm_errs[6] = '0; diff --git a/hw/top_darjeeling/ip/soc_proxy/data/soc_proxy.hjson b/hw/top_darjeeling/ip/soc_proxy/data/soc_proxy.hjson index e1d97d87177f80..5ed02a0438df16 100644 --- a/hw/top_darjeeling/ip/soc_proxy/data/soc_proxy.hjson +++ b/hw/top_darjeeling/ip/soc_proxy/data/soc_proxy.hjson @@ -33,7 +33,7 @@ clocking: [ { clock: "clk_i", reset: "rst_ni", primary: true } - { clock: "clk_aon_i", reset: "rst_aon_ni" } + { clock: "clk_aon_i", reset: "rst_por_ni" } ] bus_interfaces: [ diff --git a/hw/top_darjeeling/ip/soc_proxy/rtl/soc_proxy.sv b/hw/top_darjeeling/ip/soc_proxy/rtl/soc_proxy.sv index c8fb7eb1636552..cf63a793843b1c 100644 --- a/hw/top_darjeeling/ip/soc_proxy/rtl/soc_proxy.sv +++ b/hw/top_darjeeling/ip/soc_proxy/rtl/soc_proxy.sv @@ -15,7 +15,7 @@ module soc_proxy input logic clk_i, input logic rst_ni, input logic clk_aon_i, - input logic rst_aon_ni, + input logic rst_por_ni, input tlul_pkg::tl_h2d_t core_tl_i, output tlul_pkg::tl_d2h_t core_tl_o, @@ -373,7 +373,7 @@ module soc_proxy .Width(1) ) u_prim_flop_2sync_soc_wkup ( .clk_i (clk_aon_i), - .rst_ni (rst_aon_ni), + .rst_ni (rst_por_ni), .d_i (soc_wkup_async_i), .q_o (wkup_external_req_o) ); @@ -388,7 +388,7 @@ module soc_proxy .Cycles(3) ) u_prim_filter_wkup ( .clk_i (clk_aon_i), - .rst_ni (rst_aon_ni), + .rst_ni (rst_por_ni), .enable_i (1'b1), .filter_i (async_wkup), .filter_o (wkup_internal_req_o) @@ -400,7 +400,7 @@ module soc_proxy .Cycles(4) ) u_prim_filter_soc_rst_req ( .clk_i (clk_aon_i), - .rst_ni (rst_aon_ni), + .rst_ni (rst_por_ni), .enable_i (1'b1), .filter_i (soc_rst_req_async_i), .filter_o (rst_req_external_o) diff --git a/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv index 9918f78ad39c22..840beb88f33260 100644 --- a/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv +++ b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv @@ -1035,6 +1035,7 @@ module chip_darjeeling_asic #( // pwrmgr interface pwrmgr_pkg::pwr_ast_req_t base_ast_pwr; pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status; // assorted ast status ast_pkg::ast_pwst_t ast_pwst; @@ -1556,13 +1557,14 @@ module chip_darjeeling_asic #( .dma_ctn_tl_d2h_i ( ctn_tl_d2h[1] ), .mbx_tl_req_i ( tlul_pkg::TL_H2D_DEFAULT ), .mbx_tl_rsp_o ( ), + .pwrmgr_boot_status_o ( pwrmgr_boot_status ), .soc_fatal_alert_req_i ( soc_fatal_alert_req ), .soc_fatal_alert_rsp_o ( ), .soc_recov_alert_req_i ( soc_recov_alert_req ), .soc_recov_alert_rsp_o ( ), .soc_intr_async_i ( '0 ), .soc_wkup_async_i ( 1'b0 ), - .soc_rst_req_async_i ( 1'b0 ), + .soc_rst_req_async_i ( pwrmgr_boot_status.light_reset_req), // FIXME: Needs better loopback fix .soc_lsio_trigger_i ( '0 ), .entropy_src_hw_if_req_o ( entropy_src_hw_if_req ), .entropy_src_hw_if_rsp_i ( entropy_src_hw_if_rsp ), diff --git a/hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv index 3178a740b4ddf9..4f221c7f94a9a4 100644 --- a/hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv +++ b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv @@ -875,6 +875,7 @@ module chip_darjeeling_cw310 #( // pwrmgr interface pwrmgr_pkg::pwr_ast_req_t base_ast_pwr; pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status; // assorted ast status ast_pkg::ast_pwst_t ast_pwst; diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv index 4c5ea9885b9476..67d086974e4d33 100644 --- a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv @@ -148,6 +148,7 @@ module top_darjeeling #( input prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg_i, input prim_ram_2p_pkg::ram_2p_cfg_t spi_ram_2p_cfg_i, input prim_rom_pkg::rom_cfg_t rom_cfg_i, + output pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status_o, output prim_mubi_pkg::mubi4_t clk_main_jitter_en_o, output prim_mubi_pkg::mubi4_t io_clk_byp_req_o, input prim_mubi_pkg::mubi4_t io_clk_byp_ack_i, @@ -1303,6 +1304,7 @@ module top_darjeeling #( .alert_rx_i ( alert_rx[14:14] ), // Inter-module signals + .boot_status_o(pwrmgr_boot_status_o), .pwr_ast_o(pwrmgr_ast_req_o), .pwr_ast_i(pwrmgr_ast_rsp_i), .pwr_rst_o(pwrmgr_aon_pwr_rst_req), @@ -1623,7 +1625,7 @@ module top_darjeeling #( .clk_i (clkmgr_aon_clocks.clk_main_infra), .clk_aon_i (clkmgr_aon_clocks.clk_aon_infra), .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), - .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::Domain0Sel]) + .rst_por_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::Domain0Sel]) ); sram_ctrl #( .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:52]), diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index d6679910b29571..b8be1e6dd658fd 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -2876,6 +2876,16 @@ param_list: [] inter_signal_list: [ + { + name: boot_status + struct: pwr_boot_status + package: pwrmgr_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + index: -1 + } { name: pwr_ast struct: pwr_ast @@ -17147,6 +17157,16 @@ top_signame: usbdev_tl index: -1 } + { + name: boot_status + struct: pwr_boot_status + package: pwrmgr_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + index: -1 + } { name: pwr_ast struct: pwr_ast diff --git a/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson b/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson index f58eb4ce303334..4ee06b63fa3598 100644 --- a/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson +++ b/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson @@ -69,6 +69,12 @@ ], inter_signal_list: [ + { struct: "pwr_boot_status", + type: "uni", + name: "boot_status", + act: "req", + package: "pwrmgr_pkg", + }, { struct: "pwr_ast", type: "req_rsp", name: "pwr_ast", diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv index 91057bfc3ffe52..700b9498501368 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv @@ -702,6 +702,7 @@ module chip_earlgrey_asic #( // pwrmgr interface pwrmgr_pkg::pwr_ast_req_t base_ast_pwr; pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status; // assorted ast status ast_pkg::ast_pwst_t ast_pwst; diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv index 846beec5314dd1..74c38f68d07753 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv @@ -646,6 +646,7 @@ module chip_earlgrey_cw310 #( // pwrmgr interface pwrmgr_pkg::pwr_ast_req_t base_ast_pwr; pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status; // assorted ast status ast_pkg::ast_pwst_t ast_pwst; diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 397cc8ba53efc6..aab5a60aa81b19 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -1713,6 +1713,7 @@ module top_earlgrey #( .alert_rx_i ( alert_rx[22:22] ), // Inter-module signals + .boot_status_o(), .pwr_ast_o(pwrmgr_ast_req_o), .pwr_ast_i(pwrmgr_ast_rsp_i), .pwr_rst_o(pwrmgr_aon_pwr_rst_req), diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl index 6e07e3eeb6e600..c0b39507ceeb2e 100644 --- a/util/topgen/templates/chiplevel.sv.tpl +++ b/util/topgen/templates/chiplevel.sv.tpl @@ -498,6 +498,7 @@ module chip_${top["name"]}_${target["name"]} #( // pwrmgr interface pwrmgr_pkg::pwr_ast_req_t base_ast_pwr; pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status; // assorted ast status ast_pkg::ast_pwst_t ast_pwst; @@ -1288,13 +1289,14 @@ module chip_${top["name"]}_${target["name"]} #( .dma_ctn_tl_d2h_i ( ctn_tl_d2h[1] ), .mbx_tl_req_i ( tlul_pkg::TL_H2D_DEFAULT ), .mbx_tl_rsp_o ( ), + .pwrmgr_boot_status_o ( pwrmgr_boot_status ), .soc_fatal_alert_req_i ( soc_fatal_alert_req ), .soc_fatal_alert_rsp_o ( ), .soc_recov_alert_req_i ( soc_recov_alert_req ), .soc_recov_alert_rsp_o ( ), .soc_intr_async_i ( '0 ), .soc_wkup_async_i ( 1'b0 ), - .soc_rst_req_async_i ( 1'b0 ), + .soc_rst_req_async_i ( pwrmgr_boot_status.light_reset_req), // FIXME: Needs better loopback fix .soc_lsio_trigger_i ( '0 ), .entropy_src_hw_if_req_o ( entropy_src_hw_if_req ), .entropy_src_hw_if_rsp_i ( entropy_src_hw_if_rsp ),