From bf9b50a9fe8f37fb38ede193de46756441e4fcd8 Mon Sep 17 00:00:00 2001 From: Michael Schaffner Date: Thu, 3 Aug 2023 16:31:19 -0700 Subject: [PATCH] [otp_ctrl] Make ERR_CODE register non-compact This allows us to write more parametric DIF code. Signed-off-by: Michael Schaffner --- hw/ip/otp_ctrl/data/otp_ctrl.hjson | 1 + hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl | 1 + hw/ip/otp_ctrl/dv/env/otp_ctrl_env_cov.sv | 17 +- hw/ip/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv | 15 +- .../dv/env/seq_lib/otp_ctrl_base_vseq.sv | 2 +- .../dv/env/seq_lib/otp_ctrl_init_fail_vseq.sv | 4 +- .../dv/env/seq_lib/otp_ctrl_smoke_vseq.sv | 30 +- hw/ip/otp_ctrl/rtl/otp_ctrl_core_reg_top.sv | 447 +++++++++++------- hw/ip/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv | 186 +++++--- sw/device/lib/dif/dif_otp_ctrl.c | 139 ++---- sw/device/lib/dif/dif_otp_ctrl_unittest.cc | 12 +- sw/host/opentitanlib/src/dif/otp_ctrl.rs | 11 +- 12 files changed, 487 insertions(+), 378 deletions(-) diff --git a/hw/ip/otp_ctrl/data/otp_ctrl.hjson b/hw/ip/otp_ctrl/data/otp_ctrl.hjson index d46878e5fbddef..35219eefa5916c 100644 --- a/hw/ip/otp_ctrl/data/otp_ctrl.hjson +++ b/hw/ip/otp_ctrl/data/otp_ctrl.hjson @@ -1773,6 +1773,7 @@ hwaccess: "hwo", hwext: "true", cname: "AGENT", + compact: "false", resval: 0, tags: [ // OTP internal HW can modify the error code registers "excl:CsrAllTests:CsrExclCheck"], diff --git a/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl b/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl index 4f168242481d82..2ba4ed0df85c0d 100644 --- a/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl +++ b/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl @@ -771,6 +771,7 @@ hwaccess: "hwo", hwext: "true", cname: "AGENT", + compact: "false", resval: 0, tags: [ // OTP internal HW can modify the error code registers "excl:CsrAllTests:CsrExclCheck"], diff --git a/hw/ip/otp_ctrl/dv/env/otp_ctrl_env_cov.sv b/hw/ip/otp_ctrl/dv/env/otp_ctrl_env_cov.sv index e1ceb4766dd901..a756c65c61ec65 100644 --- a/hw/ip/otp_ctrl/dv/env/otp_ctrl_env_cov.sv +++ b/hw/ip/otp_ctrl/dv/env/otp_ctrl_env_cov.sv @@ -75,7 +75,16 @@ class otp_ctrl_csr_rd_after_alert_cg_wrap; bins direct_access_rdata = {ral.direct_access_rdata[0].get_offset(), ral.direct_access_rdata[1].get_offset()}; bins status = {ral.status.get_offset()}; - bins error_code = {ral.err_code[0].get_offset()}; + bins error_code = {ral.err_code[0].get_offset(), + ral.err_code[1].get_offset(), + ral.err_code[2].get_offset(), + ral.err_code[3].get_offset(), + ral.err_code[4].get_offset(), + ral.err_code[5].get_offset(), + ral.err_code[6].get_offset(), + ral.err_code[7].get_offset(), + ral.err_code[8].get_offset(), + ral.err_code[9].get_offset()}; } endgroup @@ -292,9 +301,9 @@ class otp_ctrl_env_cov extends cip_base_env_cov #(.CFG_T(otp_ctrl_env_cfg)); function void collect_err_code_cov(bit [TL_DW-1:0] val, int part_idx = DaiIdx); dv_base_reg_field err_code_flds[$]; - cfg.ral.err_code[0].get_dv_base_reg_fields(err_code_flds); - foreach (err_code_flds[i]) begin - collect_err_code_field_cov(i, get_field_val(err_code_flds[i], val), part_idx); + for (int k = 0; k <= OtpLciErrIdx; k++) begin + cfg.ral.err_code[k].get_dv_base_reg_fields(err_code_flds); + collect_err_code_field_cov(k, get_field_val(err_code_flds[0], val), part_idx); end endfunction diff --git a/hw/ip/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv b/hw/ip/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv index 0da26dab287b70..e2f0487a81f15b 100644 --- a/hw/ip/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv +++ b/hw/ip/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv @@ -902,7 +902,8 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) end end end - "err_code": begin + "err_code_0", "err_code_1", "err_code_2", "err_code_3", "err_code_4", "err_code_5", + "err_code_6", "err_code_7", "err_code_8", "err_code_9": begin // If lc_prog in progress, err_code might update anytime in DUT. Ignore checking until req // is acknowledged. if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; @@ -1218,15 +1219,15 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) if (err_code == OtpNoError) begin `uvm_error(`gfn, $sformatf("please set status error: %0s error code", status_err_idx.name)) end - ral.err_code[0].get_dv_base_reg_fields(err_code_flds); + ral.err_code[status_err_idx].get_dv_base_reg_fields(err_code_flds); - if (`gmv(err_code_flds[status_err_idx]) inside {OTP_TERMINAL_ERRS}) begin + if (`gmv(err_code_flds[0]) inside {OTP_TERMINAL_ERRS}) begin `uvm_info(`gfn, "terminal error cannot be updated", UVM_HIGH) end else if (status_err_idx == OtpLciErrIdx && - `gmv(err_code_flds[status_err_idx]) != OtpNoError) begin + `gmv(err_code_flds[0]) != OtpNoError) begin `uvm_info(`gfn, "For LC partition, all errors are terminal error!", UVM_HIGH) end else begin - void'(err_code_flds[status_err_idx].predict(.value(err_code), .kind(UVM_PREDICT_READ))); + void'(err_code_flds[0].predict(.value(err_code), .kind(UVM_PREDICT_READ))); end end @@ -1240,8 +1241,8 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) if (status_err_idx <= OtpLciErrIdx) begin dv_base_reg_field err_code_flds[$]; - ral.err_code[0].get_dv_base_reg_fields(err_code_flds); - void'(err_code_flds[status_err_idx].predict(OtpNoError)); + ral.err_code[status_err_idx].get_dv_base_reg_fields(err_code_flds); + void'(err_code_flds[0].predict(OtpNoError)); end endfunction diff --git a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv index d74614c4723d00..bf957eeff22eea 100644 --- a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv +++ b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv @@ -417,7 +417,7 @@ class otp_ctrl_base_vseq extends cip_base_vseq #( forever begin bit [TL_DW-1:0] err_val; cfg.clk_rst_vif.wait_clks(1); - csr_rd(.ptr(ral.err_code[0].err_code[7]), .value(err_val), .backdoor(1)); + csr_rd(.ptr(ral.err_code[DaiIdx].err_code), .value(err_val), .backdoor(1)); // Break if error will cause fatal alerts if (err_val inside {OTP_TERMINAL_ERRS}) break; end diff --git a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_init_fail_vseq.sv b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_init_fail_vseq.sv index 96f0066bdaa1f5..ce6eb3490780cb 100644 --- a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_init_fail_vseq.sv +++ b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_init_fail_vseq.sv @@ -178,7 +178,6 @@ class otp_ctrl_init_fail_vseq extends otp_ctrl_smoke_vseq; OtpCheckFailError : OtpMacroEccUncorrError; otp_err_code_e err_code; dv_base_reg_field err_code_flds[$]; - ral.err_code[0].get_dv_base_reg_fields(err_code_flds); cfg.otp_ctrl_vif.drive_pwr_otp_init(1); @@ -200,8 +199,9 @@ class otp_ctrl_init_fail_vseq extends otp_ctrl_smoke_vseq; // escalation. The logic below tries to confirm the first fatal alert is triggered with the // correct error code. for (int i = 0; i <= OtpLciErrIdx; i++) begin + ral.err_code[i].get_dv_base_reg_fields(err_code_flds); if (exp_status[i]) begin - csr_rd(err_code_flds[i], err_code); + csr_rd(err_code_flds[0], err_code); if (err_code == exp_err_code) begin error_cnt++; end else if (err_code != OtpFsmStateError) begin diff --git a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_smoke_vseq.sv b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_smoke_vseq.sv index 990d3365d6e7c9..eb2658afea7cf9 100644 --- a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_smoke_vseq.sv +++ b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_smoke_vseq.sv @@ -137,7 +137,11 @@ class otp_ctrl_smoke_vseq extends otp_ctrl_base_vseq; if (do_lc_trans && !cfg.otp_ctrl_vif.alert_reqs) begin req_lc_transition(do_lc_trans, lc_prog_blocking); - if (cfg.otp_ctrl_vif.lc_prog_req == 0) csr_rd(.ptr(ral.err_code[0]), .value(tlul_val)); + if (cfg.otp_ctrl_vif.lc_prog_req == 0) begin + for (int k = 0; k <= LciIdx; k++) begin + csr_rd(.ptr(ral.err_code[k]), .value(tlul_val)); + end + end end for (int i = 0; i < num_dai_op; i++) begin @@ -152,7 +156,11 @@ class otp_ctrl_smoke_vseq extends otp_ctrl_base_vseq; // OTP write via DAI if (rand_wr && !digest_calculated[part_idx]) begin dai_wr(dai_addr, wdata0, wdata1); - if (cfg.otp_ctrl_vif.lc_prog_req == 0) csr_rd(.ptr(ral.err_code[0]), .value(tlul_val)); + if (cfg.otp_ctrl_vif.lc_prog_req == 0) begin + for (int k = 0; k <= LciIdx; k++) begin + csr_rd(.ptr(ral.err_code[k]), .value(tlul_val)); + end + end end // Inject ECC error. @@ -186,7 +194,11 @@ class otp_ctrl_smoke_vseq extends otp_ctrl_base_vseq; if (!$urandom_range(0, 9) && access_locked_parts) write_sw_digests(); if ($urandom_range(0, 1)) csr_rd(.ptr(ral.direct_access_regwen), .value(tlul_val)); if ($urandom_range(0, 1)) csr_rd(.ptr(ral.status), .value(tlul_val)); - if (cfg.otp_ctrl_vif.lc_prog_req == 0) csr_rd(.ptr(ral.err_code[0]), .value(tlul_val)); + if (cfg.otp_ctrl_vif.lc_prog_req == 0) begin + for (int k = 0; k <= LciIdx; k++) begin + csr_rd(.ptr(ral.err_code[k]), .value(tlul_val)); + end + end end // Read/write test access memory @@ -197,7 +209,11 @@ class otp_ctrl_smoke_vseq extends otp_ctrl_base_vseq; cal_hw_digests(); if ($urandom_range(0, 1)) csr_rd(.ptr(ral.status), .value(tlul_val)); - if (cfg.otp_ctrl_vif.lc_prog_req == 0) csr_rd(.ptr(ral.err_code[0]), .value(tlul_val)); + if (cfg.otp_ctrl_vif.lc_prog_req == 0) begin + for (int k = 0; k <= LciIdx; k++) begin + csr_rd(.ptr(ral.err_code[k]), .value(tlul_val)); + end + end if ($urandom_range(0, 1)) rd_digests(); if (do_dut_init) dut_init(); @@ -208,7 +224,11 @@ class otp_ctrl_smoke_vseq extends otp_ctrl_base_vseq; // send request to the interfaces again after partitions are locked if (do_lc_trans && !cfg.otp_ctrl_vif.alert_reqs) begin req_lc_transition(do_lc_trans, lc_prog_blocking); - if (cfg.otp_ctrl_vif.lc_prog_req == 0) csr_rd(.ptr(ral.err_code[0]), .value(tlul_val)); + if (cfg.otp_ctrl_vif.lc_prog_req == 0) begin + for (int k = 0; k <= LciIdx; k++) begin + csr_rd(.ptr(ral.err_code[k]), .value(tlul_val)); + end + end end if (do_req_keys && !cfg.otp_ctrl_vif.alert_reqs && !cfg.smoke_test) begin diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl_core_reg_top.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl_core_reg_top.sv index bf7191d3f507c9..3706f39f020b70 100644 --- a/hw/ip/otp_ctrl/rtl/otp_ctrl_core_reg_top.sv +++ b/hw/ip/otp_ctrl/rtl/otp_ctrl_core_reg_top.sv @@ -57,9 +57,9 @@ module otp_ctrl_core_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [35:0] reg_we_check; + logic [44:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(36) + .OneHotWidth(45) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -207,17 +207,26 @@ module otp_ctrl_core_reg_top ( logic status_bus_integ_error_qs; logic status_dai_idle_qs; logic status_check_pending_qs; - logic err_code_re; - logic [2:0] err_code_err_code_0_qs; - logic [2:0] err_code_err_code_1_qs; - logic [2:0] err_code_err_code_2_qs; - logic [2:0] err_code_err_code_3_qs; - logic [2:0] err_code_err_code_4_qs; - logic [2:0] err_code_err_code_5_qs; - logic [2:0] err_code_err_code_6_qs; - logic [2:0] err_code_err_code_7_qs; - logic [2:0] err_code_err_code_8_qs; - logic [2:0] err_code_err_code_9_qs; + logic err_code_0_re; + logic [2:0] err_code_0_qs; + logic err_code_1_re; + logic [2:0] err_code_1_qs; + logic err_code_2_re; + logic [2:0] err_code_2_qs; + logic err_code_3_re; + logic [2:0] err_code_3_qs; + logic err_code_4_re; + logic [2:0] err_code_4_qs; + logic err_code_5_re; + logic [2:0] err_code_5_qs; + logic err_code_6_re; + logic [2:0] err_code_6_qs; + logic err_code_7_re; + logic [2:0] err_code_7_qs; + logic err_code_8_re; + logic [2:0] err_code_8_qs; + logic err_code_9_re; + logic [2:0] err_code_9_qs; logic direct_access_regwen_re; logic direct_access_regwen_qs; logic direct_access_cmd_we; @@ -786,12 +795,11 @@ module otp_ctrl_core_reg_top ( // Subregister 0 of Multireg err_code - // R[err_code]: V(True) - // F[err_code_0]: 2:0 + // R[err_code_0]: V(True) prim_subreg_ext #( .DW (3) - ) u_err_code_err_code_0 ( - .re (err_code_re), + ) u_err_code_0 ( + .re (err_code_0_re), .we (1'b0), .wd ('0), .d (hw2reg.err_code[0].d), @@ -799,14 +807,16 @@ module otp_ctrl_core_reg_top ( .qe (), .q (), .ds (), - .qs (err_code_err_code_0_qs) + .qs (err_code_0_qs) ); - // F[err_code_1]: 5:3 + + // Subregister 1 of Multireg err_code + // R[err_code_1]: V(True) prim_subreg_ext #( .DW (3) - ) u_err_code_err_code_1 ( - .re (err_code_re), + ) u_err_code_1 ( + .re (err_code_1_re), .we (1'b0), .wd ('0), .d (hw2reg.err_code[1].d), @@ -814,14 +824,16 @@ module otp_ctrl_core_reg_top ( .qe (), .q (), .ds (), - .qs (err_code_err_code_1_qs) + .qs (err_code_1_qs) ); - // F[err_code_2]: 8:6 + + // Subregister 2 of Multireg err_code + // R[err_code_2]: V(True) prim_subreg_ext #( .DW (3) - ) u_err_code_err_code_2 ( - .re (err_code_re), + ) u_err_code_2 ( + .re (err_code_2_re), .we (1'b0), .wd ('0), .d (hw2reg.err_code[2].d), @@ -829,14 +841,16 @@ module otp_ctrl_core_reg_top ( .qe (), .q (), .ds (), - .qs (err_code_err_code_2_qs) + .qs (err_code_2_qs) ); - // F[err_code_3]: 11:9 + + // Subregister 3 of Multireg err_code + // R[err_code_3]: V(True) prim_subreg_ext #( .DW (3) - ) u_err_code_err_code_3 ( - .re (err_code_re), + ) u_err_code_3 ( + .re (err_code_3_re), .we (1'b0), .wd ('0), .d (hw2reg.err_code[3].d), @@ -844,14 +858,16 @@ module otp_ctrl_core_reg_top ( .qe (), .q (), .ds (), - .qs (err_code_err_code_3_qs) + .qs (err_code_3_qs) ); - // F[err_code_4]: 14:12 + + // Subregister 4 of Multireg err_code + // R[err_code_4]: V(True) prim_subreg_ext #( .DW (3) - ) u_err_code_err_code_4 ( - .re (err_code_re), + ) u_err_code_4 ( + .re (err_code_4_re), .we (1'b0), .wd ('0), .d (hw2reg.err_code[4].d), @@ -859,14 +875,16 @@ module otp_ctrl_core_reg_top ( .qe (), .q (), .ds (), - .qs (err_code_err_code_4_qs) + .qs (err_code_4_qs) ); - // F[err_code_5]: 17:15 + + // Subregister 5 of Multireg err_code + // R[err_code_5]: V(True) prim_subreg_ext #( .DW (3) - ) u_err_code_err_code_5 ( - .re (err_code_re), + ) u_err_code_5 ( + .re (err_code_5_re), .we (1'b0), .wd ('0), .d (hw2reg.err_code[5].d), @@ -874,14 +892,16 @@ module otp_ctrl_core_reg_top ( .qe (), .q (), .ds (), - .qs (err_code_err_code_5_qs) + .qs (err_code_5_qs) ); - // F[err_code_6]: 20:18 + + // Subregister 6 of Multireg err_code + // R[err_code_6]: V(True) prim_subreg_ext #( .DW (3) - ) u_err_code_err_code_6 ( - .re (err_code_re), + ) u_err_code_6 ( + .re (err_code_6_re), .we (1'b0), .wd ('0), .d (hw2reg.err_code[6].d), @@ -889,14 +909,16 @@ module otp_ctrl_core_reg_top ( .qe (), .q (), .ds (), - .qs (err_code_err_code_6_qs) + .qs (err_code_6_qs) ); - // F[err_code_7]: 23:21 + + // Subregister 7 of Multireg err_code + // R[err_code_7]: V(True) prim_subreg_ext #( .DW (3) - ) u_err_code_err_code_7 ( - .re (err_code_re), + ) u_err_code_7 ( + .re (err_code_7_re), .we (1'b0), .wd ('0), .d (hw2reg.err_code[7].d), @@ -904,14 +926,16 @@ module otp_ctrl_core_reg_top ( .qe (), .q (), .ds (), - .qs (err_code_err_code_7_qs) + .qs (err_code_7_qs) ); - // F[err_code_8]: 26:24 + + // Subregister 8 of Multireg err_code + // R[err_code_8]: V(True) prim_subreg_ext #( .DW (3) - ) u_err_code_err_code_8 ( - .re (err_code_re), + ) u_err_code_8 ( + .re (err_code_8_re), .we (1'b0), .wd ('0), .d (hw2reg.err_code[8].d), @@ -919,14 +943,16 @@ module otp_ctrl_core_reg_top ( .qe (), .q (), .ds (), - .qs (err_code_err_code_8_qs) + .qs (err_code_8_qs) ); - // F[err_code_9]: 29:27 + + // Subregister 9 of Multireg err_code + // R[err_code_9]: V(True) prim_subreg_ext #( .DW (3) - ) u_err_code_err_code_9 ( - .re (err_code_re), + ) u_err_code_9 ( + .re (err_code_9_re), .we (1'b0), .wd ('0), .d (hw2reg.err_code[9].d), @@ -934,7 +960,7 @@ module otp_ctrl_core_reg_top ( .qe (), .q (), .ds (), - .qs (err_code_err_code_9_qs) + .qs (err_code_9_qs) ); @@ -1660,7 +1686,7 @@ module otp_ctrl_core_reg_top ( - logic [35:0] addr_hit; + logic [44:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == OTP_CTRL_INTR_STATE_OFFSET); @@ -1668,37 +1694,46 @@ module otp_ctrl_core_reg_top ( addr_hit[ 2] = (reg_addr == OTP_CTRL_INTR_TEST_OFFSET); addr_hit[ 3] = (reg_addr == OTP_CTRL_ALERT_TEST_OFFSET); addr_hit[ 4] = (reg_addr == OTP_CTRL_STATUS_OFFSET); - addr_hit[ 5] = (reg_addr == OTP_CTRL_ERR_CODE_OFFSET); - addr_hit[ 6] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET); - addr_hit[ 7] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET); - addr_hit[ 8] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET); - addr_hit[ 9] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET); - addr_hit[10] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET); - addr_hit[11] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET); - addr_hit[12] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET); - addr_hit[13] = (reg_addr == OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET); - addr_hit[14] = (reg_addr == OTP_CTRL_CHECK_TRIGGER_OFFSET); - addr_hit[15] = (reg_addr == OTP_CTRL_CHECK_REGWEN_OFFSET); - addr_hit[16] = (reg_addr == OTP_CTRL_CHECK_TIMEOUT_OFFSET); - addr_hit[17] = (reg_addr == OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET); - addr_hit[18] = (reg_addr == OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET); - addr_hit[19] = (reg_addr == OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET); - addr_hit[20] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET); - addr_hit[21] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET); - addr_hit[22] = (reg_addr == OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET); - addr_hit[23] = (reg_addr == OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET); - addr_hit[24] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET); - addr_hit[25] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET); - addr_hit[26] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET); - addr_hit[27] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET); - addr_hit[28] = (reg_addr == OTP_CTRL_HW_CFG_DIGEST_0_OFFSET); - addr_hit[29] = (reg_addr == OTP_CTRL_HW_CFG_DIGEST_1_OFFSET); - addr_hit[30] = (reg_addr == OTP_CTRL_SECRET0_DIGEST_0_OFFSET); - addr_hit[31] = (reg_addr == OTP_CTRL_SECRET0_DIGEST_1_OFFSET); - addr_hit[32] = (reg_addr == OTP_CTRL_SECRET1_DIGEST_0_OFFSET); - addr_hit[33] = (reg_addr == OTP_CTRL_SECRET1_DIGEST_1_OFFSET); - addr_hit[34] = (reg_addr == OTP_CTRL_SECRET2_DIGEST_0_OFFSET); - addr_hit[35] = (reg_addr == OTP_CTRL_SECRET2_DIGEST_1_OFFSET); + addr_hit[ 5] = (reg_addr == OTP_CTRL_ERR_CODE_0_OFFSET); + addr_hit[ 6] = (reg_addr == OTP_CTRL_ERR_CODE_1_OFFSET); + addr_hit[ 7] = (reg_addr == OTP_CTRL_ERR_CODE_2_OFFSET); + addr_hit[ 8] = (reg_addr == OTP_CTRL_ERR_CODE_3_OFFSET); + addr_hit[ 9] = (reg_addr == OTP_CTRL_ERR_CODE_4_OFFSET); + addr_hit[10] = (reg_addr == OTP_CTRL_ERR_CODE_5_OFFSET); + addr_hit[11] = (reg_addr == OTP_CTRL_ERR_CODE_6_OFFSET); + addr_hit[12] = (reg_addr == OTP_CTRL_ERR_CODE_7_OFFSET); + addr_hit[13] = (reg_addr == OTP_CTRL_ERR_CODE_8_OFFSET); + addr_hit[14] = (reg_addr == OTP_CTRL_ERR_CODE_9_OFFSET); + addr_hit[15] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET); + addr_hit[16] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET); + addr_hit[17] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET); + addr_hit[18] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET); + addr_hit[19] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET); + addr_hit[20] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET); + addr_hit[21] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET); + addr_hit[22] = (reg_addr == OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET); + addr_hit[23] = (reg_addr == OTP_CTRL_CHECK_TRIGGER_OFFSET); + addr_hit[24] = (reg_addr == OTP_CTRL_CHECK_REGWEN_OFFSET); + addr_hit[25] = (reg_addr == OTP_CTRL_CHECK_TIMEOUT_OFFSET); + addr_hit[26] = (reg_addr == OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET); + addr_hit[27] = (reg_addr == OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET); + addr_hit[28] = (reg_addr == OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET); + addr_hit[29] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET); + addr_hit[30] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET); + addr_hit[31] = (reg_addr == OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET); + addr_hit[32] = (reg_addr == OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET); + addr_hit[33] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET); + addr_hit[34] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET); + addr_hit[35] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET); + addr_hit[36] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET); + addr_hit[37] = (reg_addr == OTP_CTRL_HW_CFG_DIGEST_0_OFFSET); + addr_hit[38] = (reg_addr == OTP_CTRL_HW_CFG_DIGEST_1_OFFSET); + addr_hit[39] = (reg_addr == OTP_CTRL_SECRET0_DIGEST_0_OFFSET); + addr_hit[40] = (reg_addr == OTP_CTRL_SECRET0_DIGEST_1_OFFSET); + addr_hit[41] = (reg_addr == OTP_CTRL_SECRET1_DIGEST_0_OFFSET); + addr_hit[42] = (reg_addr == OTP_CTRL_SECRET1_DIGEST_1_OFFSET); + addr_hit[43] = (reg_addr == OTP_CTRL_SECRET2_DIGEST_0_OFFSET); + addr_hit[44] = (reg_addr == OTP_CTRL_SECRET2_DIGEST_1_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -1741,7 +1776,16 @@ module otp_ctrl_core_reg_top ( (addr_hit[32] & (|(OTP_CTRL_CORE_PERMIT[32] & ~reg_be))) | (addr_hit[33] & (|(OTP_CTRL_CORE_PERMIT[33] & ~reg_be))) | (addr_hit[34] & (|(OTP_CTRL_CORE_PERMIT[34] & ~reg_be))) | - (addr_hit[35] & (|(OTP_CTRL_CORE_PERMIT[35] & ~reg_be))))); + (addr_hit[35] & (|(OTP_CTRL_CORE_PERMIT[35] & ~reg_be))) | + (addr_hit[36] & (|(OTP_CTRL_CORE_PERMIT[36] & ~reg_be))) | + (addr_hit[37] & (|(OTP_CTRL_CORE_PERMIT[37] & ~reg_be))) | + (addr_hit[38] & (|(OTP_CTRL_CORE_PERMIT[38] & ~reg_be))) | + (addr_hit[39] & (|(OTP_CTRL_CORE_PERMIT[39] & ~reg_be))) | + (addr_hit[40] & (|(OTP_CTRL_CORE_PERMIT[40] & ~reg_be))) | + (addr_hit[41] & (|(OTP_CTRL_CORE_PERMIT[41] & ~reg_be))) | + (addr_hit[42] & (|(OTP_CTRL_CORE_PERMIT[42] & ~reg_be))) | + (addr_hit[43] & (|(OTP_CTRL_CORE_PERMIT[43] & ~reg_be))) | + (addr_hit[44] & (|(OTP_CTRL_CORE_PERMIT[44] & ~reg_be))))); end // Generate write-enables @@ -1772,69 +1816,78 @@ module otp_ctrl_core_reg_top ( assign alert_test_recov_prim_otp_alert_wd = reg_wdata[4]; assign status_re = addr_hit[4] & reg_re & !reg_error; - assign err_code_re = addr_hit[5] & reg_re & !reg_error; - assign direct_access_regwen_re = addr_hit[6] & reg_re & !reg_error; - assign direct_access_cmd_we = addr_hit[7] & reg_we & !reg_error; + assign err_code_0_re = addr_hit[5] & reg_re & !reg_error; + assign err_code_1_re = addr_hit[6] & reg_re & !reg_error; + assign err_code_2_re = addr_hit[7] & reg_re & !reg_error; + assign err_code_3_re = addr_hit[8] & reg_re & !reg_error; + assign err_code_4_re = addr_hit[9] & reg_re & !reg_error; + assign err_code_5_re = addr_hit[10] & reg_re & !reg_error; + assign err_code_6_re = addr_hit[11] & reg_re & !reg_error; + assign err_code_7_re = addr_hit[12] & reg_re & !reg_error; + assign err_code_8_re = addr_hit[13] & reg_re & !reg_error; + assign err_code_9_re = addr_hit[14] & reg_re & !reg_error; + assign direct_access_regwen_re = addr_hit[15] & reg_re & !reg_error; + assign direct_access_cmd_we = addr_hit[16] & reg_we & !reg_error; assign direct_access_cmd_rd_wd = reg_wdata[0]; assign direct_access_cmd_wr_wd = reg_wdata[1]; assign direct_access_cmd_digest_wd = reg_wdata[2]; - assign direct_access_address_we = addr_hit[8] & reg_we & !reg_error; + assign direct_access_address_we = addr_hit[17] & reg_we & !reg_error; assign direct_access_address_wd = reg_wdata[10:0]; - assign direct_access_wdata_0_we = addr_hit[9] & reg_we & !reg_error; + assign direct_access_wdata_0_we = addr_hit[18] & reg_we & !reg_error; assign direct_access_wdata_0_wd = reg_wdata[31:0]; - assign direct_access_wdata_1_we = addr_hit[10] & reg_we & !reg_error; + assign direct_access_wdata_1_we = addr_hit[19] & reg_we & !reg_error; assign direct_access_wdata_1_wd = reg_wdata[31:0]; - assign direct_access_rdata_0_re = addr_hit[11] & reg_re & !reg_error; - assign direct_access_rdata_1_re = addr_hit[12] & reg_re & !reg_error; - assign check_trigger_regwen_we = addr_hit[13] & reg_we & !reg_error; + assign direct_access_rdata_0_re = addr_hit[20] & reg_re & !reg_error; + assign direct_access_rdata_1_re = addr_hit[21] & reg_re & !reg_error; + assign check_trigger_regwen_we = addr_hit[22] & reg_we & !reg_error; assign check_trigger_regwen_wd = reg_wdata[0]; - assign check_trigger_we = addr_hit[14] & reg_we & !reg_error; + assign check_trigger_we = addr_hit[23] & reg_we & !reg_error; assign check_trigger_integrity_wd = reg_wdata[0]; assign check_trigger_consistency_wd = reg_wdata[1]; - assign check_regwen_we = addr_hit[15] & reg_we & !reg_error; + assign check_regwen_we = addr_hit[24] & reg_we & !reg_error; assign check_regwen_wd = reg_wdata[0]; - assign check_timeout_we = addr_hit[16] & reg_we & !reg_error; + assign check_timeout_we = addr_hit[25] & reg_we & !reg_error; assign check_timeout_wd = reg_wdata[31:0]; - assign integrity_check_period_we = addr_hit[17] & reg_we & !reg_error; + assign integrity_check_period_we = addr_hit[26] & reg_we & !reg_error; assign integrity_check_period_wd = reg_wdata[31:0]; - assign consistency_check_period_we = addr_hit[18] & reg_we & !reg_error; + assign consistency_check_period_we = addr_hit[27] & reg_we & !reg_error; assign consistency_check_period_wd = reg_wdata[31:0]; - assign vendor_test_read_lock_we = addr_hit[19] & reg_we & !reg_error; + assign vendor_test_read_lock_we = addr_hit[28] & reg_we & !reg_error; assign vendor_test_read_lock_wd = reg_wdata[0]; - assign creator_sw_cfg_read_lock_we = addr_hit[20] & reg_we & !reg_error; + assign creator_sw_cfg_read_lock_we = addr_hit[29] & reg_we & !reg_error; assign creator_sw_cfg_read_lock_wd = reg_wdata[0]; - assign owner_sw_cfg_read_lock_we = addr_hit[21] & reg_we & !reg_error; + assign owner_sw_cfg_read_lock_we = addr_hit[30] & reg_we & !reg_error; assign owner_sw_cfg_read_lock_wd = reg_wdata[0]; - assign vendor_test_digest_0_re = addr_hit[22] & reg_re & !reg_error; - assign vendor_test_digest_1_re = addr_hit[23] & reg_re & !reg_error; - assign creator_sw_cfg_digest_0_re = addr_hit[24] & reg_re & !reg_error; - assign creator_sw_cfg_digest_1_re = addr_hit[25] & reg_re & !reg_error; - assign owner_sw_cfg_digest_0_re = addr_hit[26] & reg_re & !reg_error; - assign owner_sw_cfg_digest_1_re = addr_hit[27] & reg_re & !reg_error; - assign hw_cfg_digest_0_re = addr_hit[28] & reg_re & !reg_error; - assign hw_cfg_digest_1_re = addr_hit[29] & reg_re & !reg_error; - assign secret0_digest_0_re = addr_hit[30] & reg_re & !reg_error; - assign secret0_digest_1_re = addr_hit[31] & reg_re & !reg_error; - assign secret1_digest_0_re = addr_hit[32] & reg_re & !reg_error; - assign secret1_digest_1_re = addr_hit[33] & reg_re & !reg_error; - assign secret2_digest_0_re = addr_hit[34] & reg_re & !reg_error; - assign secret2_digest_1_re = addr_hit[35] & reg_re & !reg_error; + assign vendor_test_digest_0_re = addr_hit[31] & reg_re & !reg_error; + assign vendor_test_digest_1_re = addr_hit[32] & reg_re & !reg_error; + assign creator_sw_cfg_digest_0_re = addr_hit[33] & reg_re & !reg_error; + assign creator_sw_cfg_digest_1_re = addr_hit[34] & reg_re & !reg_error; + assign owner_sw_cfg_digest_0_re = addr_hit[35] & reg_re & !reg_error; + assign owner_sw_cfg_digest_1_re = addr_hit[36] & reg_re & !reg_error; + assign hw_cfg_digest_0_re = addr_hit[37] & reg_re & !reg_error; + assign hw_cfg_digest_1_re = addr_hit[38] & reg_re & !reg_error; + assign secret0_digest_0_re = addr_hit[39] & reg_re & !reg_error; + assign secret0_digest_1_re = addr_hit[40] & reg_re & !reg_error; + assign secret1_digest_0_re = addr_hit[41] & reg_re & !reg_error; + assign secret1_digest_1_re = addr_hit[42] & reg_re & !reg_error; + assign secret2_digest_0_re = addr_hit[43] & reg_re & !reg_error; + assign secret2_digest_1_re = addr_hit[44] & reg_re & !reg_error; // Assign write-enables to checker logic vector. always_comb begin @@ -1846,35 +1899,44 @@ module otp_ctrl_core_reg_top ( reg_we_check[4] = 1'b0; reg_we_check[5] = 1'b0; reg_we_check[6] = 1'b0; - reg_we_check[7] = direct_access_cmd_gated_we; - reg_we_check[8] = direct_access_address_gated_we; - reg_we_check[9] = direct_access_wdata_0_gated_we; - reg_we_check[10] = direct_access_wdata_1_gated_we; + reg_we_check[7] = 1'b0; + reg_we_check[8] = 1'b0; + reg_we_check[9] = 1'b0; + reg_we_check[10] = 1'b0; reg_we_check[11] = 1'b0; reg_we_check[12] = 1'b0; - reg_we_check[13] = check_trigger_regwen_we; - reg_we_check[14] = check_trigger_gated_we; - reg_we_check[15] = check_regwen_we; - reg_we_check[16] = check_timeout_gated_we; - reg_we_check[17] = integrity_check_period_gated_we; - reg_we_check[18] = consistency_check_period_gated_we; - reg_we_check[19] = vendor_test_read_lock_gated_we; - reg_we_check[20] = creator_sw_cfg_read_lock_gated_we; - reg_we_check[21] = owner_sw_cfg_read_lock_gated_we; - reg_we_check[22] = 1'b0; - reg_we_check[23] = 1'b0; - reg_we_check[24] = 1'b0; - reg_we_check[25] = 1'b0; - reg_we_check[26] = 1'b0; - reg_we_check[27] = 1'b0; - reg_we_check[28] = 1'b0; - reg_we_check[29] = 1'b0; - reg_we_check[30] = 1'b0; + reg_we_check[13] = 1'b0; + reg_we_check[14] = 1'b0; + reg_we_check[15] = 1'b0; + reg_we_check[16] = direct_access_cmd_gated_we; + reg_we_check[17] = direct_access_address_gated_we; + reg_we_check[18] = direct_access_wdata_0_gated_we; + reg_we_check[19] = direct_access_wdata_1_gated_we; + reg_we_check[20] = 1'b0; + reg_we_check[21] = 1'b0; + reg_we_check[22] = check_trigger_regwen_we; + reg_we_check[23] = check_trigger_gated_we; + reg_we_check[24] = check_regwen_we; + reg_we_check[25] = check_timeout_gated_we; + reg_we_check[26] = integrity_check_period_gated_we; + reg_we_check[27] = consistency_check_period_gated_we; + reg_we_check[28] = vendor_test_read_lock_gated_we; + reg_we_check[29] = creator_sw_cfg_read_lock_gated_we; + reg_we_check[30] = owner_sw_cfg_read_lock_gated_we; reg_we_check[31] = 1'b0; reg_we_check[32] = 1'b0; reg_we_check[33] = 1'b0; reg_we_check[34] = 1'b0; reg_we_check[35] = 1'b0; + reg_we_check[36] = 1'b0; + reg_we_check[37] = 1'b0; + reg_we_check[38] = 1'b0; + reg_we_check[39] = 1'b0; + reg_we_check[40] = 1'b0; + reg_we_check[41] = 1'b0; + reg_we_check[42] = 1'b0; + reg_we_check[43] = 1'b0; + reg_we_check[44] = 1'b0; end // Read data return @@ -1925,138 +1987,165 @@ module otp_ctrl_core_reg_top ( end addr_hit[5]: begin - reg_rdata_next[2:0] = err_code_err_code_0_qs; - reg_rdata_next[5:3] = err_code_err_code_1_qs; - reg_rdata_next[8:6] = err_code_err_code_2_qs; - reg_rdata_next[11:9] = err_code_err_code_3_qs; - reg_rdata_next[14:12] = err_code_err_code_4_qs; - reg_rdata_next[17:15] = err_code_err_code_5_qs; - reg_rdata_next[20:18] = err_code_err_code_6_qs; - reg_rdata_next[23:21] = err_code_err_code_7_qs; - reg_rdata_next[26:24] = err_code_err_code_8_qs; - reg_rdata_next[29:27] = err_code_err_code_9_qs; + reg_rdata_next[2:0] = err_code_0_qs; end addr_hit[6]: begin - reg_rdata_next[0] = direct_access_regwen_qs; + reg_rdata_next[2:0] = err_code_1_qs; end addr_hit[7]: begin + reg_rdata_next[2:0] = err_code_2_qs; + end + + addr_hit[8]: begin + reg_rdata_next[2:0] = err_code_3_qs; + end + + addr_hit[9]: begin + reg_rdata_next[2:0] = err_code_4_qs; + end + + addr_hit[10]: begin + reg_rdata_next[2:0] = err_code_5_qs; + end + + addr_hit[11]: begin + reg_rdata_next[2:0] = err_code_6_qs; + end + + addr_hit[12]: begin + reg_rdata_next[2:0] = err_code_7_qs; + end + + addr_hit[13]: begin + reg_rdata_next[2:0] = err_code_8_qs; + end + + addr_hit[14]: begin + reg_rdata_next[2:0] = err_code_9_qs; + end + + addr_hit[15]: begin + reg_rdata_next[0] = direct_access_regwen_qs; + end + + addr_hit[16]: begin reg_rdata_next[0] = '0; reg_rdata_next[1] = '0; reg_rdata_next[2] = '0; end - addr_hit[8]: begin + addr_hit[17]: begin reg_rdata_next[10:0] = direct_access_address_qs; end - addr_hit[9]: begin + addr_hit[18]: begin reg_rdata_next[31:0] = direct_access_wdata_0_qs; end - addr_hit[10]: begin + addr_hit[19]: begin reg_rdata_next[31:0] = direct_access_wdata_1_qs; end - addr_hit[11]: begin + addr_hit[20]: begin reg_rdata_next[31:0] = direct_access_rdata_0_qs; end - addr_hit[12]: begin + addr_hit[21]: begin reg_rdata_next[31:0] = direct_access_rdata_1_qs; end - addr_hit[13]: begin + addr_hit[22]: begin reg_rdata_next[0] = check_trigger_regwen_qs; end - addr_hit[14]: begin + addr_hit[23]: begin reg_rdata_next[0] = '0; reg_rdata_next[1] = '0; end - addr_hit[15]: begin + addr_hit[24]: begin reg_rdata_next[0] = check_regwen_qs; end - addr_hit[16]: begin + addr_hit[25]: begin reg_rdata_next[31:0] = check_timeout_qs; end - addr_hit[17]: begin + addr_hit[26]: begin reg_rdata_next[31:0] = integrity_check_period_qs; end - addr_hit[18]: begin + addr_hit[27]: begin reg_rdata_next[31:0] = consistency_check_period_qs; end - addr_hit[19]: begin + addr_hit[28]: begin reg_rdata_next[0] = vendor_test_read_lock_qs; end - addr_hit[20]: begin + addr_hit[29]: begin reg_rdata_next[0] = creator_sw_cfg_read_lock_qs; end - addr_hit[21]: begin + addr_hit[30]: begin reg_rdata_next[0] = owner_sw_cfg_read_lock_qs; end - addr_hit[22]: begin + addr_hit[31]: begin reg_rdata_next[31:0] = vendor_test_digest_0_qs; end - addr_hit[23]: begin + addr_hit[32]: begin reg_rdata_next[31:0] = vendor_test_digest_1_qs; end - addr_hit[24]: begin + addr_hit[33]: begin reg_rdata_next[31:0] = creator_sw_cfg_digest_0_qs; end - addr_hit[25]: begin + addr_hit[34]: begin reg_rdata_next[31:0] = creator_sw_cfg_digest_1_qs; end - addr_hit[26]: begin + addr_hit[35]: begin reg_rdata_next[31:0] = owner_sw_cfg_digest_0_qs; end - addr_hit[27]: begin + addr_hit[36]: begin reg_rdata_next[31:0] = owner_sw_cfg_digest_1_qs; end - addr_hit[28]: begin + addr_hit[37]: begin reg_rdata_next[31:0] = hw_cfg_digest_0_qs; end - addr_hit[29]: begin + addr_hit[38]: begin reg_rdata_next[31:0] = hw_cfg_digest_1_qs; end - addr_hit[30]: begin + addr_hit[39]: begin reg_rdata_next[31:0] = secret0_digest_0_qs; end - addr_hit[31]: begin + addr_hit[40]: begin reg_rdata_next[31:0] = secret0_digest_1_qs; end - addr_hit[32]: begin + addr_hit[41]: begin reg_rdata_next[31:0] = secret1_digest_0_qs; end - addr_hit[33]: begin + addr_hit[42]: begin reg_rdata_next[31:0] = secret1_digest_1_qs; end - addr_hit[34]: begin + addr_hit[43]: begin reg_rdata_next[31:0] = secret2_digest_0_qs; end - addr_hit[35]: begin + addr_hit[44]: begin reg_rdata_next[31:0] = secret2_digest_1_qs; end diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv index 73af5276829a09..b3f66bdd25245f 100644 --- a/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv +++ b/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv @@ -445,37 +445,46 @@ package otp_ctrl_reg_pkg; parameter logic [CoreAw-1:0] OTP_CTRL_INTR_TEST_OFFSET = 13'h 8; parameter logic [CoreAw-1:0] OTP_CTRL_ALERT_TEST_OFFSET = 13'h c; parameter logic [CoreAw-1:0] OTP_CTRL_STATUS_OFFSET = 13'h 10; - parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_OFFSET = 13'h 14; - parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET = 13'h 18; - parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET = 13'h 1c; - parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET = 13'h 20; - parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET = 13'h 24; - parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET = 13'h 28; - parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET = 13'h 2c; - parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET = 13'h 30; - parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET = 13'h 34; - parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_OFFSET = 13'h 38; - parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_REGWEN_OFFSET = 13'h 3c; - parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TIMEOUT_OFFSET = 13'h 40; - parameter logic [CoreAw-1:0] OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET = 13'h 44; - parameter logic [CoreAw-1:0] OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET = 13'h 48; - parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET = 13'h 4c; - parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET = 13'h 50; - parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET = 13'h 54; - parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET = 13'h 58; - parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET = 13'h 5c; - parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET = 13'h 60; - parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET = 13'h 64; - parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET = 13'h 68; - parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET = 13'h 6c; - parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG_DIGEST_0_OFFSET = 13'h 70; - parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG_DIGEST_1_OFFSET = 13'h 74; - parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_0_OFFSET = 13'h 78; - parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_1_OFFSET = 13'h 7c; - parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_0_OFFSET = 13'h 80; - parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_1_OFFSET = 13'h 84; - parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_0_OFFSET = 13'h 88; - parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_1_OFFSET = 13'h 8c; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_0_OFFSET = 13'h 14; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_1_OFFSET = 13'h 18; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_2_OFFSET = 13'h 1c; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_3_OFFSET = 13'h 20; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_4_OFFSET = 13'h 24; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_5_OFFSET = 13'h 28; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_6_OFFSET = 13'h 2c; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_7_OFFSET = 13'h 30; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_8_OFFSET = 13'h 34; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_9_OFFSET = 13'h 38; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET = 13'h 3c; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET = 13'h 40; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET = 13'h 44; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET = 13'h 48; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET = 13'h 4c; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET = 13'h 50; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET = 13'h 54; + parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET = 13'h 58; + parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_OFFSET = 13'h 5c; + parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_REGWEN_OFFSET = 13'h 60; + parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TIMEOUT_OFFSET = 13'h 64; + parameter logic [CoreAw-1:0] OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET = 13'h 68; + parameter logic [CoreAw-1:0] OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET = 13'h 6c; + parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET = 13'h 70; + parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET = 13'h 74; + parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET = 13'h 78; + parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET = 13'h 7c; + parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET = 13'h 80; + parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET = 13'h 84; + parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET = 13'h 88; + parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET = 13'h 8c; + parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET = 13'h 90; + parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG_DIGEST_0_OFFSET = 13'h 94; + parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG_DIGEST_1_OFFSET = 13'h 98; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_0_OFFSET = 13'h 9c; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_1_OFFSET = 13'h a0; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_0_OFFSET = 13'h a4; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_1_OFFSET = 13'h a8; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_0_OFFSET = 13'h ac; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_1_OFFSET = 13'h b0; // Reset values for hwext registers and their fields for core interface parameter logic [1:0] OTP_CTRL_INTR_TEST_RESVAL = 2'h 0; @@ -505,17 +514,26 @@ package otp_ctrl_reg_pkg; parameter logic [0:0] OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL = 1'h 0; parameter logic [0:0] OTP_CTRL_STATUS_DAI_IDLE_RESVAL = 1'h 0; parameter logic [0:0] OTP_CTRL_STATUS_CHECK_PENDING_RESVAL = 1'h 0; - parameter logic [29:0] OTP_CTRL_ERR_CODE_RESVAL = 30'h 0; - parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL = 3'h 0; - parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL = 3'h 0; - parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL = 3'h 0; - parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL = 3'h 0; - parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL = 3'h 0; - parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL = 3'h 0; - parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL = 3'h 0; - parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL = 3'h 0; - parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL = 3'h 0; - parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_0_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_0_ERR_CODE_0_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_1_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_1_ERR_CODE_1_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_2_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_2_ERR_CODE_2_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_3_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_3_ERR_CODE_3_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_4_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_4_ERR_CODE_4_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_5_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_5_ERR_CODE_5_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_6_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_6_ERR_CODE_6_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_7_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_7_ERR_CODE_7_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_8_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_8_ERR_CODE_8_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_9_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_9_ERR_CODE_9_RESVAL = 3'h 0; parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL = 1'h 1; parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL = 1'h 1; parameter logic [2:0] OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL = 3'h 0; @@ -569,7 +587,16 @@ package otp_ctrl_reg_pkg; OTP_CTRL_INTR_TEST, OTP_CTRL_ALERT_TEST, OTP_CTRL_STATUS, - OTP_CTRL_ERR_CODE, + OTP_CTRL_ERR_CODE_0, + OTP_CTRL_ERR_CODE_1, + OTP_CTRL_ERR_CODE_2, + OTP_CTRL_ERR_CODE_3, + OTP_CTRL_ERR_CODE_4, + OTP_CTRL_ERR_CODE_5, + OTP_CTRL_ERR_CODE_6, + OTP_CTRL_ERR_CODE_7, + OTP_CTRL_ERR_CODE_8, + OTP_CTRL_ERR_CODE_9, OTP_CTRL_DIRECT_ACCESS_REGWEN, OTP_CTRL_DIRECT_ACCESS_CMD, OTP_CTRL_DIRECT_ACCESS_ADDRESS, @@ -603,43 +630,52 @@ package otp_ctrl_reg_pkg; } otp_ctrl_core_id_e; // Register width information to check illegal writes for core interface - parameter logic [3:0] OTP_CTRL_CORE_PERMIT [36] = '{ + parameter logic [3:0] OTP_CTRL_CORE_PERMIT [45] = '{ 4'b 0001, // index[ 0] OTP_CTRL_INTR_STATE 4'b 0001, // index[ 1] OTP_CTRL_INTR_ENABLE 4'b 0001, // index[ 2] OTP_CTRL_INTR_TEST 4'b 0001, // index[ 3] OTP_CTRL_ALERT_TEST 4'b 0111, // index[ 4] OTP_CTRL_STATUS - 4'b 1111, // index[ 5] OTP_CTRL_ERR_CODE - 4'b 0001, // index[ 6] OTP_CTRL_DIRECT_ACCESS_REGWEN - 4'b 0001, // index[ 7] OTP_CTRL_DIRECT_ACCESS_CMD - 4'b 0011, // index[ 8] OTP_CTRL_DIRECT_ACCESS_ADDRESS - 4'b 1111, // index[ 9] OTP_CTRL_DIRECT_ACCESS_WDATA_0 - 4'b 1111, // index[10] OTP_CTRL_DIRECT_ACCESS_WDATA_1 - 4'b 1111, // index[11] OTP_CTRL_DIRECT_ACCESS_RDATA_0 - 4'b 1111, // index[12] OTP_CTRL_DIRECT_ACCESS_RDATA_1 - 4'b 0001, // index[13] OTP_CTRL_CHECK_TRIGGER_REGWEN - 4'b 0001, // index[14] OTP_CTRL_CHECK_TRIGGER - 4'b 0001, // index[15] OTP_CTRL_CHECK_REGWEN - 4'b 1111, // index[16] OTP_CTRL_CHECK_TIMEOUT - 4'b 1111, // index[17] OTP_CTRL_INTEGRITY_CHECK_PERIOD - 4'b 1111, // index[18] OTP_CTRL_CONSISTENCY_CHECK_PERIOD - 4'b 0001, // index[19] OTP_CTRL_VENDOR_TEST_READ_LOCK - 4'b 0001, // index[20] OTP_CTRL_CREATOR_SW_CFG_READ_LOCK - 4'b 0001, // index[21] OTP_CTRL_OWNER_SW_CFG_READ_LOCK - 4'b 1111, // index[22] OTP_CTRL_VENDOR_TEST_DIGEST_0 - 4'b 1111, // index[23] OTP_CTRL_VENDOR_TEST_DIGEST_1 - 4'b 1111, // index[24] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0 - 4'b 1111, // index[25] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1 - 4'b 1111, // index[26] OTP_CTRL_OWNER_SW_CFG_DIGEST_0 - 4'b 1111, // index[27] OTP_CTRL_OWNER_SW_CFG_DIGEST_1 - 4'b 1111, // index[28] OTP_CTRL_HW_CFG_DIGEST_0 - 4'b 1111, // index[29] OTP_CTRL_HW_CFG_DIGEST_1 - 4'b 1111, // index[30] OTP_CTRL_SECRET0_DIGEST_0 - 4'b 1111, // index[31] OTP_CTRL_SECRET0_DIGEST_1 - 4'b 1111, // index[32] OTP_CTRL_SECRET1_DIGEST_0 - 4'b 1111, // index[33] OTP_CTRL_SECRET1_DIGEST_1 - 4'b 1111, // index[34] OTP_CTRL_SECRET2_DIGEST_0 - 4'b 1111 // index[35] OTP_CTRL_SECRET2_DIGEST_1 + 4'b 0001, // index[ 5] OTP_CTRL_ERR_CODE_0 + 4'b 0001, // index[ 6] OTP_CTRL_ERR_CODE_1 + 4'b 0001, // index[ 7] OTP_CTRL_ERR_CODE_2 + 4'b 0001, // index[ 8] OTP_CTRL_ERR_CODE_3 + 4'b 0001, // index[ 9] OTP_CTRL_ERR_CODE_4 + 4'b 0001, // index[10] OTP_CTRL_ERR_CODE_5 + 4'b 0001, // index[11] OTP_CTRL_ERR_CODE_6 + 4'b 0001, // index[12] OTP_CTRL_ERR_CODE_7 + 4'b 0001, // index[13] OTP_CTRL_ERR_CODE_8 + 4'b 0001, // index[14] OTP_CTRL_ERR_CODE_9 + 4'b 0001, // index[15] OTP_CTRL_DIRECT_ACCESS_REGWEN + 4'b 0001, // index[16] OTP_CTRL_DIRECT_ACCESS_CMD + 4'b 0011, // index[17] OTP_CTRL_DIRECT_ACCESS_ADDRESS + 4'b 1111, // index[18] OTP_CTRL_DIRECT_ACCESS_WDATA_0 + 4'b 1111, // index[19] OTP_CTRL_DIRECT_ACCESS_WDATA_1 + 4'b 1111, // index[20] OTP_CTRL_DIRECT_ACCESS_RDATA_0 + 4'b 1111, // index[21] OTP_CTRL_DIRECT_ACCESS_RDATA_1 + 4'b 0001, // index[22] OTP_CTRL_CHECK_TRIGGER_REGWEN + 4'b 0001, // index[23] OTP_CTRL_CHECK_TRIGGER + 4'b 0001, // index[24] OTP_CTRL_CHECK_REGWEN + 4'b 1111, // index[25] OTP_CTRL_CHECK_TIMEOUT + 4'b 1111, // index[26] OTP_CTRL_INTEGRITY_CHECK_PERIOD + 4'b 1111, // index[27] OTP_CTRL_CONSISTENCY_CHECK_PERIOD + 4'b 0001, // index[28] OTP_CTRL_VENDOR_TEST_READ_LOCK + 4'b 0001, // index[29] OTP_CTRL_CREATOR_SW_CFG_READ_LOCK + 4'b 0001, // index[30] OTP_CTRL_OWNER_SW_CFG_READ_LOCK + 4'b 1111, // index[31] OTP_CTRL_VENDOR_TEST_DIGEST_0 + 4'b 1111, // index[32] OTP_CTRL_VENDOR_TEST_DIGEST_1 + 4'b 1111, // index[33] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0 + 4'b 1111, // index[34] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1 + 4'b 1111, // index[35] OTP_CTRL_OWNER_SW_CFG_DIGEST_0 + 4'b 1111, // index[36] OTP_CTRL_OWNER_SW_CFG_DIGEST_1 + 4'b 1111, // index[37] OTP_CTRL_HW_CFG_DIGEST_0 + 4'b 1111, // index[38] OTP_CTRL_HW_CFG_DIGEST_1 + 4'b 1111, // index[39] OTP_CTRL_SECRET0_DIGEST_0 + 4'b 1111, // index[40] OTP_CTRL_SECRET0_DIGEST_1 + 4'b 1111, // index[41] OTP_CTRL_SECRET1_DIGEST_0 + 4'b 1111, // index[42] OTP_CTRL_SECRET1_DIGEST_1 + 4'b 1111, // index[43] OTP_CTRL_SECRET2_DIGEST_0 + 4'b 1111 // index[44] OTP_CTRL_SECRET2_DIGEST_1 }; /////////////////////////////////////////////// diff --git a/sw/device/lib/dif/dif_otp_ctrl.c b/sw/device/lib/dif/dif_otp_ctrl.c index a6df71fd322b63..ff0aa1e0d31376 100644 --- a/sw/device/lib/dif/dif_otp_ctrl.c +++ b/sw/device/lib/dif/dif_otp_ctrl.c @@ -228,8 +228,6 @@ dif_result_t dif_otp_ctrl_get_status(const dif_otp_ctrl_t *otp, status->codes = 0; uint32_t status_code = mmio_region_read32(otp->base_addr, OTP_CTRL_STATUS_REG_OFFSET); - uint32_t error_codes = - mmio_region_read32(otp->base_addr, OTP_CTRL_ERR_CODE_REG_OFFSET); for (int i = 0; i < ARRAYSIZE(kIndices); ++i) { // If the error is not present at all, we clear its cause bit if relevant, // and bail immediately. @@ -243,103 +241,48 @@ dif_result_t dif_otp_ctrl_get_status(const dif_otp_ctrl_t *otp, status->codes = bitfield_bit32_write(status->codes, (bitfield_bit32_index_t)i, true); - bitfield_field32_t field; - switch (i) { - case kDifOtpCtrlStatusCodeVendorTestError: - field = (bitfield_field32_t){ - .mask = OTP_CTRL_ERR_CODE_ERR_CODE_0_MASK, - .index = OTP_CTRL_ERR_CODE_ERR_CODE_0_OFFSET, - }; - break; - case kDifOtpCtrlStatusCodeCreatorSwCfgError: - field = (bitfield_field32_t){ - .mask = OTP_CTRL_ERR_CODE_ERR_CODE_1_MASK, - .index = OTP_CTRL_ERR_CODE_ERR_CODE_1_OFFSET, - }; - break; - case kDifOtpCtrlStatusCodeOwnerSwCfgError: - field = (bitfield_field32_t){ - .mask = OTP_CTRL_ERR_CODE_ERR_CODE_2_MASK, - .index = OTP_CTRL_ERR_CODE_ERR_CODE_2_OFFSET, - }; - break; - case kDifOtpCtrlStatusCodeHwCfgError: - field = (bitfield_field32_t){ - .mask = OTP_CTRL_ERR_CODE_ERR_CODE_3_MASK, - .index = OTP_CTRL_ERR_CODE_ERR_CODE_3_OFFSET, - }; - break; - case kDifOtpCtrlStatusCodeSecret0Error: - field = (bitfield_field32_t){ - .mask = OTP_CTRL_ERR_CODE_ERR_CODE_4_MASK, - .index = OTP_CTRL_ERR_CODE_ERR_CODE_4_OFFSET, - }; - break; - case kDifOtpCtrlStatusCodeSecret1Error: - field = (bitfield_field32_t){ - .mask = OTP_CTRL_ERR_CODE_ERR_CODE_5_MASK, - .index = OTP_CTRL_ERR_CODE_ERR_CODE_5_OFFSET, - }; - break; - case kDifOtpCtrlStatusCodeSecret2Error: - field = (bitfield_field32_t){ - .mask = OTP_CTRL_ERR_CODE_ERR_CODE_6_MASK, - .index = OTP_CTRL_ERR_CODE_ERR_CODE_6_OFFSET, - }; - break; - case kDifOtpCtrlStatusCodeLifeCycleError: - field = (bitfield_field32_t){ - .mask = OTP_CTRL_ERR_CODE_ERR_CODE_7_MASK, - .index = OTP_CTRL_ERR_CODE_ERR_CODE_7_OFFSET, - }; - break; - case kDifOtpCtrlStatusCodeDaiError: - field = (bitfield_field32_t){ - .mask = OTP_CTRL_ERR_CODE_ERR_CODE_8_MASK, - .index = OTP_CTRL_ERR_CODE_ERR_CODE_8_OFFSET, - }; - break; - case kDifOtpCtrlStatusCodeLciError: - field = (bitfield_field32_t){ - .mask = OTP_CTRL_ERR_CODE_ERR_CODE_9_MASK, - .index = OTP_CTRL_ERR_CODE_ERR_CODE_9_OFFSET, - }; - break; - // Not an error status, so there's nothing to do. - default: - continue; - } - - dif_otp_ctrl_error_t err; - switch (bitfield_field32_read(error_codes, field)) { - case OTP_CTRL_ERR_CODE_ERR_CODE_0_VALUE_NO_ERROR: - err = kDifOtpCtrlErrorOk; - break; - case OTP_CTRL_ERR_CODE_ERR_CODE_0_VALUE_MACRO_ERROR: - err = kDifOtpCtrlErrorMacroUnspecified; - break; - case OTP_CTRL_ERR_CODE_ERR_CODE_0_VALUE_MACRO_ECC_CORR_ERROR: - err = kDifOtpCtrlErrorMacroRecoverableRead; - break; - case OTP_CTRL_ERR_CODE_ERR_CODE_0_VALUE_MACRO_ECC_UNCORR_ERROR: - err = kDifOtpCtrlErrorMacroUnrecoverableRead; - break; - case OTP_CTRL_ERR_CODE_ERR_CODE_0_VALUE_MACRO_WRITE_BLANK_ERROR: - err = kDifOtpCtrlErrorMacroBlankCheckFailed; - break; - case OTP_CTRL_ERR_CODE_ERR_CODE_0_VALUE_ACCESS_ERROR: - err = kDifOtpCtrlErrorLockedAccess; - break; - case OTP_CTRL_ERR_CODE_ERR_CODE_0_VALUE_CHECK_FAIL_ERROR: - err = kDifOtpCtrlErrorBackgroundCheckFailed; - break; - case OTP_CTRL_ERR_CODE_ERR_CODE_0_VALUE_FSM_STATE_ERROR: - err = kDifOtpCtrlErrorFsmBadState; - break; - default: - return kDifError; + if (i <= kDifOtpCtrlStatusCodeHasCauseLast) { + bitfield_field32_t field; + field = (bitfield_field32_t){ + .mask = OTP_CTRL_ERR_CODE_0_ERR_CODE_0_MASK, + .index = OTP_CTRL_ERR_CODE_0_ERR_CODE_0_OFFSET, + }; + + ptrdiff_t address = + OTP_CTRL_ERR_CODE_0_REG_OFFSET + i * (ptrdiff_t)sizeof(uint32_t); + uint32_t error_code = mmio_region_read32(otp->base_addr, address); + + dif_otp_ctrl_error_t err; + switch (bitfield_field32_read(error_code, field)) { + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_NO_ERROR: + err = kDifOtpCtrlErrorOk; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ERROR: + err = kDifOtpCtrlErrorMacroUnspecified; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ECC_CORR_ERROR: + err = kDifOtpCtrlErrorMacroRecoverableRead; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ECC_UNCORR_ERROR: + err = kDifOtpCtrlErrorMacroUnrecoverableRead; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_WRITE_BLANK_ERROR: + err = kDifOtpCtrlErrorMacroBlankCheckFailed; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_ACCESS_ERROR: + err = kDifOtpCtrlErrorLockedAccess; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_CHECK_FAIL_ERROR: + err = kDifOtpCtrlErrorBackgroundCheckFailed; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_FSM_STATE_ERROR: + err = kDifOtpCtrlErrorFsmBadState; + break; + default: + return kDifError; + } + status->causes[i] = err; } - status->causes[i] = err; } return kDifOk; diff --git a/sw/device/lib/dif/dif_otp_ctrl_unittest.cc b/sw/device/lib/dif/dif_otp_ctrl_unittest.cc index 4839eaa27bc1d4..4e0ab81405051d 100644 --- a/sw/device/lib/dif/dif_otp_ctrl_unittest.cc +++ b/sw/device/lib/dif/dif_otp_ctrl_unittest.cc @@ -218,7 +218,6 @@ TEST_F(StatusTest, Idle) { EXPECT_READ32(OTP_CTRL_STATUS_REG_OFFSET, {{OTP_CTRL_STATUS_DAI_IDLE_BIT, true}}); - EXPECT_READ32(OTP_CTRL_ERR_CODE_REG_OFFSET, 0); EXPECT_DIF_OK(dif_otp_ctrl_get_status(&otp_, &status)); EXPECT_EQ(status.codes, 1 << kDifOtpCtrlStatusCodeDaiIdle); @@ -235,11 +234,12 @@ TEST_F(StatusTest, Errors) { {OTP_CTRL_STATUS_LCI_ERROR_BIT, true}, }); - EXPECT_READ32(OTP_CTRL_ERR_CODE_REG_OFFSET, - {{OTP_CTRL_ERR_CODE_ERR_CODE_3_OFFSET, - OTP_CTRL_ERR_CODE_ERR_CODE_0_VALUE_MACRO_ECC_CORR_ERROR}, - {OTP_CTRL_ERR_CODE_ERR_CODE_9_OFFSET, - OTP_CTRL_ERR_CODE_ERR_CODE_0_VALUE_MACRO_ERROR}}); + EXPECT_READ32(OTP_CTRL_ERR_CODE_3_REG_OFFSET, + {{OTP_CTRL_ERR_CODE_0_ERR_CODE_0_OFFSET, + OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ECC_CORR_ERROR}}); + EXPECT_READ32(OTP_CTRL_ERR_CODE_9_REG_OFFSET, + {{OTP_CTRL_ERR_CODE_0_ERR_CODE_0_OFFSET, + OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ERROR}}); EXPECT_DIF_OK(dif_otp_ctrl_get_status(&otp_, &status)); EXPECT_EQ(status.codes, (1 << kDifOtpCtrlStatusCodeDaiIdle) | diff --git a/sw/host/opentitanlib/src/dif/otp_ctrl.rs b/sw/host/opentitanlib/src/dif/otp_ctrl.rs index 2183c27574a3db..dde0676bc986d5 100644 --- a/sw/host/opentitanlib/src/dif/otp_ctrl.rs +++ b/sw/host/opentitanlib/src/dif/otp_ctrl.rs @@ -19,7 +19,16 @@ pub enum OtpCtrlReg { IntrTest = dif::OTP_CTRL_INTR_TEST_REG_OFFSET, AlertTest = dif::OTP_CTRL_ALERT_TEST_REG_OFFSET, Status = dif::OTP_CTRL_STATUS_REG_OFFSET, - ErrCode = dif::OTP_CTRL_ERR_CODE_REG_OFFSET, + ErrCode0 = dif::OTP_CTRL_ERR_CODE_0_REG_OFFSET, + ErrCode1 = dif::OTP_CTRL_ERR_CODE_1_REG_OFFSET, + ErrCode2 = dif::OTP_CTRL_ERR_CODE_2_REG_OFFSET, + ErrCode3 = dif::OTP_CTRL_ERR_CODE_3_REG_OFFSET, + ErrCode4 = dif::OTP_CTRL_ERR_CODE_4_REG_OFFSET, + ErrCode5 = dif::OTP_CTRL_ERR_CODE_5_REG_OFFSET, + ErrCode6 = dif::OTP_CTRL_ERR_CODE_6_REG_OFFSET, + ErrCode7 = dif::OTP_CTRL_ERR_CODE_7_REG_OFFSET, + ErrCode8 = dif::OTP_CTRL_ERR_CODE_8_REG_OFFSET, + ErrCode9 = dif::OTP_CTRL_ERR_CODE_9_REG_OFFSET, DirectAccessRegwen = dif::OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, DirectAccessCmd = dif::OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, DirectAccessAddress = dif::OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET,