From b5189862fc529ed9641d1204bf5359f9f9a1f8a6 Mon Sep 17 00:00:00 2001 From: Robert Schilling Date: Tue, 14 May 2024 21:11:32 +0200 Subject: [PATCH] [topgen] Improve support for multiple address spaces Individually generate C and Rust collateral for all address spaces Signed-off-by: Robert Schilling --- .../data/autogen/top_darjeeling.gen.hjson | 1 + hw/top_darjeeling/data/top_darjeeling.hjson | 2 +- hw/top_darjeeling/data/xbar_second.hjson | 70 ++++++ .../rtl/autogen/top_darjeeling_soc_dbg_pkg.sv | 46 ++++ .../rtl/autogen/top_darjeeling_soc_mbx_pkg.sv | 106 +++++++++ hw/top_darjeeling/sw/autogen/chip/mod.rs | 4 + .../sw/autogen/chip/top_darjeeling_soc_dbg.rs | 71 ++++++ .../chip/top_darjeeling_soc_dbg_memory.rs | 62 +++++ .../sw/autogen/chip/top_darjeeling_soc_mbx.rs | 149 +++++++++++++ .../chip/top_darjeeling_soc_mbx_memory.rs | 140 ++++++++++++ hw/top_darjeeling/sw/autogen/top_darjeeling.c | 1 + .../sw/autogen/top_darjeeling_soc_dbg.c | 6 + .../sw/autogen/top_darjeeling_soc_dbg.h | 103 +++++++++ .../autogen/top_darjeeling_soc_dbg_memory.h | 92 ++++++++ .../sw/autogen/top_darjeeling_soc_mbx.c | 6 + .../sw/autogen/top_darjeeling_soc_mbx.h | 211 ++++++++++++++++++ .../autogen/top_darjeeling_soc_mbx_memory.h | 194 ++++++++++++++++ .../data/autogen/top_earlgrey.gen.hjson | 1 + hw/top_earlgrey/data/top_earlgrey.hjson | 2 +- hw/top_earlgrey/sw/autogen/top_earlgrey.c | 1 + util/topgen.py | 209 +++++++++-------- util/topgen/c.py | 13 +- util/topgen/c_test.py | 8 +- util/topgen/rust.py | 13 +- util/topgen/templates/toplevel.c.tpl | 4 +- util/topgen/templates/toplevel.h.tpl | 2 + util/topgen/templates/toplevel.rs.tpl | 2 + util/topgen/templates/toplevel_mod.rs.tpl | 10 +- util/topgen/templates/toplevel_pkg.sv.tpl | 2 + 29 files changed, 1424 insertions(+), 107 deletions(-) create mode 100644 hw/top_darjeeling/data/xbar_second.hjson create mode 100644 hw/top_darjeeling/rtl/autogen/top_darjeeling_soc_dbg_pkg.sv create mode 100644 hw/top_darjeeling/rtl/autogen/top_darjeeling_soc_mbx_pkg.sv create mode 100644 hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_dbg.rs create mode 100644 hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_dbg_memory.rs create mode 100644 hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_mbx.rs create mode 100644 hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_mbx_memory.rs create mode 100644 hw/top_darjeeling/sw/autogen/top_darjeeling_soc_dbg.c create mode 100644 hw/top_darjeeling/sw/autogen/top_darjeeling_soc_dbg.h create mode 100644 hw/top_darjeeling/sw/autogen/top_darjeeling_soc_dbg_memory.h create mode 100644 hw/top_darjeeling/sw/autogen/top_darjeeling_soc_mbx.c create mode 100644 hw/top_darjeeling/sw/autogen/top_darjeeling_soc_mbx.h create mode 100644 hw/top_darjeeling/sw/autogen/top_darjeeling_soc_mbx_memory.h diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson index 226faefaad6a09..8a5078ba571134 100644 --- a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson @@ -454,6 +454,7 @@ { name: hart desc: The main address space, shared between the CPU and DM + default: true } { name: soc_mbx diff --git a/hw/top_darjeeling/data/top_darjeeling.hjson b/hw/top_darjeeling/data/top_darjeeling.hjson index ec2c11cc675a83..de91449fb9babe 100644 --- a/hw/top_darjeeling/data/top_darjeeling.hjson +++ b/hw/top_darjeeling/data/top_darjeeling.hjson @@ -166,7 +166,7 @@ // all peripherals, though not every peripheral will be accessible to every // host in that address space--Access privileges are separate from addresses. addr_spaces: [ - { name: "hart", desc: "The main address space, shared between the CPU and DM"}, + { name: "hart", desc: "The main address space, shared between the CPU and DM", default: true}, { name: "soc_mbx", desc: "SoC address space for mailbox access"}, { name: "soc_dbg", desc: "SoC address space for debug module interfaces"}, ] diff --git a/hw/top_darjeeling/data/xbar_second.hjson b/hw/top_darjeeling/data/xbar_second.hjson new file mode 100644 index 00000000000000..3ed6e26b0b7227 --- /dev/null +++ b/hw/top_darjeeling/data/xbar_second.hjson @@ -0,0 +1,70 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ name: "second", + type: "xbar", + clock_primary: "clk_main_i", // Main clock, used in sockets + other_clock_list: [ "clk_fixed_i", "clk_usb_i"] // Secondary clocks used by specific nodes + reset_primary: "rst_main_ni", // Main reset, used in sockets + other_reset_list: [ "rst_fixed_ni", "rst_usb_ni"] // Secondary resets used by specific nodes + + // Rationale for pipeline and req/rsp_fifo_pass: + // For host interfaces that are used during production state (corei/cored), + // minimize the amount of host introduced latency. This is accomplished + // by setting pipeline to false. + // For host interfaces that are only used for debug, relax the timing by + // inserting a register slice and not allowing passthrough (more access + // latency. This is accomplished by setting `req/rsp_fifo_pass` to false, + // and implicitly using the default of pipeline true. + // + // For device interfaces, especially configuration registers, latency is + // not generally a concern, thus use `req/rsp_fifo_pass` false and pipeline + // true. + // For device accesses to memories (ram / rom / flash), performance is a concern, + // so use pipeline false where permissible by timing. If not, find a combination + // that works. + nodes: [ + { name: "rv_core_ibex_second.corei", + type: "host", + addr_space: "hart_second", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false + }, + { name: "rv_core_ibex_second.cored", + type: "host", + addr_space: "hart_second", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false + }, + { name: "rv_core_ibex_second.cfg", + type: "device", + clock: "clk_main_i" + reset: "rst_main_ni" + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "sram_ctrl_second.regs", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "sram_ctrl_second.ram", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false + }, + ], + connections: { + // TODO: remove rv_core_ibex_second.corei - sram_ctrl_second.ram connection + rv_core_ibex_second.corei: ["sram_ctrl_second.ram"], + rv_core_ibex_second.cored: [ + "sram_ctrl_second.ram", "sram_ctrl_second.regs", + "rv_core_ibex_second.cfg" + ] + }, +} diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling_soc_dbg_pkg.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling_soc_dbg_pkg.sv new file mode 100644 index 00000000000000..cb8142e1a6bafd --- /dev/null +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling_soc_dbg_pkg.sv @@ -0,0 +1,46 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson \ +// -o hw/top_darjeeling/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + +package top_darjeeling_pkg; + /** + * Peripheral base address for dmi device on lc_ctrl in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR = 32'h20000; + + /** + * Peripheral size in bytes for dmi device on lc_ctrl in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES = 32'h1000; + + /** + * Peripheral base address for dbg device on rv_dm in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RV_DM_DBG_BASE_ADDR = 32'h0; + + /** + * Peripheral size in bytes for dbg device on rv_dm in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES = 32'h200; + + /** + * Peripheral base address for soc device on mbx_jtag in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR = 32'h1000; + + /** + * Peripheral size in bytes for soc device on mbx_jtag in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES = 32'h20; + + + +endpackage diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling_soc_mbx_pkg.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling_soc_mbx_pkg.sv new file mode 100644 index 00000000000000..118a9095151d01 --- /dev/null +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling_soc_mbx_pkg.sv @@ -0,0 +1,106 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson \ +// -o hw/top_darjeeling/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + +package top_darjeeling_pkg; + /** + * Peripheral base address for soc device on mbx0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX0_SOC_BASE_ADDR = 32'h1465000; + + /** + * Peripheral size in bytes for soc device on mbx0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX0_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for soc device on mbx1 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX1_SOC_BASE_ADDR = 32'h1465100; + + /** + * Peripheral size in bytes for soc device on mbx1 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX1_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for soc device on mbx2 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX2_SOC_BASE_ADDR = 32'h1465200; + + /** + * Peripheral size in bytes for soc device on mbx2 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX2_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for soc device on mbx3 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX3_SOC_BASE_ADDR = 32'h1465300; + + /** + * Peripheral size in bytes for soc device on mbx3 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX3_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for soc device on mbx4 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX4_SOC_BASE_ADDR = 32'h1465400; + + /** + * Peripheral size in bytes for soc device on mbx4 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX4_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for soc device on mbx5 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX5_SOC_BASE_ADDR = 32'h1465500; + + /** + * Peripheral size in bytes for soc device on mbx5 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX5_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for soc device on mbx6 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX6_SOC_BASE_ADDR = 32'h1465600; + + /** + * Peripheral size in bytes for soc device on mbx6 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX6_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for soc device on mbx_pcie0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR = 32'h1460100; + + /** + * Peripheral size in bytes for soc device on mbx_pcie0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for soc device on mbx_pcie1 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR = 32'h1460200; + + /** + * Peripheral size in bytes for soc device on mbx_pcie1 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES = 32'h20; + + + +endpackage diff --git a/hw/top_darjeeling/sw/autogen/chip/mod.rs b/hw/top_darjeeling/sw/autogen/chip/mod.rs index 3964c8cd116472..05a5abe61af5ee 100644 --- a/hw/top_darjeeling/sw/autogen/chip/mod.rs +++ b/hw/top_darjeeling/sw/autogen/chip/mod.rs @@ -4,3 +4,7 @@ pub mod top_darjeeling; pub mod top_darjeeling_memory; +pub mod top_darjeeling_soc_mbx; +pub mod top_darjeeling_soc_mbx_memory; +pub mod top_darjeeling_soc_dbg; +pub mod top_darjeeling_soc_dbg_memory; diff --git a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_dbg.rs b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_dbg.rs new file mode 100644 index 00000000000000..5408bdb8f34e86 --- /dev/null +++ b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_dbg.rs @@ -0,0 +1,71 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file was generated automatically. +// Please do not modify content of this file directly. +// File generated by using template: "toplevel.rs.tpl" +// To regenerate this file follow OpenTitan topgen documentations. + +#![allow(dead_code)] + +//! This file contains enums and consts for use within the Rust codebase. +//! +//! These definitions are for information that depends on the top-specific chip +//! configuration, which includes: +//! - Device Memory Information (for Peripherals and Memory) +//! - PLIC Interrupt ID Names and Source Mappings +//! - Alert ID Names and Source Mappings +//! - Pinmux Pin/Select Names +//! - Power Manager Wakeups + +use core::convert::TryFrom; + +/// Peripheral base address for dmi device on lc_ctrl in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR: usize = 0x20000; + +/// Peripheral size for dmi device on lc_ctrl in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR and +/// `TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR + TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES`. +pub const TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES: usize = 0x1000; +/// Peripheral base address for dbg device on rv_dm in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_RV_DM_DBG_BASE_ADDR: usize = 0x0; + +/// Peripheral size for dbg device on rv_dm in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_RV_DM_DBG_BASE_ADDR and +/// `TOP_DARJEELING_RV_DM_DBG_BASE_ADDR + TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES`. +pub const TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES: usize = 0x200; +/// Peripheral base address for soc device on mbx_jtag in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR: usize = 0x1000; + +/// Peripheral size for soc device on mbx_jtag in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES: usize = 0x20; + + +/// MMIO Region +/// +/// MMIO region excludes any memory that is separate from the module +/// configuration space, i.e. ROM, main SRAM, and flash are excluded but +/// retention SRAM, spi_device memory, or usbdev memory are included. +pub const TOP_DARJEELING_MMIO_BASE_ADDR: usize = 0x1000; +pub const TOP_DARJEELING_MMIO_SIZE_BYTES: usize = 0x20000; diff --git a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_dbg_memory.rs b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_dbg_memory.rs new file mode 100644 index 00000000000000..9416878f7a5167 --- /dev/null +++ b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_dbg_memory.rs @@ -0,0 +1,62 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file was generated automatically. +// Please do not modify content of this file directly. +// File generated by using template: "toplevel_memory.rs.tpl" +// To regenerate this file follow OpenTitan topgen documentations. + +#![allow(dead_code)] + +//! Rust Top-Specific Definitions. +//! +//! This file contains const definitions for use within Rust code. + +/// Peripheral base address for dmi device on lc_ctrl in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR: usize = 0x20000; + +/// Peripheral size for dmi device on lc_ctrl in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR and +/// `TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR + TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES`. +pub const TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES: usize = 0x1000; +/// Peripheral base address for dbg device on rv_dm in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_RV_DM_DBG_BASE_ADDR: usize = 0x0; + +/// Peripheral size for dbg device on rv_dm in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_RV_DM_DBG_BASE_ADDR and +/// `TOP_DARJEELING_RV_DM_DBG_BASE_ADDR + TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES`. +pub const TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES: usize = 0x200; +/// Peripheral base address for soc device on mbx_jtag in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR: usize = 0x1000; + +/// Peripheral size for soc device on mbx_jtag in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES: usize = 0x20; + +/// MMIO Region +/// +/// MMIO region excludes any memory that is separate from the module +/// configuration space, i.e. ROM, main SRAM, and flash are excluded but +/// retention SRAM, spi_device memory, or usbdev memory are included. +pub const TOP_DARJEELING_MMIO_BASE_ADDR: usize = 0x1000; +pub const TOP_DARJEELING_MMIO_SIZE_BYTES: usize = 0x20000; diff --git a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_mbx.rs b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_mbx.rs new file mode 100644 index 00000000000000..49ee137dbac635 --- /dev/null +++ b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_mbx.rs @@ -0,0 +1,149 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file was generated automatically. +// Please do not modify content of this file directly. +// File generated by using template: "toplevel.rs.tpl" +// To regenerate this file follow OpenTitan topgen documentations. + +#![allow(dead_code)] + +//! This file contains enums and consts for use within the Rust codebase. +//! +//! These definitions are for information that depends on the top-specific chip +//! configuration, which includes: +//! - Device Memory Information (for Peripherals and Memory) +//! - PLIC Interrupt ID Names and Source Mappings +//! - Alert ID Names and Source Mappings +//! - Pinmux Pin/Select Names +//! - Power Manager Wakeups + +use core::convert::TryFrom; + +/// Peripheral base address for soc device on mbx0 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX0_SOC_BASE_ADDR: usize = 0x1465000; + +/// Peripheral size for soc device on mbx0 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX0_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX0_SOC_BASE_ADDR + TOP_DARJEELING_MBX0_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX0_SOC_SIZE_BYTES: usize = 0x20; +/// Peripheral base address for soc device on mbx1 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX1_SOC_BASE_ADDR: usize = 0x1465100; + +/// Peripheral size for soc device on mbx1 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX1_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX1_SOC_BASE_ADDR + TOP_DARJEELING_MBX1_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX1_SOC_SIZE_BYTES: usize = 0x20; +/// Peripheral base address for soc device on mbx2 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX2_SOC_BASE_ADDR: usize = 0x1465200; + +/// Peripheral size for soc device on mbx2 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX2_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX2_SOC_BASE_ADDR + TOP_DARJEELING_MBX2_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX2_SOC_SIZE_BYTES: usize = 0x20; +/// Peripheral base address for soc device on mbx3 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX3_SOC_BASE_ADDR: usize = 0x1465300; + +/// Peripheral size for soc device on mbx3 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX3_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX3_SOC_BASE_ADDR + TOP_DARJEELING_MBX3_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX3_SOC_SIZE_BYTES: usize = 0x20; +/// Peripheral base address for soc device on mbx4 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX4_SOC_BASE_ADDR: usize = 0x1465400; + +/// Peripheral size for soc device on mbx4 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX4_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX4_SOC_BASE_ADDR + TOP_DARJEELING_MBX4_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX4_SOC_SIZE_BYTES: usize = 0x20; +/// Peripheral base address for soc device on mbx5 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX5_SOC_BASE_ADDR: usize = 0x1465500; + +/// Peripheral size for soc device on mbx5 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX5_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX5_SOC_BASE_ADDR + TOP_DARJEELING_MBX5_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX5_SOC_SIZE_BYTES: usize = 0x20; +/// Peripheral base address for soc device on mbx6 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX6_SOC_BASE_ADDR: usize = 0x1465600; + +/// Peripheral size for soc device on mbx6 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX6_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX6_SOC_BASE_ADDR + TOP_DARJEELING_MBX6_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX6_SOC_SIZE_BYTES: usize = 0x20; +/// Peripheral base address for soc device on mbx_pcie0 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR: usize = 0x1460100; + +/// Peripheral size for soc device on mbx_pcie0 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR + TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES: usize = 0x20; +/// Peripheral base address for soc device on mbx_pcie1 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR: usize = 0x1460200; + +/// Peripheral size for soc device on mbx_pcie1 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR + TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES: usize = 0x20; + + +/// MMIO Region +/// +/// MMIO region excludes any memory that is separate from the module +/// configuration space, i.e. ROM, main SRAM, and flash are excluded but +/// retention SRAM, spi_device memory, or usbdev memory are included. +pub const TOP_DARJEELING_MMIO_BASE_ADDR: usize = 0x1460100; +pub const TOP_DARJEELING_MMIO_SIZE_BYTES: usize = 0x5520; diff --git a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_mbx_memory.rs b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_mbx_memory.rs new file mode 100644 index 00000000000000..0cb35d53f73587 --- /dev/null +++ b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_mbx_memory.rs @@ -0,0 +1,140 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file was generated automatically. +// Please do not modify content of this file directly. +// File generated by using template: "toplevel_memory.rs.tpl" +// To regenerate this file follow OpenTitan topgen documentations. + +#![allow(dead_code)] + +//! Rust Top-Specific Definitions. +//! +//! This file contains const definitions for use within Rust code. + +/// Peripheral base address for soc device on mbx0 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX0_SOC_BASE_ADDR: usize = 0x1465000; + +/// Peripheral size for soc device on mbx0 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX0_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX0_SOC_BASE_ADDR + TOP_DARJEELING_MBX0_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX0_SOC_SIZE_BYTES: usize = 0x20; +/// Peripheral base address for soc device on mbx1 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX1_SOC_BASE_ADDR: usize = 0x1465100; + +/// Peripheral size for soc device on mbx1 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX1_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX1_SOC_BASE_ADDR + TOP_DARJEELING_MBX1_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX1_SOC_SIZE_BYTES: usize = 0x20; +/// Peripheral base address for soc device on mbx2 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX2_SOC_BASE_ADDR: usize = 0x1465200; + +/// Peripheral size for soc device on mbx2 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX2_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX2_SOC_BASE_ADDR + TOP_DARJEELING_MBX2_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX2_SOC_SIZE_BYTES: usize = 0x20; +/// Peripheral base address for soc device on mbx3 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX3_SOC_BASE_ADDR: usize = 0x1465300; + +/// Peripheral size for soc device on mbx3 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX3_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX3_SOC_BASE_ADDR + TOP_DARJEELING_MBX3_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX3_SOC_SIZE_BYTES: usize = 0x20; +/// Peripheral base address for soc device on mbx4 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX4_SOC_BASE_ADDR: usize = 0x1465400; + +/// Peripheral size for soc device on mbx4 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX4_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX4_SOC_BASE_ADDR + TOP_DARJEELING_MBX4_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX4_SOC_SIZE_BYTES: usize = 0x20; +/// Peripheral base address for soc device on mbx5 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX5_SOC_BASE_ADDR: usize = 0x1465500; + +/// Peripheral size for soc device on mbx5 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX5_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX5_SOC_BASE_ADDR + TOP_DARJEELING_MBX5_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX5_SOC_SIZE_BYTES: usize = 0x20; +/// Peripheral base address for soc device on mbx6 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX6_SOC_BASE_ADDR: usize = 0x1465600; + +/// Peripheral size for soc device on mbx6 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX6_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX6_SOC_BASE_ADDR + TOP_DARJEELING_MBX6_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX6_SOC_SIZE_BYTES: usize = 0x20; +/// Peripheral base address for soc device on mbx_pcie0 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR: usize = 0x1460100; + +/// Peripheral size for soc device on mbx_pcie0 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR + TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES: usize = 0x20; +/// Peripheral base address for soc device on mbx_pcie1 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR: usize = 0x1460200; + +/// Peripheral size for soc device on mbx_pcie1 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR and +/// `TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR + TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES`. +pub const TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES: usize = 0x20; + +/// MMIO Region +/// +/// MMIO region excludes any memory that is separate from the module +/// configuration space, i.e. ROM, main SRAM, and flash are excluded but +/// retention SRAM, spi_device memory, or usbdev memory are included. +pub const TOP_DARJEELING_MMIO_BASE_ADDR: usize = 0x1460100; +pub const TOP_DARJEELING_MMIO_SIZE_BYTES: usize = 0x5520; diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling.c b/hw/top_darjeeling/sw/autogen/top_darjeeling.c index 4f8608619a17b6..0ff7d42da7b417 100644 --- a/hw/top_darjeeling/sw/autogen/top_darjeeling.c +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling.c @@ -286,3 +286,4 @@ const top_darjeeling_alert_peripheral_t [kTopDarjeelingAlertIdRvCoreIbexFatalHwErr] = kTopDarjeelingAlertPeripheralRvCoreIbex, [kTopDarjeelingAlertIdRvCoreIbexRecovHwErr] = kTopDarjeelingAlertPeripheralRvCoreIbex, }; + diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_dbg.c b/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_dbg.c new file mode 100644 index 00000000000000..947486f67ca058 --- /dev/null +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_dbg.c @@ -0,0 +1,6 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "hw/top_darjeeling/sw/autogen/top_darjeeling_soc_dbg.h" + diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_dbg.h b/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_dbg.h new file mode 100644 index 00000000000000..8c458dfb10eb7c --- /dev/null +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_dbg.h @@ -0,0 +1,103 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef OPENTITAN_SOC_DBG_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_H_ +#define OPENTITAN_SOC_DBG_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_H_ + +#include "top_darjeeling_flash_ctrl_dummy.h" +#include "top_darjeeling_keymgr_dummy.h" + +/** + * @file + * @brief Top-specific Definitions + * + * This file contains preprocessor and type definitions for use within the + * device C/C++ codebase. + * + * These definitions are for information that depends on the top-specific chip + * configuration, which includes: + * - Device Memory Information (for Peripherals and Memory) + * - PLIC Interrupt ID Names and Source Mappings + * - Alert ID Names and Source Mappings + * - Pinmux Pin/Select Names + * - Power Manager Wakeups + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Peripheral base address for dmi device on lc_ctrl in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR 0x20000u + +/** + * Peripheral size for dmi device on lc_ctrl in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR and + * `TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR + TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES`. + */ +#define TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES 0x1000u + +/** + * Peripheral base address for dbg device on rv_dm in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_RV_DM_DBG_BASE_ADDR 0x0u + +/** + * Peripheral size for dbg device on rv_dm in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_RV_DM_DBG_BASE_ADDR and + * `TOP_DARJEELING_RV_DM_DBG_BASE_ADDR + TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES`. + */ +#define TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES 0x200u + +/** + * Peripheral base address for soc device on mbx_jtag in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR 0x1000u + +/** + * Peripheral size for soc device on mbx_jtag in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES 0x20u + + + + +/** + * MMIO Region + * + * MMIO region excludes any memory that is separate from the module + * configuration space, i.e. ROM, main SRAM, and flash are excluded but + * retention SRAM, spi_device memory, or usbdev memory are included. + */ +#define TOP_DARJEELING_MMIO_BASE_ADDR 0x1000u +#define TOP_DARJEELING_MMIO_SIZE_BYTES 0x20000u + +// Header Extern Guard +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // OPENTITAN_SOC_DBG_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_H_ diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_dbg_memory.h b/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_dbg_memory.h new file mode 100644 index 00000000000000..d4f97e96ffbc08 --- /dev/null +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_dbg_memory.h @@ -0,0 +1,92 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef OPENTITAN_SOC_DBG_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_MEMORY_H_ +#define OPENTITAN_SOC_DBG_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_MEMORY_H_ + +#include "top_darjeeling_flash_ctrl_dummy.h" +#include "top_darjeeling_keymgr_dummy.h" + +/** + * @file + * @brief Assembler-only Top-Specific Definitions. + * + * This file contains preprocessor definitions for use within assembly code. + * + * These are not shared with C/C++ code because these are only allowed to be + * preprocessor definitions, no data or type declarations are allowed. The + * assembler is also stricter about literals (not allowing suffixes for + * signed/unsigned which are sensible to use for unsigned values in C/C++). + */ + +// Include guard for assembler +#ifdef __ASSEMBLER__ + + + +/** + * Peripheral base address for dmi device on lc_ctrl in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR 0x20000 + +/** + * Peripheral size for dmi device on lc_ctrl in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR and + * `TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR + TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES`. + */ +#define TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES 0x1000 +/** + * Peripheral base address for dbg device on rv_dm in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_RV_DM_DBG_BASE_ADDR 0x0 + +/** + * Peripheral size for dbg device on rv_dm in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_RV_DM_DBG_BASE_ADDR and + * `TOP_DARJEELING_RV_DM_DBG_BASE_ADDR + TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES`. + */ +#define TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES 0x200 +/** + * Peripheral base address for soc device on mbx_jtag in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR 0x1000 + +/** + * Peripheral size for soc device on mbx_jtag in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES 0x20 + +/** + * MMIO Region + * + * MMIO region excludes any memory that is separate from the module + * configuration space, i.e. ROM, main SRAM, and flash are excluded but + * retention SRAM, spi_device memory, or usbdev memory are included. + */ +#define TOP_DARJEELING_MMIO_BASE_ADDR 0x1000 +#define TOP_DARJEELING_MMIO_SIZE_BYTES 0x20000 + +#endif // __ASSEMBLER__ + +#endif // OPENTITAN_SOC_DBG_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_MEMORY_H_ diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_mbx.c b/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_mbx.c new file mode 100644 index 00000000000000..09ee787e4c9f69 --- /dev/null +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_mbx.c @@ -0,0 +1,6 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "hw/top_darjeeling/sw/autogen/top_darjeeling_soc_mbx.h" + diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_mbx.h b/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_mbx.h new file mode 100644 index 00000000000000..5e2133836b13ca --- /dev/null +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_mbx.h @@ -0,0 +1,211 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef OPENTITAN_SOC_MBX_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_H_ +#define OPENTITAN_SOC_MBX_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_H_ + +#include "top_darjeeling_flash_ctrl_dummy.h" +#include "top_darjeeling_keymgr_dummy.h" + +/** + * @file + * @brief Top-specific Definitions + * + * This file contains preprocessor and type definitions for use within the + * device C/C++ codebase. + * + * These definitions are for information that depends on the top-specific chip + * configuration, which includes: + * - Device Memory Information (for Peripherals and Memory) + * - PLIC Interrupt ID Names and Source Mappings + * - Alert ID Names and Source Mappings + * - Pinmux Pin/Select Names + * - Power Manager Wakeups + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Peripheral base address for soc device on mbx0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX0_SOC_BASE_ADDR 0x1465000u + +/** + * Peripheral size for soc device on mbx0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX0_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX0_SOC_BASE_ADDR + TOP_DARJEELING_MBX0_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX0_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for soc device on mbx1 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX1_SOC_BASE_ADDR 0x1465100u + +/** + * Peripheral size for soc device on mbx1 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX1_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX1_SOC_BASE_ADDR + TOP_DARJEELING_MBX1_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX1_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for soc device on mbx2 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX2_SOC_BASE_ADDR 0x1465200u + +/** + * Peripheral size for soc device on mbx2 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX2_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX2_SOC_BASE_ADDR + TOP_DARJEELING_MBX2_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX2_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for soc device on mbx3 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX3_SOC_BASE_ADDR 0x1465300u + +/** + * Peripheral size for soc device on mbx3 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX3_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX3_SOC_BASE_ADDR + TOP_DARJEELING_MBX3_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX3_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for soc device on mbx4 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX4_SOC_BASE_ADDR 0x1465400u + +/** + * Peripheral size for soc device on mbx4 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX4_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX4_SOC_BASE_ADDR + TOP_DARJEELING_MBX4_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX4_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for soc device on mbx5 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX5_SOC_BASE_ADDR 0x1465500u + +/** + * Peripheral size for soc device on mbx5 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX5_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX5_SOC_BASE_ADDR + TOP_DARJEELING_MBX5_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX5_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for soc device on mbx6 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX6_SOC_BASE_ADDR 0x1465600u + +/** + * Peripheral size for soc device on mbx6 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX6_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX6_SOC_BASE_ADDR + TOP_DARJEELING_MBX6_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX6_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for soc device on mbx_pcie0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR 0x1460100u + +/** + * Peripheral size for soc device on mbx_pcie0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR + TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for soc device on mbx_pcie1 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR 0x1460200u + +/** + * Peripheral size for soc device on mbx_pcie1 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR + TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES 0x20u + + + + +/** + * MMIO Region + * + * MMIO region excludes any memory that is separate from the module + * configuration space, i.e. ROM, main SRAM, and flash are excluded but + * retention SRAM, spi_device memory, or usbdev memory are included. + */ +#define TOP_DARJEELING_MMIO_BASE_ADDR 0x1460100u +#define TOP_DARJEELING_MMIO_SIZE_BYTES 0x5520u + +// Header Extern Guard +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // OPENTITAN_SOC_MBX_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_H_ diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_mbx_memory.h b/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_mbx_memory.h new file mode 100644 index 00000000000000..d0d03d4527e026 --- /dev/null +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling_soc_mbx_memory.h @@ -0,0 +1,194 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef OPENTITAN_SOC_MBX_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_MEMORY_H_ +#define OPENTITAN_SOC_MBX_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_MEMORY_H_ + +#include "top_darjeeling_flash_ctrl_dummy.h" +#include "top_darjeeling_keymgr_dummy.h" + +/** + * @file + * @brief Assembler-only Top-Specific Definitions. + * + * This file contains preprocessor definitions for use within assembly code. + * + * These are not shared with C/C++ code because these are only allowed to be + * preprocessor definitions, no data or type declarations are allowed. The + * assembler is also stricter about literals (not allowing suffixes for + * signed/unsigned which are sensible to use for unsigned values in C/C++). + */ + +// Include guard for assembler +#ifdef __ASSEMBLER__ + + + +/** + * Peripheral base address for soc device on mbx0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX0_SOC_BASE_ADDR 0x1465000 + +/** + * Peripheral size for soc device on mbx0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX0_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX0_SOC_BASE_ADDR + TOP_DARJEELING_MBX0_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX0_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for soc device on mbx1 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX1_SOC_BASE_ADDR 0x1465100 + +/** + * Peripheral size for soc device on mbx1 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX1_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX1_SOC_BASE_ADDR + TOP_DARJEELING_MBX1_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX1_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for soc device on mbx2 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX2_SOC_BASE_ADDR 0x1465200 + +/** + * Peripheral size for soc device on mbx2 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX2_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX2_SOC_BASE_ADDR + TOP_DARJEELING_MBX2_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX2_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for soc device on mbx3 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX3_SOC_BASE_ADDR 0x1465300 + +/** + * Peripheral size for soc device on mbx3 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX3_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX3_SOC_BASE_ADDR + TOP_DARJEELING_MBX3_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX3_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for soc device on mbx4 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX4_SOC_BASE_ADDR 0x1465400 + +/** + * Peripheral size for soc device on mbx4 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX4_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX4_SOC_BASE_ADDR + TOP_DARJEELING_MBX4_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX4_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for soc device on mbx5 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX5_SOC_BASE_ADDR 0x1465500 + +/** + * Peripheral size for soc device on mbx5 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX5_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX5_SOC_BASE_ADDR + TOP_DARJEELING_MBX5_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX5_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for soc device on mbx6 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX6_SOC_BASE_ADDR 0x1465600 + +/** + * Peripheral size for soc device on mbx6 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX6_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX6_SOC_BASE_ADDR + TOP_DARJEELING_MBX6_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX6_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for soc device on mbx_pcie0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR 0x1460100 + +/** + * Peripheral size for soc device on mbx_pcie0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR + TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for soc device on mbx_pcie1 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR 0x1460200 + +/** + * Peripheral size for soc device on mbx_pcie1 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR and + * `TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR + TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES 0x20 + +/** + * MMIO Region + * + * MMIO region excludes any memory that is separate from the module + * configuration space, i.e. ROM, main SRAM, and flash are excluded but + * retention SRAM, spi_device memory, or usbdev memory are included. + */ +#define TOP_DARJEELING_MMIO_BASE_ADDR 0x1460100 +#define TOP_DARJEELING_MMIO_SIZE_BYTES 0x5520 + +#endif // __ASSEMBLER__ + +#endif // OPENTITAN_SOC_MBX_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_MEMORY_H_ diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index c82d7060678c78..a63d07b36f4286 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -524,6 +524,7 @@ { name: hart desc: The main address space, shared between the CPU and DM + default: true } ] module: diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index fe30cc4ed34803..1678ab05ea910c 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson @@ -171,7 +171,7 @@ // all peripherals, though not every peripheral will be accessible to every // host in that address space--Access privileges are separate from addresses. addr_spaces: [ - { name: "hart", desc: "The main address space, shared between the CPU and DM"}, + { name: "hart", desc: "The main address space, shared between the CPU and DM", default: true}, ] // `module` defines the peripherals. diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c index cc192afa80284f..0b3aff0eba01c0 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c @@ -274,3 +274,4 @@ const top_earlgrey_alert_peripheral_t [kTopEarlgreyAlertIdRvCoreIbexFatalHwErr] = kTopEarlgreyAlertPeripheralRvCoreIbex, [kTopEarlgreyAlertIdRvCoreIbexRecovHwErr] = kTopEarlgreyAlertPeripheralRvCoreIbex, }; + diff --git a/util/topgen.py b/util/topgen.py index e442352d14d8dd..ec4879f248f29b 100755 --- a/util/topgen.py +++ b/util/topgen.py @@ -776,30 +776,38 @@ def render_template(template_path: str, rendered_path: Path, **other_info): with rendered_path.open(mode="w", encoding="UTF-8") as fout: fout.write(template_contents) - # The Rust file needs some complex information, so we initialize this - # object to store it. - rs_helper = TopGenRust(completecfg, name_to_block, version_stamp) + for addr_space in completecfg['addr_spaces']: + default_addr_space = addr_space.get('default', False) - rust_files = [("toplevel_mod.rs.tpl", "mod.rs"), - ("toplevel.rs.tpl", f"top_{topname}.rs"), - ("toplevel_memory.rs.tpl", f"top_{topname}_memory.rs")] + addr_space_suffix = "" + if not default_addr_space: + addr_space_suffix = "_" + addr_space['name'] - # Creating Rust output directory - rsformat_dir = out_path / "sw/autogen/chip/" - rsformat_dir.mkdir(parents=True, exist_ok=True) + # The Rust file needs some complex information, so we initialize this + # object to store it. + rs_helper = TopGenRust(completecfg, name_to_block, version_stamp, addr_space['name']) + + rust_files = [("toplevel_mod.rs.tpl", "mod.rs"), + ("toplevel.rs.tpl", f"top_{topname}{addr_space_suffix}.rs"), + ("toplevel_memory.rs.tpl", f"top_{topname}{addr_space_suffix}_memory.rs")] - # Generating Rust device description for external sw usage - for (template, source) in rust_files: - render_template(topgen_template_path / template, - rsformat_dir / source, - helper=rs_helper) + # Creating Rust output directory + rsformat_dir = out_path / "sw/autogen/chip/" + rsformat_dir.mkdir(parents=True, exist_ok=True) - # Generating Rust host-side files - rsformat_dir = src_tree_top / "sw/host/opentitanlib/src/chip/autogen" - rsformat_dir.mkdir(parents=True, exist_ok=True) - render_template(topgen_template_path / "host_toplevel.rs.tpl", - rsformat_dir / f"{topname}.rs", - helper=rs_helper) + # Generating Rust device description for external sw usage + for (template, source) in rust_files: + render_template(topgen_template_path / template, + rsformat_dir / source, + helper=rs_helper) + + if default_addr_space: + # Generating Rust host-side files + rsformat_dir = src_tree_top / "sw/host/opentitanlib/src/chip/autogen" + rsformat_dir.mkdir(parents=True, exist_ok=True) + render_template(topgen_template_path / "host_toplevel.rs.tpl", + rsformat_dir / f"{topname}.rs", + helper=rs_helper) def _process_top(topcfg, args, repo_top_path, out_path, pass_idx): @@ -1286,7 +1294,7 @@ def render_template(template_path: str, rendered_path: Path, fout.write(template_contents) # Header for SV files - gencmd = warnhdr + """// + gencmd_sv = warnhdr + """// // util/topgen.py -t hw/top_{topname}/data/top_{topname}.hjson \\ // -o hw/top_{topname}/ \\ // --rnd_cnst_seed \\ @@ -1297,7 +1305,7 @@ def render_template(template_path: str, rendered_path: Path, # "toplevel.sv.tpl" -> "rtl/autogen/top_{topname}.sv" render_template(TOPGEN_TEMPLATE_PATH / "toplevel.sv.tpl", out_path / f"rtl/autogen/top_{topname}.sv", - gencmd=gencmd) + gencmd=gencmd_sv) # Multiple chip-levels (ASIC, FPGA, Verilator, etc) for target in topcfg["targets"]: @@ -1305,75 +1313,95 @@ def render_template(template_path: str, rendered_path: Path, render_template(TOPGEN_TEMPLATE_PATH / "chiplevel.sv.tpl", out_path / f"rtl/autogen/chip_{topname}_{target_name}.sv", - gencmd=gencmd, + gencmd=gencmd_sv, target=target) - # The C / SV file needs some complex information, so we initialize this - # object to store it. - c_helper = TopGenCTest(completecfg, name_to_block) - - # "toplevel_pkg.sv.tpl" -> "rtl/autogen/top_{topname}_pkg.sv" - render_template(TOPGEN_TEMPLATE_PATH / "toplevel_pkg.sv.tpl", - out_path / f"rtl/autogen/top_{topname}_pkg.sv", - helper=c_helper, - gencmd=gencmd) - # compile-time random netlist constants render_template(TOPGEN_TEMPLATE_PATH / "toplevel_rnd_cnst_pkg.sv.tpl", out_path / f"rtl/autogen/top_{topname}_rnd_cnst_pkg.sv", - gencmd=gencmd) - - # Since SW does not use FuseSoC and instead expects those files always - # to be in hw/top_{topname}/sw/autogen, we currently create these files - # twice: - # - Once under out_path/sw/autogen - # - Once under hw/top_{topname}/sw/autogen - root_paths = [out_path.resolve(), SRCTREE_TOP] - out_paths = [ - out_path.resolve(), - (SRCTREE_TOP / "hw/top_{}/".format(topname)).resolve() - ] - for idx, path in enumerate(out_paths): - # C Header + C File + Clang-format file - - # "clang-format" -> "sw/autogen/.clang-format" - cformat_tplpath = TOPGEN_TEMPLATE_PATH / "clang-format" - cformat_dir = path / "sw/autogen" - cformat_dir.mkdir(parents=True, exist_ok=True) - cformat_path = cformat_dir / ".clang-format" - cformat_path.write_text(cformat_tplpath.read_text()) - - # Save the header macro prefix into `c_helper` - rel_header_dir = cformat_dir.relative_to(root_paths[idx]) - c_helper.header_macro_prefix = ( - "OPENTITAN_" + str(rel_header_dir).replace("/", "_").upper()) - - # "top_{topname}.h.tpl" -> "sw/autogen/top_{topname}.h" - cheader_path = cformat_dir / f"top_{topname}.h" - render_template(TOPGEN_TEMPLATE_PATH / "toplevel.h.tpl", - cheader_path, - helper=c_helper) - - # Save the relative header path into `c_helper` - rel_header_path = cheader_path.relative_to(root_paths[idx]) - c_helper.header_path = str(rel_header_path) - - # "toplevel.c.tpl" -> "sw/autogen/top_{topname}.c" - render_template(TOPGEN_TEMPLATE_PATH / "toplevel.c.tpl", - cformat_dir / f"top_{topname}.c", - helper=c_helper) - - # "toplevel_memory.ld.tpl" -> "sw/autogen/top_{topname}_memory.ld" - render_template(TOPGEN_TEMPLATE_PATH / "toplevel_memory.ld.tpl", - cformat_dir / f"top_{topname}_memory.ld", - helper=c_helper) - - # "toplevel_memory.h.tpl" -> "sw/autogen/top_{topname}_memory.h" - memory_cheader_path = cformat_dir / f"top_{topname}_memory.h" - render_template(TOPGEN_TEMPLATE_PATH / "toplevel_memory.h.tpl", - memory_cheader_path, - helper=c_helper) + gencmd=gencmd_sv) + + for addr_space in topcfg['addr_spaces']: + default_addr_space = addr_space.get('default', False) + + addr_space_suffix = "" + if not default_addr_space: + addr_space_suffix = "_" + addr_space['name'] + + # The C / SV file needs some complex information, so we initialize this + # object to store it. + c_helper = TopGenCTest(completecfg, name_to_block, addr_space['name']) + + # "toplevel_pkg.sv.tpl" -> "rtl/autogen/top_{topname}{topname}{addr_space_suffix}_pkg.sv" + render_template(TOPGEN_TEMPLATE_PATH / "toplevel_pkg.sv.tpl", + out_path / f"rtl/autogen/top_{topname}{addr_space_suffix}_pkg.sv", + helper=c_helper, + gencmd=gencmd_sv) + + # Since SW does not use FuseSoC and instead expects those files always + # to be in hw/top_{topname}/sw/autogen, we currently create these files + # twice: + # - Once under out_path/sw/autogen + # - Once under hw/top_{topname}/sw/autogen + root_paths = [out_path.resolve(), SRCTREE_TOP] + out_paths = [ + out_path.resolve(), + (SRCTREE_TOP / "hw/top_{}/".format(topname)).resolve() + ] + for idx, path in enumerate(out_paths): + # C Header + C File + Clang-format file + + # "clang-format" -> "sw/autogen/.clang-format" + cformat_tplpath = TOPGEN_TEMPLATE_PATH / "clang-format" + cformat_dir = path / "sw/autogen" + cformat_dir.mkdir(parents=True, exist_ok=True) + cformat_path = cformat_dir / ".clang-format" + cformat_path.write_text(cformat_tplpath.read_text()) + + # Save the header macro prefix into `c_helper` + rel_header_dir = cformat_dir.relative_to(root_paths[idx]) + c_helper.header_macro_prefix = ( + f"OPENTITAN{addr_space_suffix.upper()}_" + str(rel_header_dir).replace("/", "_").upper()) + + # "top_{topname}.h.tpl" -> "sw/autogen/top_{topname}{addr_space_suffix}.h" + cheader_path = cformat_dir / f"top_{topname}{addr_space_suffix}.h" + render_template(TOPGEN_TEMPLATE_PATH / "toplevel.h.tpl", + cheader_path, + helper=c_helper) + + # Save the relative header path into `c_helper` + rel_header_path = cheader_path.relative_to(root_paths[idx]) + c_helper.header_path = str(rel_header_path) + + # "toplevel.c.tpl" -> "sw/autogen/top_{topname}{addr_space_suffix}.c" + render_template(TOPGEN_TEMPLATE_PATH / "toplevel.c.tpl", + cformat_dir / f"top_{topname}{addr_space_suffix}.c", + helper=c_helper) + + # "toplevel_memory.h.tpl" -> "sw/autogen/top_{topname}{addr_space_suffix}_memory.h" + memory_cheader_path = cformat_dir / f"top_{topname}{addr_space_suffix}_memory.h" + render_template(TOPGEN_TEMPLATE_PATH / "toplevel_memory.h.tpl", + memory_cheader_path, + helper=c_helper) + + + if default_addr_space: + # "toplevel_memory.ld.tpl" -> "sw/autogen/top_{topname}{addr_space_suffix}_memory.ld" + render_template(TOPGEN_TEMPLATE_PATH / "toplevel_memory.ld.tpl", + cformat_dir / f"top_{topname}{addr_space_suffix}_memory.ld", + helper=c_helper) + + + + # Auto-generate tests in "sw/device/tests/autogen" area. + gencmd = warnhdr + GENCMD.format(topname=topname) + for fname in ["plic_all_irqs_test.c", "alert_test.c", "BUILD"]: + outfile = SRCTREE_TOP / f"sw/device/tests/autogen/top_{topname}" / fname + render_template(TOPGEN_TEMPLATE_PATH / f"{fname}.tpl", + outfile, + helper=c_helper, + gencmd=gencmd) # generate chip level xbar and alert_handler TB tb_files = [ @@ -1387,7 +1415,7 @@ def render_template(template_path: str, rendered_path: Path, template_contents = generate_top(completecfg, name_to_block, str(xbar_chip_data_path), - gencmd=gencmd) + gencmd=gencmd_sv) rendered_dir = out_path / "dv/autogen" rendered_dir.mkdir(parents=True, exist_ok=True) @@ -1412,14 +1440,7 @@ def render_template(template_path: str, rendered_path: Path, # generate documentation for toplevel gen_top_docs(completecfg, c_helper, out_path) - # Auto-generate tests in "sw/device/tests/autogen" area. - gencmd = warnhdr + GENCMD.format(topname=topname) - for fname in ["plic_all_irqs_test.c", "alert_test.c", "BUILD"]: - outfile = SRCTREE_TOP / f"sw/device/tests/autogen/top_{topname}" / fname - render_template(TOPGEN_TEMPLATE_PATH / f"{fname}.tpl", - outfile, - helper=c_helper, - gencmd=gencmd) + if __name__ == "__main__": diff --git a/util/topgen/c.py b/util/topgen/c.py index ad7f1c42f49fa6..1a406689f09e05 100644 --- a/util/topgen/c.py +++ b/util/topgen/c.py @@ -103,7 +103,7 @@ def render_definition(self): class TopGenC: - def __init__(self, top_info, name_to_block: Dict[str, IpBlock]): + def __init__(self, top_info, name_to_block: Dict[str, IpBlock], addr_space: str): self.top = top_info self._top_name = Name(["top"]) + Name.from_snake_case(top_info["name"]) self._name_to_block = name_to_block @@ -111,8 +111,15 @@ def __init__(self, top_info, name_to_block: Dict[str, IpBlock]): # The .c file needs the .h file's relative path, store it here self.header_path = None - # TODO: Don't hardcode the address space used for software. - self.addr_space = "hart" + self.addr_space = addr_space + + # Determine default address space from the top config + self.default_addr_space = None + for addr_space in top_info['addr_spaces']: + default = addr_space.get('default', False) + if default: + self.default_addr_space = addr_space['name'] + assert(self.default_addr_space) self._init_plic_targets() self._init_plic_mapping() diff --git a/util/topgen/c_test.py b/util/topgen/c_test.py index c9d134f22a3dfc..daa6bfecd933fa 100644 --- a/util/topgen/c_test.py +++ b/util/topgen/c_test.py @@ -59,13 +59,15 @@ def __init__(self, name: str, inst_name: str, base_addr_name: str, class TopGenCTest(TopGenC): - def __init__(self, top_info, name_to_block: Dict[str, IpBlock]): - super().__init__(top_info, name_to_block) + def __init__(self, top_info, name_to_block: Dict[str, IpBlock], addr_space: str): + super().__init__(top_info, name_to_block, addr_space) self.irq_peripherals = self._get_irq_peripherals() self.alert_peripherals = self._get_alert_peripherals() def _get_irq_peripherals(self): + if self.addr_space != self.default_addr_space: + return [] irq_peripherals = [] self.devices() for entry in self.top['module']: @@ -118,6 +120,8 @@ def _get_irq_peripherals(self): return irq_peripherals def _get_alert_peripherals(self): + if self.addr_space != self.default_addr_space: + return [] alert_peripherals = [] self.devices() for entry in self.top['module']: diff --git a/util/topgen/rust.py b/util/topgen/rust.py index 6fe1e6e0fc554b..ff9d7027662525 100644 --- a/util/topgen/rust.py +++ b/util/topgen/rust.py @@ -195,15 +195,22 @@ def render(self): class TopGenRust: - def __init__(self, top_info, name_to_block: Dict[str, IpBlock], version_stamp: Dict[str, str]): + def __init__(self, top_info, name_to_block: Dict[str, IpBlock], version_stamp: Dict[str, str], addr_space: str): self.top = top_info self._top_name = Name(["top"]) + Name.from_snake_case(top_info["name"]) self._name_to_block = name_to_block self.regwidth = int(top_info["datawidth"]) self.file_header = RustFileHeader("foo.tpl", version_stamp, len(version_stamp) == 0) - # TODO: Don't hardcode the address space used for software. - self.addr_space = "hart" + self.addr_space = addr_space + + # Determine default address space from the top config + self.default_addr_space = None + for addr_space in top_info['addr_spaces']: + default = addr_space.get('default', False) + if default: + self.default_addr_space = addr_space['name'] + assert(self.default_addr_space) self._init_plic_targets() self._init_plic_mapping() diff --git a/util/topgen/templates/toplevel.c.tpl b/util/topgen/templates/toplevel.c.tpl index e0f0e178a71cf0..4b6d5e17429ec9 100644 --- a/util/topgen/templates/toplevel.c.tpl +++ b/util/topgen/templates/toplevel.c.tpl @@ -4,6 +4,7 @@ #include "${helper.header_path}" +% if helper.addr_space == helper.default_addr_space: /** * PLIC Interrupt Source to Peripheral Map * @@ -18,4 +19,5 @@ ${helper.plic_mapping.render_definition()} * This array is a mapping from `${helper.alert_alerts.name.as_c_type()}` to * `${helper.alert_sources.name.as_c_type()}`. */ -${helper.alert_mapping.render_definition()} \ No newline at end of file +${helper.alert_mapping.render_definition()} +% endif \ No newline at end of file diff --git a/util/topgen/templates/toplevel.h.tpl b/util/topgen/templates/toplevel.h.tpl index 74b85614cd201b..2ebc004ef6f318 100644 --- a/util/topgen/templates/toplevel.h.tpl +++ b/util/topgen/templates/toplevel.h.tpl @@ -106,6 +106,7 @@ extern "C" { % endif % endfor +% if helper.addr_space == helper.default_addr_space: /** * PLIC Interrupt Source Peripheral. * @@ -233,6 +234,7 @@ ${helper.clkmgr_gateable_clocks.render()} * but the clock manager is in control of whether the clock actually is stopped. */ ${helper.clkmgr_hintable_clocks.render()} +% endif /** * MMIO Region diff --git a/util/topgen/templates/toplevel.rs.tpl b/util/topgen/templates/toplevel.rs.tpl index 9971eead9efae6..7a658b0a8e9d2c 100644 --- a/util/topgen/templates/toplevel.rs.tpl +++ b/util/topgen/templates/toplevel.rs.tpl @@ -79,6 +79,7 @@ pub const ${base_addr_name}: usize = ${hex_base_addr}; pub const ${size_bytes_name}: usize = ${hex_size_bytes}; % endif % endfor +% if helper.addr_space == helper.default_addr_space: /// PLIC Interrupt Source Peripheral. /// /// Enumeration used to determine which peripheral asserted the corresponding @@ -170,6 +171,7 @@ ${helper.clkmgr_gateable_clocks.render()} /// The Software has partial control over these clocks. It can ask them to stop, /// but the clock manager is in control of whether the clock actually is stopped. ${helper.clkmgr_hintable_clocks.render()} +% endif /// MMIO Region /// diff --git a/util/topgen/templates/toplevel_mod.rs.tpl b/util/topgen/templates/toplevel_mod.rs.tpl index 993afb89469e55..e82e832183e2ce 100644 --- a/util/topgen/templates/toplevel_mod.rs.tpl +++ b/util/topgen/templates/toplevel_mod.rs.tpl @@ -2,5 +2,11 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -pub mod top_${top["name"]}; -pub mod top_${top["name"]}_memory; +% for addr_space in top["addr_spaces"]: +<% + is_default_addr_space = addr_space.get('default', False) + addr_space_suffix = "" if is_default_addr_space else "_" + addr_space['name'] +%>\ +pub mod top_${top["name"]}${addr_space_suffix}; +pub mod top_${top["name"]}${addr_space_suffix}_memory; +% endfor \ No newline at end of file diff --git a/util/topgen/templates/toplevel_pkg.sv.tpl b/util/topgen/templates/toplevel_pkg.sv.tpl index 50fdb94857d106..323fffa68f4a65 100644 --- a/util/topgen/templates/toplevel_pkg.sv.tpl +++ b/util/topgen/templates/toplevel_pkg.sv.tpl @@ -62,6 +62,7 @@ package top_${top["name"]}_pkg; % endif % endfor +% if helper.addr_space == helper.default_addr_space: // Enumeration of alert modules typedef enum int unsigned { % for mod in top["alert_module"]: @@ -172,5 +173,6 @@ package top_${top["name"]}_pkg; `define INOUT_AI inout `define INOUT_AO inout `endif +% endif endpackage