diff --git a/hw/bitstream/vivado/BUILD b/hw/bitstream/vivado/BUILD
index ae932c2cc218a9..bfe1e6e804af65 100644
--- a/hw/bitstream/vivado/BUILD
+++ b/hw/bitstream/vivado/BUILD
@@ -168,6 +168,12 @@ bitstream_manifest_fragment(
     memories = [
         "rom",
         "otp",
+        "flash0_info0",
+        "flash0_info1",
+        "flash0_info2",
+        "flash1_info0",
+        "flash1_info1",
+        "flash1_info2",
     ],
     memory_map_file = ":cw310_mmi",
     tags = ["manual"],
@@ -192,6 +198,12 @@ bitstream_manifest_fragment(
     memories = [
         "rom",
         "otp",
+        "flash0_info0",
+        "flash0_info1",
+        "flash0_info2",
+        "flash1_info0",
+        "flash1_info1",
+        "flash1_info2",
     ],
     memory_map_file = ":cw310_hyperdebug_mmi",
     tags = ["manual"],
@@ -216,6 +228,12 @@ bitstream_manifest_fragment(
     memories = [
         "rom",
         "otp",
+        "flash0_info0",
+        "flash0_info1",
+        "flash0_info2",
+        "flash1_info0",
+        "flash1_info1",
+        "flash1_info2",
     ],
     memory_map_file = ":cw340_mmi",
     tags = ["manual"],
diff --git a/hw/top_earlgrey/chip_earlgrey_cw310.core b/hw/top_earlgrey/chip_earlgrey_cw310.core
index ea79d3f5419dc8..5ed38b7e7d54ce 100644
--- a/hw/top_earlgrey/chip_earlgrey_cw310.core
+++ b/hw/top_earlgrey/chip_earlgrey_cw310.core
@@ -23,6 +23,7 @@ filesets:
       - data/clocks.xdc
       - data/pins_cw310.xdc
       - data/placement.xdc
+      - data/synth.xdc
     file_type: xdc
 
   files_tcl:
diff --git a/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core b/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core
index 5c04b28f56a404..74f8ae3c9e96f3 100644
--- a/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core
+++ b/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core
@@ -25,6 +25,7 @@ filesets:
       # same as lowrisc:systems:chip_earlgrey_cw310.
       - data/pins_cw310_hyperdebug.xdc
       - data/placement.xdc
+      - data/synth.xdc
     file_type: xdc
 
   files_tcl:
diff --git a/hw/top_earlgrey/chip_earlgrey_cw340.core b/hw/top_earlgrey/chip_earlgrey_cw340.core
index e8adf5346d96d7..462f42f771417a 100644
--- a/hw/top_earlgrey/chip_earlgrey_cw340.core
+++ b/hw/top_earlgrey/chip_earlgrey_cw340.core
@@ -22,6 +22,7 @@ filesets:
     files:
       - data/clocks_cw341.xdc
       - data/pins_cw341.xdc
+      - data/synth.xdc
     file_type: xdc
 
   files_tcl:
diff --git a/hw/top_earlgrey/data/synth.xdc b/hw/top_earlgrey/data/synth.xdc
new file mode 100644
index 00000000000000..2615f456d1e63b
--- /dev/null
+++ b/hw/top_earlgrey/data/synth.xdc
@@ -0,0 +1,14 @@
+## Copyright lowRISC contributors (OpenTitan project).
+## Licensed under the Apache License, Version 2.0, see LICENSE for details.
+## SPDX-License-Identifier: Apache-2.0
+
+## Synthesis constraints
+
+# Prevent Vivado from combining these BRAMs, so the memories can be readily
+# spliced with updatemem.
+set_property KEEP_HIERARCHY TRUE [get_cells "top_earlgrey/u_flash_ctrl/u_eflash/u_flash/gen_generic.u_impl_generic/gen_prim_flash_banks[0].u_prim_flash_bank/gen_info_types[0].u_info_mem"]
+set_property KEEP_HIERARCHY TRUE [get_cells "top_earlgrey/u_flash_ctrl/u_eflash/u_flash/gen_generic.u_impl_generic/gen_prim_flash_banks[0].u_prim_flash_bank/gen_info_types[1].u_info_mem"]
+set_property KEEP_HIERARCHY TRUE [get_cells "top_earlgrey/u_flash_ctrl/u_eflash/u_flash/gen_generic.u_impl_generic/gen_prim_flash_banks[0].u_prim_flash_bank/gen_info_types[2].u_info_mem"]
+set_property KEEP_HIERARCHY TRUE [get_cells "top_earlgrey/u_flash_ctrl/u_eflash/u_flash/gen_generic.u_impl_generic/gen_prim_flash_banks[1].u_prim_flash_bank/gen_info_types[0].u_info_mem"]
+set_property KEEP_HIERARCHY TRUE [get_cells "top_earlgrey/u_flash_ctrl/u_eflash/u_flash/gen_generic.u_impl_generic/gen_prim_flash_banks[1].u_prim_flash_bank/gen_info_types[1].u_info_mem"]
+set_property KEEP_HIERARCHY TRUE [get_cells "top_earlgrey/u_flash_ctrl/u_eflash/u_flash/gen_generic.u_impl_generic/gen_prim_flash_banks[1].u_prim_flash_bank/gen_info_types[2].u_info_mem"]
diff --git a/hw/top_earlgrey/util/vivado_hook_write_bitstream_pre.tcl b/hw/top_earlgrey/util/vivado_hook_write_bitstream_pre.tcl
index 58e96ff78e9b07..26a832965ca8a7 100644
--- a/hw/top_earlgrey/util/vivado_hook_write_bitstream_pre.tcl
+++ b/hw/top_earlgrey/util/vivado_hook_write_bitstream_pre.tcl
@@ -201,6 +201,43 @@ dict set memInfo otp mem_type_regex $mem_type_regex
 dict set memInfo otp fake_word_width 0
 dict set memInfo otp addr_end_multiplier 16
 
+# The flash banks have 76-bit wide words. 64 bits are data, and 12 bits are metadata.
+set flash_info_brams [split [get_cells -hierarchical -filter " PRIMITIVE_TYPE =~ ${bram_regex} && NAME =~ *u_flash_ctrl*gen_prim_flash_banks[0]*gen_info_types[0].u_info_mem*"] " "]
+dict set memInfo flash0_info0 brams $flash_info_brams
+dict set memInfo flash0_info0 mem_type_regex $mem_type_regex
+dict set memInfo flash0_info0 fake_word_width 0
+dict set memInfo flash0_info0 addr_end_multiplier 1
+
+set flash_info_brams [split [get_cells -hierarchical -filter " PRIMITIVE_TYPE =~ ${bram_regex} && NAME =~ *u_flash_ctrl*gen_prim_flash_banks[0]*gen_info_types[1].u_info_mem*"] " "]
+dict set memInfo flash0_info1 brams $flash_info_brams
+dict set memInfo flash0_info1 mem_type_regex $mem_type_regex
+dict set memInfo flash0_info1 fake_word_width 0
+dict set memInfo flash0_info1 addr_end_multiplier 1
+
+set flash_info_brams [split [get_cells -hierarchical -filter " PRIMITIVE_TYPE =~ ${bram_regex} && NAME =~ *u_flash_ctrl*gen_prim_flash_banks[0]*gen_info_types[2].u_info_mem*"] " "]
+dict set memInfo flash0_info2 brams $flash_info_brams
+dict set memInfo flash0_info2 mem_type_regex $mem_type_regex
+dict set memInfo flash0_info2 fake_word_width 0
+dict set memInfo flash0_info2 addr_end_multiplier 1
+
+set flash_info_brams [split [get_cells -hierarchical -filter " PRIMITIVE_TYPE =~ ${bram_regex} && NAME =~ *u_flash_ctrl*gen_prim_flash_banks[1]*gen_info_types[0].u_info_mem*"] " "]
+dict set memInfo flash1_info0 brams $flash_info_brams
+dict set memInfo flash1_info0 mem_type_regex $mem_type_regex
+dict set memInfo flash1_info0 fake_word_width 0
+dict set memInfo flash1_info0 addr_end_multiplier 1
+
+set flash_info_brams [split [get_cells -hierarchical -filter " PRIMITIVE_TYPE =~ ${bram_regex} && NAME =~ *u_flash_ctrl*gen_prim_flash_banks[1]*gen_info_types[1].u_info_mem*"] " "]
+dict set memInfo flash1_info1 brams $flash_info_brams
+dict set memInfo flash1_info1 mem_type_regex $mem_type_regex
+dict set memInfo flash1_info1 fake_word_width 0
+dict set memInfo flash1_info1 addr_end_multiplier 1
+
+set flash_info_brams [split [get_cells -hierarchical -filter " PRIMITIVE_TYPE =~ ${bram_regex} && NAME =~ *u_flash_ctrl*gen_prim_flash_banks[1]*gen_info_types[2].u_info_mem*"] " "]
+dict set memInfo flash1_info2 brams $flash_info_brams
+dict set memInfo flash1_info2 mem_type_regex $mem_type_regex
+dict set memInfo flash1_info2 fake_word_width 0
+dict set memInfo flash1_info2 addr_end_multiplier 1
+
 generate_mmi "memories.mmi" $memInfo 1
 
 # For debugging purposes, dump the INIT_XX strings for ROM and OTP.