diff --git a/hw/ip/pwrmgr/data/pwrmgr.hjson.tpl b/hw/ip/pwrmgr/data/pwrmgr.hjson.tpl index 627be2cd9471ff..e66fafbd855429 100644 --- a/hw/ip/pwrmgr/data/pwrmgr.hjson.tpl +++ b/hw/ip/pwrmgr/data/pwrmgr.hjson.tpl @@ -68,6 +68,12 @@ ], inter_signal_list: [ + { struct: "pwr_boot_status", + type: "uni", + name: "boot_status", + act: "req", + package: "pwrmgr_pkg", + }, { struct: "pwr_ast", type: "req_rsp", name: "pwr_ast", @@ -223,6 +229,14 @@ % endfor + { name: "PwrFsmWait4ExtRst", + desc: "Number of reset requets", + type: "int", + default: "0", + local: "false", + expose: "true" + }, + { name: "NumRstReqs", desc: "Number of peripheral reset requets", type: "int", diff --git a/hw/ip/pwrmgr/dv/tb.sv b/hw/ip/pwrmgr/dv/tb.sv index 9fb11d5a7329c4..44a412b2e757f6 100644 --- a/hw/ip/pwrmgr/dv/tb.sv +++ b/hw/ip/pwrmgr/dv/tb.sv @@ -19,6 +19,7 @@ module tb; wire clk_slow, rst_slow_n; wire devmode; wire [NUM_MAX_INTERRUPTS-1:0] interrupts; + wire int_reset_req; // interfaces clk_rst_if clk_rst_if ( @@ -49,6 +50,7 @@ module tb; ); assign interrupts[0] = pwrmgr_if.intr_wakeup; + assign int_reset_req = tb.dut.internal_reset_req ; pwrmgr_if pwrmgr_if ( .clk, @@ -97,7 +99,7 @@ module tb; .fetch_en_o(pwrmgr_if.fetch_en), .wakeups_i (pwrmgr_if.wakeups_i), - .rstreqs_i (pwrmgr_if.rstreqs_i), + .rstreqs_i ({int_reset_req,pwrmgr_if.rstreqs_i[0]}), .ndmreset_req_i(pwrmgr_if.cpu_i.ndmreset_req), .lc_dft_en_i (pwrmgr_if.lc_dft_en), diff --git a/hw/ip/pwrmgr/pwrmgr_pkg.core b/hw/ip/pwrmgr/pwrmgr_pkg.core index 3e83cde44fd128..795d0811b6b07f 100644 --- a/hw/ip/pwrmgr/pwrmgr_pkg.core +++ b/hw/ip/pwrmgr/pwrmgr_pkg.core @@ -9,6 +9,7 @@ filesets: files_rtl: depend: - lowrisc:ip:pwrmgr_reg + - lowrisc:ip:rom_ctrl_pkg files: - rtl/pwrmgr_pkg.sv file_type: systemVerilogSource diff --git a/hw/ip/pwrmgr/rtl/pwrmgr.sv b/hw/ip/pwrmgr/rtl/pwrmgr.sv index 2ff4b2c52d6c28..9049f7389b336f 100644 --- a/hw/ip/pwrmgr/rtl/pwrmgr.sv +++ b/hw/ip/pwrmgr/rtl/pwrmgr.sv @@ -11,7 +11,8 @@ module pwrmgr import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*; #( - parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}} + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + parameter bit PwrFsmWait4ExtRst = 0 ) ( // Clocks and resets input clk_slow_i, @@ -59,12 +60,13 @@ module pwrmgr input pwr_cpu_t pwr_cpu_i, // SEC_CM: LC_CTRL.INTERSIG.MUBI output lc_ctrl_pkg::lc_tx_t fetch_en_o, - input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, - input lc_ctrl_pkg::lc_tx_t lc_dft_en_i, + input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, + input lc_ctrl_pkg::lc_tx_t lc_dft_en_i, + output pwr_boot_status_t boot_status_o, // peripherals wakeup and reset requests - input [NumWkups-1:0] wakeups_i, - input [NumRstReqs-1:0] rstreqs_i, + input [NumWkups-1:0] wakeups_i, + input [NumRstReqs-1:0] rstreqs_i, // cpu related inputs input ndmreset_req_i, @@ -88,6 +90,11 @@ module pwrmgr output intr_wakeup_o ); + + logic internal_reset_req; + logic strap_sampled; + logic ext_reset_req; + //////////////////////////////////////////////////// // Input handling // //////////////////////////////////////////////////// @@ -504,6 +511,20 @@ module pwrmgr {NumIntRstReqs{1'b1}}, slow_reset_en}; + assign internal_reset_req =|( + slow_peri_reqs.rstreqs & + {{NumSwRstReq{1'b1}}, // SW driven reset + {NumDebugRstReqs{1'b1}}, // debugger reset + {NumIntRstReqs{1'b1}}, // {ESC reset, slow_fsm} + // exclude the external async reset + {1'b0,slow_reset_en[0]} + } + ); + + // bit1 is ext rst Do not mask. + // Always want to propagate to clear Reset Wait state in fast FSM + assign ext_reset_req = slow_peri_reqs.rstreqs[NumRstReqs-1] ; + for (genvar i = 0; i < NumWkups; i++) begin : gen_wakeup_status assign hw2reg.wake_status[i].de = 1'b1; assign hw2reg.wake_status[i].d = peri_reqs_masked.wakeups[i]; @@ -574,7 +595,9 @@ module pwrmgr assign low_power_hint = reg2hw.control.low_power_hint.q == LowPower; - pwrmgr_fsm u_fsm ( + pwrmgr_fsm #( + .PwrFsmWait4ExtRst(PwrFsmWait4ExtRst) + ) u_fsm ( .clk_i, .rst_ni, .clk_slow_i, @@ -602,6 +625,8 @@ module pwrmgr .fall_through_o (low_power_fall_through), .abort_o (low_power_abort), .clr_hint_o (clr_hint), + .light_rst_req_i (internal_reset_req), + .ext_reset_req_i (ext_reset_req), // rstmgr .pwr_rst_o (pwr_rst_o), @@ -635,6 +660,7 @@ module pwrmgr // pinmux and other peripherals .strap_o, + .strap_sampled_o (strap_sampled), // to debug monitoring logic .low_power_o ); @@ -685,6 +711,16 @@ module pwrmgr .intr_o (intr_wakeup_o) ); + //////////////////////////////////////////////////// + // Routing sstaus signal outputs for monitoring + //////////////////////////////////////////////////// + assign boot_status_o.cpu_fetch_en = fetch_en_o; + assign boot_status_o.rom_ctrl_status = rom_ctrl_i; + assign boot_status_o.lc_done = pwr_lc_i.lc_done; + assign boot_status_o.otp_done = otp_rsp.otp_done; + assign boot_status_o.clk_status = pwr_clk_i; + assign boot_status_o.light_reset_req = internal_reset_req; + assign boot_status_o.strapSampled = strap_sampled; //////////////////////////// /// Assertions diff --git a/hw/ip/pwrmgr/rtl/pwrmgr_fsm.sv b/hw/ip/pwrmgr/rtl/pwrmgr_fsm.sv index 2bbc5bb975eb6f..f36cfac082e04f 100644 --- a/hw/ip/pwrmgr/rtl/pwrmgr_fsm.sv +++ b/hw/ip/pwrmgr/rtl/pwrmgr_fsm.sv @@ -7,7 +7,12 @@ `include "prim_assert.sv" -module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( +module pwrmgr_fsm + import pwrmgr_pkg::*; + import pwrmgr_reg_pkg::*; +#( + parameter bit PwrFsmWait4ExtRst = 0 +) ( input clk_i, input rst_ni, input clk_slow_i, @@ -33,6 +38,9 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( output logic abort_o, output logic clr_hint_o, output logic clr_cfg_lock_o, + input logic light_rst_req_i, // internally generated reset request. + // Send to platform to assert reset + input logic ext_reset_req_i, // Internal Req held until ext reset deasserts // rstmgr output pwr_rst_req_t pwr_rst_o, @@ -63,6 +71,7 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( // pinmux output logic strap_o, + output logic strap_sampled_o, output logic low_power_o, // processing elements @@ -103,7 +112,7 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( // strap sample should only happen on cold boot or when the // the system goes through a reset cycle - logic strap_sampled; + // [output] logic strap_sampled; // disable processing element fetching lc_ctrl_pkg::lc_tx_t fetch_en_q, fetch_en_d; @@ -118,6 +127,8 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( logic otp_init; logic lc_init; logic low_power_q, low_power_d; + logic ext_rst_req_d, ext_rst_req_q; + logic light_rst_req_q; assign pd_n_rsts_asserted = pwr_rst_i.rst_lc_src_n[PowerDomains-1:OffDomainSelStart] == '0 & pwr_rst_i.rst_sys_src_n[PowerDomains-1:OffDomainSelStart] == '0; @@ -153,6 +164,33 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( assign reset_valid = reset_cause_q == LowPwrEntry ? main_pd_ni | pd_n_rsts_asserted : reset_cause_q == HwReq ? all_rsts_asserted : 1'b0; + + if (PwrFsmWait4ExtRst) begin : gen_wait2ext_rst + + assign ext_rst_req_d = ext_reset_req_i; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + light_rst_req_q <= 0; + ext_rst_req_q <= 0; + end else begin + ext_rst_req_q <= ext_rst_req_d; + if(light_rst_req_q && !ext_rst_req_d && ext_rst_req_q) begin + light_rst_req_q <= '0; + end else if (light_rst_req_i) begin + light_rst_req_q <= 1'b1; + end + end + end + end : gen_wait2ext_rst + else + begin : gen_no_wait2ext_rst + assign light_rst_req_q = 0; + assign ext_rst_req_q = 0; + assign ext_rst_req_d = 0; + end : gen_no_wait2ext_rst + + always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin ack_pwrup_q <= 1'b0; @@ -180,11 +218,11 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin - strap_sampled <= 1'b0; + strap_sampled_o <= 1'b0; end else if (&rst_sys_req_q) begin - strap_sampled <= 1'b0; + strap_sampled_o <= 1'b0; end else if (strap_o) begin - strap_sampled <= 1'b1; + strap_sampled_o <= 1'b1; end end @@ -338,7 +376,7 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( end FastPwrStateStrap: begin - strap_o = ~strap_sampled; + strap_o = ~strap_sampled_o; state_d = FastPwrStateRomCheckDone; end @@ -471,7 +509,10 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( // cleared before proceeding. This also implies if the system is under a persistent // glitch, or if someone just turned off the power before pwrmgr turns it off itself, // we will stay stuck here and perpetually hold the system in reset. - if (reset_valid && !reset_reqs_i[ResetMainPwrIdx]) begin + // NumRstReqs-1 is the External SoC reset request. + // Need to hold in reset until external reset deasserts (i.e. light_rst_req_q goes low) + if (reset_valid && !reset_reqs_i[ResetMainPwrIdx] + && !light_rst_req_q ) begin state_d = FastPwrStateLowPower; end end diff --git a/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv b/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv index c86e8fb4959da3..0c4597d856f112 100644 --- a/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv +++ b/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv @@ -155,6 +155,16 @@ package pwrmgr_pkg; logic ndmreset_req; } pwrmgr_cpu_t; + typedef struct packed { + lc_ctrl_pkg::lc_tx_t cpu_fetch_en; + rom_ctrl_pkg::pwrmgr_data_t [pwrmgr_reg_pkg::NumRomInputs-1:0] rom_ctrl_status; + logic lc_done; + logic otp_done; + logic strapSampled; + logic light_reset_req; + pwr_clk_rsp_t clk_status; + } pwr_boot_status_t; + // exported resets // default value for pwrmgr_ast_rsp_t (for dangling ports) diff --git a/hw/ip/rstmgr/rstmgr_pkg.core b/hw/ip/rstmgr/rstmgr_pkg.core index 4c86dc5f1c04c4..27f8fb30c35a68 100644 --- a/hw/ip/rstmgr/rstmgr_pkg.core +++ b/hw/ip/rstmgr/rstmgr_pkg.core @@ -9,6 +9,7 @@ filesets: files_rtl: depend: - lowrisc:ip:alert_handler_component + - lowrisc:ip:rom_ctrl_pkg - lowrisc:ip:pwrmgr_pkg - lowrisc:ip:rstmgr_reg - "fileset_top ? (lowrisc:systems:rstmgr_pkg)" diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson index 16728c62de0d87..8bcd0b01ecc152 100644 --- a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson @@ -266,6 +266,7 @@ domains: [ Aon + "0" ] shadowed: false sw: false @@ -310,7 +311,6 @@ domains: [ Aon - "0" ] shadowed: false sw: false @@ -2055,6 +2055,10 @@ { name: pwrmgr_aon type: pwrmgr + param_decl: + { + PwrFsmWait4ExtRst: "1" + } clock_group: powerup clock_srcs: { @@ -2108,10 +2112,34 @@ clk_lc_i: clkmgr_aon_clocks.clk_io_div4_powerup clk_esc_i: clkmgr_aon_clocks.clk_io_div4_secure } - param_decl: {} - param_list: [] + memory: {} + param_list: + [ + { + name: PwrFsmWait4ExtRst + desc: Number of reset requets + type: int + default: "1" + expose: "true" + name_top: PwrmgrAonPwrFsmWait4ExtRst + } + ] inter_signal_list: [ + { + name: boot_status + struct: pwr_boot_status + package: pwrmgr_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + external: true + top_signame: pwrmgr_boot_status + conn_type: false + index: -1 + } { name: pwr_ast struct: pwr_ast @@ -3687,9 +3715,9 @@ name: lc domain: "0" } - rst_aon_ni: + rst_por_ni: { - name: lc_aon + name: por_io_div4 domain: "0" } } @@ -9604,6 +9632,7 @@ ast.ram_1p_cfg: ram_1p_cfg ast.spi_ram_2p_cfg: spi_ram_2p_cfg ast.rom_cfg: rom_cfg + pwrmgr_aon.boot_status: pwrmgr_boot_status clkmgr_aon.jitter_en: clk_main_jitter_en clkmgr_aon.io_clk_byp_req: io_clk_byp_req clkmgr_aon.io_clk_byp_ack: io_clk_byp_ack @@ -18416,6 +18445,20 @@ top_signame: spi_host0_tl index: -1 } + { + name: boot_status + struct: pwr_boot_status + package: pwrmgr_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + external: true + top_signame: pwrmgr_boot_status + conn_type: false + index: -1 + } { name: pwr_ast struct: pwr_ast @@ -23530,6 +23573,18 @@ index: -1 netname: ast_rom_cfg } + { + package: pwrmgr_pkg + struct: pwr_boot_status + signame: pwrmgr_boot_status_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: pwrmgr_boot_status + } { package: prim_mubi_pkg struct: mubi4 diff --git a/hw/top_darjeeling/data/top_darjeeling.hjson b/hw/top_darjeeling/data/top_darjeeling.hjson index 3893f223720971..780a4c36e704d0 100644 --- a/hw/top_darjeeling/data/top_darjeeling.hjson +++ b/hw/top_darjeeling/data/top_darjeeling.hjson @@ -292,6 +292,9 @@ }, { name: "pwrmgr_aon", type: "pwrmgr", + param_decl: { + PwrFsmWait4ExtRst: "1" + } clock_group: "powerup", clock_srcs: { clk_i: "io_div4", @@ -510,7 +513,12 @@ type: "soc_proxy", clock_srcs: {clk_i: "main", clk_aon_i: "aon"}, clock_group: "infra", - reset_connections: {rst_ni: "lc", rst_aon_ni: "lc_aon"}, + reset_connections: { + rst_ni: "lc", + rst_por_ni: "por_io_div4" //{ + // name: "por_io_div4" + // }, + } base_addrs: { core: {hart: "0x22030000"}, ctn: {hart: "0x40000000"}, @@ -1214,6 +1222,7 @@ 'ast.ram_1p_cfg' : 'ram_1p_cfg', 'ast.spi_ram_2p_cfg' : 'spi_ram_2p_cfg', 'ast.rom_cfg' : 'rom_cfg', + 'pwrmgr_aon.boot_status' : 'pwrmgr_boot_status', 'clkmgr_aon.jitter_en' : 'clk_main_jitter_en', 'clkmgr_aon.io_clk_byp_req' : 'io_clk_byp_req', 'clkmgr_aon.io_clk_byp_ack' : 'io_clk_byp_ack', diff --git a/hw/top_darjeeling/dv/autogen/rstmgr_tgl_excl.cfg b/hw/top_darjeeling/dv/autogen/rstmgr_tgl_excl.cfg index d4763e5384aa21..95062639e48a88 100644 --- a/hw/top_darjeeling/dv/autogen/rstmgr_tgl_excl.cfg +++ b/hw/top_darjeeling/dv/autogen/rstmgr_tgl_excl.cfg @@ -18,7 +18,7 @@ -node tb.dut*.u_rstmgr_aon.resets_o.rst_por_n[1] -node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_n[1] -node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_div2_n[1] --node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_div4_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_aon_n[1] -node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_io_div2_n[1] -node tb.dut*.u_rstmgr_aon.resets_o.rst_sys_n[0] -node tb.dut*.u_rstmgr_aon.resets_o.rst_sys_io_div4_n[1] diff --git a/hw/top_darjeeling/ip/pwrmgr/data/autogen/pwrmgr.hjson b/hw/top_darjeeling/ip/pwrmgr/data/autogen/pwrmgr.hjson index cf513b52497143..f3d9f6047cb1c7 100644 --- a/hw/top_darjeeling/ip/pwrmgr/data/autogen/pwrmgr.hjson +++ b/hw/top_darjeeling/ip/pwrmgr/data/autogen/pwrmgr.hjson @@ -69,6 +69,12 @@ ], inter_signal_list: [ + { struct: "pwr_boot_status", + type: "uni", + name: "boot_status", + act: "req", + package: "pwrmgr_pkg", + }, { struct: "pwr_ast", type: "req_rsp", name: "pwr_ast", @@ -257,6 +263,14 @@ }, + { name: "PwrFsmWait4ExtRst", + desc: "Number of reset requets", + type: "int", + default: "0", + local: "false", + expose: "true" + }, + { name: "NumRstReqs", desc: "Number of peripheral reset requets", type: "int", diff --git a/hw/top_darjeeling/ip/rstmgr/dv/env/autogen/rstmgr_env_pkg.sv b/hw/top_darjeeling/ip/rstmgr/dv/env/autogen/rstmgr_env_pkg.sv index 6923aeceddde00..85212d0e7e9f5b 100644 --- a/hw/top_darjeeling/ip/rstmgr/dv/env/autogen/rstmgr_env_pkg.sv +++ b/hw/top_darjeeling/ip/rstmgr/dv/env/autogen/rstmgr_env_pkg.sv @@ -40,6 +40,7 @@ package rstmgr_env_pkg; "u_daon_por_io", "u_daon_por_io_div2", "u_daon_por_io_div4", + "u_d0_por_io_div4", "u_daon_por_usb", "u_d0_por_usb", "u_d0_lc", @@ -47,7 +48,6 @@ package rstmgr_env_pkg; "u_daon_lc", "u_daon_lc_shadowed", "u_daon_lc_aon", - "u_d0_lc_aon", "u_daon_lc_io", "u_d0_lc_io", "u_daon_lc_io_div2", diff --git a/hw/top_darjeeling/ip/rstmgr/rtl/autogen/rstmgr.sv b/hw/top_darjeeling/ip/rstmgr/rtl/autogen/rstmgr.sv index d4ea11bcef2ab8..345f3ebca8f89e 100644 --- a/hw/top_darjeeling/ip/rstmgr/rtl/autogen/rstmgr.sv +++ b/hw/top_darjeeling/ip/rstmgr/rtl/autogen/rstmgr.sv @@ -397,7 +397,7 @@ module rstmgr assign shadow_fsm_errs[2] = '0; // Generating resets for por_io_div4 - // Power Domains: ['Aon'] + // Power Domains: ['Aon', '0'] // Shadowed: False rstmgr_leaf_rst #( .SecCheck(SecCheck), @@ -423,10 +423,30 @@ module rstmgr u_daon_por_io_div4.gen_rst_chk.u_rst_chk.u_state_regs, alert_tx_o[0]) end - assign resets_o.rst_por_io_div4_n[Domain0Sel] = '0; - assign cnsty_chk_errs[3][Domain0Sel] = '0; - assign fsm_errs[3][Domain0Sel] = '0; - assign rst_en_o.por_io_div4[Domain0Sel] = MuBi4True; + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_d0_por_io_div4 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_por_aon_n[Domain0Sel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.por_io_div4[Domain0Sel]), + .leaf_rst_o(resets_o.rst_por_io_div4_n[Domain0Sel]), + .err_o(cnsty_chk_errs[3][Domain0Sel]), + .fsm_err_o(fsm_errs[3][Domain0Sel]) + ); + + if (SecCheck) begin : gen_d0_por_io_div4_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + D0PorIoDiv4FsmCheck_A, + u_d0_por_io_div4.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end assign shadow_cnsty_chk_errs[3] = '0; assign shadow_fsm_errs[3] = '0; @@ -585,7 +605,7 @@ module rstmgr end // Generating resets for lc_aon - // Power Domains: ['Aon', '0'] + // Power Domains: ['Aon'] // Shadowed: False rstmgr_leaf_rst #( .SecCheck(SecCheck), @@ -611,30 +631,10 @@ module rstmgr u_daon_lc_aon.gen_rst_chk.u_rst_chk.u_state_regs, alert_tx_o[0]) end - rstmgr_leaf_rst #( - .SecCheck(SecCheck), - .SecMaxSyncDelay(SecMaxSyncDelay), - .SwRstReq(1'b0) - ) u_d0_lc_aon ( - .clk_i, - .rst_ni, - .leaf_clk_i(clk_aon_i), - .parent_rst_ni(rst_lc_src_n[Domain0Sel]), - .sw_rst_req_ni(1'b1), - .scan_rst_ni, - .scanmode_i, - .rst_en_o(rst_en_o.lc_aon[Domain0Sel]), - .leaf_rst_o(resets_o.rst_lc_aon_n[Domain0Sel]), - .err_o(cnsty_chk_errs[6][Domain0Sel]), - .fsm_err_o(fsm_errs[6][Domain0Sel]) - ); - - if (SecCheck) begin : gen_d0_lc_aon_assert - `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( - D0LcAonFsmCheck_A, - u_d0_lc_aon.gen_rst_chk.u_rst_chk.u_state_regs, - alert_tx_o[0]) - end + assign resets_o.rst_lc_aon_n[Domain0Sel] = '0; + assign cnsty_chk_errs[6][Domain0Sel] = '0; + assign fsm_errs[6][Domain0Sel] = '0; + assign rst_en_o.lc_aon[Domain0Sel] = MuBi4True; assign shadow_cnsty_chk_errs[6] = '0; assign shadow_fsm_errs[6] = '0; diff --git a/hw/top_darjeeling/ip/soc_proxy/data/soc_proxy.hjson b/hw/top_darjeeling/ip/soc_proxy/data/soc_proxy.hjson index e1d97d87177f80..5ed02a0438df16 100644 --- a/hw/top_darjeeling/ip/soc_proxy/data/soc_proxy.hjson +++ b/hw/top_darjeeling/ip/soc_proxy/data/soc_proxy.hjson @@ -33,7 +33,7 @@ clocking: [ { clock: "clk_i", reset: "rst_ni", primary: true } - { clock: "clk_aon_i", reset: "rst_aon_ni" } + { clock: "clk_aon_i", reset: "rst_por_ni" } ] bus_interfaces: [ diff --git a/hw/top_darjeeling/ip/soc_proxy/rtl/soc_proxy.sv b/hw/top_darjeeling/ip/soc_proxy/rtl/soc_proxy.sv index c8fb7eb1636552..cf63a793843b1c 100644 --- a/hw/top_darjeeling/ip/soc_proxy/rtl/soc_proxy.sv +++ b/hw/top_darjeeling/ip/soc_proxy/rtl/soc_proxy.sv @@ -15,7 +15,7 @@ module soc_proxy input logic clk_i, input logic rst_ni, input logic clk_aon_i, - input logic rst_aon_ni, + input logic rst_por_ni, input tlul_pkg::tl_h2d_t core_tl_i, output tlul_pkg::tl_d2h_t core_tl_o, @@ -373,7 +373,7 @@ module soc_proxy .Width(1) ) u_prim_flop_2sync_soc_wkup ( .clk_i (clk_aon_i), - .rst_ni (rst_aon_ni), + .rst_ni (rst_por_ni), .d_i (soc_wkup_async_i), .q_o (wkup_external_req_o) ); @@ -388,7 +388,7 @@ module soc_proxy .Cycles(3) ) u_prim_filter_wkup ( .clk_i (clk_aon_i), - .rst_ni (rst_aon_ni), + .rst_ni (rst_por_ni), .enable_i (1'b1), .filter_i (async_wkup), .filter_o (wkup_internal_req_o) @@ -400,7 +400,7 @@ module soc_proxy .Cycles(4) ) u_prim_filter_soc_rst_req ( .clk_i (clk_aon_i), - .rst_ni (rst_aon_ni), + .rst_ni (rst_por_ni), .enable_i (1'b1), .filter_i (soc_rst_req_async_i), .filter_o (rst_req_external_o) diff --git a/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv index 9918f78ad39c22..b865840d5f9b12 100644 --- a/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv +++ b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv @@ -1035,6 +1035,7 @@ module chip_darjeeling_asic #( // pwrmgr interface pwrmgr_pkg::pwr_ast_req_t base_ast_pwr; pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status; // assorted ast status ast_pkg::ast_pwst_t ast_pwst; @@ -1556,13 +1557,16 @@ module chip_darjeeling_asic #( .dma_ctn_tl_d2h_i ( ctn_tl_d2h[1] ), .mbx_tl_req_i ( tlul_pkg::TL_H2D_DEFAULT ), .mbx_tl_rsp_o ( ), + .pwrmgr_boot_status_o ( pwrmgr_boot_status ), .soc_fatal_alert_req_i ( soc_fatal_alert_req ), .soc_fatal_alert_rsp_o ( ), .soc_recov_alert_req_i ( soc_recov_alert_req ), .soc_recov_alert_rsp_o ( ), .soc_intr_async_i ( '0 ), .soc_wkup_async_i ( 1'b0 ), - .soc_rst_req_async_i ( 1'b0 ), + // FIXME: Needs better loopback fix + .soc_rst_req_async_i ( pwrmgr_boot_status.light_reset_req), + // FIXME_END .soc_lsio_trigger_i ( '0 ), .entropy_src_hw_if_req_o ( entropy_src_hw_if_req ), .entropy_src_hw_if_rsp_i ( entropy_src_hw_if_rsp ), diff --git a/hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv index 3178a740b4ddf9..a67bea62f417c2 100644 --- a/hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv +++ b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv @@ -875,6 +875,7 @@ module chip_darjeeling_cw310 #( // pwrmgr interface pwrmgr_pkg::pwr_ast_req_t base_ast_pwr; pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status; // assorted ast status ast_pkg::ast_pwst_t ast_pwst; @@ -1362,6 +1363,30 @@ module chip_darjeeling_cw310 #( assign srst_n = manual_in_por_button_n; + logic internal_request_d, internal_request_q; + logic external_reset, count_up; + logic [3:0] count; + assign internal_request_d = pwrmgr_boot_status.light_reset_req; + always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin : extrst + if (!por_n[0]) begin + external_reset <= 1'b0; + internal_request_q <= 1'b0; + count_up <= '0; + count <= '0; + end else begin + internal_request_q <= internal_request_d; + if (!internal_request_q && internal_request_d) begin + count_up <= 1'b1; + external_reset <= 1; + end else if (count == 'd8) begin + count_up <= 0; + external_reset <= 0; + count <= '0; + end else if (count_up) + count <= count + 1; + end + end : extrst + ////////////////////// // Top-level design // ////////////////////// diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv index 4c5ea9885b9476..04d43b6f651c8e 100644 --- a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv @@ -33,6 +33,7 @@ module top_darjeeling #( // parameters for alert_handler // parameters for spi_host0 // parameters for pwrmgr_aon + parameter int PwrmgrAonPwrFsmWait4ExtRst = 1, // parameters for rstmgr_aon parameter bit SecRstmgrAonCheck = 1'b1, parameter int SecRstmgrAonMaxSyncDelay = 2, @@ -148,6 +149,7 @@ module top_darjeeling #( input prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg_i, input prim_ram_2p_pkg::ram_2p_cfg_t spi_ram_2p_cfg_i, input prim_rom_pkg::rom_cfg_t rom_cfg_i, + output pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status_o, output prim_mubi_pkg::mubi4_t clk_main_jitter_en_o, output prim_mubi_pkg::mubi4_t io_clk_byp_req_o, input prim_mubi_pkg::mubi4_t io_clk_byp_ack_i, @@ -1293,7 +1295,8 @@ module top_darjeeling #( .rst_ni (rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel]) ); pwrmgr #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[14:14]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[14:14]), + .PwrFsmWait4ExtRst(PwrmgrAonPwrFsmWait4ExtRst) ) u_pwrmgr_aon ( // Interrupt @@ -1303,6 +1306,7 @@ module top_darjeeling #( .alert_rx_i ( alert_rx[14:14] ), // Inter-module signals + .boot_status_o(pwrmgr_boot_status_o), .pwr_ast_o(pwrmgr_ast_req_o), .pwr_ast_i(pwrmgr_ast_rsp_i), .pwr_rst_o(pwrmgr_aon_pwr_rst_req), @@ -1623,7 +1627,7 @@ module top_darjeeling #( .clk_i (clkmgr_aon_clocks.clk_main_infra), .clk_aon_i (clkmgr_aon_clocks.clk_aon_infra), .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), - .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::Domain0Sel]) + .rst_por_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::Domain0Sel]) ); sram_ctrl #( .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:52]), diff --git a/hw/top_darjeeling/rtl/chip_darjeeling_verilator.sv b/hw/top_darjeeling/rtl/chip_darjeeling_verilator.sv index 39928e209fdde5..296694ea62a272 100644 --- a/hw/top_darjeeling/rtl/chip_darjeeling_verilator.sv +++ b/hw/top_darjeeling/rtl/chip_darjeeling_verilator.sv @@ -164,6 +164,7 @@ module chip_darjeeling_verilator ( // pwrmgr interface pwrmgr_pkg::pwr_ast_req_t base_ast_pwr; pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status; ast_pkg::ast_clks_t ast_base_clks; @@ -540,6 +541,30 @@ module chip_darjeeling_verilator ( logic [rstmgr_pkg::PowerDomains-1:0] por_n; assign por_n = {ast_pwst.main_pok, ast_pwst.aon_pok}; + logic internal_request_d, internal_request_q; + logic external_reset, count_up; + logic [3:0] count; + assign internal_request_d = pwrmgr_boot_status.light_reset_req; + always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin : extrst + if (!por_n[0]) begin + external_reset <= 1'b0; + internal_request_q <= 1'b0; + count_up <= '0; + count <= '0; + end else begin + internal_request_q <= internal_request_d; + if (!internal_request_q && internal_request_d) begin + count_up <= 1'b1; + external_reset <= 1; + end else if (count == 'd8) begin + count_up <= 0; + external_reset <= 0; + count <= '0; + end else if (count_up) + count <= count + 1; + end + end : extrst + top_darjeeling #( .PinmuxAonTargetCfg(PinmuxTargetCfg), .SecAesAllowForcingMasks(1'b1), @@ -593,13 +618,16 @@ module chip_darjeeling_verilator ( .dma_sys_rsp_i ( '0 ), .dma_ctn_tl_h2d_o ( ), .dma_ctn_tl_d2h_i ( tlul_pkg::TL_D2H_DEFAULT ), + .pwrmgr_boot_status_o ( pwrmgr_boot_status ), .soc_fatal_alert_req_i ( 1'b0 ), .soc_fatal_alert_rsp_o ( ), .soc_recov_alert_req_i ( ), .soc_recov_alert_rsp_o ( ), .soc_intr_async_i ( '0 ), .soc_wkup_async_i ( 1'b0 ), - .soc_rst_req_async_i ( 1'b0 ), + // FIXME: Needs better loopback fix + .soc_rst_req_async_i ( external_reset), + // FIXME_END .soc_lsio_trigger_i ( '0 ), // OTP external voltage diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index d6679910b29571..3ea6fbe8c6bba2 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -2873,9 +2873,30 @@ clk_esc_i: clkmgr_aon_clocks.clk_io_div4_secure } param_decl: {} - param_list: [] + memory: {} + param_list: + [ + { + name: PwrFsmWait4ExtRst + desc: Number of reset requets + type: int + default: "0" + expose: "true" + name_top: PwrmgrAonPwrFsmWait4ExtRst + } + ] inter_signal_list: [ + { + name: boot_status + struct: pwr_boot_status + package: pwrmgr_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + index: -1 + } { name: pwr_ast struct: pwr_ast @@ -17147,6 +17168,16 @@ top_signame: usbdev_tl index: -1 } + { + name: boot_status + struct: pwr_boot_status + package: pwrmgr_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + index: -1 + } { name: pwr_ast struct: pwr_ast diff --git a/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson b/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson index f58eb4ce303334..62c96db5aae192 100644 --- a/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson +++ b/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson @@ -69,6 +69,12 @@ ], inter_signal_list: [ + { struct: "pwr_boot_status", + type: "uni", + name: "boot_status", + act: "req", + package: "pwrmgr_pkg", + }, { struct: "pwr_ast", type: "req_rsp", name: "pwr_ast", @@ -257,6 +263,14 @@ }, + { name: "PwrFsmWait4ExtRst", + desc: "Number of reset requets", + type: "int", + default: "0", + local: "false", + expose: "true" + }, + { name: "NumRstReqs", desc: "Number of peripheral reset requets", type: "int", diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv index 91057bfc3ffe52..700b9498501368 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv @@ -702,6 +702,7 @@ module chip_earlgrey_asic #( // pwrmgr interface pwrmgr_pkg::pwr_ast_req_t base_ast_pwr; pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status; // assorted ast status ast_pkg::ast_pwst_t ast_pwst; diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv index 846beec5314dd1..611e6a36cd5e25 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv @@ -646,6 +646,7 @@ module chip_earlgrey_cw310 #( // pwrmgr interface pwrmgr_pkg::pwr_ast_req_t base_ast_pwr; pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status; // assorted ast status ast_pkg::ast_pwst_t ast_pwst; @@ -976,6 +977,7 @@ module chip_earlgrey_cw310 #( assign srst_n = manual_in_por_button_n; + ////////////////////// // Top-level design // ////////////////////// diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 397cc8ba53efc6..fcb77ad1dcfd72 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -44,6 +44,7 @@ module top_earlgrey #( parameter bit UsbdevStub = 0, parameter int UsbdevRcvrWakeTimeUs = 100, // parameters for pwrmgr_aon + parameter int PwrmgrAonPwrFsmWait4ExtRst = 0, // parameters for rstmgr_aon parameter bit SecRstmgrAonCheck = 1'b1, parameter int SecRstmgrAonMaxSyncDelay = 2, @@ -1703,7 +1704,8 @@ module top_earlgrey #( .rst_aon_ni (rstmgr_aon_resets.rst_usb_aon_n[rstmgr_pkg::Domain0Sel]) ); pwrmgr #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[22:22]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[22:22]), + .PwrFsmWait4ExtRst(PwrmgrAonPwrFsmWait4ExtRst) ) u_pwrmgr_aon ( // Interrupt @@ -1713,6 +1715,7 @@ module top_earlgrey #( .alert_rx_i ( alert_rx[22:22] ), // Inter-module signals + .boot_status_o(), .pwr_ast_o(pwrmgr_ast_req_o), .pwr_ast_i(pwrmgr_ast_rsp_i), .pwr_rst_o(pwrmgr_aon_pwr_rst_req), diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl index 6e07e3eeb6e600..d660f8c8c9fd40 100644 --- a/util/topgen/templates/chiplevel.sv.tpl +++ b/util/topgen/templates/chiplevel.sv.tpl @@ -498,6 +498,7 @@ module chip_${top["name"]}_${target["name"]} #( // pwrmgr interface pwrmgr_pkg::pwr_ast_req_t base_ast_pwr; pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status; // assorted ast status ast_pkg::ast_pwst_t ast_pwst; @@ -1288,13 +1289,16 @@ module chip_${top["name"]}_${target["name"]} #( .dma_ctn_tl_d2h_i ( ctn_tl_d2h[1] ), .mbx_tl_req_i ( tlul_pkg::TL_H2D_DEFAULT ), .mbx_tl_rsp_o ( ), + .pwrmgr_boot_status_o ( pwrmgr_boot_status ), .soc_fatal_alert_req_i ( soc_fatal_alert_req ), .soc_fatal_alert_rsp_o ( ), .soc_recov_alert_req_i ( soc_recov_alert_req ), .soc_recov_alert_rsp_o ( ), .soc_intr_async_i ( '0 ), .soc_wkup_async_i ( 1'b0 ), - .soc_rst_req_async_i ( 1'b0 ), + // FIXME: Needs better loopback fix + .soc_rst_req_async_i ( pwrmgr_boot_status.light_reset_req), + // FIXME_END .soc_lsio_trigger_i ( '0 ), .entropy_src_hw_if_req_o ( entropy_src_hw_if_req ), .entropy_src_hw_if_rsp_i ( entropy_src_hw_if_rsp ), @@ -1438,6 +1442,32 @@ module chip_${top["name"]}_${target["name"]} #( assign otp_obs_o = '0; % endif + % if top["name"] == "darjeeling": + logic internal_request_d, internal_request_q; + logic external_reset, count_up; + logic [3:0] count; + assign internal_request_d = pwrmgr_boot_status.light_reset_req; + always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin : extrst + if (!por_n[0]) begin + external_reset <= 1'b0; + internal_request_q <= 1'b0; + count_up <= '0; + count <= '0; + end else begin + internal_request_q <= internal_request_d; + if (!internal_request_q && internal_request_d) begin + count_up <= 1'b1; + external_reset <= 1; + end else if (count == 'd8) begin + count_up <= 0; + external_reset <= 0; + count <= '0; + end else if (count_up) + count <= count + 1; + end + end : extrst + % endif + ////////////////////// // Top-level design // //////////////////////