From a9be9a9e7251846dfc4e5955ed03a2972370e56d Mon Sep 17 00:00:00 2001 From: Robert Schilling Date: Fri, 20 Dec 2024 14:25:12 +0100 Subject: [PATCH] [hw,spi_host,rtl] Remove configopts multi register FW needs to set up configopts before starting a transfer Signed-off-by: Robert Schilling --- hw/ip/spi_host/data/spi_host.hjson | 146 +++++++++--------- hw/ip/spi_host/doc/registers.md | 68 ++++---- hw/ip/spi_host/dv/README.md | 14 +- .../dv/env/seq_lib/spi_host_base_vseq.sv | 18 +-- .../spi_host_overflow_underflow_vseq.sv | 2 +- hw/ip/spi_host/dv/env/spi_host_env_cov.sv | 15 +- hw/ip/spi_host/dv/env/spi_host_env_pkg.sv | 14 +- hw/ip/spi_host/dv/env/spi_host_scoreboard.sv | 25 +-- hw/ip/spi_host/rtl/spi_host.sv | 28 ++-- hw/ip/spi_host/rtl/spi_host_reg_pkg.sv | 4 +- hw/ip/spi_host/rtl/spi_host_reg_top.sv | 127 ++++++++------- 11 files changed, 214 insertions(+), 247 deletions(-) diff --git a/hw/ip/spi_host/data/spi_host.hjson b/hw/ip/spi_host/data/spi_host.hjson index 86389e5879fc0..d7735f1b78c19 100644 --- a/hw/ip/spi_host/data/spi_host.hjson +++ b/hw/ip/spi_host/data/spi_host.hjson @@ -317,81 +317,79 @@ "excl:CsrAllTests:CsrExclCheck"] }, - { multireg: { name: "CONFIGOPTS", - desc: '''Configuration options register. + { name: "CONFIGOPTS", + desc: '''Configuration options register. - Contains options for controlling each peripheral. One register per - cs_n line''', - swaccess: "rw", - hwaccess: "hro", - cname: "configopts", - count: "NumCS", - fields: [ - { bits: "31", - name: "CPOL", - desc: '''The polarity of the sck clock signal. When CPOL is 0, - sck is low when idle, and emits high pulses. When CPOL - is 1, sck is high when idle, and emits a series of low - pulses.''' - resval: "0x0" - }, - { bits: "30", - name: "CPHA", - desc: '''The phase of the sck clock signal relative to the data. When - CPHA = 0, the data changes on the trailing edge of sck - and is typically sampled on the leading edge. Conversely - if CPHA = 1 high, data lines change on the leading edge of - sck and are typically sampled on the trailing edge. - CPHA should be chosen to match the phase of the selected - device. The sampling behavior is modified by the - !!CONFIGOPTS.FULLCYC bit.''', - resval: "0x0" - }, - { bits: "29", - name: "FULLCYC", - desc: '''Full cycle. Modifies the CPHA sampling behaviour to allow - for longer device logic setup times. Rather than sampling the SD - bus a half cycle after shifting out data, the data is sampled - a full cycle after shifting data out. This means that if - CPHA = 0, data is shifted out on the trailing edge, and - sampled a full cycle later. If CPHA = 1, data is shifted and - sampled with the trailing edge, also separated by a - full cycle.''', - resval: 0 - }, - { bits: "27:24", - name: "CSNLEAD", - desc: '''CS_N Leading Time. Indicates the number of half sck cycles, - CSNLEAD+1, to leave between the falling edge of cs_n and - the first edge of sck. Setting this register to zero - corresponds to the minimum delay of one-half sck cycle''' - resval: 0 - }, - { bits: "23:20", - name: "CSNTRAIL" - desc: '''CS_N Trailing Time. Indicates the number of half sck cycles, - CSNTRAIL+1, to leave between last edge of sck and the rising - edge of cs_n. Setting this register to zero corresponds - to the minimum delay of one-half sck cycle.''' - resval: 0 - }, - { bits: "19:16", - name: "CSNIDLE" - desc: '''Minimum idle time between commands. Indicates the minimum - number of sck half-cycles to hold cs_n high between commands. - Setting this register to zero creates a minimally-wide CS_N-high - pulse of one-half sck cycle.''' - resval: 0 - }, - { bits: "15:0", - name: "CLKDIV", - desc: '''Core clock divider. Slows down subsequent SPI transactions by a - factor of (CLKDIV+1) relative to the core clock frequency. The - period of sck, T(sck) then becomes `2*(CLK_DIV+1)*T(core)`''' - resval: 0 - }, - ] - } + Contains options for controlling the current peripheral. + Firmware needs to configure the options before the transfer. + ''' + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "31", + name: "CPOL", + desc: '''The polarity of the sck clock signal. When CPOL is 0, + sck is low when idle, and emits high pulses. When CPOL + is 1, sck is high when idle, and emits a series of low + pulses.''' + resval: "0x0" + }, + { bits: "30", + name: "CPHA", + desc: '''The phase of the sck clock signal relative to the data. When + CPHA = 0, the data changes on the trailing edge of sck + and is typically sampled on the leading edge. Conversely + if CPHA = 1 high, data lines change on the leading edge of + sck and are typically sampled on the trailing edge. + CPHA should be chosen to match the phase of the selected + device. The sampling behavior is modified by the + !!CONFIGOPTS.FULLCYC bit.''', + resval: "0x0" + }, + { bits: "29", + name: "FULLCYC", + desc: '''Full cycle. Modifies the CPHA sampling behaviour to allow + for longer device logic setup times. Rather than sampling the SD + bus a half cycle after shifting out data, the data is sampled + a full cycle after shifting data out. This means that if + CPHA = 0, data is shifted out on the trailing edge, and + sampled a full cycle later. If CPHA = 1, data is shifted and + sampled with the trailing edge, also separated by a + full cycle.''', + resval: 0 + }, + { bits: "27:24", + name: "CSNLEAD", + desc: '''CS_N Leading Time. Indicates the number of half sck cycles, + CSNLEAD+1, to leave between the falling edge of cs_n and + the first edge of sck. Setting this register to zero + corresponds to the minimum delay of one-half sck cycle''' + resval: 0 + }, + { bits: "23:20", + name: "CSNTRAIL" + desc: '''CS_N Trailing Time. Indicates the number of half sck cycles, + CSNTRAIL+1, to leave between last edge of sck and the rising + edge of cs_n. Setting this register to zero corresponds + to the minimum delay of one-half sck cycle.''' + resval: 0 + }, + { bits: "19:16", + name: "CSNIDLE" + desc: '''Minimum idle time between commands. Indicates the minimum + number of sck half-cycles to hold cs_n high between commands. + Setting this register to zero creates a minimally-wide CS_N-high + pulse of one-half sck cycle.''' + resval: 0 + }, + { bits: "15:0", + name: "CLKDIV", + desc: '''Core clock divider. Slows down subsequent SPI transactions by a + factor of (CLKDIV+1) relative to the core clock frequency. The + period of sck, T(sck) then becomes `2*(CLK_DIV+1)*T(core)`''' + resval: 0 + }, + ] }, { name: "CSID", desc: '''Chip-Select ID diff --git a/hw/ip/spi_host/doc/registers.md b/hw/ip/spi_host/doc/registers.md index df17ebc3a29d1..0479080d2db37 100644 --- a/hw/ip/spi_host/doc/registers.md +++ b/hw/ip/spi_host/doc/registers.md @@ -171,18 +171,12 @@ Status register ## CONFIGOPTS Configuration options register. - Contains options for controlling each peripheral. One register per - cs_n line + Contains options for controlling the current peripheral. + Firmware needs to configure the options before the transfer. +- Offset: `0x18` - Reset default: `0x0` - Reset mask: `0xefffffff` -### Instances - -| Name | Offset | -|:-----------|:---------| -| CONFIGOPTS | 0x18 | - - ### Fields ```wavejson @@ -202,52 +196,52 @@ Configuration options register. ### CONFIGOPTS . CPOL The polarity of the sck clock signal. When CPOL is 0, - sck is low when idle, and emits high pulses. When CPOL - is 1, sck is high when idle, and emits a series of low - pulses. + sck is low when idle, and emits high pulses. When CPOL + is 1, sck is high when idle, and emits a series of low + pulses. ### CONFIGOPTS . CPHA The phase of the sck clock signal relative to the data. When - CPHA = 0, the data changes on the trailing edge of sck - and is typically sampled on the leading edge. Conversely - if CPHA = 1 high, data lines change on the leading edge of - sck and are typically sampled on the trailing edge. - CPHA should be chosen to match the phase of the selected - device. The sampling behavior is modified by the - [`CONFIGOPTS.FULLCYC`](#configopts) bit. + CPHA = 0, the data changes on the trailing edge of sck + and is typically sampled on the leading edge. Conversely + if CPHA = 1 high, data lines change on the leading edge of + sck and are typically sampled on the trailing edge. + CPHA should be chosen to match the phase of the selected + device. The sampling behavior is modified by the + [`CONFIGOPTS.FULLCYC`](#configopts) bit. ### CONFIGOPTS . FULLCYC Full cycle. Modifies the CPHA sampling behaviour to allow - for longer device logic setup times. Rather than sampling the SD - bus a half cycle after shifting out data, the data is sampled - a full cycle after shifting data out. This means that if - CPHA = 0, data is shifted out on the trailing edge, and - sampled a full cycle later. If CPHA = 1, data is shifted and - sampled with the trailing edge, also separated by a - full cycle. + for longer device logic setup times. Rather than sampling the SD + bus a half cycle after shifting out data, the data is sampled + a full cycle after shifting data out. This means that if + CPHA = 0, data is shifted out on the trailing edge, and + sampled a full cycle later. If CPHA = 1, data is shifted and + sampled with the trailing edge, also separated by a + full cycle. ### CONFIGOPTS . CSNLEAD CS_N Leading Time. Indicates the number of half sck cycles, - CSNLEAD+1, to leave between the falling edge of cs_n and - the first edge of sck. Setting this register to zero - corresponds to the minimum delay of one-half sck cycle + CSNLEAD+1, to leave between the falling edge of cs_n and + the first edge of sck. Setting this register to zero + corresponds to the minimum delay of one-half sck cycle ### CONFIGOPTS . CSNTRAIL CS_N Trailing Time. Indicates the number of half sck cycles, - CSNTRAIL+1, to leave between last edge of sck and the rising - edge of cs_n. Setting this register to zero corresponds - to the minimum delay of one-half sck cycle. + CSNTRAIL+1, to leave between last edge of sck and the rising + edge of cs_n. Setting this register to zero corresponds + to the minimum delay of one-half sck cycle. ### CONFIGOPTS . CSNIDLE Minimum idle time between commands. Indicates the minimum - number of sck half-cycles to hold cs_n high between commands. - Setting this register to zero creates a minimally-wide CS_N-high - pulse of one-half sck cycle. + number of sck half-cycles to hold cs_n high between commands. + Setting this register to zero creates a minimally-wide CS_N-high + pulse of one-half sck cycle. ### CONFIGOPTS . CLKDIV Core clock divider. Slows down subsequent SPI transactions by a - factor of (CLKDIV+1) relative to the core clock frequency. The - period of sck, T(sck) then becomes `2*(CLK_DIV+1)*T(core)` + factor of (CLKDIV+1) relative to the core clock frequency. The + period of sck, T(sck) then becomes `2*(CLK_DIV+1)*T(core)` ## CSID Chip-Select ID diff --git a/hw/ip/spi_host/dv/README.md b/hw/ip/spi_host/dv/README.md index 5fc7c9974cde2..609a58b34b042 100644 --- a/hw/ip/spi_host/dv/README.md +++ b/hw/ip/spi_host/dv/README.md @@ -74,13 +74,13 @@ All common types and methods defined at the package level can be found in // spi config typedef struct { // configopts register fields - rand bit cpol[SPI_HOST_NUM_CS]; - rand bit cpha[SPI_HOST_NUM_CS]; - rand bit fullcyc[SPI_HOST_NUM_CS]; - rand bit [3:0] csnlead[SPI_HOST_NUM_CS]; - rand bit [3:0] csntrail[SPI_HOST_NUM_CS]; - rand bit [3:0] csnidle[SPI_HOST_NUM_CS]; - rand bit [15:0] clkdiv[SPI_HOST_NUM_CS]; + rand bit cpol; + rand bit cpha; + rand bit fullcyc; + rand bit [3:0] csnlead; + rand bit [3:0] csntrail; + rand bit [3:0] csnidle; + rand bit [15:0] clkdiv; } spi_host_configopts_t; typedef struct { diff --git a/hw/ip/spi_host/dv/env/seq_lib/spi_host_base_vseq.sv b/hw/ip/spi_host/dv/env/seq_lib/spi_host_base_vseq.sv index 36c4a5aecf512..25732263dadd3 100644 --- a/hw/ip/spi_host/dv/env/seq_lib/spi_host_base_vseq.sv +++ b/hw/ip/spi_host/dv/env/seq_lib/spi_host_base_vseq.sv @@ -248,16 +248,14 @@ class spi_host_base_vseq extends cip_base_vseq #( // CONFIGOPTS register fields virtual task program_configopt_regs(); - for (int i = 0; i < SPI_HOST_NUM_CS; i++) begin - ral.configopts[i].cpol.set(spi_config_regs.cpol[0]); - ral.configopts[i].cpha.set(spi_config_regs.cpha[0]); - ral.configopts[i].fullcyc.set(spi_config_regs.fullcyc[0]); - ral.configopts[i].csnlead.set(spi_config_regs.csnlead[0]); - ral.configopts[i].csntrail.set(spi_config_regs.csntrail[0]); - ral.configopts[i].csnidle.set(spi_config_regs.csnidle[0]); - ral.configopts[i].clkdiv.set(spi_config_regs.clkdiv[0]); - csr_wr(ral.configopts[i], .value(ral.configopts[i].get())); - end + ral.configopts.cpol.set(spi_config_regs.cpol[0]); + ral.configopts.cpha.set(spi_config_regs.cpha[0]); + ral.configopts.fullcyc.set(spi_config_regs.fullcyc[0]); + ral.configopts.csnlead.set(spi_config_regs.csnlead[0]); + ral.configopts.csntrail.set(spi_config_regs.csntrail[0]); + ral.configopts.csnidle.set(spi_config_regs.csnidle[0]); + ral.configopts.clkdiv.set(spi_config_regs.clkdiv[0]); + csr_wr(ral.configopts, .value(ral.configopts.get())); endtask : program_configopt_regs diff --git a/hw/ip/spi_host/dv/env/seq_lib/spi_host_overflow_underflow_vseq.sv b/hw/ip/spi_host/dv/env/seq_lib/spi_host_overflow_underflow_vseq.sv index 7d202f9a11e9b..472a9391b0a32 100644 --- a/hw/ip/spi_host/dv/env/seq_lib/spi_host_overflow_underflow_vseq.sv +++ b/hw/ip/spi_host/dv/env/seq_lib/spi_host_overflow_underflow_vseq.sv @@ -47,7 +47,7 @@ class spi_host_overflow_underflow_vseq extends spi_host_tx_rx_vseq; access_data_fifo(read_q, RxFifo, 1'b0); // attempting empty read error underflow check_error(ral.error_status.underflow,1); - csr_wr(.ptr(ral.configopts[0].clkdiv), .value(16'h28)); // clk div set to 20 + csr_wr(.ptr(ral.configopts.clkdiv), .value(16'h28)); // clk div set to 20 while (segms_words <= (SPI_HOST_TX_DEPTH + 1)) begin check_error(ral.error_status.overflow,0); diff --git a/hw/ip/spi_host/dv/env/spi_host_env_cov.sv b/hw/ip/spi_host/dv/env/spi_host_env_cov.sv index cd2b651addcf6..1bde1766ccc44 100644 --- a/hw/ip/spi_host/dv/env/spi_host_env_cov.sv +++ b/hw/ip/spi_host/dv/env/spi_host_env_cov.sv @@ -7,7 +7,6 @@ * only in build_phase can be defined here * Covergroups may also be wrapped inside helper classes if needed. */ -//TODO(#18886) we only support SPI_HOST_NUM_CS=1 class spi_host_env_cov extends cip_base_env_cov #(.CFG_T(spi_host_env_cfg)); `uvm_component_utils(spi_host_env_cov) @@ -29,18 +28,18 @@ class spi_host_env_cov extends cip_base_env_cov #(.CFG_T(spi_host_env_cfg)); endgroup : rx_fifo_underflow_cg covergroup config_opts_cg with function sample(spi_host_configopts_t spi_configopts); - cpol_cp : coverpoint spi_configopts.cpol[SPI_HOST_NUM_CS-1]{ bins cpol[] = {[0:1]}; } - cpha_cp : coverpoint spi_configopts.cpha[SPI_HOST_NUM_CS-1]{ bins cpha[] = {[0:1]}; } - fullcyc_cp : coverpoint spi_configopts.fullcyc[SPI_HOST_NUM_CS-1]{ + cpol_cp : coverpoint spi_configopts.cpol{ bins cpol[] = {[0:1]}; } + cpha_cp : coverpoint spi_configopts.cpha{ bins cpha[] = {[0:1]}; } + fullcyc_cp : coverpoint spi_configopts.fullcyc{ bins fullcyc[] = {[0:1]}; } - csnlead_cp : coverpoint spi_configopts.csnlead[SPI_HOST_NUM_CS-1]{ + csnlead_cp : coverpoint spi_configopts.csnlead{ bins csnlead[] = {[0:15]}; } - csnidle_cp : coverpoint spi_configopts.csnidle[SPI_HOST_NUM_CS-1]{ + csnidle_cp : coverpoint spi_configopts.csnidle{ bins csnidle[] = {[0:15]}; } - clkdiv_cp : coverpoint spi_configopts.clkdiv[SPI_HOST_NUM_CS-1]{ + clkdiv_cp : coverpoint spi_configopts.clkdiv{ // (Period) T_sck = 2*(clkdiv+1)*T_core // If clkdiv == 16'h00fe, F_sck = F_core / 254 bins clk_div_zero = {0}; @@ -48,7 +47,7 @@ class spi_host_env_cov extends cip_base_env_cov #(.CFG_T(spi_host_env_cfg)); bins clk_divm_upper_eight[30] = {[16'h00ff:16'hfffe]}; bins clk_divm_max = {16'hffff}; } - csntrail_cp : coverpoint spi_configopts.csntrail[SPI_HOST_NUM_CS-1]{ + csntrail_cp : coverpoint spi_configopts.csntrail{ bins csntrail[] = {[0:15]}; } cpol_cpha_cross : cross cpol_cp, cpha_cp; diff --git a/hw/ip/spi_host/dv/env/spi_host_env_pkg.sv b/hw/ip/spi_host/dv/env/spi_host_env_pkg.sv index c582cda61205a..cba674cd11de4 100644 --- a/hw/ip/spi_host/dv/env/spi_host_env_pkg.sv +++ b/hw/ip/spi_host/dv/env/spi_host_env_pkg.sv @@ -58,13 +58,13 @@ package spi_host_env_pkg; // spi config typedef struct { // configopts register fields - rand bit cpol[SPI_HOST_NUM_CS]; - rand bit cpha[SPI_HOST_NUM_CS]; - rand bit fullcyc[SPI_HOST_NUM_CS]; - rand bit [3:0] csnlead[SPI_HOST_NUM_CS]; - rand bit [3:0] csntrail[SPI_HOST_NUM_CS]; - rand bit [3:0] csnidle[SPI_HOST_NUM_CS]; - rand bit [15:0] clkdiv[SPI_HOST_NUM_CS]; + rand bit cpol; + rand bit cpha; + rand bit fullcyc; + rand bit [3:0] csnlead; + rand bit [3:0] csntrail; + rand bit [3:0] csnidle; + rand bit [15:0] clkdiv; } spi_host_configopts_t; typedef struct { diff --git a/hw/ip/spi_host/dv/env/spi_host_scoreboard.sv b/hw/ip/spi_host/dv/env/spi_host_scoreboard.sv index ccbf808a8807a..9bc2edc6ff7d0 100644 --- a/hw/ip/spi_host/dv/env/spi_host_scoreboard.sv +++ b/hw/ip/spi_host/dv/env/spi_host_scoreboard.sv @@ -387,24 +387,13 @@ class spi_host_scoreboard extends cip_base_scoreboard #( end "configopts": begin - // Note: CONFIGOPTS is actually a multireg, but we've only got a count of 1, which means - // the CSR is called "configopts" (instead of e.g. configopts0). Manufacture CSR index - // accordingly. - int csr_idx = 0; - spi_configopts.cpol[csr_idx] = get_field_val(ral.configopts[csr_idx].cpol, - item.a_data); - spi_configopts.cpha[csr_idx] = get_field_val(ral.configopts[csr_idx].cpha, - item.a_data); - spi_configopts.fullcyc[csr_idx] = get_field_val(ral.configopts[csr_idx].fullcyc, - item.a_data); - spi_configopts.csnlead[csr_idx] = get_field_val(ral.configopts[csr_idx].csnlead, - item.a_data); - spi_configopts.csnidle[csr_idx] = get_field_val(ral.configopts[csr_idx].csnidle, - item.a_data); - spi_configopts.clkdiv[csr_idx] = get_field_val(ral.configopts[csr_idx].clkdiv, - item.a_data); - spi_configopts.csntrail[csr_idx] = get_field_val(ral.configopts[csr_idx].csntrail, - item.a_data); + spi_configopts.cpol = get_field_val(ral.configopts.cpol, item.a_data); + spi_configopts.cpha = get_field_val(ral.configopts.cpha, item.a_data); + spi_configopts.fullcyc = get_field_val(ral.configopts.fullcyc, item.a_data); + spi_configopts.csnlead = get_field_val(ral.configopts.csnlead, item.a_data); + spi_configopts.csnidle = get_field_val(ral.configopts.csnidle, item.a_data); + spi_configopts.clkdiv = get_field_val(ral.configopts.clkdiv, item.a_data); + spi_configopts.csntrail = get_field_val(ral.configopts.csntrail, item.a_data); if (cfg.en_cov) begin cov.config_opts_cg.sample(spi_configopts); end diff --git a/hw/ip/spi_host/rtl/spi_host.sv b/hw/ip/spi_host/rtl/spi_host.sv index ab91529fe902f..bf9de365e9402 100644 --- a/hw/ip/spi_host/rtl/spi_host.sv +++ b/hw/ip/spi_host/rtl/spi_host.sv @@ -216,25 +216,15 @@ module spi_host assign error_cmd_inval = command_valid & ~command_busy & (test_speed_inval | test_dir_inval); - spi_host_reg_pkg::spi_host_reg2hw_configopts_mreg_t configopts; - - if (NumCS == 1) begin : gen_single_device - assign configopts = reg2hw.configopts[0]; - assign command.csid = '0; - end else begin : gen_multiple_devices - logic [CSW-1:0] csid; - assign csid = (test_csid_inval) ? '0 : reg2hw.csid.q[CSW-1:0]; - assign configopts = reg2hw.configopts[csid]; - assign command.csid = csid; - end : gen_multiple_devices - - assign command.configopts.clkdiv = configopts.clkdiv.q; - assign command.configopts.csnidle = configopts.csnidle.q; - assign command.configopts.csnlead = configopts.csnlead.q; - assign command.configopts.csntrail = configopts.csntrail.q; - assign command.configopts.full_cyc = configopts.fullcyc.q; - assign command.configopts.cpha = configopts.cpha.q; - assign command.configopts.cpol = configopts.cpol.q; + assign command.csid = (test_csid_inval) ? '0 : reg2hw.csid.q[CSW-1:0];; + + assign command.configopts.clkdiv = reg2hw.configopts.clkdiv.q; + assign command.configopts.csnidle = reg2hw.configopts.csnidle.q; + assign command.configopts.csnlead = reg2hw.configopts.csnlead.q; + assign command.configopts.csntrail = reg2hw.configopts.csntrail.q; + assign command.configopts.full_cyc = reg2hw.configopts.fullcyc.q; + assign command.configopts.cpha = reg2hw.configopts.cpha.q; + assign command.configopts.cpol = reg2hw.configopts.cpol.q; assign command.segment.len = reg2hw.command.len.q; assign command.segment.csaat = reg2hw.command.csaat.q; diff --git a/hw/ip/spi_host/rtl/spi_host_reg_pkg.sv b/hw/ip/spi_host/rtl/spi_host_reg_pkg.sv index 97e30acf97af3..1ba5fd4968b8b 100644 --- a/hw/ip/spi_host/rtl/spi_host_reg_pkg.sv +++ b/hw/ip/spi_host/rtl/spi_host_reg_pkg.sv @@ -95,7 +95,7 @@ package spi_host_reg_pkg; struct packed { logic [15:0] q; } clkdiv; - } spi_host_reg2hw_configopts_mreg_t; + } spi_host_reg2hw_configopts_reg_t; typedef struct packed { logic [31:0] q; @@ -284,7 +284,7 @@ package spi_host_reg_pkg; spi_host_reg2hw_intr_test_reg_t intr_test; // [122:119] spi_host_reg2hw_alert_test_reg_t alert_test; // [118:117] spi_host_reg2hw_control_reg_t control; // [116:98] - spi_host_reg2hw_configopts_mreg_t [0:0] configopts; // [97:67] + spi_host_reg2hw_configopts_reg_t configopts; // [97:67] spi_host_reg2hw_csid_reg_t csid; // [66:35] spi_host_reg2hw_command_reg_t command; // [34:17] spi_host_reg2hw_error_enable_reg_t error_enable; // [16:12] diff --git a/hw/ip/spi_host/rtl/spi_host_reg_top.sv b/hw/ip/spi_host/rtl/spi_host_reg_top.sv index 75ce27dc226d2..e9e1072a565c3 100644 --- a/hw/ip/spi_host/rtl/spi_host_reg_top.sv +++ b/hw/ip/spi_host/rtl/spi_host_reg_top.sv @@ -213,20 +213,20 @@ module spi_host_reg_top ( logic status_active_qs; logic status_ready_qs; logic configopts_we; - logic [15:0] configopts_clkdiv_0_qs; - logic [15:0] configopts_clkdiv_0_wd; - logic [3:0] configopts_csnidle_0_qs; - logic [3:0] configopts_csnidle_0_wd; - logic [3:0] configopts_csntrail_0_qs; - logic [3:0] configopts_csntrail_0_wd; - logic [3:0] configopts_csnlead_0_qs; - logic [3:0] configopts_csnlead_0_wd; - logic configopts_fullcyc_0_qs; - logic configopts_fullcyc_0_wd; - logic configopts_cpha_0_qs; - logic configopts_cpha_0_wd; - logic configopts_cpol_0_qs; - logic configopts_cpol_0_wd; + logic [15:0] configopts_clkdiv_qs; + logic [15:0] configopts_clkdiv_wd; + logic [3:0] configopts_csnidle_qs; + logic [3:0] configopts_csnidle_wd; + logic [3:0] configopts_csntrail_qs; + logic [3:0] configopts_csntrail_wd; + logic [3:0] configopts_csnlead_qs; + logic [3:0] configopts_csnlead_wd; + logic configopts_fullcyc_qs; + logic configopts_fullcyc_wd; + logic configopts_cpha_qs; + logic configopts_cpha_wd; + logic configopts_cpol_qs; + logic configopts_cpol_wd; logic csid_we; logic [31:0] csid_qs; logic [31:0] csid_wd; @@ -960,21 +960,20 @@ module spi_host_reg_top ( ); - // Subregister 0 of Multireg configopts // R[configopts]: V(False) - // F[clkdiv_0]: 15:0 + // F[clkdiv]: 15:0 prim_subreg #( .DW (16), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (16'h0), .Mubi (1'b0) - ) u_configopts_clkdiv_0 ( + ) u_configopts_clkdiv ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (configopts_we), - .wd (configopts_clkdiv_0_wd), + .wd (configopts_clkdiv_wd), // from internal hardware .de (1'b0), @@ -982,26 +981,26 @@ module spi_host_reg_top ( // to internal hardware .qe (), - .q (reg2hw.configopts[0].clkdiv.q), + .q (reg2hw.configopts.clkdiv.q), .ds (), // to register interface (read) - .qs (configopts_clkdiv_0_qs) + .qs (configopts_clkdiv_qs) ); - // F[csnidle_0]: 19:16 + // F[csnidle]: 19:16 prim_subreg #( .DW (4), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (4'h0), .Mubi (1'b0) - ) u_configopts_csnidle_0 ( + ) u_configopts_csnidle ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (configopts_we), - .wd (configopts_csnidle_0_wd), + .wd (configopts_csnidle_wd), // from internal hardware .de (1'b0), @@ -1009,26 +1008,26 @@ module spi_host_reg_top ( // to internal hardware .qe (), - .q (reg2hw.configopts[0].csnidle.q), + .q (reg2hw.configopts.csnidle.q), .ds (), // to register interface (read) - .qs (configopts_csnidle_0_qs) + .qs (configopts_csnidle_qs) ); - // F[csntrail_0]: 23:20 + // F[csntrail]: 23:20 prim_subreg #( .DW (4), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (4'h0), .Mubi (1'b0) - ) u_configopts_csntrail_0 ( + ) u_configopts_csntrail ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (configopts_we), - .wd (configopts_csntrail_0_wd), + .wd (configopts_csntrail_wd), // from internal hardware .de (1'b0), @@ -1036,26 +1035,26 @@ module spi_host_reg_top ( // to internal hardware .qe (), - .q (reg2hw.configopts[0].csntrail.q), + .q (reg2hw.configopts.csntrail.q), .ds (), // to register interface (read) - .qs (configopts_csntrail_0_qs) + .qs (configopts_csntrail_qs) ); - // F[csnlead_0]: 27:24 + // F[csnlead]: 27:24 prim_subreg #( .DW (4), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (4'h0), .Mubi (1'b0) - ) u_configopts_csnlead_0 ( + ) u_configopts_csnlead ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (configopts_we), - .wd (configopts_csnlead_0_wd), + .wd (configopts_csnlead_wd), // from internal hardware .de (1'b0), @@ -1063,26 +1062,26 @@ module spi_host_reg_top ( // to internal hardware .qe (), - .q (reg2hw.configopts[0].csnlead.q), + .q (reg2hw.configopts.csnlead.q), .ds (), // to register interface (read) - .qs (configopts_csnlead_0_qs) + .qs (configopts_csnlead_qs) ); - // F[fullcyc_0]: 29:29 + // F[fullcyc]: 29:29 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_configopts_fullcyc_0 ( + ) u_configopts_fullcyc ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (configopts_we), - .wd (configopts_fullcyc_0_wd), + .wd (configopts_fullcyc_wd), // from internal hardware .de (1'b0), @@ -1090,26 +1089,26 @@ module spi_host_reg_top ( // to internal hardware .qe (), - .q (reg2hw.configopts[0].fullcyc.q), + .q (reg2hw.configopts.fullcyc.q), .ds (), // to register interface (read) - .qs (configopts_fullcyc_0_qs) + .qs (configopts_fullcyc_qs) ); - // F[cpha_0]: 30:30 + // F[cpha]: 30:30 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_configopts_cpha_0 ( + ) u_configopts_cpha ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (configopts_we), - .wd (configopts_cpha_0_wd), + .wd (configopts_cpha_wd), // from internal hardware .de (1'b0), @@ -1117,26 +1116,26 @@ module spi_host_reg_top ( // to internal hardware .qe (), - .q (reg2hw.configopts[0].cpha.q), + .q (reg2hw.configopts.cpha.q), .ds (), // to register interface (read) - .qs (configopts_cpha_0_qs) + .qs (configopts_cpha_qs) ); - // F[cpol_0]: 31:31 + // F[cpol]: 31:31 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_configopts_cpol_0 ( + ) u_configopts_cpol ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (configopts_we), - .wd (configopts_cpol_0_wd), + .wd (configopts_cpol_wd), // from internal hardware .de (1'b0), @@ -1144,11 +1143,11 @@ module spi_host_reg_top ( // to internal hardware .qe (), - .q (reg2hw.configopts[0].cpol.q), + .q (reg2hw.configopts.cpol.q), .ds (), // to register interface (read) - .qs (configopts_cpol_0_qs) + .qs (configopts_cpol_qs) ); @@ -1781,19 +1780,19 @@ module spi_host_reg_top ( assign control_spien_wd = reg_wdata[31]; assign configopts_we = addr_hit[6] & reg_we & !reg_error; - assign configopts_clkdiv_0_wd = reg_wdata[15:0]; + assign configopts_clkdiv_wd = reg_wdata[15:0]; - assign configopts_csnidle_0_wd = reg_wdata[19:16]; + assign configopts_csnidle_wd = reg_wdata[19:16]; - assign configopts_csntrail_0_wd = reg_wdata[23:20]; + assign configopts_csntrail_wd = reg_wdata[23:20]; - assign configopts_csnlead_0_wd = reg_wdata[27:24]; + assign configopts_csnlead_wd = reg_wdata[27:24]; - assign configopts_fullcyc_0_wd = reg_wdata[29]; + assign configopts_fullcyc_wd = reg_wdata[29]; - assign configopts_cpha_0_wd = reg_wdata[30]; + assign configopts_cpha_wd = reg_wdata[30]; - assign configopts_cpol_0_wd = reg_wdata[31]; + assign configopts_cpol_wd = reg_wdata[31]; assign csid_we = addr_hit[7] & reg_we & !reg_error; assign csid_wd = reg_wdata[31:0]; @@ -1910,13 +1909,13 @@ module spi_host_reg_top ( end addr_hit[6]: begin - reg_rdata_next[15:0] = configopts_clkdiv_0_qs; - reg_rdata_next[19:16] = configopts_csnidle_0_qs; - reg_rdata_next[23:20] = configopts_csntrail_0_qs; - reg_rdata_next[27:24] = configopts_csnlead_0_qs; - reg_rdata_next[29] = configopts_fullcyc_0_qs; - reg_rdata_next[30] = configopts_cpha_0_qs; - reg_rdata_next[31] = configopts_cpol_0_qs; + reg_rdata_next[15:0] = configopts_clkdiv_qs; + reg_rdata_next[19:16] = configopts_csnidle_qs; + reg_rdata_next[23:20] = configopts_csntrail_qs; + reg_rdata_next[27:24] = configopts_csnlead_qs; + reg_rdata_next[29] = configopts_fullcyc_qs; + reg_rdata_next[30] = configopts_cpha_qs; + reg_rdata_next[31] = configopts_cpol_qs; end addr_hit[7]: begin