diff --git a/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core b/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core
index c8b442bfb808f..ac107276ec38c 100644
--- a/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core
+++ b/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core
@@ -8,7 +8,7 @@ description: "English Breakfast toplevel for the ChipWhisperer CW305 board"
 filesets:
   files_rtl_cw305:
     depend:
-      - lowrisc:prim_xilinx:prim_xilinx_default_pkg
+      - lowrisc:prim_xilinx:englishbreakfast_xilinx_prim_pkg
       - lowrisc:systems:top_englishbreakfast:0.1
       - lowrisc:systems:ast
       - lowrisc:systems:topgen
diff --git a/hw/top_englishbreakfast/englishbreakfast_xilinx_prim_pkg.core b/hw/top_englishbreakfast/englishbreakfast_xilinx_prim_pkg.core
new file mode 100644
index 0000000000000..bbf1f824a5bca
--- /dev/null
+++ b/hw/top_englishbreakfast/englishbreakfast_xilinx_prim_pkg.core
@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim_xilinx:englishbreakfast_xilinx_prim_pkg"
+description: "Prim configuration for englishbreakfast"
+virtual:
+  - lowrisc:prim_xilinx:prim_xilinx_pkg
+filesets:
+  files_rtl:
+    files:
+      - rtl/prim_xilinx_pkg.sv
+    file_type: systemVerilogSource
+
+targets:
+  default: &default_target
+    filesets:
+      - files_rtl
diff --git a/hw/top_englishbreakfast/rtl/prim_xilinx_pkg.sv b/hw/top_englishbreakfast/rtl/prim_xilinx_pkg.sv
new file mode 100644
index 0000000000000..aa1a2b0b8f6c4
--- /dev/null
+++ b/hw/top_englishbreakfast/rtl/prim_xilinx_pkg.sv
@@ -0,0 +1,20 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package prim_xilinx_pkg;
+
+  // Accommodates updatemem by breaking up flash info arrays into data and
+  // metadata subarrays. The 76-bit width and 1 BRAM depth identifies these
+  // memories in earlgrey, and we limit the subarray size to 64 bits, which is
+  // the size of the data portion. The leftover 12 bits get placed into their
+  // own memory with a unique hierarchical path. See prim_xilinx_ram_1p.sv to
+  // see how this works.
+  function automatic int get_ram_max_width(int width, int depth);
+    if (width == 76 && depth < 4096) begin
+      return 64;
+    end
+    return 0;
+  endfunction
+
+endpackage : prim_xilinx_pkg