diff --git a/hw/ip/prim/rtl/prim_ram_1p_adv.sv b/hw/ip/prim/rtl/prim_ram_1p_adv.sv index 73a973e3df32b..275675cace99f 100644 --- a/hw/ip/prim/rtl/prim_ram_1p_adv.sv +++ b/hw/ip/prim/rtl/prim_ram_1p_adv.sv @@ -17,6 +17,7 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #( parameter int Depth = 512, + parameter int InstDepth = Depth, parameter int Width = 32, parameter int DataBitsPerMask = 1, // Number of data bits per bit of write mask parameter MemInitFile = "", // VMEM file to initialize the memory with @@ -32,25 +33,28 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #( // since this results in a more compact and faster implementation. parameter bit HammingECC = 0, - localparam int Aw = prim_util_pkg::vbits(Depth) + localparam int Aw = prim_util_pkg::vbits(Depth), + // Compute RAM tiling + localparam int NumRamInst = $ceil(Depth / InstDepth), + localparam int InstAw = prim_util_pkg::vbits(InstDepth) ) ( input clk_i, input rst_ni, - input req_i, - input write_i, - input [Aw-1:0] addr_i, - input [Width-1:0] wdata_i, - input [Width-1:0] wmask_i, - output logic [Width-1:0] rdata_o, - output logic rvalid_o, // read response (rdata_o) is valid - output logic [1:0] rerror_o, // Bit1: Uncorrectable, Bit0: Correctable + input req_i, + input write_i, + input [Aw-1:0] addr_i, + input [Width-1:0] wdata_i, + input [Width-1:0] wmask_i, + output logic [Width-1:0] rdata_o, + output logic rvalid_o, // read response (rdata_o) is valid + output logic [1:0] rerror_o, // Bit1: Uncorrectable, Bit0: Correctable // config - input ram_1p_cfg_t cfg_i, + input ram_1p_cfg_t [NumRamInst-1:0] cfg_i, // When detecting multi-bit encoding errors, raise alert. - output logic alert_o + output logic alert_o ); import prim_mubi_pkg::mubi4_t; @@ -58,6 +62,7 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #( import prim_mubi_pkg::mubi4_bool_to_mubi; import prim_mubi_pkg::mubi4_test_invalid; import prim_mubi_pkg::mubi4_test_true_loose; + import prim_mubi_pkg::mubi4_test_true_strict; import prim_mubi_pkg::MuBi4True; import prim_mubi_pkg::MuBi4False; import prim_mubi_pkg::MuBi4Width; @@ -102,23 +107,77 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #( assign req_q_b = mubi4_test_true_loose(req_q); assign write_q_b = mubi4_test_true_loose(write_q); - prim_ram_1p #( - .MemInitFile (MemInitFile), - - .Width (TotalWidth), - .Depth (Depth), - .DataBitsPerMask (LocalDataBitsPerMask) - ) u_mem ( - .clk_i, - - .req_i (req_q_b), - .write_i (write_q_b), - .addr_i (addr_q), - .wdata_i (wdata_q), - .wmask_i (wmask_q), - .rdata_o (rdata_sram), - .cfg_i - ); + logic [NumRamInst-1:0] inst_req_d, inst_req_q, rvalid_inst; + logic [InstAw-1:0] inst_addr; + logic [NumRamInst-1:0] [Width-1:0] inst_rdata; + + // The lower InstAw bits of the address are used to address within one RAM primitive + assign inst_addr = addr_q[InstAw-1:0]; + + // The upper bits Aw-1:InstAw of the address select which RAM instance is selected. A special case + // is needed when no tiling is performed and only a single RAM macro is instantiated. Here, we + // can directly use the request signal and no demuxing is needed. + always_comb begin + inst_req_d = '0; + + for (int i = 0; i < NumRamInst; i++) begin + if (NumRamInst == 1) begin + inst_req_d[i] = req_q_b; + end else begin + if (req_q_b && (i == addr_q[Aw-1:InstAw])) begin + inst_req_d[i] = 1'b1; + end + end + end + end + + // Flop the instance request signal to know + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + inst_req_q <= '0; + end else begin + inst_req_q <= inst_req_d; + end + end + + // Ensure that only one RAM instance gets activated + `ASSERT(OneHotInstReq_A, $onehot0(inst_req_d)) + + for (genvar i = 0; i < NumRamInst; i++) begin : gen_ram_inst + prim_ram_1p #( + .MemInitFile (MemInitFile), + + .Width (TotalWidth), + .Depth (InstDepth), + .DataBitsPerMask (LocalDataBitsPerMask) + ) u_mem ( + .clk_i, + + .req_i (inst_req_d[i]), + .write_i (write_q_b), + .addr_i (inst_addr), + .wdata_i (wdata_q), + .wmask_i (wmask_q), + .rdata_o (inst_rdata[i]), + .cfg_i (cfg_i[i]) + ); + end + + // Mux output data + always_comb begin + rdata_sram = '0; + + for (int i = 0; i < NumRamInst; i++) begin + // Determine which RAM tile we accessed based on the floped inst_req signal and we really + // got an rvalid. This determines if we mux the output data of that particular RAM tile. + rvalid_inst[i] = mubi4_test_true_strict( + mubi4_and_hi(mubi4_bool_to_mubi(inst_req_q[i]), rvalid_sram_q)); + + if(rvalid_inst[i]) begin + rdata_sram = inst_rdata[i]; + end + end + end assign rvalid_sram_d = mubi4_and_hi(req_q, mubi4_t'(~write_q)); diff --git a/hw/ip/prim/rtl/prim_ram_1p_scr.sv b/hw/ip/prim/rtl/prim_ram_1p_scr.sv index d31a7d5ca01c9..cd71ced68552a 100644 --- a/hw/ip/prim/rtl/prim_ram_1p_scr.sv +++ b/hw/ip/prim/rtl/prim_ram_1p_scr.sv @@ -25,6 +25,7 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #( parameter int Depth = 16*1024, // Needs to be a power of 2 if NumAddrScrRounds > 0. + parameter int InstDepth = Depth, parameter int Width = 32, // Needs to be byte aligned if byte parity is enabled. parameter int DataBitsPerMask = 8, // Needs to be set to 8 in case of byte parity. parameter bit EnableParity = 1, // Enable byte parity. @@ -58,39 +59,41 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #( // use the same key, but they use a different IV localparam int DataKeyWidth = 128, // Each 64 bit scrambling primitive requires a 64bit IV - localparam int NonceWidth = 64 * NumParScr + localparam int NonceWidth = 64 * NumParScr, + // Compute RAM tiling + localparam int NumRamInst = $ceil(Depth / InstDepth) ) ( - input clk_i, - input rst_ni, + input clk_i, + input rst_ni, // Key interface. Memory requests will not be granted if key_valid is set to 0. - input key_valid_i, - input [DataKeyWidth-1:0] key_i, - input [NonceWidth-1:0] nonce_i, + input key_valid_i, + input [DataKeyWidth-1:0] key_i, + input [NonceWidth-1:0] nonce_i, // Interface to TL-UL SRAM adapter - input req_i, - output logic gnt_o, - input write_i, - input [AddrWidth-1:0] addr_i, - input [Width-1:0] wdata_i, - input [Width-1:0] wmask_i, // Needs to be byte-aligned for parity + input req_i, + output logic gnt_o, + input write_i, + input [AddrWidth-1:0] addr_i, + input [Width-1:0] wdata_i, + input [Width-1:0] wmask_i, // Needs to be byte-aligned for parity // On integrity errors, the primitive surpresses any real transaction to the memory. - input intg_error_i, - output logic [Width-1:0] rdata_o, - output logic rvalid_o, // Read response (rdata_o) is valid - output logic [1:0] rerror_o, // Bit1: Uncorrectable, Bit0: Correctable - output logic [31:0] raddr_o, // Read address for error reporting. + input intg_error_i, + output logic [Width-1:0] rdata_o, + output logic rvalid_o, // Read response (rdata_o) is valid + output logic [1:0] rerror_o, // Bit1: Uncorrectable, Bit0: Correctable + output logic [31:0] raddr_o, // Read address for error reporting. // config - input ram_1p_cfg_t cfg_i, + input ram_1p_cfg_t [NumRamInst-1:0] cfg_i, // Write currently pending inside this module. - output logic wr_collision_o, - output logic write_pending_o, + output logic wr_collision_o, + output logic write_pending_o, // When detecting multi-bit encoding errors, raise alert. - output logic alert_o + output logic alert_o ); import prim_mubi_pkg::mubi4_t; @@ -481,6 +484,7 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #( prim_ram_1p_adv #( .Depth(Depth), + .InstDepth(InstDepth), .Width(Width), .DataBitsPerMask(DataBitsPerMask), .EnableECC(1'b0), diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv b/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv index d2e835ac33915..71915ef121cf6 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv @@ -9,20 +9,24 @@ module prim_generic_ram_1p import prim_ram_1p_pkg::*; #( parameter int Width = 32, // bit parameter int Depth = 128, + parameter int InstDepth = Depth, parameter int DataBitsPerMask = 1, // Number of data bits per bit of write mask parameter MemInitFile = "", // VMEM file to initialize the memory with - localparam int Aw = $clog2(Depth) // derived parameter + localparam int Aw = $clog2(Depth), // derived parameter + // Compute RAM tiling + localparam int NumRamInst = $ceil(Depth / InstDepth) ) ( - input logic clk_i, + input logic clk_i, - input logic req_i, - input logic write_i, - input logic [Aw-1:0] addr_i, - input logic [Width-1:0] wdata_i, - input logic [Width-1:0] wmask_i, - output logic [Width-1:0] rdata_o, // Read data. Data is returned one cycle after req_i is high. - input ram_1p_cfg_t cfg_i + input logic req_i, + input logic write_i, + input logic [Aw-1:0] addr_i, + input logic [Width-1:0] wdata_i, + input logic [Width-1:0] wmask_i, + output logic [Width-1:0] rdata_o, // Read data. Data is returned one cycle after req_i + // is high. + input ram_1p_cfg_t [NumRamInst-1:0] cfg_i ); // For certain synthesis experiments we compile the design with generic models to get an unmapped diff --git a/hw/ip/sram_ctrl/data/sram_ctrl.hjson b/hw/ip/sram_ctrl/data/sram_ctrl.hjson index d31d144388bd4..7acac62b401ec 100644 --- a/hw/ip/sram_ctrl/data/sram_ctrl.hjson +++ b/hw/ip/sram_ctrl/data/sram_ctrl.hjson @@ -79,6 +79,20 @@ type: "int", default: "0x1000" }, + { name: "InstSize", + desc: "Memory size of a single RAM tile (in bytes).", + type: "int", + default: "4096" + local: "false" + expose: "true" + }, + { name: "NumRamInst", + desc: "Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) .", + type: "int", + default: "1" + local: "false" + expose: "true" + }, { name: "InstrExec", desc: "Support execution from SRAM", type: "bit", @@ -155,6 +169,7 @@ type: "uni" name: "cfg" act: "rcv" + width: "NumRamInst", default: "'0" package: "prim_ram_1p_pkg" }, diff --git a/hw/ip/sram_ctrl/doc/interfaces.md b/hw/ip/sram_ctrl/doc/interfaces.md index 4fe25168670b3..b1c21cec2c106 100644 --- a/hw/ip/sram_ctrl/doc/interfaces.md +++ b/hw/ip/sram_ctrl/doc/interfaces.md @@ -27,15 +27,15 @@ Referring to the [Comportable guideline for peripheral device functionality](htt ## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) -| Port Name | Package::Struct | Type | Act | Width | Description | -|:-------------------|:----------------------------|:--------|:------|--------:|:--------------| -| sram_otp_key | otp_ctrl_pkg::sram_otp_key | req_rsp | req | 1 | | -| cfg | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | | -| lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| otp_en_sram_ifetch | prim_mubi_pkg::mubi8 | uni | rcv | 1 | | -| regs_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | -| ram_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | +| Port Name | Package::Struct | Type | Act | Width | Description | +|:-------------------|:----------------------------|:--------|:------|:-----------|:--------------| +| sram_otp_key | otp_ctrl_pkg::sram_otp_key | req_rsp | req | 1 | | +| cfg | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | NumRamInst | | +| lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| otp_en_sram_ifetch | prim_mubi_pkg::mubi8 | uni | rcv | 1 | | +| regs_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | +| ram_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | ## Security Alerts diff --git a/hw/ip/sram_ctrl/rtl/sram_ctrl.sv b/hw/ip/sram_ctrl/rtl/sram_ctrl.sv index 788e18f534442..0456899c5f12f 100644 --- a/hw/ip/sram_ctrl/rtl/sram_ctrl.sv +++ b/hw/ip/sram_ctrl/rtl/sram_ctrl.sv @@ -12,7 +12,9 @@ module sram_ctrl import sram_ctrl_reg_pkg::*; #( // Number of words stored in the SRAM. - parameter int MemSizeRam = 32'h1000, + parameter int MemSizeRam = 32'h1000, + parameter int InstSize = MemSizeRam, + parameter int NumRamInst = 1, // Enable asynchronous transitions on alerts. parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, // Enables the execute from SRAM feature. @@ -23,40 +25,40 @@ module sram_ctrl // Setting this to 3 lowers this to approximately 7 effective rounds. parameter int NumPrinceRoundsHalf = 3, // Random netlist constants - parameter otp_ctrl_pkg::sram_key_t RndCnstSramKey = RndCnstSramKeyDefault, - parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramNonce = RndCnstSramNonceDefault, - parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, - parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault + parameter otp_ctrl_pkg::sram_key_t RndCnstSramKey = RndCnstSramKeyDefault, + parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramNonce = RndCnstSramNonceDefault, + parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, + parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault ) ( // SRAM Clock - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // OTP Clock (for key interface) - input logic clk_otp_i, - input logic rst_otp_ni, + input logic clk_otp_i, + input logic rst_otp_ni, // Bus Interface (device) for SRAM - input tlul_pkg::tl_h2d_t ram_tl_i, - output tlul_pkg::tl_d2h_t ram_tl_o, + input tlul_pkg::tl_h2d_t ram_tl_i, + output tlul_pkg::tl_d2h_t ram_tl_o, // Bus Interface (device) for CSRs - input tlul_pkg::tl_h2d_t regs_tl_i, - output tlul_pkg::tl_d2h_t regs_tl_o, + input tlul_pkg::tl_h2d_t regs_tl_i, + output tlul_pkg::tl_d2h_t regs_tl_o, // Alert outputs. - input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, - output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, // Life-cycle escalation input (scraps the scrambling keys) // SEC_CM: LC_ESCALATE_EN.INTERSIG.MUBI - input lc_ctrl_pkg::lc_tx_t lc_escalate_en_i, + input lc_ctrl_pkg::lc_tx_t lc_escalate_en_i, // SEC_CM: LC_HW_DEBUG_EN.INTERSIG.MUBI - input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, + input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, // Otp configuration for sram execution // SEC_CM: EXEC.INTERSIG.MUBI - input prim_mubi_pkg::mubi8_t otp_en_sram_ifetch_i, + input prim_mubi_pkg::mubi8_t otp_en_sram_ifetch_i, // Key request to OTP (running on clk_fixed) // SEC_CM: SCRAMBLE.KEY.SIDELOAD - output otp_ctrl_pkg::sram_otp_key_req_t sram_otp_key_o, - input otp_ctrl_pkg::sram_otp_key_rsp_t sram_otp_key_i, + output otp_ctrl_pkg::sram_otp_key_req_t sram_otp_key_o, + input otp_ctrl_pkg::sram_otp_key_rsp_t sram_otp_key_i, // config - input prim_ram_1p_pkg::ram_1p_cfg_t cfg_i + input prim_ram_1p_pkg::ram_1p_cfg_t [NumRamInst-1:0] cfg_i ); import lc_ctrl_pkg::lc_tx_t; @@ -73,8 +75,11 @@ module sram_ctrl // This is later on pruned to the correct width at the SRAM wrapper interface. parameter int unsigned Depth = MemSizeRam >> 2; + parameter int unsigned InstDepth = InstSize >> 2; parameter int unsigned AddrWidth = prim_util_pkg::vbits(Depth); + `ASSERT_INIT(NumRamInstSameAsComputed_A, NumRamInst == $ceil(MemSizeRam / InstSize)) + `ASSERT_INIT(NonceWidthsLessThanSource_A, NonceWidth + LfsrWidth <= otp_ctrl_pkg::SramNonceWidth) @@ -541,6 +546,7 @@ module sram_ctrl prim_ram_1p_scr #( .Width(DataWidth), .Depth(Depth), + .InstDepth(InstDepth), .EnableParity(0), .DataBitsPerMask(DataWidth), .NumPrinceRoundsHalf(NumPrinceRoundsHalf) diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson index 4693e2afdbc94..e097fadca052a 100644 --- a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson @@ -4013,6 +4013,24 @@ name_top: MemSizeSramCtrlRetAonRam default: 4096 } + { + name: InstSize + desc: Memory size of a single RAM tile (in bytes). + type: int + default: "4096" + local: "false" + expose: "true" + name_top: SramCtrlRetAonInstSize + } + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + type: int + default: 1 + local: "false" + expose: "true" + name_top: SramCtrlRetAonNumRamInst + } { name: InstrExec desc: Support execution from SRAM @@ -4052,7 +4070,17 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } default: "'0" inst_name: sram_ctrl_ret_aon top_signame: ast_ram_1p_cfg @@ -6157,6 +6185,24 @@ name_top: MemSizeSramCtrlMainRam default: 65536 } + { + name: InstSize + desc: Memory size of a single RAM tile (in bytes). + type: int + default: "4096" + local: "false" + expose: "true" + name_top: SramCtrlMainInstSize + } + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + type: int + default: 1 + local: "false" + expose: "true" + name_top: SramCtrlMainNumRamInst + } { name: InstrExec desc: Support execution from SRAM @@ -6196,7 +6242,17 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } default: "'0" inst_name: sram_ctrl_main top_signame: ast_ram_1p_cfg @@ -6374,6 +6430,24 @@ name_top: MemSizeSramCtrlMboxRam default: 4096 } + { + name: InstSize + desc: Memory size of a single RAM tile (in bytes). + type: int + default: "4096" + local: "false" + expose: "true" + name_top: SramCtrlMboxInstSize + } + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + type: int + default: 1 + local: "false" + expose: "true" + name_top: SramCtrlMboxNumRamInst + } { name: InstrExec desc: Support execution from SRAM @@ -6413,7 +6487,17 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMboxNumRamInst + } default: "'0" inst_name: sram_ctrl_mbox top_signame: ast_ram_1p_cfg @@ -20307,7 +20391,17 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } default: "'0" inst_name: sram_ctrl_ret_aon top_signame: ast_ram_1p_cfg @@ -21348,7 +21442,17 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } default: "'0" inst_name: sram_ctrl_main top_signame: ast_ram_1p_cfg @@ -21434,7 +21538,17 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMboxNumRamInst + } default: "'0" inst_name: sram_ctrl_mbox top_signame: ast_ram_1p_cfg diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv index 2059d4a1cc044..03e61c50937b3 100644 --- a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv @@ -47,6 +47,8 @@ module top_darjeeling #( // parameters for sensor_ctrl // parameters for soc_proxy // parameters for sram_ctrl_ret_aon + parameter int SramCtrlRetAonInstSize = 4096, + parameter int SramCtrlRetAonNumRamInst = 1, parameter bit SramCtrlRetAonInstrExec = 0, parameter int SramCtrlRetAonNumPrinceRoundsHalf = 3, // parameters for rv_dm @@ -84,9 +86,13 @@ module top_darjeeling #( // parameters for edn0 // parameters for edn1 // parameters for sram_ctrl_main + parameter int SramCtrlMainInstSize = 4096, + parameter int SramCtrlMainNumRamInst = 1, parameter bit SramCtrlMainInstrExec = 1, parameter int SramCtrlMainNumPrinceRoundsHalf = 3, // parameters for sram_ctrl_mbox + parameter int SramCtrlMboxInstSize = 4096, + parameter int SramCtrlMboxNumRamInst = 1, parameter bit SramCtrlMboxInstrExec = 0, parameter int SramCtrlMboxNumPrinceRoundsHalf = 3, // parameters for rom_ctrl0 @@ -1640,6 +1646,8 @@ module top_darjeeling #( .RndCnstLfsrSeed(RndCnstSramCtrlRetAonLfsrSeed), .RndCnstLfsrPerm(RndCnstSramCtrlRetAonLfsrPerm), .MemSizeRam(4096), + .InstSize(SramCtrlRetAonInstSize), + .NumRamInst(SramCtrlRetAonNumRamInst), .InstrExec(SramCtrlRetAonInstrExec), .NumPrinceRoundsHalf(SramCtrlRetAonNumPrinceRoundsHalf) ) u_sram_ctrl_ret_aon ( @@ -2001,6 +2009,8 @@ module top_darjeeling #( .RndCnstLfsrSeed(RndCnstSramCtrlMainLfsrSeed), .RndCnstLfsrPerm(RndCnstSramCtrlMainLfsrPerm), .MemSizeRam(65536), + .InstSize(SramCtrlMainInstSize), + .NumRamInst(SramCtrlMainNumRamInst), .InstrExec(SramCtrlMainInstrExec), .NumPrinceRoundsHalf(SramCtrlMainNumPrinceRoundsHalf) ) u_sram_ctrl_main ( @@ -2033,6 +2043,8 @@ module top_darjeeling #( .RndCnstLfsrSeed(RndCnstSramCtrlMboxLfsrSeed), .RndCnstLfsrPerm(RndCnstSramCtrlMboxLfsrPerm), .MemSizeRam(4096), + .InstSize(SramCtrlMboxInstSize), + .NumRamInst(SramCtrlMboxNumRamInst), .InstrExec(SramCtrlMboxInstrExec), .NumPrinceRoundsHalf(SramCtrlMboxNumPrinceRoundsHalf) ) u_sram_ctrl_mbox ( diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 3948e71435783..b9746524f9b41 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -5155,6 +5155,24 @@ name_top: MemSizeSramCtrlRetAonRam default: 4096 } + { + name: InstSize + desc: Memory size of a single RAM tile (in bytes). + type: int + default: "4096" + local: "false" + expose: "true" + name_top: SramCtrlRetAonInstSize + } + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + type: int + default: 1 + local: "false" + expose: "true" + name_top: SramCtrlRetAonNumRamInst + } { name: InstrExec desc: Support execution from SRAM @@ -5194,10 +5212,22 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } default: "'0" inst_name: sram_ctrl_ret_aon - top_signame: ast_ram_1p_cfg + external: true + top_signame: sram_ctrl_ret_aon_cfg + conn_type: false index: -1 } { @@ -7970,6 +8000,24 @@ name_top: MemSizeSramCtrlMainRam default: 131072 } + { + name: InstSize + desc: Memory size of a single RAM tile (in bytes). + type: int + default: "4096" + local: "false" + expose: "true" + name_top: SramCtrlMainInstSize + } + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + type: int + default: 1 + local: "false" + expose: "true" + name_top: SramCtrlMainNumRamInst + } { name: InstrExec desc: Support execution from SRAM @@ -8009,10 +8057,22 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } default: "'0" inst_name: sram_ctrl_main - top_signame: ast_ram_1p_cfg + external: true + top_signame: sram_ctrl_main_cfg + conn_type: false index: -1 } { @@ -9052,8 +9112,6 @@ i2c0.ram_cfg i2c1.ram_cfg i2c2.ram_cfg - sram_ctrl_main.cfg - sram_ctrl_ret_aon.cfg rv_core_ibex.ram_cfg ] ast.spi_ram_2p_cfg: @@ -9648,6 +9706,8 @@ ast.lc_dft_en: "" ast.obs_ctrl: obs_ctrl ast.ram_1p_cfg: ram_1p_cfg + sram_ctrl_main.cfg: sram_ctrl_main_cfg + sram_ctrl_ret_aon.cfg: sram_ctrl_ret_aon_cfg ast.spi_ram_2p_cfg: spi_ram_2p_cfg ast.usb_ram_1p_cfg: usb_ram_1p_cfg ast.rom_cfg: rom_cfg @@ -19879,10 +19939,22 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } default: "'0" inst_name: sram_ctrl_ret_aon - top_signame: ast_ram_1p_cfg + external: true + top_signame: sram_ctrl_ret_aon_cfg + conn_type: false index: -1 } { @@ -21324,10 +21396,22 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } default: "'0" inst_name: sram_ctrl_main - top_signame: ast_ram_1p_cfg + external: true + top_signame: sram_ctrl_main_cfg + conn_type: false index: -1 } { @@ -22587,6 +22671,50 @@ index: -1 netname: ast_ram_1p_cfg } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg + signame: sram_ctrl_main_cfg_i + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } + type: uni + default: "'0" + direction: in + conn_type: false + index: -1 + netname: sram_ctrl_main_cfg + } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg + signame: sram_ctrl_ret_aon_cfg_i + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } + type: uni + default: "'0" + direction: in + conn_type: false + index: -1 + netname: sram_ctrl_ret_aon_cfg + } { package: prim_ram_2p_pkg struct: ram_2p_cfg diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index f700554f11b22..144ff8429fa46 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson @@ -1082,9 +1082,7 @@ 'i2c0.ram_cfg', 'i2c1.ram_cfg', 'i2c2.ram_cfg', - 'sram_ctrl_main.cfg', - 'sram_ctrl_ret_aon.cfg', - 'rv_core_ibex.ram_cfg'], + 'rv_core_ibex.ram_cfg'] 'ast.spi_ram_2p_cfg' : ['spi_device.ram_cfg'], 'ast.usb_ram_1p_cfg' : ['usbdev.ram_cfg'], 'ast.rom_cfg' : ['rom_ctrl.rom_cfg'], @@ -1290,6 +1288,8 @@ 'ast.lc_dft_en' : '', 'ast.obs_ctrl' : 'obs_ctrl', 'ast.ram_1p_cfg' : 'ram_1p_cfg', + 'sram_ctrl_main.cfg' : 'sram_ctrl_main_cfg' + 'sram_ctrl_ret_aon.cfg' : 'sram_ctrl_ret_aon_cfg' 'ast.spi_ram_2p_cfg' : 'spi_ram_2p_cfg', 'ast.usb_ram_1p_cfg' : 'usb_ram_1p_cfg', 'ast.rom_cfg' : 'rom_cfg', diff --git a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh index ebb9c8fda1c0e..365260c2f0520 100644 --- a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh +++ b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh @@ -49,15 +49,15 @@ `define FLASH1_INFO_MEM_HIER `FLASH_BANK1_HIER.gen_info_types[0].u_info_mem.`MEM_ARRAY_SUB `define ICACHE_WAY0_HIER `CPU_CORE_HIER.gen_rams.gen_rams_inner[0].gen_scramble_rams `define ICACHE_WAY1_HIER `CPU_CORE_HIER.gen_rams.gen_rams_inner[1].gen_scramble_rams -`define ICACHE0_TAG_MEM_HIER `ICACHE_WAY0_HIER.tag_bank.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB -`define ICACHE1_TAG_MEM_HIER `ICACHE_WAY1_HIER.tag_bank.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB -`define ICACHE0_DATA_MEM_HIER `ICACHE_WAY0_HIER.data_bank.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB -`define ICACHE1_DATA_MEM_HIER `ICACHE_WAY1_HIER.data_bank.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB -`define RAM_MAIN_MEM_HIER `RAM_MAIN_HIER.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB -`define RAM_RET_MEM_HIER `RAM_RET_HIER.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB +`define ICACHE0_TAG_MEM_HIER `ICACHE_WAY0_HIER.tag_bank.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define ICACHE1_TAG_MEM_HIER `ICACHE_WAY1_HIER.tag_bank.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define ICACHE0_DATA_MEM_HIER `ICACHE_WAY0_HIER.data_bank.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define ICACHE1_DATA_MEM_HIER `ICACHE_WAY1_HIER.data_bank.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define RAM_MAIN_MEM_HIER `RAM_MAIN_HIER.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define RAM_RET_MEM_HIER `RAM_RET_HIER.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB `define ROM_MEM_HIER `ROM_CTRL_HIER.`ROM_CTRL_INT_PATH `define OTP_GENERIC_HIER `OTP_CTRL_HIER.u_otp.gen_generic.u_impl_generic -`define OTP_MEM_HIER `OTP_GENERIC_HIER.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB -`define OTBN_IMEM_HIER `OTBN_HIER.u_imem.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB -`define OTBN_DMEM_HIER `OTBN_HIER.u_dmem.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB +`define OTP_MEM_HIER `OTP_GENERIC_HIER.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define OTBN_IMEM_HIER `OTBN_HIER.u_imem.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define OTBN_DMEM_HIER `OTBN_HIER.u_dmem.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB `define USBDEV_BUF_HIER `USBDEV_HIER.gen_no_stubbed_memory.u_memory_1p.u_mem.`MEM_ARRAY_SUB diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index b400f06c53259..3a9fea2cc6340 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -60,6 +60,8 @@ module top_earlgrey #( // parameters for aon_timer_aon // parameters for sensor_ctrl_aon // parameters for sram_ctrl_ret_aon + parameter int SramCtrlRetAonInstSize = 4096, + parameter int SramCtrlRetAonNumRamInst = 1, parameter bit SramCtrlRetAonInstrExec = 0, parameter int SramCtrlRetAonNumPrinceRoundsHalf = 3, // parameters for flash_ctrl @@ -103,6 +105,8 @@ module top_earlgrey #( // parameters for edn0 // parameters for edn1 // parameters for sram_ctrl_main + parameter int SramCtrlMainInstSize = 4096, + parameter int SramCtrlMainNumRamInst = 1, parameter bit SramCtrlMainInstrExec = 1, parameter int SramCtrlMainNumPrinceRoundsHalf = 2, // parameters for rom_ctrl @@ -160,6 +164,8 @@ module top_earlgrey #( output lc_ctrl_pkg::lc_tx_t ast_lc_dft_en_o, input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, input prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg_i, + input prim_ram_1p_pkg::ram_1p_cfg_t [SramCtrlMainNumRamInst-1:0] sram_ctrl_main_cfg_i, + input prim_ram_1p_pkg::ram_1p_cfg_t [SramCtrlRetAonNumRamInst-1:0] sram_ctrl_ret_aon_cfg_i, input prim_ram_2p_pkg::ram_2p_cfg_t spi_ram_2p_cfg_i, input prim_ram_1p_pkg::ram_1p_cfg_t usb_ram_1p_cfg_i, input prim_rom_pkg::rom_cfg_t rom_cfg_i, @@ -2107,6 +2113,8 @@ module top_earlgrey #( .RndCnstLfsrSeed(RndCnstSramCtrlRetAonLfsrSeed), .RndCnstLfsrPerm(RndCnstSramCtrlRetAonLfsrPerm), .MemSizeRam(4096), + .InstSize(SramCtrlRetAonInstSize), + .NumRamInst(SramCtrlRetAonNumRamInst), .InstrExec(SramCtrlRetAonInstrExec), .NumPrinceRoundsHalf(SramCtrlRetAonNumPrinceRoundsHalf) ) u_sram_ctrl_ret_aon ( @@ -2117,7 +2125,7 @@ module top_earlgrey #( // Inter-module signals .sram_otp_key_o(otp_ctrl_sram_otp_key_req[1]), .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[1]), - .cfg_i(ast_ram_1p_cfg), + .cfg_i(sram_ctrl_ret_aon_cfg_i), .lc_escalate_en_i(lc_ctrl_lc_escalate_en), .lc_hw_debug_en_i(lc_ctrl_pkg::Off), .otp_en_sram_ifetch_i(prim_mubi_pkg::MuBi8False), @@ -2585,6 +2593,8 @@ module top_earlgrey #( .RndCnstLfsrSeed(RndCnstSramCtrlMainLfsrSeed), .RndCnstLfsrPerm(RndCnstSramCtrlMainLfsrPerm), .MemSizeRam(131072), + .InstSize(SramCtrlMainInstSize), + .NumRamInst(SramCtrlMainNumRamInst), .InstrExec(SramCtrlMainInstrExec), .NumPrinceRoundsHalf(SramCtrlMainNumPrinceRoundsHalf) ) u_sram_ctrl_main ( @@ -2595,7 +2605,7 @@ module top_earlgrey #( // Inter-module signals .sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]), .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[0]), - .cfg_i(ast_ram_1p_cfg), + .cfg_i(sram_ctrl_main_cfg_i), .lc_escalate_en_i(lc_ctrl_lc_escalate_en), .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), .otp_en_sram_ifetch_i(sram_ctrl_main_otp_en_sram_ifetch),