From 9985c0fd3e21102e72289f882e25270c91a72270 Mon Sep 17 00:00:00 2001 From: Ghada Dessouky Date: Mon, 22 Jan 2024 10:42:27 +0100 Subject: [PATCH] [prim_sha2,rtl] prim_sha2 minor RTL and styling fixes This makes minor styling fixes and RTL changes to fix 2 AscentLint warnings and avoid waivers for them. Signed-off-by: Ghada Dessouky --- hw/ip/prim/rtl/prim_sha2.sv | 11 ++++--- hw/ip/prim/rtl/prim_sha2_32.sv | 14 ++++----- hw/ip/prim/rtl/prim_sha2_pad.sv | 51 +++++++++++++++++---------------- 3 files changed, 38 insertions(+), 38 deletions(-) diff --git a/hw/ip/prim/rtl/prim_sha2.sv b/hw/ip/prim/rtl/prim_sha2.sv index dff07813588a6d..8135d55868b6c5 100644 --- a/hw/ip/prim/rtl/prim_sha2.sv +++ b/hw/ip/prim/rtl/prim_sha2.sv @@ -55,7 +55,8 @@ module prim_sha2 import prim_sha2_pkg::*; if (!MultimodeEn) begin : gen_tie_unused logic unused_signals; assign unused_signals = ^{wipe_v_i[63:32], digest_mode_i, shaf_rdata[63:32], - digest_mode_flag_d, digest_mode_flag_q}; + digest_mode_flag_d, digest_mode_flag_q, + round_d[RndWidth512-1], round_q[RndWidth512-1]}; end assign digest_mode_flag_d = hash_start_i ? digest_mode_i : // latch in configured mode @@ -272,8 +273,6 @@ module prim_sha2 import prim_sha2_pkg::*; round_d = round_q + 1; end end - // assign most significant bit round_d (and consequently round_q) to constant 0 - if (!MultimodeEn) round_d[RndWidth512-1] = 'b0; end // update round counter (shared) @@ -309,8 +308,8 @@ module prim_sha2 import prim_sha2_pkg::*; fifoctl_state_e fifo_st_q, fifo_st_d; always_ff @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) fifo_st_q <= FifoIdle; - else fifo_st_q <= fifo_st_d; + if (!rst_ni) fifo_st_q <= FifoIdle; + else fifo_st_q <= fifo_st_d; end always_comb begin @@ -421,7 +420,7 @@ module prim_sha2 import prim_sha2_pkg::*; init_hash = 1'b1; sha_st_d = ShaCompress; end else begin - sha_st_d = ShaIdle; + sha_st_d = ShaIdle; end end diff --git a/hw/ip/prim/rtl/prim_sha2_32.sv b/hw/ip/prim/rtl/prim_sha2_32.sv index 362c95cdacbb0c..6f06099b471f37 100644 --- a/hw/ip/prim/rtl/prim_sha2_32.sv +++ b/hw/ip/prim/rtl/prim_sha2_32.sv @@ -50,13 +50,13 @@ module prim_sha2_32 import prim_sha2_pkg::*; digest_mode_e digest_mode_flag_d, digest_mode_flag_q; always_comb begin : multimode_combinational - word_part_inc = 1'b0; - word_part_reset = 1'b0; - full_word.mask = 8'hFF; // to keep the padding buffer ready to receive - full_word.data = 64'h0; - sha_process = 1'b0; - word_valid = 1'b0; - fifo_rready_o = 1'b0; + word_part_inc = 1'b0; + word_part_reset = 1'b0; + full_word.mask = 8'hFF; // to keep the padding buffer ready to receive + full_word.data = 64'h0; + sha_process = 1'b0; + word_valid = 1'b0; + fifo_rready_o = 1'b0; // assign word_buffer if (!sha_en_i || hash_start_i) word_buffer_d = 0; diff --git a/hw/ip/prim/rtl/prim_sha2_pad.sv b/hw/ip/prim/rtl/prim_sha2_pad.sv index 1e6c1467e5506d..8c7d007c4340fa 100644 --- a/hw/ip/prim/rtl/prim_sha2_pad.sv +++ b/hw/ip/prim/rtl/prim_sha2_pad.sv @@ -34,32 +34,34 @@ module prim_sha2_pad import prim_sha2_pkg::*; logic inc_txcount; logic fifo_partial; logic txcnt_eq_1a0; - logic hash_process_flag_d, hash_process_flag; - digest_mode_e digest_mode_flag_d, digest_mode_flag; + + logic hash_process_flag_d, hash_process_flag_q; + digest_mode_e digest_mode_flag_d, digest_mode_flag_q; // tie off unused inport ports and signals if (!MultimodeEn) begin : gen_tie_unused logic unused_signals; - assign unused_signals = ^{message_length_i[127:64], digest_mode_i}; + assign unused_signals = ^{message_length_i[127:64], digest_mode_i, + digest_mode_flag_q, digest_mode_flag_d}; end assign fifo_partial = MultimodeEn ? ~&fifo_rdata_i.mask : ~&fifo_rdata_i.mask[3:0]; // tx_count[8:0] == 'h1c0 --> should send LenHi - assign txcnt_eq_1a0 = (digest_mode_flag == SHA2_256 || ~MultimodeEn) ? + assign txcnt_eq_1a0 = (digest_mode_flag_q == SHA2_256 || ~MultimodeEn) ? (tx_count[8:0] == 9'h1a0) : - ((digest_mode_flag == SHA2_384) || (digest_mode_flag == SHA2_512)) ? + ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (tx_count[9:0] == 10'h340) : '0; assign hash_process_flag_d = (~sha_en_i || hash_start_i || hash_done_o) ? 1'b0 : hash_process_i ? 1'b1 : - hash_process_flag; + hash_process_flag_q; always_ff @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) hash_process_flag <= 1'b0; - else hash_process_flag <= hash_process_flag_d; + if (!rst_ni) hash_process_flag_q <= 1'b0; + else hash_process_flag_q <= hash_process_flag_d; end // data path: fout_wdata @@ -84,7 +86,7 @@ module prim_sha2_pad import prim_sha2_pkg::*; // msglen[4:3] == 01 |-> {msg, 'h80, 'h00, 'h00} // msglen[4:3] == 10 |-> {msg[15:0], 'h80, 'h00} // msglen[4:3] == 11 |-> {msg[23:0], 'h80} - if ((digest_mode_flag == SHA2_256) || ~MultimodeEn) begin + if ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) begin unique case (message_length_i[4:3]) 2'b 00: shaf_rdata_o = 64'h 0000_0000_8000_0000; 2'b 01: shaf_rdata_o = {32'h 0000_0000, fifo_rdata_i.data[31:24], 24'h 8000_00}; @@ -92,7 +94,7 @@ module prim_sha2_pad import prim_sha2_pkg::*; 2'b 11: shaf_rdata_o = {32'h 0000_0000, fifo_rdata_i.data[31: 8], 8'h 80}; default: shaf_rdata_o = 64'h0; endcase - end else if ((digest_mode_flag == SHA2_384) || (digest_mode_flag == SHA2_512)) begin + end else if ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) begin unique case (message_length_i[5:3]) 3'b 000: shaf_rdata_o = 64'h 8000_0000_0000_0000; 3'b 001: shaf_rdata_o = {fifo_rdata_i.data[63:56], 56'h 8000_0000_0000_00}; @@ -113,16 +115,16 @@ module prim_sha2_pad import prim_sha2_pkg::*; end LenHi: begin - shaf_rdata_o = ((digest_mode_flag == SHA2_256) || ~MultimodeEn) ? + shaf_rdata_o = ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) ? {32'b0, message_length_i[63:32]}: - ((digest_mode_flag == SHA2_384) || (digest_mode_flag == SHA2_512)) ? + ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[127:64] : '0; end LenLo: begin - shaf_rdata_o = ((digest_mode_flag == SHA2_256) || ~MultimodeEn) ? + shaf_rdata_o = ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) ? {32'b0, message_length_i[31:0]}: - ((digest_mode_flag == SHA2_384) || (digest_mode_flag == SHA2_512)) ? + ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[63:0]: '0; end @@ -194,7 +196,7 @@ module prim_sha2_pad import prim_sha2_pkg::*; inc_txcount = 1'b0; fifo_rready_o = 1'b0; st_d = StPad80; - end else if (!hash_process_flag) begin + end else if (!hash_process_flag_q) begin fifo_rready_o = shaf_rready_i; shaf_rvalid_o = fifo_rvalid_i; inc_txcount = shaf_rready_i; @@ -217,9 +219,9 @@ module prim_sha2_pad import prim_sha2_pkg::*; StPad80: begin sel_data = Pad80; shaf_rvalid_o = 1'b1; - fifo_rready_o = (digest_mode_flag == SHA2_256 || ~MultimodeEn) ? + fifo_rready_o = (digest_mode_flag_q == SHA2_256 || ~MultimodeEn) ? shaf_rready_i && |message_length_i[4:3] : - ((digest_mode_flag == SHA2_384) || (digest_mode_flag == SHA2_512)) ? + ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? shaf_rready_i && |message_length_i[5:3] : '0; // Only when partial // exactly 192 bits left, do not need to pad00's @@ -317,9 +319,9 @@ module prim_sha2_pad import prim_sha2_pkg::*; if (hash_start_i) begin tx_count_d = '0; end else if (inc_txcount) begin - if ((digest_mode_flag == SHA2_256) || !MultimodeEn) begin + if ((digest_mode_flag_q == SHA2_256) || !MultimodeEn) begin tx_count_d[127:5] = tx_count[127:5] + 1'b1; - end else if ((digest_mode_flag == SHA2_384) ||(digest_mode_flag == SHA2_512)) begin + end else if ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) begin tx_count_d[127:6] = tx_count[127:6] + 1'b1; end end @@ -330,17 +332,16 @@ module prim_sha2_pad import prim_sha2_pkg::*; else tx_count <= tx_count_d; end - assign digest_mode_flag_d = ~MultimodeEn ? None : // assign to constant - hash_start_i ? digest_mode_i : // latch in configured mode + assign digest_mode_flag_d = hash_start_i ? digest_mode_i : // latch in configured mode hash_done_o ? None : // clear - digest_mode_flag; // keep + digest_mode_flag_q; // keep always_ff @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) digest_mode_flag <= None; - else digest_mode_flag <= digest_mode_flag_d; + if (!rst_ni) digest_mode_flag_q <= None; + else digest_mode_flag_q <= digest_mode_flag_d; end // State machine is in Idle only when it meets tx_count == message length - assign msg_feed_complete_o = hash_process_flag && (st_q == StIdle); + assign msg_feed_complete_o = hash_process_flag_q && (st_q == StIdle); endmodule