From 8e5843987ccf5707d06c103d29a39c46216d304c Mon Sep 17 00:00:00 2001 From: Michael Schaffner Date: Mon, 12 Feb 2024 16:15:43 -0800 Subject: [PATCH] [lc_ctrl/dv] Add build modes with volatile unlock enabled and disabled This addresses the block-level DV parts of #18250. Signed-off-by: Michael Schaffner --- hw/ip/lc_ctrl/dv/README.md | 4 ++-- .../lc_ctrl_volatile_unlock_smoke_vseq.sv | 16 +++++++++++++++- ...m_cfg.hjson => lc_ctrl_base_sim_cfg.hjson} | 13 ++++++++++--- ...trl_volatile_unlock_disabled_sim_cfg.hjson | 19 +++++++++++++++++++ ...ctrl_volatile_unlock_enabled_sim_cfg.hjson | 19 +++++++++++++++++++ hw/ip/lc_ctrl/dv/tb.sv | 10 +--------- .../dv/top_earlgrey_sim_cfgs.hjson | 3 ++- 7 files changed, 68 insertions(+), 16 deletions(-) rename hw/ip/lc_ctrl/dv/{lc_ctrl_sim_cfg.hjson => lc_ctrl_base_sim_cfg.hjson} (97%) create mode 100644 hw/ip/lc_ctrl/dv/lc_ctrl_volatile_unlock_disabled_sim_cfg.hjson create mode 100644 hw/ip/lc_ctrl/dv/lc_ctrl_volatile_unlock_enabled_sim_cfg.hjson diff --git a/hw/ip/lc_ctrl/dv/README.md b/hw/ip/lc_ctrl/dv/README.md index 5c9fc05c663560..fb965ae06f72e2 100644 --- a/hw/ip/lc_ctrl/dv/README.md +++ b/hw/ip/lc_ctrl/dv/README.md @@ -101,9 +101,9 @@ It also updates the UVM register model. ## Building and running tests We are using our in-house developed [regression tool](../../../../util/dvsim/README.md) for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. -Here's how to run a smoke test: +Here's how to run a smoke test for the LC_CTRl variant with volatile RAW unlock disabled: ```console -$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/lc_ctrl/dv/lc_ctrl_sim_cfg.hjson -i lc_ctrl_smoke +$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/lc_ctrl/dv/lc_ctrl_volatile_unlock_disabled_sim.hjson -i lc_ctrl_smoke ``` ## Testplan diff --git a/hw/ip/lc_ctrl/dv/env/seq_lib/lc_ctrl_volatile_unlock_smoke_vseq.sv b/hw/ip/lc_ctrl/dv/env/seq_lib/lc_ctrl_volatile_unlock_smoke_vseq.sv index e40f41f33081f6..7ed40b15efe951 100644 --- a/hw/ip/lc_ctrl/dv/env/seq_lib/lc_ctrl_volatile_unlock_smoke_vseq.sv +++ b/hw/ip/lc_ctrl/dv/env/seq_lib/lc_ctrl_volatile_unlock_smoke_vseq.sv @@ -46,7 +46,21 @@ class lc_ctrl_volatile_unlock_smoke_vseq extends lc_ctrl_smoke_vseq; end csr_wr(ral.transition_cmd, 'h01); - if (next_state == DecLcStTestUnlocked0) begin + if (!`SEC_VOLATILE_RAW_UNLOCK_EN) begin + // We expect the VOLATILE_RAW_UNLOCK bit to stay at zero in this case. + cfg.clk_rst_vif.wait_clks(2); + csr_rd_check(.ptr(ral.transition_ctrl.volatile_raw_unlock), .compare_value(0)); + cfg.clk_rst_vif.wait_clks(10); + // Since we're performing a real transition in this case with a hashed token, we should + // be getting a token error since a real transition expects an unhashed token. + csr_spinwait(.ptr(ral.status.token_error), .exp_data(1), .timeout_ns(100_000)); + // The strap sampling override signal should be zero. + `DV_CHECK_EQ(cfg.lc_ctrl_vif.strap_en_override_o, 0); + if (cfg.en_cov) cov.volatile_raw_unlock_cg.sample(0); + end else if (next_state == DecLcStTestUnlocked0) begin + // We expect the VOLATILE_RAW_UNLOCK bit to go to one in this case. + cfg.clk_rst_vif.wait_clks(2); + csr_rd_check(.ptr(ral.transition_ctrl.volatile_raw_unlock), .compare_value(1)); csr_spinwait(.ptr(ral.status.transition_successful), .exp_data(1), .timeout_ns(100_000)); cfg.clk_rst_vif.wait_clks(10); `DV_CHECK_EQ(cfg.lc_ctrl_vif.strap_en_override_o, 1); diff --git a/hw/ip/lc_ctrl/dv/lc_ctrl_sim_cfg.hjson b/hw/ip/lc_ctrl/dv/lc_ctrl_base_sim_cfg.hjson similarity index 97% rename from hw/ip/lc_ctrl/dv/lc_ctrl_sim_cfg.hjson rename to hw/ip/lc_ctrl/dv/lc_ctrl_base_sim_cfg.hjson index 740fc0059d759a..391c2c92dc1f07 100644 --- a/hw/ip/lc_ctrl/dv/lc_ctrl_sim_cfg.hjson +++ b/hw/ip/lc_ctrl/dv/lc_ctrl_base_sim_cfg.hjson @@ -59,9 +59,16 @@ } ] - // Add LC_CTRL specific exclusion files. - vcs_cov_excl_files: ["{proj_root}/hw/ip/lc_ctrl/dv/cov/lc_ctrl_cov_unr_excl.el", - "{proj_root}/hw/ip/lc_ctrl/dv/cov/lc_ctrl_terminal_st_excl.el"] + build_modes: [ + { + name: volatile_unlock_disabled + build_opts: ["+define+SEC_VOLATILE_RAW_UNLOCK_EN=0"] + } + { + name: volatile_unlock_enabled + build_opts: ["+define+SEC_VOLATILE_RAW_UNLOCK_EN=1"] + } + ] // Default UVM test and seq class name. uvm_test: lc_ctrl_base_test diff --git a/hw/ip/lc_ctrl/dv/lc_ctrl_volatile_unlock_disabled_sim_cfg.hjson b/hw/ip/lc_ctrl/dv/lc_ctrl_volatile_unlock_disabled_sim_cfg.hjson new file mode 100644 index 00000000000000..42ba62aedc8728 --- /dev/null +++ b/hw/ip/lc_ctrl/dv/lc_ctrl_volatile_unlock_disabled_sim_cfg.hjson @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// sim cfg file for the variant of LC_CTRL without volatile unlock +{ + // Name of the sim cfg variant + variant: volatile_unlock_disabled + + // Import additional common sim cfg files. + import_cfgs: ["{proj_root}/hw/ip/lc_ctrl/dv/lc_ctrl_base_sim_cfg.hjson"] + + // Enable this build mode for all tests + en_build_modes: ["volatile_unlock_disabled"] + + // exclusion files + // TODO: redo UNR + vcs_cov_excl_files: ["{proj_root}/hw/ip/lc_ctrl/dv/cov/lc_ctrl_terminal_st_excl.el"] +} diff --git a/hw/ip/lc_ctrl/dv/lc_ctrl_volatile_unlock_enabled_sim_cfg.hjson b/hw/ip/lc_ctrl/dv/lc_ctrl_volatile_unlock_enabled_sim_cfg.hjson new file mode 100644 index 00000000000000..82c249f73da955 --- /dev/null +++ b/hw/ip/lc_ctrl/dv/lc_ctrl_volatile_unlock_enabled_sim_cfg.hjson @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// sim cfg file for the variant of LC_CTRL with volatile unlock +{ + // Name of the sim cfg variant + variant: volatile_unlock_enabled + + // Import additional common sim cfg files. + import_cfgs: ["{proj_root}/hw/ip/lc_ctrl/dv/lc_ctrl_base_sim_cfg.hjson"] + + // Enable this build mode for all tests + en_build_modes: ["volatile_unlock_enabled"] + + // exclusion files + // TODO: redo UNR + vcs_cov_excl_files: ["{proj_root}/hw/ip/lc_ctrl/dv/cov/lc_ctrl_terminal_st_excl.el"] +} diff --git a/hw/ip/lc_ctrl/dv/tb.sv b/hw/ip/lc_ctrl/dv/tb.sv index 2fe596517f4056..37bb0245cd4485 100644 --- a/hw/ip/lc_ctrl/dv/tb.sv +++ b/hw/ip/lc_ctrl/dv/tb.sv @@ -26,14 +26,6 @@ module tb; LcKeymgrDivWidth'({(LcKeymgrDivWidth/8){8'h5a}}); parameter lc_keymgr_div_t RndCnstLcKeymgrDivProduction = LcKeymgrDivWidth'({(LcKeymgrDivWidth/8){8'ha5}}); - // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ---------- - // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE - // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA - // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES. - // --------------------------------------------------------------- - // ICEBOX(#18250): The SecVolatileRawUnlockEn configuration should be tested separately for PROD. - parameter bit SecVolatileRawUnlockEn = 1; - // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END ----------- // macro includes `include "uvm_macros.svh" @@ -108,7 +100,7 @@ module tb; .SiliconCreatorId(LcCtrlSiliconCreatorId[lc_ctrl_reg_pkg::SiliconCreatorIdWidth-1:0]), .ProductId(LcCtrlProductId[lc_ctrl_reg_pkg::ProductIdWidth-1:0]), .RevisionId(LcCtrlRevisionId[lc_ctrl_reg_pkg::RevisionIdWidth-1:0]), - .SecVolatileRawUnlockEn(SecVolatileRawUnlockEn) + .SecVolatileRawUnlockEn(`SEC_VOLATILE_RAW_UNLOCK_EN) ) dut ( .clk_i (clk), .rst_ni(rst_n), diff --git a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson index 73023d8a9489de..0602527e8a2355 100644 --- a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson +++ b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson @@ -34,7 +34,8 @@ "{proj_root}/hw/ip/keymgr/dv/keymgr_sim_cfg.hjson", "{proj_root}/hw/ip/kmac/dv/kmac_masked_sim_cfg.hjson", "{proj_root}/hw/ip/kmac/dv/kmac_unmasked_sim_cfg.hjson", - "{proj_root}/hw/ip/lc_ctrl/dv/lc_ctrl_sim_cfg.hjson", + "{proj_root}/hw/ip/lc_ctrl/dv/lc_ctrl_volatile_unlock_disabled_sim_cfg.hjson", + "{proj_root}/hw/ip/lc_ctrl/dv/lc_ctrl_volatile_unlock_enabled_sim_cfg.hjson", "{proj_root}/hw/ip/otbn/dv/uvm/otbn_sim_cfg.hjson", "{proj_root}/hw/ip/otp_ctrl/dv/otp_ctrl_sim_cfg.hjson", "{proj_root}/hw/ip/pattgen/dv/pattgen_sim_cfg.hjson",