diff --git a/hw/ip/hmac/dv/cov/hmac_cov_excl.el b/hw/ip/hmac/dv/cov/hmac_cov_excl.el
index e4f09b1f70408..887a80913b5f4 100644
--- a/hw/ip/hmac/dv/cov/hmac_cov_excl.el
+++ b/hw/ip/hmac/dv/cov/hmac_cov_excl.el
@@ -4,22 +4,44 @@
 
 //==================================================
 // This file contains the Excluded objects
-// Generated By User: gdessouky
+// Generated By User: andrea.caforio
 // Format Version: 2
-// Date: Sat Jul  6 04:05:21 2024
+// Date: Wed Dec 18 09:14:03 2024
 // ExclMode: default
 //==================================================
-CHECKSUM: "1683432060 1171249183"
+CHECKSUM: "499420175 4264787725"
+INSTANCE: tb.dut.u_hmac
+ANNOTATION: "The default case cannot be reached as all the sel_rdata possible values are explicitly specified and covered."
+Branch 6 "579089686" "(!hmac_en_i)" (6) "(!hmac_en_i) 0,0,0,0,0,0"
+ANNOTATION: "Any other value than SHA2_256/384/512 is not supposed to be programmed, otherwise an interrupt is raised. This non-existing \"else\" should be excluded."
+Branch 11 "3517354206" "(!hmac_en_i)" (7) "(!hmac_en_i) 0,0,-,-,1,0,0,0"
+CHECKSUM: "2418056030 1412398065"
+INSTANCE: tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode
+ANNOTATION: "Any other value than SHA2_256/384/512 is not supposed to be programmed, otherwise an interrupt is raised. This non-existing \"else\" should be excluded."
+Branch 17 "3482269818" "wipe_secret_i" (4) "wipe_secret_i 0,0,1,0,0"
+CHECKSUM: "1959679361 399230717"
 INSTANCE: tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode.u_pad
-Fsm st_q "1171249183"
-ANNOTATION: "[INVALID] Intend to remove transition"
-Transition StLenHi->StFifoReceive "4->1"
-Fsm st_q "1171249183"
-ANNOTATION: "[INVALID] Intend to remove transition"
-Transition StPad80->StFifoReceive "2->1"
-Fsm st_q "1171249183"
-ANNOTATION: "[INVALID] Intend to remove transition"
-Transition StPad00->StFifoReceive "3->1"
-Fsm st_q "1171249183"
-ANNOTATION: "[INVALID] Intend to remove transition"
-Transition StLenLo->StFifoReceive "5->1"
+ANNOTATION: "Any other value than SHA2_256/384/512 is not supposed to be programmed, otherwise an interrupt is raised."
+Branch 5 "2629563645" "sel_data" (15) "sel_data Pad80 ,0,-,0,-,-,-,-,-"
+ANNOTATION: "Any other value than SHA2_256/384/512 is not supposed to be programmed, otherwise an interrupt is raised."
+Branch 10 "52001575" "hash_start_i" (4) "hash_start_i 0,0,1,0,0"
+ANNOTATION: "shaf_rready_i == 1'b0 cannot occur in the StLenHi and StLenLo states."
+Branch 8 "199737855" "st_q" (18) "st_q StLenHi ,-,-,-,-,-,-,-,-,-,-,-,0,-"
+ANNOTATION: "Any other value than SHA2_256/384/512 is not supposed to be programmed, otherwise an interrupt is raised."
+Branch 8 "199737855" "st_q" (10) "st_q StPad80 ,-,-,-,-,-,0,0,-,-,-,-,-,-"
+ANNOTATION: "shaf_rready_i == 1'b0 cannot occur in the StLenHi and StLenLo states."
+Branch 8 "199737855" "st_q" (20) "st_q StLenLo ,-,-,-,-,-,-,-,-,-,-,-,-,0"
+CHECKSUM: "1959679361 2615869547"
+INSTANCE: tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode.u_pad
+ANNOTATION: "This requires to trigger hash_start or hash_continue while SHA core is disabled and also while the state machine is in Idle mode. This is outside the specification and won't be easy to trigger."
+Condition 20 "3664197505" "(sha_en_i && hash_go) 1 -1" (1 "01")
+ANNOTATION: "Any other value than SHA2_256/384/512 is not supposed to be programmed, otherwise an interrupt is raised."
+Condition 40 "1493086427" "((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) 1 -1" (1 "00")
+ANNOTATION: "When shaf_rready_i is equal to 0, then the StPad80 state gets entered through the StFifoReceive state, for which hash_start_i has to be 1. Outside of prim_sha2_pad, in prim_sha2, hash_start_i == 1 causes the FIFO FSM to enter the FifoLoadFromFifo state. In this state, prim_sha2 sets prim_sha2_pad's shaf_rready_i input to 1 (through update_w_from_fifo) whenever shaf_rvalid is set. shaf_rvalid is driven by prim_sha2_pad to constant 1 in the StPad80 state. Thus shaf_rready_i == 1'b0 cannot occur."
+Condition 32 "1125024036" "(shaf_rready_i && txcnt_eq_1a0) 1 -1" (1 "01")
+ANNOTATION: "Any other value than SHA2_256/384/512 is not supposed to be programmed, otherwise an interrupt is raised."
+Condition 27 "1797031703" "(((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (shaf_rready_i && ((|message_length_i[5:3]))) : '0) 1 -1" (1 "0")
+ANNOTATION: "When shaf_rready_i is equal to 0, then the StPad80 state gets entered through the StFifoReceive state, for which hash_start_i has to be 1. Outside of prim_sha2_pad, in prim_sha2, hash_start_i == 1 causes the FIFO FSM to enter the FifoLoadFromFifo state. In this state, prim_sha2 sets prim_sha2_pad's shaf_rready_i input to 1 (through update_w_from_fifo) whenever shaf_rvalid is set. shaf_rvalid is driven by prim_sha2_pad to constant 1 in the StPad80 state. Thus shaf_rready_i == 1'b0 cannot occur."
+Condition 31 "2638115978" "(shaf_rready_i && ((|message_length_i[5:3]))) 1 -1" (1 "01")
+ANNOTATION: "Any other value than SHA2_256/384/512 is not supposed to be programmed, otherwise an interrupt is raised. "
+Condition 3 "3622116032" "((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) 1 -1" (1 "00")