From 8b51715723a2ea288d05707318cd5817323b3c40 Mon Sep 17 00:00:00 2001 From: Robert Schilling Date: Wed, 17 Jul 2024 05:47:41 -0700 Subject: [PATCH] [top] Regenerate top after removing DMA interrupt Signed-off-by: Robert Schilling --- .../data/autogen/top_darjeeling.gen.hjson | 6 - .../ip_autogen/rv_plic/data/rv_plic.hjson | 10 +- .../top_darjeeling_rv_plic.ipconfig.hjson | 2 +- .../ip_autogen/rv_plic/rtl/rv_plic.sv | 5 +- .../ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv | 372 +++++++++--------- .../ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv | 216 +++------- .../rtl/autogen/top_darjeeling.sv | 69 ++-- .../sw/autogen/chip/top_darjeeling.rs | 127 +++--- hw/top_darjeeling/sw/autogen/top_darjeeling.c | 3 +- hw/top_darjeeling/sw/autogen/top_darjeeling.h | 65 ++- .../top_darjeeling/plic_all_irqs_test.c | 2 +- 11 files changed, 371 insertions(+), 506 deletions(-) diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson index 226faefaad6a09..786c668b50462b 100644 --- a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson @@ -15871,12 +15871,6 @@ type: interrupt module_name: dma } - { - name: dma_dma_memory_buffer_limit - width: 1 - type: interrupt - module_name: dma - } { name: mbx0_mbx_ready width: 1 diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/data/rv_plic.hjson b/hw/top_darjeeling/ip_autogen/rv_plic/data/rv_plic.hjson index aaf18d0b131aa9..32fabacba39bfe 100644 --- a/hw/top_darjeeling/ip_autogen/rv_plic/data/rv_plic.hjson +++ b/hw/top_darjeeling/ip_autogen/rv_plic/data/rv_plic.hjson @@ -37,7 +37,7 @@ { name: "NumSrc", desc: "Number of interrupt sources", type: "int", - default: "163", + default: "162", local: "true" }, { name: "NumTarget", @@ -1394,14 +1394,6 @@ { bits: "1:0" } ], } - { name: "PRIO162", - desc: "Interrupt Source 162 Priority", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "1:0" } - ], - } { skipto: "0x00001000" } { multireg: { name: "IP", diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/data/top_darjeeling_rv_plic.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/rv_plic/data/top_darjeeling_rv_plic.ipconfig.hjson index dc7422c5f0faa7..75ddbc73c7b66f 100644 --- a/hw/top_darjeeling/ip_autogen/rv_plic/data/top_darjeeling_rv_plic.ipconfig.hjson +++ b/hw/top_darjeeling/ip_autogen/rv_plic/data/top_darjeeling_rv_plic.ipconfig.hjson @@ -5,7 +5,7 @@ instance_name: top_darjeeling_rv_plic param_values: { - src: 163 + src: 162 target: 1 prio: 3 top_name: darjeeling diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic.sv b/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic.sv index 999fea0646b806..32d5700037ab24 100644 --- a/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic.sv +++ b/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic.sv @@ -260,12 +260,11 @@ module rv_plic import rv_plic_reg_pkg::*; #( assign prio[159] = reg2hw.prio159.q; assign prio[160] = reg2hw.prio160.q; assign prio[161] = reg2hw.prio161.q; - assign prio[162] = reg2hw.prio162.q; ////////////////////// // Interrupt Enable // ////////////////////// - for (genvar s = 0; s < 163; s++) begin : gen_ie0 + for (genvar s = 0; s < 162; s++) begin : gen_ie0 assign ie[0][s] = reg2hw.ie0[s].q; end @@ -291,7 +290,7 @@ module rv_plic import rv_plic_reg_pkg::*; #( //////// // IP // //////// - for (genvar s = 0; s < 163; s++) begin : gen_ip + for (genvar s = 0; s < 162; s++) begin : gen_ip assign hw2reg.ip[s].de = 1'b1; // Always write assign hw2reg.ip[s].d = ip[s]; end diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv b/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv index 3edea4e79e7440..d187d981a26f77 100644 --- a/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv +++ b/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv @@ -7,7 +7,7 @@ package rv_plic_reg_pkg; // Param list - parameter int NumSrc = 163; + parameter int NumSrc = 162; parameter int NumTarget = 1; parameter int PrioWidth = 2; parameter int NumAlerts = 1; @@ -667,10 +667,6 @@ package rv_plic_reg_pkg; logic [1:0] q; } rv_plic_reg2hw_prio161_reg_t; - typedef struct packed { - logic [1:0] q; - } rv_plic_reg2hw_prio162_reg_t; - typedef struct packed { logic q; } rv_plic_reg2hw_ie0_mreg_t; @@ -705,170 +701,169 @@ package rv_plic_reg_pkg; // Register -> HW type typedef struct packed { - rv_plic_reg2hw_prio0_reg_t prio0; // [503:502] - rv_plic_reg2hw_prio1_reg_t prio1; // [501:500] - rv_plic_reg2hw_prio2_reg_t prio2; // [499:498] - rv_plic_reg2hw_prio3_reg_t prio3; // [497:496] - rv_plic_reg2hw_prio4_reg_t prio4; // [495:494] - rv_plic_reg2hw_prio5_reg_t prio5; // [493:492] - rv_plic_reg2hw_prio6_reg_t prio6; // [491:490] - rv_plic_reg2hw_prio7_reg_t prio7; // [489:488] - rv_plic_reg2hw_prio8_reg_t prio8; // [487:486] - rv_plic_reg2hw_prio9_reg_t prio9; // [485:484] - rv_plic_reg2hw_prio10_reg_t prio10; // [483:482] - rv_plic_reg2hw_prio11_reg_t prio11; // [481:480] - rv_plic_reg2hw_prio12_reg_t prio12; // [479:478] - rv_plic_reg2hw_prio13_reg_t prio13; // [477:476] - rv_plic_reg2hw_prio14_reg_t prio14; // [475:474] - rv_plic_reg2hw_prio15_reg_t prio15; // [473:472] - rv_plic_reg2hw_prio16_reg_t prio16; // [471:470] - rv_plic_reg2hw_prio17_reg_t prio17; // [469:468] - rv_plic_reg2hw_prio18_reg_t prio18; // [467:466] - rv_plic_reg2hw_prio19_reg_t prio19; // [465:464] - rv_plic_reg2hw_prio20_reg_t prio20; // [463:462] - rv_plic_reg2hw_prio21_reg_t prio21; // [461:460] - rv_plic_reg2hw_prio22_reg_t prio22; // [459:458] - rv_plic_reg2hw_prio23_reg_t prio23; // [457:456] - rv_plic_reg2hw_prio24_reg_t prio24; // [455:454] - rv_plic_reg2hw_prio25_reg_t prio25; // [453:452] - rv_plic_reg2hw_prio26_reg_t prio26; // [451:450] - rv_plic_reg2hw_prio27_reg_t prio27; // [449:448] - rv_plic_reg2hw_prio28_reg_t prio28; // [447:446] - rv_plic_reg2hw_prio29_reg_t prio29; // [445:444] - rv_plic_reg2hw_prio30_reg_t prio30; // [443:442] - rv_plic_reg2hw_prio31_reg_t prio31; // [441:440] - rv_plic_reg2hw_prio32_reg_t prio32; // [439:438] - rv_plic_reg2hw_prio33_reg_t prio33; // [437:436] - rv_plic_reg2hw_prio34_reg_t prio34; // [435:434] - rv_plic_reg2hw_prio35_reg_t prio35; // [433:432] - rv_plic_reg2hw_prio36_reg_t prio36; // [431:430] - rv_plic_reg2hw_prio37_reg_t prio37; // [429:428] - rv_plic_reg2hw_prio38_reg_t prio38; // [427:426] - rv_plic_reg2hw_prio39_reg_t prio39; // [425:424] - rv_plic_reg2hw_prio40_reg_t prio40; // [423:422] - rv_plic_reg2hw_prio41_reg_t prio41; // [421:420] - rv_plic_reg2hw_prio42_reg_t prio42; // [419:418] - rv_plic_reg2hw_prio43_reg_t prio43; // [417:416] - rv_plic_reg2hw_prio44_reg_t prio44; // [415:414] - rv_plic_reg2hw_prio45_reg_t prio45; // [413:412] - rv_plic_reg2hw_prio46_reg_t prio46; // [411:410] - rv_plic_reg2hw_prio47_reg_t prio47; // [409:408] - rv_plic_reg2hw_prio48_reg_t prio48; // [407:406] - rv_plic_reg2hw_prio49_reg_t prio49; // [405:404] - rv_plic_reg2hw_prio50_reg_t prio50; // [403:402] - rv_plic_reg2hw_prio51_reg_t prio51; // [401:400] - rv_plic_reg2hw_prio52_reg_t prio52; // [399:398] - rv_plic_reg2hw_prio53_reg_t prio53; // [397:396] - rv_plic_reg2hw_prio54_reg_t prio54; // [395:394] - rv_plic_reg2hw_prio55_reg_t prio55; // [393:392] - rv_plic_reg2hw_prio56_reg_t prio56; // [391:390] - rv_plic_reg2hw_prio57_reg_t prio57; // [389:388] - rv_plic_reg2hw_prio58_reg_t prio58; // [387:386] - rv_plic_reg2hw_prio59_reg_t prio59; // [385:384] - rv_plic_reg2hw_prio60_reg_t prio60; // [383:382] - rv_plic_reg2hw_prio61_reg_t prio61; // [381:380] - rv_plic_reg2hw_prio62_reg_t prio62; // [379:378] - rv_plic_reg2hw_prio63_reg_t prio63; // [377:376] - rv_plic_reg2hw_prio64_reg_t prio64; // [375:374] - rv_plic_reg2hw_prio65_reg_t prio65; // [373:372] - rv_plic_reg2hw_prio66_reg_t prio66; // [371:370] - rv_plic_reg2hw_prio67_reg_t prio67; // [369:368] - rv_plic_reg2hw_prio68_reg_t prio68; // [367:366] - rv_plic_reg2hw_prio69_reg_t prio69; // [365:364] - rv_plic_reg2hw_prio70_reg_t prio70; // [363:362] - rv_plic_reg2hw_prio71_reg_t prio71; // [361:360] - rv_plic_reg2hw_prio72_reg_t prio72; // [359:358] - rv_plic_reg2hw_prio73_reg_t prio73; // [357:356] - rv_plic_reg2hw_prio74_reg_t prio74; // [355:354] - rv_plic_reg2hw_prio75_reg_t prio75; // [353:352] - rv_plic_reg2hw_prio76_reg_t prio76; // [351:350] - rv_plic_reg2hw_prio77_reg_t prio77; // [349:348] - rv_plic_reg2hw_prio78_reg_t prio78; // [347:346] - rv_plic_reg2hw_prio79_reg_t prio79; // [345:344] - rv_plic_reg2hw_prio80_reg_t prio80; // [343:342] - rv_plic_reg2hw_prio81_reg_t prio81; // [341:340] - rv_plic_reg2hw_prio82_reg_t prio82; // [339:338] - rv_plic_reg2hw_prio83_reg_t prio83; // [337:336] - rv_plic_reg2hw_prio84_reg_t prio84; // [335:334] - rv_plic_reg2hw_prio85_reg_t prio85; // [333:332] - rv_plic_reg2hw_prio86_reg_t prio86; // [331:330] - rv_plic_reg2hw_prio87_reg_t prio87; // [329:328] - rv_plic_reg2hw_prio88_reg_t prio88; // [327:326] - rv_plic_reg2hw_prio89_reg_t prio89; // [325:324] - rv_plic_reg2hw_prio90_reg_t prio90; // [323:322] - rv_plic_reg2hw_prio91_reg_t prio91; // [321:320] - rv_plic_reg2hw_prio92_reg_t prio92; // [319:318] - rv_plic_reg2hw_prio93_reg_t prio93; // [317:316] - rv_plic_reg2hw_prio94_reg_t prio94; // [315:314] - rv_plic_reg2hw_prio95_reg_t prio95; // [313:312] - rv_plic_reg2hw_prio96_reg_t prio96; // [311:310] - rv_plic_reg2hw_prio97_reg_t prio97; // [309:308] - rv_plic_reg2hw_prio98_reg_t prio98; // [307:306] - rv_plic_reg2hw_prio99_reg_t prio99; // [305:304] - rv_plic_reg2hw_prio100_reg_t prio100; // [303:302] - rv_plic_reg2hw_prio101_reg_t prio101; // [301:300] - rv_plic_reg2hw_prio102_reg_t prio102; // [299:298] - rv_plic_reg2hw_prio103_reg_t prio103; // [297:296] - rv_plic_reg2hw_prio104_reg_t prio104; // [295:294] - rv_plic_reg2hw_prio105_reg_t prio105; // [293:292] - rv_plic_reg2hw_prio106_reg_t prio106; // [291:290] - rv_plic_reg2hw_prio107_reg_t prio107; // [289:288] - rv_plic_reg2hw_prio108_reg_t prio108; // [287:286] - rv_plic_reg2hw_prio109_reg_t prio109; // [285:284] - rv_plic_reg2hw_prio110_reg_t prio110; // [283:282] - rv_plic_reg2hw_prio111_reg_t prio111; // [281:280] - rv_plic_reg2hw_prio112_reg_t prio112; // [279:278] - rv_plic_reg2hw_prio113_reg_t prio113; // [277:276] - rv_plic_reg2hw_prio114_reg_t prio114; // [275:274] - rv_plic_reg2hw_prio115_reg_t prio115; // [273:272] - rv_plic_reg2hw_prio116_reg_t prio116; // [271:270] - rv_plic_reg2hw_prio117_reg_t prio117; // [269:268] - rv_plic_reg2hw_prio118_reg_t prio118; // [267:266] - rv_plic_reg2hw_prio119_reg_t prio119; // [265:264] - rv_plic_reg2hw_prio120_reg_t prio120; // [263:262] - rv_plic_reg2hw_prio121_reg_t prio121; // [261:260] - rv_plic_reg2hw_prio122_reg_t prio122; // [259:258] - rv_plic_reg2hw_prio123_reg_t prio123; // [257:256] - rv_plic_reg2hw_prio124_reg_t prio124; // [255:254] - rv_plic_reg2hw_prio125_reg_t prio125; // [253:252] - rv_plic_reg2hw_prio126_reg_t prio126; // [251:250] - rv_plic_reg2hw_prio127_reg_t prio127; // [249:248] - rv_plic_reg2hw_prio128_reg_t prio128; // [247:246] - rv_plic_reg2hw_prio129_reg_t prio129; // [245:244] - rv_plic_reg2hw_prio130_reg_t prio130; // [243:242] - rv_plic_reg2hw_prio131_reg_t prio131; // [241:240] - rv_plic_reg2hw_prio132_reg_t prio132; // [239:238] - rv_plic_reg2hw_prio133_reg_t prio133; // [237:236] - rv_plic_reg2hw_prio134_reg_t prio134; // [235:234] - rv_plic_reg2hw_prio135_reg_t prio135; // [233:232] - rv_plic_reg2hw_prio136_reg_t prio136; // [231:230] - rv_plic_reg2hw_prio137_reg_t prio137; // [229:228] - rv_plic_reg2hw_prio138_reg_t prio138; // [227:226] - rv_plic_reg2hw_prio139_reg_t prio139; // [225:224] - rv_plic_reg2hw_prio140_reg_t prio140; // [223:222] - rv_plic_reg2hw_prio141_reg_t prio141; // [221:220] - rv_plic_reg2hw_prio142_reg_t prio142; // [219:218] - rv_plic_reg2hw_prio143_reg_t prio143; // [217:216] - rv_plic_reg2hw_prio144_reg_t prio144; // [215:214] - rv_plic_reg2hw_prio145_reg_t prio145; // [213:212] - rv_plic_reg2hw_prio146_reg_t prio146; // [211:210] - rv_plic_reg2hw_prio147_reg_t prio147; // [209:208] - rv_plic_reg2hw_prio148_reg_t prio148; // [207:206] - rv_plic_reg2hw_prio149_reg_t prio149; // [205:204] - rv_plic_reg2hw_prio150_reg_t prio150; // [203:202] - rv_plic_reg2hw_prio151_reg_t prio151; // [201:200] - rv_plic_reg2hw_prio152_reg_t prio152; // [199:198] - rv_plic_reg2hw_prio153_reg_t prio153; // [197:196] - rv_plic_reg2hw_prio154_reg_t prio154; // [195:194] - rv_plic_reg2hw_prio155_reg_t prio155; // [193:192] - rv_plic_reg2hw_prio156_reg_t prio156; // [191:190] - rv_plic_reg2hw_prio157_reg_t prio157; // [189:188] - rv_plic_reg2hw_prio158_reg_t prio158; // [187:186] - rv_plic_reg2hw_prio159_reg_t prio159; // [185:184] - rv_plic_reg2hw_prio160_reg_t prio160; // [183:182] - rv_plic_reg2hw_prio161_reg_t prio161; // [181:180] - rv_plic_reg2hw_prio162_reg_t prio162; // [179:178] - rv_plic_reg2hw_ie0_mreg_t [162:0] ie0; // [177:15] + rv_plic_reg2hw_prio0_reg_t prio0; // [500:499] + rv_plic_reg2hw_prio1_reg_t prio1; // [498:497] + rv_plic_reg2hw_prio2_reg_t prio2; // [496:495] + rv_plic_reg2hw_prio3_reg_t prio3; // [494:493] + rv_plic_reg2hw_prio4_reg_t prio4; // [492:491] + rv_plic_reg2hw_prio5_reg_t prio5; // [490:489] + rv_plic_reg2hw_prio6_reg_t prio6; // [488:487] + rv_plic_reg2hw_prio7_reg_t prio7; // [486:485] + rv_plic_reg2hw_prio8_reg_t prio8; // [484:483] + rv_plic_reg2hw_prio9_reg_t prio9; // [482:481] + rv_plic_reg2hw_prio10_reg_t prio10; // [480:479] + rv_plic_reg2hw_prio11_reg_t prio11; // [478:477] + rv_plic_reg2hw_prio12_reg_t prio12; // [476:475] + rv_plic_reg2hw_prio13_reg_t prio13; // [474:473] + rv_plic_reg2hw_prio14_reg_t prio14; // [472:471] + rv_plic_reg2hw_prio15_reg_t prio15; // [470:469] + rv_plic_reg2hw_prio16_reg_t prio16; // [468:467] + rv_plic_reg2hw_prio17_reg_t prio17; // [466:465] + rv_plic_reg2hw_prio18_reg_t prio18; // [464:463] + rv_plic_reg2hw_prio19_reg_t prio19; // [462:461] + rv_plic_reg2hw_prio20_reg_t prio20; // [460:459] + rv_plic_reg2hw_prio21_reg_t prio21; // [458:457] + rv_plic_reg2hw_prio22_reg_t prio22; // [456:455] + rv_plic_reg2hw_prio23_reg_t prio23; // [454:453] + rv_plic_reg2hw_prio24_reg_t prio24; // [452:451] + rv_plic_reg2hw_prio25_reg_t prio25; // [450:449] + rv_plic_reg2hw_prio26_reg_t prio26; // [448:447] + rv_plic_reg2hw_prio27_reg_t prio27; // [446:445] + rv_plic_reg2hw_prio28_reg_t prio28; // [444:443] + rv_plic_reg2hw_prio29_reg_t prio29; // [442:441] + rv_plic_reg2hw_prio30_reg_t prio30; // [440:439] + rv_plic_reg2hw_prio31_reg_t prio31; // [438:437] + rv_plic_reg2hw_prio32_reg_t prio32; // [436:435] + rv_plic_reg2hw_prio33_reg_t prio33; // [434:433] + rv_plic_reg2hw_prio34_reg_t prio34; // [432:431] + rv_plic_reg2hw_prio35_reg_t prio35; // [430:429] + rv_plic_reg2hw_prio36_reg_t prio36; // [428:427] + rv_plic_reg2hw_prio37_reg_t prio37; // [426:425] + rv_plic_reg2hw_prio38_reg_t prio38; // [424:423] + rv_plic_reg2hw_prio39_reg_t prio39; // [422:421] + rv_plic_reg2hw_prio40_reg_t prio40; // [420:419] + rv_plic_reg2hw_prio41_reg_t prio41; // [418:417] + rv_plic_reg2hw_prio42_reg_t prio42; // [416:415] + rv_plic_reg2hw_prio43_reg_t prio43; // [414:413] + rv_plic_reg2hw_prio44_reg_t prio44; // [412:411] + rv_plic_reg2hw_prio45_reg_t prio45; // [410:409] + rv_plic_reg2hw_prio46_reg_t prio46; // [408:407] + rv_plic_reg2hw_prio47_reg_t prio47; // [406:405] + rv_plic_reg2hw_prio48_reg_t prio48; // [404:403] + rv_plic_reg2hw_prio49_reg_t prio49; // [402:401] + rv_plic_reg2hw_prio50_reg_t prio50; // [400:399] + rv_plic_reg2hw_prio51_reg_t prio51; // [398:397] + rv_plic_reg2hw_prio52_reg_t prio52; // [396:395] + rv_plic_reg2hw_prio53_reg_t prio53; // [394:393] + rv_plic_reg2hw_prio54_reg_t prio54; // [392:391] + rv_plic_reg2hw_prio55_reg_t prio55; // [390:389] + rv_plic_reg2hw_prio56_reg_t prio56; // [388:387] + rv_plic_reg2hw_prio57_reg_t prio57; // [386:385] + rv_plic_reg2hw_prio58_reg_t prio58; // [384:383] + rv_plic_reg2hw_prio59_reg_t prio59; // [382:381] + rv_plic_reg2hw_prio60_reg_t prio60; // [380:379] + rv_plic_reg2hw_prio61_reg_t prio61; // [378:377] + rv_plic_reg2hw_prio62_reg_t prio62; // [376:375] + rv_plic_reg2hw_prio63_reg_t prio63; // [374:373] + rv_plic_reg2hw_prio64_reg_t prio64; // [372:371] + rv_plic_reg2hw_prio65_reg_t prio65; // [370:369] + rv_plic_reg2hw_prio66_reg_t prio66; // [368:367] + rv_plic_reg2hw_prio67_reg_t prio67; // [366:365] + rv_plic_reg2hw_prio68_reg_t prio68; // [364:363] + rv_plic_reg2hw_prio69_reg_t prio69; // [362:361] + rv_plic_reg2hw_prio70_reg_t prio70; // [360:359] + rv_plic_reg2hw_prio71_reg_t prio71; // [358:357] + rv_plic_reg2hw_prio72_reg_t prio72; // [356:355] + rv_plic_reg2hw_prio73_reg_t prio73; // [354:353] + rv_plic_reg2hw_prio74_reg_t prio74; // [352:351] + rv_plic_reg2hw_prio75_reg_t prio75; // [350:349] + rv_plic_reg2hw_prio76_reg_t prio76; // [348:347] + rv_plic_reg2hw_prio77_reg_t prio77; // [346:345] + rv_plic_reg2hw_prio78_reg_t prio78; // [344:343] + rv_plic_reg2hw_prio79_reg_t prio79; // [342:341] + rv_plic_reg2hw_prio80_reg_t prio80; // [340:339] + rv_plic_reg2hw_prio81_reg_t prio81; // [338:337] + rv_plic_reg2hw_prio82_reg_t prio82; // [336:335] + rv_plic_reg2hw_prio83_reg_t prio83; // [334:333] + rv_plic_reg2hw_prio84_reg_t prio84; // [332:331] + rv_plic_reg2hw_prio85_reg_t prio85; // [330:329] + rv_plic_reg2hw_prio86_reg_t prio86; // [328:327] + rv_plic_reg2hw_prio87_reg_t prio87; // [326:325] + rv_plic_reg2hw_prio88_reg_t prio88; // [324:323] + rv_plic_reg2hw_prio89_reg_t prio89; // [322:321] + rv_plic_reg2hw_prio90_reg_t prio90; // [320:319] + rv_plic_reg2hw_prio91_reg_t prio91; // [318:317] + rv_plic_reg2hw_prio92_reg_t prio92; // [316:315] + rv_plic_reg2hw_prio93_reg_t prio93; // [314:313] + rv_plic_reg2hw_prio94_reg_t prio94; // [312:311] + rv_plic_reg2hw_prio95_reg_t prio95; // [310:309] + rv_plic_reg2hw_prio96_reg_t prio96; // [308:307] + rv_plic_reg2hw_prio97_reg_t prio97; // [306:305] + rv_plic_reg2hw_prio98_reg_t prio98; // [304:303] + rv_plic_reg2hw_prio99_reg_t prio99; // [302:301] + rv_plic_reg2hw_prio100_reg_t prio100; // [300:299] + rv_plic_reg2hw_prio101_reg_t prio101; // [298:297] + rv_plic_reg2hw_prio102_reg_t prio102; // [296:295] + rv_plic_reg2hw_prio103_reg_t prio103; // [294:293] + rv_plic_reg2hw_prio104_reg_t prio104; // [292:291] + rv_plic_reg2hw_prio105_reg_t prio105; // [290:289] + rv_plic_reg2hw_prio106_reg_t prio106; // [288:287] + rv_plic_reg2hw_prio107_reg_t prio107; // [286:285] + rv_plic_reg2hw_prio108_reg_t prio108; // [284:283] + rv_plic_reg2hw_prio109_reg_t prio109; // [282:281] + rv_plic_reg2hw_prio110_reg_t prio110; // [280:279] + rv_plic_reg2hw_prio111_reg_t prio111; // [278:277] + rv_plic_reg2hw_prio112_reg_t prio112; // [276:275] + rv_plic_reg2hw_prio113_reg_t prio113; // [274:273] + rv_plic_reg2hw_prio114_reg_t prio114; // [272:271] + rv_plic_reg2hw_prio115_reg_t prio115; // [270:269] + rv_plic_reg2hw_prio116_reg_t prio116; // [268:267] + rv_plic_reg2hw_prio117_reg_t prio117; // [266:265] + rv_plic_reg2hw_prio118_reg_t prio118; // [264:263] + rv_plic_reg2hw_prio119_reg_t prio119; // [262:261] + rv_plic_reg2hw_prio120_reg_t prio120; // [260:259] + rv_plic_reg2hw_prio121_reg_t prio121; // [258:257] + rv_plic_reg2hw_prio122_reg_t prio122; // [256:255] + rv_plic_reg2hw_prio123_reg_t prio123; // [254:253] + rv_plic_reg2hw_prio124_reg_t prio124; // [252:251] + rv_plic_reg2hw_prio125_reg_t prio125; // [250:249] + rv_plic_reg2hw_prio126_reg_t prio126; // [248:247] + rv_plic_reg2hw_prio127_reg_t prio127; // [246:245] + rv_plic_reg2hw_prio128_reg_t prio128; // [244:243] + rv_plic_reg2hw_prio129_reg_t prio129; // [242:241] + rv_plic_reg2hw_prio130_reg_t prio130; // [240:239] + rv_plic_reg2hw_prio131_reg_t prio131; // [238:237] + rv_plic_reg2hw_prio132_reg_t prio132; // [236:235] + rv_plic_reg2hw_prio133_reg_t prio133; // [234:233] + rv_plic_reg2hw_prio134_reg_t prio134; // [232:231] + rv_plic_reg2hw_prio135_reg_t prio135; // [230:229] + rv_plic_reg2hw_prio136_reg_t prio136; // [228:227] + rv_plic_reg2hw_prio137_reg_t prio137; // [226:225] + rv_plic_reg2hw_prio138_reg_t prio138; // [224:223] + rv_plic_reg2hw_prio139_reg_t prio139; // [222:221] + rv_plic_reg2hw_prio140_reg_t prio140; // [220:219] + rv_plic_reg2hw_prio141_reg_t prio141; // [218:217] + rv_plic_reg2hw_prio142_reg_t prio142; // [216:215] + rv_plic_reg2hw_prio143_reg_t prio143; // [214:213] + rv_plic_reg2hw_prio144_reg_t prio144; // [212:211] + rv_plic_reg2hw_prio145_reg_t prio145; // [210:209] + rv_plic_reg2hw_prio146_reg_t prio146; // [208:207] + rv_plic_reg2hw_prio147_reg_t prio147; // [206:205] + rv_plic_reg2hw_prio148_reg_t prio148; // [204:203] + rv_plic_reg2hw_prio149_reg_t prio149; // [202:201] + rv_plic_reg2hw_prio150_reg_t prio150; // [200:199] + rv_plic_reg2hw_prio151_reg_t prio151; // [198:197] + rv_plic_reg2hw_prio152_reg_t prio152; // [196:195] + rv_plic_reg2hw_prio153_reg_t prio153; // [194:193] + rv_plic_reg2hw_prio154_reg_t prio154; // [192:191] + rv_plic_reg2hw_prio155_reg_t prio155; // [190:189] + rv_plic_reg2hw_prio156_reg_t prio156; // [188:187] + rv_plic_reg2hw_prio157_reg_t prio157; // [186:185] + rv_plic_reg2hw_prio158_reg_t prio158; // [184:183] + rv_plic_reg2hw_prio159_reg_t prio159; // [182:181] + rv_plic_reg2hw_prio160_reg_t prio160; // [180:179] + rv_plic_reg2hw_prio161_reg_t prio161; // [178:177] + rv_plic_reg2hw_ie0_mreg_t [161:0] ie0; // [176:15] rv_plic_reg2hw_threshold0_reg_t threshold0; // [14:13] rv_plic_reg2hw_cc0_reg_t cc0; // [12:3] rv_plic_reg2hw_msip0_reg_t msip0; // [2:2] @@ -877,7 +872,7 @@ package rv_plic_reg_pkg; // HW -> register type typedef struct packed { - rv_plic_hw2reg_ip_mreg_t [162:0] ip; // [333:8] + rv_plic_hw2reg_ip_mreg_t [161:0] ip; // [331:8] rv_plic_hw2reg_cc0_reg_t cc0; // [7:0] } rv_plic_hw2reg_t; @@ -1044,7 +1039,6 @@ package rv_plic_reg_pkg; parameter logic [BlockAw-1:0] RV_PLIC_PRIO159_OFFSET = 27'h 27c; parameter logic [BlockAw-1:0] RV_PLIC_PRIO160_OFFSET = 27'h 280; parameter logic [BlockAw-1:0] RV_PLIC_PRIO161_OFFSET = 27'h 284; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO162_OFFSET = 27'h 288; parameter logic [BlockAw-1:0] RV_PLIC_IP_0_OFFSET = 27'h 1000; parameter logic [BlockAw-1:0] RV_PLIC_IP_1_OFFSET = 27'h 1004; parameter logic [BlockAw-1:0] RV_PLIC_IP_2_OFFSET = 27'h 1008; @@ -1230,7 +1224,6 @@ package rv_plic_reg_pkg; RV_PLIC_PRIO159, RV_PLIC_PRIO160, RV_PLIC_PRIO161, - RV_PLIC_PRIO162, RV_PLIC_IP_0, RV_PLIC_IP_1, RV_PLIC_IP_2, @@ -1250,7 +1243,7 @@ package rv_plic_reg_pkg; } rv_plic_id_e; // Register width information to check illegal writes - parameter logic [3:0] RV_PLIC_PERMIT [179] = '{ + parameter logic [3:0] RV_PLIC_PERMIT [178] = '{ 4'b 0001, // index[ 0] RV_PLIC_PRIO0 4'b 0001, // index[ 1] RV_PLIC_PRIO1 4'b 0001, // index[ 2] RV_PLIC_PRIO2 @@ -1413,23 +1406,22 @@ package rv_plic_reg_pkg; 4'b 0001, // index[159] RV_PLIC_PRIO159 4'b 0001, // index[160] RV_PLIC_PRIO160 4'b 0001, // index[161] RV_PLIC_PRIO161 - 4'b 0001, // index[162] RV_PLIC_PRIO162 - 4'b 1111, // index[163] RV_PLIC_IP_0 - 4'b 1111, // index[164] RV_PLIC_IP_1 - 4'b 1111, // index[165] RV_PLIC_IP_2 - 4'b 1111, // index[166] RV_PLIC_IP_3 - 4'b 1111, // index[167] RV_PLIC_IP_4 - 4'b 0001, // index[168] RV_PLIC_IP_5 - 4'b 1111, // index[169] RV_PLIC_IE0_0 - 4'b 1111, // index[170] RV_PLIC_IE0_1 - 4'b 1111, // index[171] RV_PLIC_IE0_2 - 4'b 1111, // index[172] RV_PLIC_IE0_3 - 4'b 1111, // index[173] RV_PLIC_IE0_4 - 4'b 0001, // index[174] RV_PLIC_IE0_5 - 4'b 0001, // index[175] RV_PLIC_THRESHOLD0 - 4'b 0001, // index[176] RV_PLIC_CC0 - 4'b 0001, // index[177] RV_PLIC_MSIP0 - 4'b 0001 // index[178] RV_PLIC_ALERT_TEST + 4'b 1111, // index[162] RV_PLIC_IP_0 + 4'b 1111, // index[163] RV_PLIC_IP_1 + 4'b 1111, // index[164] RV_PLIC_IP_2 + 4'b 1111, // index[165] RV_PLIC_IP_3 + 4'b 1111, // index[166] RV_PLIC_IP_4 + 4'b 0001, // index[167] RV_PLIC_IP_5 + 4'b 1111, // index[168] RV_PLIC_IE0_0 + 4'b 1111, // index[169] RV_PLIC_IE0_1 + 4'b 1111, // index[170] RV_PLIC_IE0_2 + 4'b 1111, // index[171] RV_PLIC_IE0_3 + 4'b 1111, // index[172] RV_PLIC_IE0_4 + 4'b 0001, // index[173] RV_PLIC_IE0_5 + 4'b 0001, // index[174] RV_PLIC_THRESHOLD0 + 4'b 0001, // index[175] RV_PLIC_CC0 + 4'b 0001, // index[176] RV_PLIC_MSIP0 + 4'b 0001 // index[177] RV_PLIC_ALERT_TEST }; endpackage diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv b/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv index 4b78435c1bd486..0c325bef7bc4d4 100644 --- a/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv +++ b/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv @@ -55,9 +55,9 @@ module rv_plic_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [178:0] reg_we_check; + logic [177:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(179) + .OneHotWidth(178) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -610,9 +610,6 @@ module rv_plic_reg_top ( logic prio161_we; logic [1:0] prio161_qs; logic [1:0] prio161_wd; - logic prio162_we; - logic [1:0] prio162_qs; - logic [1:0] prio162_wd; logic ip_0_p_0_qs; logic ip_0_p_1_qs; logic ip_0_p_2_qs; @@ -775,7 +772,6 @@ module rv_plic_reg_top ( logic ip_4_p_159_qs; logic ip_5_p_160_qs; logic ip_5_p_161_qs; - logic ip_5_p_162_qs; logic ie0_0_we; logic ie0_0_e_0_qs; logic ie0_0_e_0_wd; @@ -1106,8 +1102,6 @@ module rv_plic_reg_top ( logic ie0_5_e_160_wd; logic ie0_5_e_161_qs; logic ie0_5_e_161_wd; - logic ie0_5_e_162_qs; - logic ie0_5_e_162_wd; logic threshold0_we; logic [1:0] threshold0_qs; logic [1:0] threshold0_wd; @@ -5658,34 +5652,6 @@ module rv_plic_reg_top ( ); - // R[prio162]: V(False) - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_prio162 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (prio162_we), - .wd (prio162_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.prio162.q), - .ds (), - - // to register interface (read) - .qs (prio162_qs) - ); - - // Subregister 0 of Multireg ip // R[ip_0]: V(False) // F[p_0]: 0:0 @@ -10077,33 +10043,6 @@ module rv_plic_reg_top ( .qs (ip_5_p_161_qs) ); - // F[p_162]: 2:2 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_ip_5_p_162 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.ip[162].de), - .d (hw2reg.ip[162].d), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (ip_5_p_162_qs) - ); - // Subregister 0 of Multireg ie0 // R[ie0_0]: V(False) @@ -14496,33 +14435,6 @@ module rv_plic_reg_top ( .qs (ie0_5_e_161_qs) ); - // F[e_162]: 2:2 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_ie0_5_e_162 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (ie0_5_we), - .wd (ie0_5_e_162_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.ie0[162].q), - .ds (), - - // to register interface (read) - .qs (ie0_5_e_162_qs) - ); - // R[threshold0]: V(False) prim_subreg #( @@ -14621,7 +14533,7 @@ module rv_plic_reg_top ( - logic [178:0] addr_hit; + logic [177:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == RV_PLIC_PRIO0_OFFSET); @@ -14786,23 +14698,22 @@ module rv_plic_reg_top ( addr_hit[159] = (reg_addr == RV_PLIC_PRIO159_OFFSET); addr_hit[160] = (reg_addr == RV_PLIC_PRIO160_OFFSET); addr_hit[161] = (reg_addr == RV_PLIC_PRIO161_OFFSET); - addr_hit[162] = (reg_addr == RV_PLIC_PRIO162_OFFSET); - addr_hit[163] = (reg_addr == RV_PLIC_IP_0_OFFSET); - addr_hit[164] = (reg_addr == RV_PLIC_IP_1_OFFSET); - addr_hit[165] = (reg_addr == RV_PLIC_IP_2_OFFSET); - addr_hit[166] = (reg_addr == RV_PLIC_IP_3_OFFSET); - addr_hit[167] = (reg_addr == RV_PLIC_IP_4_OFFSET); - addr_hit[168] = (reg_addr == RV_PLIC_IP_5_OFFSET); - addr_hit[169] = (reg_addr == RV_PLIC_IE0_0_OFFSET); - addr_hit[170] = (reg_addr == RV_PLIC_IE0_1_OFFSET); - addr_hit[171] = (reg_addr == RV_PLIC_IE0_2_OFFSET); - addr_hit[172] = (reg_addr == RV_PLIC_IE0_3_OFFSET); - addr_hit[173] = (reg_addr == RV_PLIC_IE0_4_OFFSET); - addr_hit[174] = (reg_addr == RV_PLIC_IE0_5_OFFSET); - addr_hit[175] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET); - addr_hit[176] = (reg_addr == RV_PLIC_CC0_OFFSET); - addr_hit[177] = (reg_addr == RV_PLIC_MSIP0_OFFSET); - addr_hit[178] = (reg_addr == RV_PLIC_ALERT_TEST_OFFSET); + addr_hit[162] = (reg_addr == RV_PLIC_IP_0_OFFSET); + addr_hit[163] = (reg_addr == RV_PLIC_IP_1_OFFSET); + addr_hit[164] = (reg_addr == RV_PLIC_IP_2_OFFSET); + addr_hit[165] = (reg_addr == RV_PLIC_IP_3_OFFSET); + addr_hit[166] = (reg_addr == RV_PLIC_IP_4_OFFSET); + addr_hit[167] = (reg_addr == RV_PLIC_IP_5_OFFSET); + addr_hit[168] = (reg_addr == RV_PLIC_IE0_0_OFFSET); + addr_hit[169] = (reg_addr == RV_PLIC_IE0_1_OFFSET); + addr_hit[170] = (reg_addr == RV_PLIC_IE0_2_OFFSET); + addr_hit[171] = (reg_addr == RV_PLIC_IE0_3_OFFSET); + addr_hit[172] = (reg_addr == RV_PLIC_IE0_4_OFFSET); + addr_hit[173] = (reg_addr == RV_PLIC_IE0_5_OFFSET); + addr_hit[174] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET); + addr_hit[175] = (reg_addr == RV_PLIC_CC0_OFFSET); + addr_hit[176] = (reg_addr == RV_PLIC_MSIP0_OFFSET); + addr_hit[177] = (reg_addr == RV_PLIC_ALERT_TEST_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -14987,8 +14898,7 @@ module rv_plic_reg_top ( (addr_hit[174] & (|(RV_PLIC_PERMIT[174] & ~reg_be))) | (addr_hit[175] & (|(RV_PLIC_PERMIT[175] & ~reg_be))) | (addr_hit[176] & (|(RV_PLIC_PERMIT[176] & ~reg_be))) | - (addr_hit[177] & (|(RV_PLIC_PERMIT[177] & ~reg_be))) | - (addr_hit[178] & (|(RV_PLIC_PERMIT[178] & ~reg_be))))); + (addr_hit[177] & (|(RV_PLIC_PERMIT[177] & ~reg_be))))); end // Generate write-enables @@ -15478,10 +15388,7 @@ module rv_plic_reg_top ( assign prio161_we = addr_hit[161] & reg_we & !reg_error; assign prio161_wd = reg_wdata[1:0]; - assign prio162_we = addr_hit[162] & reg_we & !reg_error; - - assign prio162_wd = reg_wdata[1:0]; - assign ie0_0_we = addr_hit[169] & reg_we & !reg_error; + assign ie0_0_we = addr_hit[168] & reg_we & !reg_error; assign ie0_0_e_0_wd = reg_wdata[0]; @@ -15546,7 +15453,7 @@ module rv_plic_reg_top ( assign ie0_0_e_30_wd = reg_wdata[30]; assign ie0_0_e_31_wd = reg_wdata[31]; - assign ie0_1_we = addr_hit[170] & reg_we & !reg_error; + assign ie0_1_we = addr_hit[169] & reg_we & !reg_error; assign ie0_1_e_32_wd = reg_wdata[0]; @@ -15611,7 +15518,7 @@ module rv_plic_reg_top ( assign ie0_1_e_62_wd = reg_wdata[30]; assign ie0_1_e_63_wd = reg_wdata[31]; - assign ie0_2_we = addr_hit[171] & reg_we & !reg_error; + assign ie0_2_we = addr_hit[170] & reg_we & !reg_error; assign ie0_2_e_64_wd = reg_wdata[0]; @@ -15676,7 +15583,7 @@ module rv_plic_reg_top ( assign ie0_2_e_94_wd = reg_wdata[30]; assign ie0_2_e_95_wd = reg_wdata[31]; - assign ie0_3_we = addr_hit[172] & reg_we & !reg_error; + assign ie0_3_we = addr_hit[171] & reg_we & !reg_error; assign ie0_3_e_96_wd = reg_wdata[0]; @@ -15741,7 +15648,7 @@ module rv_plic_reg_top ( assign ie0_3_e_126_wd = reg_wdata[30]; assign ie0_3_e_127_wd = reg_wdata[31]; - assign ie0_4_we = addr_hit[173] & reg_we & !reg_error; + assign ie0_4_we = addr_hit[172] & reg_we & !reg_error; assign ie0_4_e_128_wd = reg_wdata[0]; @@ -15806,24 +15713,22 @@ module rv_plic_reg_top ( assign ie0_4_e_158_wd = reg_wdata[30]; assign ie0_4_e_159_wd = reg_wdata[31]; - assign ie0_5_we = addr_hit[174] & reg_we & !reg_error; + assign ie0_5_we = addr_hit[173] & reg_we & !reg_error; assign ie0_5_e_160_wd = reg_wdata[0]; assign ie0_5_e_161_wd = reg_wdata[1]; - - assign ie0_5_e_162_wd = reg_wdata[2]; - assign threshold0_we = addr_hit[175] & reg_we & !reg_error; + assign threshold0_we = addr_hit[174] & reg_we & !reg_error; assign threshold0_wd = reg_wdata[1:0]; - assign cc0_re = addr_hit[176] & reg_re & !reg_error; - assign cc0_we = addr_hit[176] & reg_we & !reg_error; + assign cc0_re = addr_hit[175] & reg_re & !reg_error; + assign cc0_we = addr_hit[175] & reg_we & !reg_error; assign cc0_wd = reg_wdata[7:0]; - assign msip0_we = addr_hit[177] & reg_we & !reg_error; + assign msip0_we = addr_hit[176] & reg_we & !reg_error; assign msip0_wd = reg_wdata[0]; - assign alert_test_we = addr_hit[178] & reg_we & !reg_error; + assign alert_test_we = addr_hit[177] & reg_we & !reg_error; assign alert_test_wd = reg_wdata[0]; @@ -15992,23 +15897,22 @@ module rv_plic_reg_top ( reg_we_check[159] = prio159_we; reg_we_check[160] = prio160_we; reg_we_check[161] = prio161_we; - reg_we_check[162] = prio162_we; + reg_we_check[162] = 1'b0; reg_we_check[163] = 1'b0; reg_we_check[164] = 1'b0; reg_we_check[165] = 1'b0; reg_we_check[166] = 1'b0; reg_we_check[167] = 1'b0; - reg_we_check[168] = 1'b0; - reg_we_check[169] = ie0_0_we; - reg_we_check[170] = ie0_1_we; - reg_we_check[171] = ie0_2_we; - reg_we_check[172] = ie0_3_we; - reg_we_check[173] = ie0_4_we; - reg_we_check[174] = ie0_5_we; - reg_we_check[175] = threshold0_we; - reg_we_check[176] = cc0_we; - reg_we_check[177] = msip0_we; - reg_we_check[178] = alert_test_we; + reg_we_check[168] = ie0_0_we; + reg_we_check[169] = ie0_1_we; + reg_we_check[170] = ie0_2_we; + reg_we_check[171] = ie0_3_we; + reg_we_check[172] = ie0_4_we; + reg_we_check[173] = ie0_5_we; + reg_we_check[174] = threshold0_we; + reg_we_check[175] = cc0_we; + reg_we_check[176] = msip0_we; + reg_we_check[177] = alert_test_we; end // Read data return @@ -16664,10 +16568,6 @@ module rv_plic_reg_top ( end addr_hit[162]: begin - reg_rdata_next[1:0] = prio162_qs; - end - - addr_hit[163]: begin reg_rdata_next[0] = ip_0_p_0_qs; reg_rdata_next[1] = ip_0_p_1_qs; reg_rdata_next[2] = ip_0_p_2_qs; @@ -16702,7 +16602,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_0_p_31_qs; end - addr_hit[164]: begin + addr_hit[163]: begin reg_rdata_next[0] = ip_1_p_32_qs; reg_rdata_next[1] = ip_1_p_33_qs; reg_rdata_next[2] = ip_1_p_34_qs; @@ -16737,7 +16637,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_1_p_63_qs; end - addr_hit[165]: begin + addr_hit[164]: begin reg_rdata_next[0] = ip_2_p_64_qs; reg_rdata_next[1] = ip_2_p_65_qs; reg_rdata_next[2] = ip_2_p_66_qs; @@ -16772,7 +16672,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_2_p_95_qs; end - addr_hit[166]: begin + addr_hit[165]: begin reg_rdata_next[0] = ip_3_p_96_qs; reg_rdata_next[1] = ip_3_p_97_qs; reg_rdata_next[2] = ip_3_p_98_qs; @@ -16807,7 +16707,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_3_p_127_qs; end - addr_hit[167]: begin + addr_hit[166]: begin reg_rdata_next[0] = ip_4_p_128_qs; reg_rdata_next[1] = ip_4_p_129_qs; reg_rdata_next[2] = ip_4_p_130_qs; @@ -16842,13 +16742,12 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_4_p_159_qs; end - addr_hit[168]: begin + addr_hit[167]: begin reg_rdata_next[0] = ip_5_p_160_qs; reg_rdata_next[1] = ip_5_p_161_qs; - reg_rdata_next[2] = ip_5_p_162_qs; end - addr_hit[169]: begin + addr_hit[168]: begin reg_rdata_next[0] = ie0_0_e_0_qs; reg_rdata_next[1] = ie0_0_e_1_qs; reg_rdata_next[2] = ie0_0_e_2_qs; @@ -16883,7 +16782,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_0_e_31_qs; end - addr_hit[170]: begin + addr_hit[169]: begin reg_rdata_next[0] = ie0_1_e_32_qs; reg_rdata_next[1] = ie0_1_e_33_qs; reg_rdata_next[2] = ie0_1_e_34_qs; @@ -16918,7 +16817,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_1_e_63_qs; end - addr_hit[171]: begin + addr_hit[170]: begin reg_rdata_next[0] = ie0_2_e_64_qs; reg_rdata_next[1] = ie0_2_e_65_qs; reg_rdata_next[2] = ie0_2_e_66_qs; @@ -16953,7 +16852,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_2_e_95_qs; end - addr_hit[172]: begin + addr_hit[171]: begin reg_rdata_next[0] = ie0_3_e_96_qs; reg_rdata_next[1] = ie0_3_e_97_qs; reg_rdata_next[2] = ie0_3_e_98_qs; @@ -16988,7 +16887,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_3_e_127_qs; end - addr_hit[173]: begin + addr_hit[172]: begin reg_rdata_next[0] = ie0_4_e_128_qs; reg_rdata_next[1] = ie0_4_e_129_qs; reg_rdata_next[2] = ie0_4_e_130_qs; @@ -17023,25 +16922,24 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_4_e_159_qs; end - addr_hit[174]: begin + addr_hit[173]: begin reg_rdata_next[0] = ie0_5_e_160_qs; reg_rdata_next[1] = ie0_5_e_161_qs; - reg_rdata_next[2] = ie0_5_e_162_qs; end - addr_hit[175]: begin + addr_hit[174]: begin reg_rdata_next[1:0] = threshold0_qs; end - addr_hit[176]: begin + addr_hit[175]: begin reg_rdata_next[7:0] = cc0_qs; end - addr_hit[177]: begin + addr_hit[176]: begin reg_rdata_next[0] = msip0_qs; end - addr_hit[178]: begin + addr_hit[177]: begin reg_rdata_next[0] = '0; end diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv index c974cfd4e15b13..29dac55ba9f34e 100644 --- a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv @@ -344,7 +344,7 @@ module top_darjeeling #( // rv_core_ibex - logic [162:0] intr_vector; + logic [161:0] intr_vector; // Interrupt source list logic intr_uart0_tx_watermark; logic intr_uart0_rx_watermark; @@ -415,7 +415,6 @@ module top_darjeeling #( logic intr_edn1_edn_fatal_err; logic intr_dma_dma_done; logic intr_dma_dma_error; - logic intr_dma_dma_memory_buffer_limit; logic intr_mbx0_mbx_ready; logic intr_mbx0_mbx_abort; logic intr_mbx0_mbx_error; @@ -2105,9 +2104,8 @@ module top_darjeeling #( ) u_dma ( // Interrupt - .intr_dma_done_o (intr_dma_dma_done), - .intr_dma_error_o (intr_dma_dma_error), - .intr_dma_memory_buffer_limit_o (intr_dma_dma_memory_buffer_limit), + .intr_dma_done_o (intr_dma_dma_done), + .intr_dma_error_o (intr_dma_dma_error), // [74]: fatal_fault .alert_tx_o ( alert_tx[74:74] ), .alert_rx_i ( alert_rx[74:74] ), @@ -2495,37 +2493,36 @@ module top_darjeeling #( ); // interrupt assignments assign intr_vector = { - intr_mbx_pcie1_mbx_error, // IDs [162 +: 1] - intr_mbx_pcie1_mbx_abort, // IDs [161 +: 1] - intr_mbx_pcie1_mbx_ready, // IDs [160 +: 1] - intr_mbx_pcie0_mbx_error, // IDs [159 +: 1] - intr_mbx_pcie0_mbx_abort, // IDs [158 +: 1] - intr_mbx_pcie0_mbx_ready, // IDs [157 +: 1] - intr_mbx_jtag_mbx_error, // IDs [156 +: 1] - intr_mbx_jtag_mbx_abort, // IDs [155 +: 1] - intr_mbx_jtag_mbx_ready, // IDs [154 +: 1] - intr_mbx6_mbx_error, // IDs [153 +: 1] - intr_mbx6_mbx_abort, // IDs [152 +: 1] - intr_mbx6_mbx_ready, // IDs [151 +: 1] - intr_mbx5_mbx_error, // IDs [150 +: 1] - intr_mbx5_mbx_abort, // IDs [149 +: 1] - intr_mbx5_mbx_ready, // IDs [148 +: 1] - intr_mbx4_mbx_error, // IDs [147 +: 1] - intr_mbx4_mbx_abort, // IDs [146 +: 1] - intr_mbx4_mbx_ready, // IDs [145 +: 1] - intr_mbx3_mbx_error, // IDs [144 +: 1] - intr_mbx3_mbx_abort, // IDs [143 +: 1] - intr_mbx3_mbx_ready, // IDs [142 +: 1] - intr_mbx2_mbx_error, // IDs [141 +: 1] - intr_mbx2_mbx_abort, // IDs [140 +: 1] - intr_mbx2_mbx_ready, // IDs [139 +: 1] - intr_mbx1_mbx_error, // IDs [138 +: 1] - intr_mbx1_mbx_abort, // IDs [137 +: 1] - intr_mbx1_mbx_ready, // IDs [136 +: 1] - intr_mbx0_mbx_error, // IDs [135 +: 1] - intr_mbx0_mbx_abort, // IDs [134 +: 1] - intr_mbx0_mbx_ready, // IDs [133 +: 1] - intr_dma_dma_memory_buffer_limit, // IDs [132 +: 1] + intr_mbx_pcie1_mbx_error, // IDs [161 +: 1] + intr_mbx_pcie1_mbx_abort, // IDs [160 +: 1] + intr_mbx_pcie1_mbx_ready, // IDs [159 +: 1] + intr_mbx_pcie0_mbx_error, // IDs [158 +: 1] + intr_mbx_pcie0_mbx_abort, // IDs [157 +: 1] + intr_mbx_pcie0_mbx_ready, // IDs [156 +: 1] + intr_mbx_jtag_mbx_error, // IDs [155 +: 1] + intr_mbx_jtag_mbx_abort, // IDs [154 +: 1] + intr_mbx_jtag_mbx_ready, // IDs [153 +: 1] + intr_mbx6_mbx_error, // IDs [152 +: 1] + intr_mbx6_mbx_abort, // IDs [151 +: 1] + intr_mbx6_mbx_ready, // IDs [150 +: 1] + intr_mbx5_mbx_error, // IDs [149 +: 1] + intr_mbx5_mbx_abort, // IDs [148 +: 1] + intr_mbx5_mbx_ready, // IDs [147 +: 1] + intr_mbx4_mbx_error, // IDs [146 +: 1] + intr_mbx4_mbx_abort, // IDs [145 +: 1] + intr_mbx4_mbx_ready, // IDs [144 +: 1] + intr_mbx3_mbx_error, // IDs [143 +: 1] + intr_mbx3_mbx_abort, // IDs [142 +: 1] + intr_mbx3_mbx_ready, // IDs [141 +: 1] + intr_mbx2_mbx_error, // IDs [140 +: 1] + intr_mbx2_mbx_abort, // IDs [139 +: 1] + intr_mbx2_mbx_ready, // IDs [138 +: 1] + intr_mbx1_mbx_error, // IDs [137 +: 1] + intr_mbx1_mbx_abort, // IDs [136 +: 1] + intr_mbx1_mbx_ready, // IDs [135 +: 1] + intr_mbx0_mbx_error, // IDs [134 +: 1] + intr_mbx0_mbx_abort, // IDs [133 +: 1] + intr_mbx0_mbx_ready, // IDs [132 +: 1] intr_dma_dma_error, // IDs [131 +: 1] intr_dma_dma_done, // IDs [130 +: 1] intr_edn1_edn_fatal_err, // IDs [129 +: 1] diff --git a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs index 2798bf4982658f..d82eaefe392de3 100644 --- a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs +++ b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs @@ -1119,68 +1119,66 @@ pub enum TopDarjeelingPlicIrqId { DmaDmaDone = 130, /// dma_dma_error DmaDmaError = 131, - /// dma_dma_memory_buffer_limit - DmaDmaMemoryBufferLimit = 132, /// mbx0_mbx_ready - Mbx0MbxReady = 133, + Mbx0MbxReady = 132, /// mbx0_mbx_abort - Mbx0MbxAbort = 134, + Mbx0MbxAbort = 133, /// mbx0_mbx_error - Mbx0MbxError = 135, + Mbx0MbxError = 134, /// mbx1_mbx_ready - Mbx1MbxReady = 136, + Mbx1MbxReady = 135, /// mbx1_mbx_abort - Mbx1MbxAbort = 137, + Mbx1MbxAbort = 136, /// mbx1_mbx_error - Mbx1MbxError = 138, + Mbx1MbxError = 137, /// mbx2_mbx_ready - Mbx2MbxReady = 139, + Mbx2MbxReady = 138, /// mbx2_mbx_abort - Mbx2MbxAbort = 140, + Mbx2MbxAbort = 139, /// mbx2_mbx_error - Mbx2MbxError = 141, + Mbx2MbxError = 140, /// mbx3_mbx_ready - Mbx3MbxReady = 142, + Mbx3MbxReady = 141, /// mbx3_mbx_abort - Mbx3MbxAbort = 143, + Mbx3MbxAbort = 142, /// mbx3_mbx_error - Mbx3MbxError = 144, + Mbx3MbxError = 143, /// mbx4_mbx_ready - Mbx4MbxReady = 145, + Mbx4MbxReady = 144, /// mbx4_mbx_abort - Mbx4MbxAbort = 146, + Mbx4MbxAbort = 145, /// mbx4_mbx_error - Mbx4MbxError = 147, + Mbx4MbxError = 146, /// mbx5_mbx_ready - Mbx5MbxReady = 148, + Mbx5MbxReady = 147, /// mbx5_mbx_abort - Mbx5MbxAbort = 149, + Mbx5MbxAbort = 148, /// mbx5_mbx_error - Mbx5MbxError = 150, + Mbx5MbxError = 149, /// mbx6_mbx_ready - Mbx6MbxReady = 151, + Mbx6MbxReady = 150, /// mbx6_mbx_abort - Mbx6MbxAbort = 152, + Mbx6MbxAbort = 151, /// mbx6_mbx_error - Mbx6MbxError = 153, + Mbx6MbxError = 152, /// mbx_jtag_mbx_ready - MbxJtagMbxReady = 154, + MbxJtagMbxReady = 153, /// mbx_jtag_mbx_abort - MbxJtagMbxAbort = 155, + MbxJtagMbxAbort = 154, /// mbx_jtag_mbx_error - MbxJtagMbxError = 156, + MbxJtagMbxError = 155, /// mbx_pcie0_mbx_ready - MbxPcie0MbxReady = 157, + MbxPcie0MbxReady = 156, /// mbx_pcie0_mbx_abort - MbxPcie0MbxAbort = 158, + MbxPcie0MbxAbort = 157, /// mbx_pcie0_mbx_error - MbxPcie0MbxError = 159, + MbxPcie0MbxError = 158, /// mbx_pcie1_mbx_ready - MbxPcie1MbxReady = 160, + MbxPcie1MbxReady = 159, /// mbx_pcie1_mbx_abort - MbxPcie1MbxAbort = 161, + MbxPcie1MbxAbort = 160, /// mbx_pcie1_mbx_error - MbxPcie1MbxError = 162, + MbxPcie1MbxError = 161, } impl TryFrom for TopDarjeelingPlicIrqId { @@ -1319,37 +1317,36 @@ impl TryFrom for TopDarjeelingPlicIrqId { 129 => Ok(Self::Edn1EdnFatalErr), 130 => Ok(Self::DmaDmaDone), 131 => Ok(Self::DmaDmaError), - 132 => Ok(Self::DmaDmaMemoryBufferLimit), - 133 => Ok(Self::Mbx0MbxReady), - 134 => Ok(Self::Mbx0MbxAbort), - 135 => Ok(Self::Mbx0MbxError), - 136 => Ok(Self::Mbx1MbxReady), - 137 => Ok(Self::Mbx1MbxAbort), - 138 => Ok(Self::Mbx1MbxError), - 139 => Ok(Self::Mbx2MbxReady), - 140 => Ok(Self::Mbx2MbxAbort), - 141 => Ok(Self::Mbx2MbxError), - 142 => Ok(Self::Mbx3MbxReady), - 143 => Ok(Self::Mbx3MbxAbort), - 144 => Ok(Self::Mbx3MbxError), - 145 => Ok(Self::Mbx4MbxReady), - 146 => Ok(Self::Mbx4MbxAbort), - 147 => Ok(Self::Mbx4MbxError), - 148 => Ok(Self::Mbx5MbxReady), - 149 => Ok(Self::Mbx5MbxAbort), - 150 => Ok(Self::Mbx5MbxError), - 151 => Ok(Self::Mbx6MbxReady), - 152 => Ok(Self::Mbx6MbxAbort), - 153 => Ok(Self::Mbx6MbxError), - 154 => Ok(Self::MbxJtagMbxReady), - 155 => Ok(Self::MbxJtagMbxAbort), - 156 => Ok(Self::MbxJtagMbxError), - 157 => Ok(Self::MbxPcie0MbxReady), - 158 => Ok(Self::MbxPcie0MbxAbort), - 159 => Ok(Self::MbxPcie0MbxError), - 160 => Ok(Self::MbxPcie1MbxReady), - 161 => Ok(Self::MbxPcie1MbxAbort), - 162 => Ok(Self::MbxPcie1MbxError), + 132 => Ok(Self::Mbx0MbxReady), + 133 => Ok(Self::Mbx0MbxAbort), + 134 => Ok(Self::Mbx0MbxError), + 135 => Ok(Self::Mbx1MbxReady), + 136 => Ok(Self::Mbx1MbxAbort), + 137 => Ok(Self::Mbx1MbxError), + 138 => Ok(Self::Mbx2MbxReady), + 139 => Ok(Self::Mbx2MbxAbort), + 140 => Ok(Self::Mbx2MbxError), + 141 => Ok(Self::Mbx3MbxReady), + 142 => Ok(Self::Mbx3MbxAbort), + 143 => Ok(Self::Mbx3MbxError), + 144 => Ok(Self::Mbx4MbxReady), + 145 => Ok(Self::Mbx4MbxAbort), + 146 => Ok(Self::Mbx4MbxError), + 147 => Ok(Self::Mbx5MbxReady), + 148 => Ok(Self::Mbx5MbxAbort), + 149 => Ok(Self::Mbx5MbxError), + 150 => Ok(Self::Mbx6MbxReady), + 151 => Ok(Self::Mbx6MbxAbort), + 152 => Ok(Self::Mbx6MbxError), + 153 => Ok(Self::MbxJtagMbxReady), + 154 => Ok(Self::MbxJtagMbxAbort), + 155 => Ok(Self::MbxJtagMbxError), + 156 => Ok(Self::MbxPcie0MbxReady), + 157 => Ok(Self::MbxPcie0MbxAbort), + 158 => Ok(Self::MbxPcie0MbxError), + 159 => Ok(Self::MbxPcie1MbxReady), + 160 => Ok(Self::MbxPcie1MbxAbort), + 161 => Ok(Self::MbxPcie1MbxError), _ => Err(val), } } @@ -1775,7 +1772,7 @@ impl TryFrom for TopDarjeelingAlertId { /// /// This array is a mapping from `TopDarjeelingPlicIrqId` to /// `TopDarjeelingPlicPeripheral`. -pub const TOP_DARJEELING_PLIC_INTERRUPT_FOR_PERIPHERAL: [TopDarjeelingPlicPeripheral; 163] = [ +pub const TOP_DARJEELING_PLIC_INTERRUPT_FOR_PERIPHERAL: [TopDarjeelingPlicPeripheral; 162] = [ // None -> TopDarjeelingPlicPeripheral::Unknown TopDarjeelingPlicPeripheral::Unknown, // Uart0TxWatermark -> TopDarjeelingPlicPeripheral::Uart0 @@ -2040,8 +2037,6 @@ pub const TOP_DARJEELING_PLIC_INTERRUPT_FOR_PERIPHERAL: [TopDarjeelingPlicPeriph TopDarjeelingPlicPeripheral::Dma, // DmaDmaError -> TopDarjeelingPlicPeripheral::Dma TopDarjeelingPlicPeripheral::Dma, - // DmaDmaMemoryBufferLimit -> TopDarjeelingPlicPeripheral::Dma - TopDarjeelingPlicPeripheral::Dma, // Mbx0MbxReady -> TopDarjeelingPlicPeripheral::Mbx0 TopDarjeelingPlicPeripheral::Mbx0, // Mbx0MbxAbort -> TopDarjeelingPlicPeripheral::Mbx0 diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling.c b/hw/top_darjeeling/sw/autogen/top_darjeeling.c index 4f8608619a17b6..46790ffbf793d2 100644 --- a/hw/top_darjeeling/sw/autogen/top_darjeeling.c +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling.c @@ -11,7 +11,7 @@ * `top_darjeeling_plic_peripheral_t`. */ const top_darjeeling_plic_peripheral_t - top_darjeeling_plic_interrupt_for_peripheral[163] = { + top_darjeeling_plic_interrupt_for_peripheral[162] = { [kTopDarjeelingPlicIrqIdNone] = kTopDarjeelingPlicPeripheralUnknown, [kTopDarjeelingPlicIrqIdUart0TxWatermark] = kTopDarjeelingPlicPeripheralUart0, [kTopDarjeelingPlicIrqIdUart0RxWatermark] = kTopDarjeelingPlicPeripheralUart0, @@ -144,7 +144,6 @@ const top_darjeeling_plic_peripheral_t [kTopDarjeelingPlicIrqIdEdn1EdnFatalErr] = kTopDarjeelingPlicPeripheralEdn1, [kTopDarjeelingPlicIrqIdDmaDmaDone] = kTopDarjeelingPlicPeripheralDma, [kTopDarjeelingPlicIrqIdDmaDmaError] = kTopDarjeelingPlicPeripheralDma, - [kTopDarjeelingPlicIrqIdDmaDmaMemoryBufferLimit] = kTopDarjeelingPlicPeripheralDma, [kTopDarjeelingPlicIrqIdMbx0MbxReady] = kTopDarjeelingPlicPeripheralMbx0, [kTopDarjeelingPlicIrqIdMbx0MbxAbort] = kTopDarjeelingPlicPeripheralMbx0, [kTopDarjeelingPlicIrqIdMbx0MbxError] = kTopDarjeelingPlicPeripheralMbx0, diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling.h b/hw/top_darjeeling/sw/autogen/top_darjeeling.h index 391c067a9445f8..b034d5fba5ffdb 100644 --- a/hw/top_darjeeling/sw/autogen/top_darjeeling.h +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling.h @@ -1215,38 +1215,37 @@ typedef enum top_darjeeling_plic_irq_id { kTopDarjeelingPlicIrqIdEdn1EdnFatalErr = 129, /**< edn1_edn_fatal_err */ kTopDarjeelingPlicIrqIdDmaDmaDone = 130, /**< dma_dma_done */ kTopDarjeelingPlicIrqIdDmaDmaError = 131, /**< dma_dma_error */ - kTopDarjeelingPlicIrqIdDmaDmaMemoryBufferLimit = 132, /**< dma_dma_memory_buffer_limit */ - kTopDarjeelingPlicIrqIdMbx0MbxReady = 133, /**< mbx0_mbx_ready */ - kTopDarjeelingPlicIrqIdMbx0MbxAbort = 134, /**< mbx0_mbx_abort */ - kTopDarjeelingPlicIrqIdMbx0MbxError = 135, /**< mbx0_mbx_error */ - kTopDarjeelingPlicIrqIdMbx1MbxReady = 136, /**< mbx1_mbx_ready */ - kTopDarjeelingPlicIrqIdMbx1MbxAbort = 137, /**< mbx1_mbx_abort */ - kTopDarjeelingPlicIrqIdMbx1MbxError = 138, /**< mbx1_mbx_error */ - kTopDarjeelingPlicIrqIdMbx2MbxReady = 139, /**< mbx2_mbx_ready */ - kTopDarjeelingPlicIrqIdMbx2MbxAbort = 140, /**< mbx2_mbx_abort */ - kTopDarjeelingPlicIrqIdMbx2MbxError = 141, /**< mbx2_mbx_error */ - kTopDarjeelingPlicIrqIdMbx3MbxReady = 142, /**< mbx3_mbx_ready */ - kTopDarjeelingPlicIrqIdMbx3MbxAbort = 143, /**< mbx3_mbx_abort */ - kTopDarjeelingPlicIrqIdMbx3MbxError = 144, /**< mbx3_mbx_error */ - kTopDarjeelingPlicIrqIdMbx4MbxReady = 145, /**< mbx4_mbx_ready */ - kTopDarjeelingPlicIrqIdMbx4MbxAbort = 146, /**< mbx4_mbx_abort */ - kTopDarjeelingPlicIrqIdMbx4MbxError = 147, /**< mbx4_mbx_error */ - kTopDarjeelingPlicIrqIdMbx5MbxReady = 148, /**< mbx5_mbx_ready */ - kTopDarjeelingPlicIrqIdMbx5MbxAbort = 149, /**< mbx5_mbx_abort */ - kTopDarjeelingPlicIrqIdMbx5MbxError = 150, /**< mbx5_mbx_error */ - kTopDarjeelingPlicIrqIdMbx6MbxReady = 151, /**< mbx6_mbx_ready */ - kTopDarjeelingPlicIrqIdMbx6MbxAbort = 152, /**< mbx6_mbx_abort */ - kTopDarjeelingPlicIrqIdMbx6MbxError = 153, /**< mbx6_mbx_error */ - kTopDarjeelingPlicIrqIdMbxJtagMbxReady = 154, /**< mbx_jtag_mbx_ready */ - kTopDarjeelingPlicIrqIdMbxJtagMbxAbort = 155, /**< mbx_jtag_mbx_abort */ - kTopDarjeelingPlicIrqIdMbxJtagMbxError = 156, /**< mbx_jtag_mbx_error */ - kTopDarjeelingPlicIrqIdMbxPcie0MbxReady = 157, /**< mbx_pcie0_mbx_ready */ - kTopDarjeelingPlicIrqIdMbxPcie0MbxAbort = 158, /**< mbx_pcie0_mbx_abort */ - kTopDarjeelingPlicIrqIdMbxPcie0MbxError = 159, /**< mbx_pcie0_mbx_error */ - kTopDarjeelingPlicIrqIdMbxPcie1MbxReady = 160, /**< mbx_pcie1_mbx_ready */ - kTopDarjeelingPlicIrqIdMbxPcie1MbxAbort = 161, /**< mbx_pcie1_mbx_abort */ - kTopDarjeelingPlicIrqIdMbxPcie1MbxError = 162, /**< mbx_pcie1_mbx_error */ - kTopDarjeelingPlicIrqIdLast = 162, /**< \internal The Last Valid Interrupt ID. */ + kTopDarjeelingPlicIrqIdMbx0MbxReady = 132, /**< mbx0_mbx_ready */ + kTopDarjeelingPlicIrqIdMbx0MbxAbort = 133, /**< mbx0_mbx_abort */ + kTopDarjeelingPlicIrqIdMbx0MbxError = 134, /**< mbx0_mbx_error */ + kTopDarjeelingPlicIrqIdMbx1MbxReady = 135, /**< mbx1_mbx_ready */ + kTopDarjeelingPlicIrqIdMbx1MbxAbort = 136, /**< mbx1_mbx_abort */ + kTopDarjeelingPlicIrqIdMbx1MbxError = 137, /**< mbx1_mbx_error */ + kTopDarjeelingPlicIrqIdMbx2MbxReady = 138, /**< mbx2_mbx_ready */ + kTopDarjeelingPlicIrqIdMbx2MbxAbort = 139, /**< mbx2_mbx_abort */ + kTopDarjeelingPlicIrqIdMbx2MbxError = 140, /**< mbx2_mbx_error */ + kTopDarjeelingPlicIrqIdMbx3MbxReady = 141, /**< mbx3_mbx_ready */ + kTopDarjeelingPlicIrqIdMbx3MbxAbort = 142, /**< mbx3_mbx_abort */ + kTopDarjeelingPlicIrqIdMbx3MbxError = 143, /**< mbx3_mbx_error */ + kTopDarjeelingPlicIrqIdMbx4MbxReady = 144, /**< mbx4_mbx_ready */ + kTopDarjeelingPlicIrqIdMbx4MbxAbort = 145, /**< mbx4_mbx_abort */ + kTopDarjeelingPlicIrqIdMbx4MbxError = 146, /**< mbx4_mbx_error */ + kTopDarjeelingPlicIrqIdMbx5MbxReady = 147, /**< mbx5_mbx_ready */ + kTopDarjeelingPlicIrqIdMbx5MbxAbort = 148, /**< mbx5_mbx_abort */ + kTopDarjeelingPlicIrqIdMbx5MbxError = 149, /**< mbx5_mbx_error */ + kTopDarjeelingPlicIrqIdMbx6MbxReady = 150, /**< mbx6_mbx_ready */ + kTopDarjeelingPlicIrqIdMbx6MbxAbort = 151, /**< mbx6_mbx_abort */ + kTopDarjeelingPlicIrqIdMbx6MbxError = 152, /**< mbx6_mbx_error */ + kTopDarjeelingPlicIrqIdMbxJtagMbxReady = 153, /**< mbx_jtag_mbx_ready */ + kTopDarjeelingPlicIrqIdMbxJtagMbxAbort = 154, /**< mbx_jtag_mbx_abort */ + kTopDarjeelingPlicIrqIdMbxJtagMbxError = 155, /**< mbx_jtag_mbx_error */ + kTopDarjeelingPlicIrqIdMbxPcie0MbxReady = 156, /**< mbx_pcie0_mbx_ready */ + kTopDarjeelingPlicIrqIdMbxPcie0MbxAbort = 157, /**< mbx_pcie0_mbx_abort */ + kTopDarjeelingPlicIrqIdMbxPcie0MbxError = 158, /**< mbx_pcie0_mbx_error */ + kTopDarjeelingPlicIrqIdMbxPcie1MbxReady = 159, /**< mbx_pcie1_mbx_ready */ + kTopDarjeelingPlicIrqIdMbxPcie1MbxAbort = 160, /**< mbx_pcie1_mbx_abort */ + kTopDarjeelingPlicIrqIdMbxPcie1MbxError = 161, /**< mbx_pcie1_mbx_error */ + kTopDarjeelingPlicIrqIdLast = 161, /**< \internal The Last Valid Interrupt ID. */ } top_darjeeling_plic_irq_id_t; /** @@ -1256,7 +1255,7 @@ typedef enum top_darjeeling_plic_irq_id { * `top_darjeeling_plic_peripheral_t`. */ extern const top_darjeeling_plic_peripheral_t - top_darjeeling_plic_interrupt_for_peripheral[163]; + top_darjeeling_plic_interrupt_for_peripheral[162]; /** * PLIC Interrupt Target. diff --git a/sw/device/tests/autogen/top_darjeeling/plic_all_irqs_test.c b/sw/device/tests/autogen/top_darjeeling/plic_all_irqs_test.c index 8273158bbe5b8b..a37bb3b46305e8 100644 --- a/sw/device/tests/autogen/top_darjeeling/plic_all_irqs_test.c +++ b/sw/device/tests/autogen/top_darjeeling/plic_all_irqs_test.c @@ -1120,7 +1120,7 @@ static void peripheral_irqs_trigger(void) { peripheral_expected = kTopDarjeelingPlicPeripheralDma; for (dif_dma_irq_t irq = kDifDmaIrqDmaDone; - irq <= kDifDmaIrqDmaMemoryBufferLimit; ++irq) { + irq <= kDifDmaIrqDmaError; ++irq) { dma_irq_expected = irq; LOG_INFO("Triggering dma IRQ %d.", irq); CHECK_DIF_OK(dif_dma_irq_force(&dma, irq, true));