From 88d88c948534742e06fe6d66d26f97c7568363c8 Mon Sep 17 00:00:00 2001 From: Marcelo Carvalho Faleiro de Almeida Date: Fri, 6 Dec 2024 15:28:34 +0000 Subject: [PATCH] replaced task wait_clk to wait_clks_or_rst Updates to the sequences to replace the wait_clk to wait_clks_or_rst. Signed-off-by: Marcelo Carvalho Faleiro de Almeida Removed new lines Signed-off-by: Marcelo Carvalho Faleiro de Almeida Remove new lines Just to fix the lint errors about new lines and spaces Signed-off-by: Marcelo Carvalho Faleiro de Almeida --- hw/ip/gpio/dv/env/gpio_env_cfg.sv | 3 +++ .../gpio_dout_din_regs_random_rw_vseq.sv | 15 ++++++++++++--- .../dv/env/seq_lib/gpio_intr_rand_pgm_vseq.sv | 9 ++++++--- .../env/seq_lib/gpio_rand_intr_trigger_vseq.sv | 10 +++++++--- .../dv/env/seq_lib/gpio_random_dout_din_vseq.sv | 10 ++++++++-- ...pio_random_long_reg_writes_reg_reads_vseq.sv | 9 ++++++--- hw/ip/gpio/dv/env/seq_lib/gpio_smoke_vseq.sv | 17 ++++++++++++----- 7 files changed, 54 insertions(+), 19 deletions(-) diff --git a/hw/ip/gpio/dv/env/gpio_env_cfg.sv b/hw/ip/gpio/dv/env/gpio_env_cfg.sv index c8af480a21b31..fd21e0783fa24 100644 --- a/hw/ip/gpio/dv/env/gpio_env_cfg.sv +++ b/hw/ip/gpio/dv/env/gpio_env_cfg.sv @@ -27,6 +27,9 @@ class gpio_env_cfg extends cip_base_env_cfg #( // only support 1 outstanding TL item m_tl_agent_cfg.max_outstanding_req = 1; + + // Used to allow reset operation during a stress all tests and check the CSR after that. + can_reset_with_csr_accesses = 1'b1; endfunction : initialize endclass diff --git a/hw/ip/gpio/dv/env/seq_lib/gpio_dout_din_regs_random_rw_vseq.sv b/hw/ip/gpio/dv/env/seq_lib/gpio_dout_din_regs_random_rw_vseq.sv index 2b4503cd40eb6..88482ac265ed8 100644 --- a/hw/ip/gpio/dv/env/seq_lib/gpio_dout_din_regs_random_rw_vseq.sv +++ b/hw/ip/gpio/dv/env/seq_lib/gpio_dout_din_regs_random_rw_vseq.sv @@ -22,7 +22,9 @@ class gpio_dout_din_regs_random_rw_vseq extends gpio_base_vseq; `DV_CHECK_RANDOMIZE_FATAL(this) // Insert some random delay - cfg.clk_rst_vif.wait_clks(delay); + cfg.clk_rst_vif.wait_clks_or_rst(delay); + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) return; randcase // drive new gpio data in @@ -35,7 +37,11 @@ class gpio_dout_din_regs_random_rw_vseq extends gpio_base_vseq; `DV_CHECK_STD_RANDOMIZE_FATAL(gpio_i) // drive gpio_vif after setting all output enables to 0's drive_gpio_in(gpio_i); - cfg.clk_rst_vif.wait_clks(1); + cfg.clk_rst_vif.wait_clks_or_rst(1); + + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) break; + // read data_in register csr_rd(.ptr(ral.data_in), .value(data_in)); end @@ -52,7 +58,10 @@ class gpio_dout_din_regs_random_rw_vseq extends gpio_base_vseq; 1: begin // Add single clock cycle delay to avoid update and predict at // the same time due to weak pull-up after undrive_gpio_in() - cfg.clk_rst_vif.wait_clks(1); + cfg.clk_rst_vif.wait_clks_or_rst(1); + + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) break; // DATA_IN register is RO, but writing random value to it // should have no impact on gpio functionality csr_wr(.ptr(ral.data_in), .value(csr_val)); diff --git a/hw/ip/gpio/dv/env/seq_lib/gpio_intr_rand_pgm_vseq.sv b/hw/ip/gpio/dv/env/seq_lib/gpio_intr_rand_pgm_vseq.sv index 65456d0d1903e..600010086eef9 100644 --- a/hw/ip/gpio/dv/env/seq_lib/gpio_intr_rand_pgm_vseq.sv +++ b/hw/ip/gpio/dv/env/seq_lib/gpio_intr_rand_pgm_vseq.sv @@ -24,7 +24,9 @@ class gpio_intr_rand_pgm_vseq extends gpio_base_vseq; string msg_id = {`gfn, $sformatf(" Transaction-%0d", tr_num)}; `DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay) - cfg.clk_rst_vif.wait_clks(delay); + cfg.clk_rst_vif.wait_clks_or_rst(delay); + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) return; randcase // drive new gpio data in @@ -36,7 +38,8 @@ class gpio_intr_rand_pgm_vseq extends gpio_base_vseq; `uvm_info(msg_id, "drive random value on gpio_i", UVM_HIGH) // drive gpio_vif after setting all output enables to 0's drive_gpio_in(gpio_i); - cfg.clk_rst_vif.wait_clks(1); + + cfg.clk_rst_vif.wait_clks_or_rst(1); // read data_in register csr_rd(.ptr(ral.data_in), .value(data_in)); end @@ -79,7 +82,7 @@ class gpio_intr_rand_pgm_vseq extends gpio_base_vseq; begin bit [TL_DW-1:0] reg_rd_data; `DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay) - cfg.clk_rst_vif.wait_clks(delay); + cfg.clk_rst_vif.wait_clks_or_rst(delay); // read intr_state register csr_rd(.ptr(ral.intr_state), .value(reg_rd_data)); end diff --git a/hw/ip/gpio/dv/env/seq_lib/gpio_rand_intr_trigger_vseq.sv b/hw/ip/gpio/dv/env/seq_lib/gpio_rand_intr_trigger_vseq.sv index 87dc63ab1d13b..f12449e40a6ce 100644 --- a/hw/ip/gpio/dv/env/seq_lib/gpio_rand_intr_trigger_vseq.sv +++ b/hw/ip/gpio/dv/env/seq_lib/gpio_rand_intr_trigger_vseq.sv @@ -28,7 +28,7 @@ class gpio_rand_intr_trigger_vseq extends gpio_base_vseq; string msg_id = {`gfn, $sformatf(" Transaction-%0d", tr_num)}; `DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay) - cfg.clk_rst_vif.wait_clks(delay); + cfg.clk_rst_vif.wait_clks_or_rst(delay); `uvm_info(msg_id, $sformatf("delay = %0d", delay), UVM_HIGH) // Step-1 Program interrupt registers @@ -52,7 +52,7 @@ class gpio_rand_intr_trigger_vseq extends gpio_base_vseq; cfg.gpio_vif.drive(gpio_i); `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(delay_before_gpio_change, delay_before_gpio_change inside {[1:5]};) - cfg.clk_rst_vif.wait_clks(delay_before_gpio_change); + cfg.clk_rst_vif.wait_clks_or_rst(delay_before_gpio_change); end gpio_tgl_cycle_done = 1'b1; end @@ -61,7 +61,11 @@ class gpio_rand_intr_trigger_vseq extends gpio_base_vseq; uint rd_period; bit [TL_DW-1:0] reg_rd_data; `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(rd_period, rd_period inside {[2:20]};) - cfg.clk_rst_vif.wait_clks(rd_period); + + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) break; + + cfg.clk_rst_vif.wait_clks_or_rst(rd_period); `uvm_info(msg_id, $sformatf("Reading intr_state after %0d more clock cycles", rd_period), UVM_HIGH) randcase diff --git a/hw/ip/gpio/dv/env/seq_lib/gpio_random_dout_din_vseq.sv b/hw/ip/gpio/dv/env/seq_lib/gpio_random_dout_din_vseq.sv index ec512d6ca7ca6..b6c5db5036ca1 100644 --- a/hw/ip/gpio/dv/env/seq_lib/gpio_random_dout_din_vseq.sv +++ b/hw/ip/gpio/dv/env/seq_lib/gpio_random_dout_din_vseq.sv @@ -29,7 +29,7 @@ class gpio_random_dout_din_vseq extends gpio_base_vseq; for (uint tr_num = 0; tr_num < num_trans; tr_num++) begin `DV_CHECK_RANDOMIZE_FATAL(this) - cfg.clk_rst_vif.wait_clks(delay); + cfg.clk_rst_vif.wait_clks_or_rst(delay); randcase // drive new gpio data in @@ -42,7 +42,13 @@ class gpio_random_dout_din_vseq extends gpio_base_vseq; `DV_CHECK_STD_RANDOMIZE_FATAL(gpio_i) // drive gpio_vif after setting all output enables to 0's drive_gpio_in(gpio_i); - cfg.clk_rst_vif.wait_clks(1); + + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) break; + cfg.clk_rst_vif.wait_clks_or_rst(1); + + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) break; // read data_in register csr_rd(.ptr(ral.data_in), .value(data_in)); end diff --git a/hw/ip/gpio/dv/env/seq_lib/gpio_random_long_reg_writes_reg_reads_vseq.sv b/hw/ip/gpio/dv/env/seq_lib/gpio_random_long_reg_writes_reg_reads_vseq.sv index 49bb5fb687725..f5e34c9154b56 100644 --- a/hw/ip/gpio/dv/env/seq_lib/gpio_random_long_reg_writes_reg_reads_vseq.sv +++ b/hw/ip/gpio/dv/env/seq_lib/gpio_random_long_reg_writes_reg_reads_vseq.sv @@ -23,7 +23,7 @@ class gpio_random_long_reg_writes_reg_reads_vseq extends gpio_base_vseq; // Wait for minimum 1 clock cycle initially to avoid reading of data_in // immediately as the first iteration after reset, while data_in prediction // is still being processed - cfg.clk_rst_vif.wait_clks(1); + cfg.clk_rst_vif.wait_clks_or_rst(1); for (uint tr_num = 0; tr_num < num_trans; tr_num++) begin string msg_id = {`gfn, $sformatf(" Transaction-%0d", tr_num)}; @@ -31,7 +31,10 @@ class gpio_random_long_reg_writes_reg_reads_vseq extends gpio_base_vseq; `DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay) `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(num_reg_op, num_reg_op inside {[25:50]};) - cfg.clk_rst_vif.wait_clks(delay); + cfg.clk_rst_vif.wait_clks_or_rst(delay); + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) return; + randcase // drive new gpio data in 1: begin @@ -41,7 +44,7 @@ class gpio_random_long_reg_writes_reg_reads_vseq extends gpio_base_vseq; // drive gpio_vif after setting all output enables to 0's drive_gpio_in(gpio_i); // Wait for one clock cycle for us to read data_in reg reliably - cfg.clk_rst_vif.wait_clks(1); + cfg.clk_rst_vif.wait_clks_or_rst(1); end // long reg write 1: begin diff --git a/hw/ip/gpio/dv/env/seq_lib/gpio_smoke_vseq.sv b/hw/ip/gpio/dv/env/seq_lib/gpio_smoke_vseq.sv index ca7cbefa2a544..c9f67cbee9030 100644 --- a/hw/ip/gpio/dv/env/seq_lib/gpio_smoke_vseq.sv +++ b/hw/ip/gpio/dv/env/seq_lib/gpio_smoke_vseq.sv @@ -29,12 +29,12 @@ class gpio_smoke_vseq extends gpio_base_vseq; task body(); // test gpio inputs `DV_CHECK_MEMBER_RANDOMIZE_FATAL(num_trans) - `uvm_info(`gfn, $sformatf("No. of transactions (gpio_i) = %0d", num_trans), UVM_HIGH) for (uint tr_num = 0; tr_num < num_trans; tr_num++) begin bit [TL_DW-1:0] csr_rd_val; string msg_id = {`gfn, $sformatf(" Transaction-%0d: ", tr_num)}; `DV_CHECK_MEMBER_RANDOMIZE_FATAL(gpio_i) - `uvm_info(msg_id, $sformatf("gpio_i = %0h", gpio_i), UVM_HIGH) + `uvm_info(msg_id, $sformatf("gpio_i = %0h", gpio_i), UVM_LOW) + cfg.gpio_vif.drive(gpio_i); `ifdef GPIO_ASYNC_ON // If the CDC synchronizer prims are instantiated, it takes 2-3 cycles longer for inputs @@ -44,7 +44,11 @@ class gpio_smoke_vseq extends gpio_base_vseq; // Wait at least one clock cycle `DV_CHECK_MEMBER_RANDOMIZE_WITH_FATAL(delay, delay >= 1;) `endif - cfg.clk_rst_vif.wait_clks(delay); + + cfg.clk_rst_vif.wait_clks_or_rst(delay); + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) return; + // Reading data_in will trigger a check inside scoreboard csr_rd(.ptr(ral.data_in), .value(csr_rd_val)); `uvm_info(msg_id, {$sformatf("reading data_in after %0d clock cycles ", delay), @@ -70,8 +74,11 @@ class gpio_smoke_vseq extends gpio_base_vseq; csr_update(.csr(ral.direct_oe)); // Wait at least one clock cycle `DV_CHECK_MEMBER_RANDOMIZE_WITH_FATAL(delay, delay >= 1;) - cfg.clk_rst_vif.wait_clks(delay); - `uvm_info(msg_id, $sformatf("waiting for %0d clock cycles", delay), UVM_HIGH) + + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) return; + cfg.clk_rst_vif.wait_clks_or_rst(delay); + `uvm_info(msg_id, $sformatf("waiting for %0d clock cycles", delay), UVM_LOW) end endtask : body