From 6e63cd1a26c86fc8c395d5664c02133f754747d8 Mon Sep 17 00:00:00 2001 From: Robert Schilling Date: Wed, 17 Jul 2024 05:45:04 -0700 Subject: [PATCH] [hw,dma,rtl] Remove memory threshold interrupt from RTL and DIF Signed-off-by: Robert Schilling --- hw/ip/dma/data/dma.hjson | 85 +-- hw/ip/dma/data/dma_testplan.hjson | 10 +- hw/ip/dma/doc/registers.md | 325 ++++------ hw/ip/dma/doc/theory_of_operation.md | 8 - hw/ip/dma/dv/dma_sim_cfg.hjson | 6 - hw/ip/dma/dv/env/dma_env.core | 1 - hw/ip/dma/dv/env/dma_env_cov.sv | 22 - hw/ip/dma/dv/env/dma_env_pkg.sv | 1 - hw/ip/dma/dv/env/dma_scoreboard.sv | 29 - hw/ip/dma/dv/env/dma_seq_item.sv | 63 -- hw/ip/dma/dv/env/seq_lib/dma_base_vseq.sv | 11 - hw/ip/dma/dv/env/seq_lib/dma_generic_vseq.sv | 18 +- .../dma/dv/env/seq_lib/dma_mem_limit_vseq.sv | 63 -- hw/ip/dma/dv/env/seq_lib/dma_vseq_list.sv | 1 - hw/ip/dma/dv/tb/tb.sv | 1 - hw/ip/dma/rtl/dma.sv | 75 --- hw/ip/dma/rtl/dma_reg_pkg.sv | 261 ++++---- hw/ip/dma/rtl/dma_reg_top.sv | 568 +++++------------- sw/ip/dma/dif/autogen/dif_dma_autogen.c | 7 +- sw/ip/dma/dif/autogen/dif_dma_autogen.h | 4 - .../dif/autogen/dif_dma_autogen_unittest.cc | 28 +- sw/ip/dma/dif/dif_dma.c | 39 -- sw/ip/dma/dif/dif_dma.h | 42 +- sw/ip/dma/dif/dif_dma_unittest.cc | 41 +- 24 files changed, 385 insertions(+), 1324 deletions(-) delete mode 100644 hw/ip/dma/dv/env/seq_lib/dma_mem_limit_vseq.sv diff --git a/hw/ip/dma/data/dma.hjson b/hw/ip/dma/data/dma.hjson index 53009e9cdc1d3c..690b2d62e8c5bc 100644 --- a/hw/ip/dma/data/dma.hjson +++ b/hw/ip/dma/data/dma.hjson @@ -104,9 +104,6 @@ { name: "dma_error" desc: "DMA error has occurred. DMA_STATUS.error_code register shows the details." } - { name: "dma_memory_buffer_limit" - desc: "Memory buffer limit address reached." - } ] alert_list: [ { name: "fatal_fault" @@ -423,86 +420,6 @@ } ] } - { name: "DST_ADDR_LIMIT_LO" - desc: "Lower 32 bits of DMA memory buffer limit address." - swaccess: "rw" - hwaccess: "hro" - regwen: "CFG_REGWEN" - fields: [ - { bits: "31:0" - name: "addr_limit_lo" - resval: 0x0 - desc: ''' - Limit address configuration. - - Used in conjunction with the address auto-increment mode for hardware handshake operation to - generate an interrupt when memory buffer address approaches memory buffer address limit. - This field is optional. - However this field is expected to be implicitly valid if the CONTROL.memory_buffer_auto_increment_enable register (bit 7) is set. - ''' - } - ] - } - { name: "DST_ADDR_LIMIT_HI" - desc: "Upper 32 bits of DMA memory buffer limit address." - swaccess: "rw" - hwaccess: "hro" - regwen: "CFG_REGWEN" - fields: [ - { bits: "31:0" - name: "addr_limit_hi" - resval: 0x0 - desc: ''' - Limit address configuration. - - Used in conjunction with the address auto-increment mode for hardware handshake operation to - generate an interrupt when memory buffer address approaches memory buffer address limit. - This field is optional. - However this field is expected to be implicitly valid if the CONTROL.memory_buffer_auto_increment_enable register (bit 7) is set. - ''' - } - ] - } - { name: "DST_ADDR_ALMOST_LIMIT_LO" - desc: "Lower 32 bits of DMA memory buffer limit address." - swaccess: "rw" - hwaccess: "hro" - regwen: "CFG_REGWEN" - fields: [ - { bits: "31:0" - name: "addr_limit_lo" - resval: 0x0 - desc: ''' - Threshold for detecting that the buffer limit is approaching so as to prevent destination buffer overflow. - Used in conjunction with the address auto-increment mode for hardware handshake operation to generate an - interrupt when the buffer address approaches close to the buffer (i.e. reaches this threshold) address limit. - Enables firmware to take appropriate action prior to reaching the final limit. - This field is optional. - However this field is expected to be implicitly valid if the CONTROL.memory_buffer_auto_increment_enable register (bit 7) is set. - ''' - } - ] - } - { name: "DST_ADDR_ALMOST_LIMIT_HI" - desc: "Upper 32 bits of DMA memory buffer limit address." - swaccess: "rw" - hwaccess: "hro" - regwen: "CFG_REGWEN" - fields: [ - { bits: "31:0" - name: "addr_limit_hi" - resval: 0x0 - desc: ''' - Threshold for detecting that the buffer limit is approaching so as to prevent destination buffer overflow. - Used in conjunction with the address auto-increment mode for hardware handshake operation to generate an - interrupt when the buffer address approaches close to the buffer (i.e. reaches this threshold) address limit. - Enables firmware to take appropriate action prior to reaching the final limit. - This field is optional. - However this field is expected to be implicitly valid if the CONTROL.memory_buffer_auto_increment_enable register (bit 7) is set. - ''' - } - ] - } { name: "CONTROL" desc: "Control register for DMA data movement." swaccess: "rw" @@ -804,7 +721,7 @@ ] } } - { skipto: "0x12C" } + { skipto: "0x11C" } { multireg: { name: "INTR_SRC_WR_VAL" desc: "Write value for interrupt clearing write." diff --git a/hw/ip/dma/data/dma_testplan.hjson b/hw/ip/dma/data/dma_testplan.hjson index c46403043a362f..8f18a2e42272b6 100644 --- a/hw/ip/dma/data/dma_testplan.hjson +++ b/hw/ip/dma/data/dma_testplan.hjson @@ -226,13 +226,9 @@ Stimulus: - Configure DMA for 'hardware handshake' mode - Set memory_buffer_addr_auto_increment - - Set memory_buffer_threshold and memory_buffer_limit such that - * Threshold is less than the limit and - * Threshold and limit are within the DMA memory region - Start DMA operation by setting DMAC.GO bit - Assert Low Speed IO (LSIO) interrupt - Wait for TLUL transaction on the output interface - - Respond with random number of data items such that the amount exceeds either the memory_buffer_threshold or memory_buffer_limit - Deassert LSIO interrupt - Wait for the operation to complete - Repeat the operation with different source and destination parameters @@ -245,7 +241,7 @@ - Check if PLIC interrupt is asserted when memory_buffer_auto_increment is enabled ''' stage: V2 - tests: ["dma_handshake_stress", "dma_mem_limit"] + tests: ["dma_handshake_stress"] } { name: dma_abort @@ -308,8 +304,6 @@ * Total data size * Chunk data size * Transfer width - * Destination address limit - * Destination address almost limit * Control register fields: + opcode + hardware handshake enable @@ -330,7 +324,7 @@ * opcode, hardware handshake enable, data direction, and initial transfer * source and destination address, DMA-enabled memory range base and limit, and data direction * source and destination address alignment, total data size alignment, and transfer width - * memory buffer auto increment enable, data direction, and the results of (destination address + total data size) compared to {destination address limit, destination address almost limit} + * memory buffer auto increment enable, data direction, and the results of (destination address + total data size) ''' } { diff --git a/hw/ip/dma/doc/registers.md b/hw/ip/dma/doc/registers.md index a5f3e43c55ab24..41ba14f7915516 100644 --- a/hw/ip/dma/doc/registers.md +++ b/hw/ip/dma/doc/registers.md @@ -22,111 +22,104 @@ | dma.[`TOTAL_DATA_SIZE`](#total_data_size) | 0x38 | 4 | Total size of the data blob involved in DMA movement. | | dma.[`CHUNK_DATA_SIZE`](#chunk_data_size) | 0x3c | 4 | Number of bytes to be transferred in response to each interrupt/firmware request. | | dma.[`TRANSFER_WIDTH`](#transfer_width) | 0x40 | 4 | Denotes the width of each transaction that the DMA shall issue. | -| dma.[`DST_ADDR_LIMIT_LO`](#dst_addr_limit_lo) | 0x44 | 4 | Lower 32 bits of DMA memory buffer limit address. | -| dma.[`DST_ADDR_LIMIT_HI`](#dst_addr_limit_hi) | 0x48 | 4 | Upper 32 bits of DMA memory buffer limit address. | -| dma.[`DST_ADDR_ALMOST_LIMIT_LO`](#dst_addr_almost_limit_lo) | 0x4c | 4 | Lower 32 bits of DMA memory buffer limit address. | -| dma.[`DST_ADDR_ALMOST_LIMIT_HI`](#dst_addr_almost_limit_hi) | 0x50 | 4 | Upper 32 bits of DMA memory buffer limit address. | -| dma.[`CONTROL`](#control) | 0x54 | 4 | Control register for DMA data movement. | -| dma.[`STATUS`](#status) | 0x58 | 4 | Status indication for DMA data movement. | -| dma.[`ERROR_CODE`](#error_code) | 0x5c | 4 | Denotes the source of the operational error. | -| dma.[`SHA2_DIGEST_0`](#sha2_digest) | 0x60 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_1`](#sha2_digest) | 0x64 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_2`](#sha2_digest) | 0x68 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_3`](#sha2_digest) | 0x6c | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_4`](#sha2_digest) | 0x70 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_5`](#sha2_digest) | 0x74 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_6`](#sha2_digest) | 0x78 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_7`](#sha2_digest) | 0x7c | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_8`](#sha2_digest) | 0x80 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_9`](#sha2_digest) | 0x84 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_10`](#sha2_digest) | 0x88 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_11`](#sha2_digest) | 0x8c | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_12`](#sha2_digest) | 0x90 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_13`](#sha2_digest) | 0x94 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_14`](#sha2_digest) | 0x98 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_15`](#sha2_digest) | 0x9c | 4 | Digest register for the inline hashing operation. | -| dma.[`HANDSHAKE_INTR_ENABLE`](#handshake_intr_enable) | 0xa0 | 4 | Enable bits for incoming handshake interrupt wires. | -| dma.[`CLEAR_INTR_SRC`](#clear_intr_src) | 0xa4 | 4 | Valid bits for which interrupt sources need clearing. | -| dma.[`CLEAR_INTR_BUS`](#clear_intr_bus) | 0xa8 | 4 | Bus selection bit where the clearing command should be performed." | -| dma.[`INTR_SRC_ADDR_0`](#intr_src_addr) | 0xac | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_1`](#intr_src_addr) | 0xb0 | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_2`](#intr_src_addr) | 0xb4 | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_3`](#intr_src_addr) | 0xb8 | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_4`](#intr_src_addr) | 0xbc | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_5`](#intr_src_addr) | 0xc0 | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_6`](#intr_src_addr) | 0xc4 | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_7`](#intr_src_addr) | 0xc8 | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_8`](#intr_src_addr) | 0xcc | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_9`](#intr_src_addr) | 0xd0 | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_10`](#intr_src_addr) | 0xd4 | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_WR_VAL_0`](#intr_src_wr_val) | 0x12c | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_1`](#intr_src_wr_val) | 0x130 | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_2`](#intr_src_wr_val) | 0x134 | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_3`](#intr_src_wr_val) | 0x138 | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_4`](#intr_src_wr_val) | 0x13c | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_5`](#intr_src_wr_val) | 0x140 | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_6`](#intr_src_wr_val) | 0x144 | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_7`](#intr_src_wr_val) | 0x148 | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_8`](#intr_src_wr_val) | 0x14c | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_9`](#intr_src_wr_val) | 0x150 | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_10`](#intr_src_wr_val) | 0x154 | 4 | Write value for interrupt clearing write. | +| dma.[`CONTROL`](#control) | 0x44 | 4 | Control register for DMA data movement. | +| dma.[`STATUS`](#status) | 0x48 | 4 | Status indication for DMA data movement. | +| dma.[`ERROR_CODE`](#error_code) | 0x4c | 4 | Denotes the source of the operational error. | +| dma.[`SHA2_DIGEST_0`](#sha2_digest) | 0x50 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_1`](#sha2_digest) | 0x54 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_2`](#sha2_digest) | 0x58 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_3`](#sha2_digest) | 0x5c | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_4`](#sha2_digest) | 0x60 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_5`](#sha2_digest) | 0x64 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_6`](#sha2_digest) | 0x68 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_7`](#sha2_digest) | 0x6c | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_8`](#sha2_digest) | 0x70 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_9`](#sha2_digest) | 0x74 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_10`](#sha2_digest) | 0x78 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_11`](#sha2_digest) | 0x7c | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_12`](#sha2_digest) | 0x80 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_13`](#sha2_digest) | 0x84 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_14`](#sha2_digest) | 0x88 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_15`](#sha2_digest) | 0x8c | 4 | Digest register for the inline hashing operation. | +| dma.[`HANDSHAKE_INTR_ENABLE`](#handshake_intr_enable) | 0x90 | 4 | Enable bits for incoming handshake interrupt wires. | +| dma.[`CLEAR_INTR_SRC`](#clear_intr_src) | 0x94 | 4 | Valid bits for which interrupt sources need clearing. | +| dma.[`CLEAR_INTR_BUS`](#clear_intr_bus) | 0x98 | 4 | Bus selection bit where the clearing command should be performed." | +| dma.[`INTR_SRC_ADDR_0`](#intr_src_addr) | 0x9c | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_1`](#intr_src_addr) | 0xa0 | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_2`](#intr_src_addr) | 0xa4 | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_3`](#intr_src_addr) | 0xa8 | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_4`](#intr_src_addr) | 0xac | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_5`](#intr_src_addr) | 0xb0 | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_6`](#intr_src_addr) | 0xb4 | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_7`](#intr_src_addr) | 0xb8 | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_8`](#intr_src_addr) | 0xbc | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_9`](#intr_src_addr) | 0xc0 | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_10`](#intr_src_addr) | 0xc4 | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_WR_VAL_0`](#intr_src_wr_val) | 0x11c | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_1`](#intr_src_wr_val) | 0x120 | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_2`](#intr_src_wr_val) | 0x124 | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_3`](#intr_src_wr_val) | 0x128 | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_4`](#intr_src_wr_val) | 0x12c | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_5`](#intr_src_wr_val) | 0x130 | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_6`](#intr_src_wr_val) | 0x134 | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_7`](#intr_src_wr_val) | 0x138 | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_8`](#intr_src_wr_val) | 0x13c | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_9`](#intr_src_wr_val) | 0x140 | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_10`](#intr_src_wr_val) | 0x144 | 4 | Write value for interrupt clearing write. | ## INTR_STATE Interrupt State Register - Offset: `0x0` - Reset default: `0x0` -- Reset mask: `0x7` +- Reset mask: `0x3` ### Fields ```wavejson -{"reg": [{"name": "dma_done", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "dma_error", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "dma_memory_buffer_limit", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}} +{"reg": [{"name": "dma_done", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "dma_error", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} ``` -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------------------|:--------------------------------------------------------------------------| -| 31:3 | | | | Reserved | -| 2 | rw1c | 0x0 | dma_memory_buffer_limit | Memory buffer limit address reached. | -| 1 | rw1c | 0x0 | dma_error | DMA error has occurred. DMA_STATUS.error_code register shows the details. | -| 0 | rw1c | 0x0 | dma_done | DMA operation has been completed. | +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | rw1c | 0x0 | dma_error | DMA error has occurred. DMA_STATUS.error_code register shows the details. | +| 0 | rw1c | 0x0 | dma_done | DMA operation has been completed. | ## INTR_ENABLE Interrupt Enable Register - Offset: `0x4` - Reset default: `0x0` -- Reset mask: `0x7` +- Reset mask: `0x3` ### Fields ```wavejson -{"reg": [{"name": "dma_done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "dma_error", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "dma_memory_buffer_limit", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}} +{"reg": [{"name": "dma_done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "dma_error", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} ``` -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------------------|:----------------------------------------------------------------------------------| -| 31:3 | | | | Reserved | -| 2 | rw | 0x0 | dma_memory_buffer_limit | Enable interrupt when [`INTR_STATE.dma_memory_buffer_limit`](#intr_state) is set. | -| 1 | rw | 0x0 | dma_error | Enable interrupt when [`INTR_STATE.dma_error`](#intr_state) is set. | -| 0 | rw | 0x0 | dma_done | Enable interrupt when [`INTR_STATE.dma_done`](#intr_state) is set. | +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | rw | 0x0 | dma_error | Enable interrupt when [`INTR_STATE.dma_error`](#intr_state) is set. | +| 0 | rw | 0x0 | dma_done | Enable interrupt when [`INTR_STATE.dma_done`](#intr_state) is set. | ## INTR_TEST Interrupt Test Register - Offset: `0x8` - Reset default: `0x0` -- Reset mask: `0x7` +- Reset mask: `0x3` ### Fields ```wavejson -{"reg": [{"name": "dma_done", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "dma_error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "dma_memory_buffer_limit", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}} +{"reg": [{"name": "dma_done", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "dma_error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} ``` -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------------------|:---------------------------------------------------------------------------| -| 31:3 | | | | Reserved | -| 2 | wo | 0x0 | dma_memory_buffer_limit | Write 1 to force [`INTR_STATE.dma_memory_buffer_limit`](#intr_state) to 1. | -| 1 | wo | 0x0 | dma_error | Write 1 to force [`INTR_STATE.dma_error`](#intr_state) to 1. | -| 0 | wo | 0x0 | dma_done | Write 1 to force [`INTR_STATE.dma_done`](#intr_state) to 1. | +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------|:-------------------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | wo | 0x0 | dma_error | Write 1 to force [`INTR_STATE.dma_error`](#intr_state) to 1. | +| 0 | wo | 0x0 | dma_done | Write 1 to force [`INTR_STATE.dma_done`](#intr_state) to 1. | ## ALERT_TEST Alert Test Register @@ -456,109 +449,9 @@ Note that the value 3 for this register represents an invalid configuration that Other values are reserved. -## DST_ADDR_LIMIT_LO -Lower 32 bits of DMA memory buffer limit address. -- Offset: `0x44` -- Reset default: `0x0` -- Reset mask: `0xffffffff` -- Register enable: [`CFG_REGWEN`](#cfg_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "addr_limit_lo", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:---------------------------------------------------| -| 31:0 | rw | 0x0 | [addr_limit_lo](#dst_addr_limit_lo--addr_limit_lo) | - -### DST_ADDR_LIMIT_LO . addr_limit_lo -Limit address configuration. - -Used in conjunction with the address auto-increment mode for hardware handshake operation to -generate an interrupt when memory buffer address approaches memory buffer address limit. -This field is optional. -However this field is expected to be implicitly valid if the CONTROL.memory_buffer_auto_increment_enable register (bit 7) is set. - -## DST_ADDR_LIMIT_HI -Upper 32 bits of DMA memory buffer limit address. -- Offset: `0x48` -- Reset default: `0x0` -- Reset mask: `0xffffffff` -- Register enable: [`CFG_REGWEN`](#cfg_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "addr_limit_hi", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:---------------------------------------------------| -| 31:0 | rw | 0x0 | [addr_limit_hi](#dst_addr_limit_hi--addr_limit_hi) | - -### DST_ADDR_LIMIT_HI . addr_limit_hi -Limit address configuration. - -Used in conjunction with the address auto-increment mode for hardware handshake operation to -generate an interrupt when memory buffer address approaches memory buffer address limit. -This field is optional. -However this field is expected to be implicitly valid if the CONTROL.memory_buffer_auto_increment_enable register (bit 7) is set. - -## DST_ADDR_ALMOST_LIMIT_LO -Lower 32 bits of DMA memory buffer limit address. -- Offset: `0x4c` -- Reset default: `0x0` -- Reset mask: `0xffffffff` -- Register enable: [`CFG_REGWEN`](#cfg_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "addr_limit_lo", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:----------------------------------------------------------| -| 31:0 | rw | 0x0 | [addr_limit_lo](#dst_addr_almost_limit_lo--addr_limit_lo) | - -### DST_ADDR_ALMOST_LIMIT_LO . addr_limit_lo -Threshold for detecting that the buffer limit is approaching so as to prevent destination buffer overflow. -Used in conjunction with the address auto-increment mode for hardware handshake operation to generate an -interrupt when the buffer address approaches close to the buffer (i.e. reaches this threshold) address limit. -Enables firmware to take appropriate action prior to reaching the final limit. -This field is optional. -However this field is expected to be implicitly valid if the CONTROL.memory_buffer_auto_increment_enable register (bit 7) is set. - -## DST_ADDR_ALMOST_LIMIT_HI -Upper 32 bits of DMA memory buffer limit address. -- Offset: `0x50` -- Reset default: `0x0` -- Reset mask: `0xffffffff` -- Register enable: [`CFG_REGWEN`](#cfg_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "addr_limit_hi", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:----------------------------------------------------------| -| 31:0 | rw | 0x0 | [addr_limit_hi](#dst_addr_almost_limit_hi--addr_limit_hi) | - -### DST_ADDR_ALMOST_LIMIT_HI . addr_limit_hi -Threshold for detecting that the buffer limit is approaching so as to prevent destination buffer overflow. -Used in conjunction with the address auto-increment mode for hardware handshake operation to generate an -interrupt when the buffer address approaches close to the buffer (i.e. reaches this threshold) address limit. -Enables firmware to take appropriate action prior to reaching the final limit. -This field is optional. -However this field is expected to be implicitly valid if the CONTROL.memory_buffer_auto_increment_enable register (bit 7) is set. - ## CONTROL Control register for DMA data movement. -- Offset: `0x54` +- Offset: `0x44` - Reset default: `0x0` - Reset mask: `0x880001ff` @@ -637,7 +530,7 @@ Other values are reserved. ## STATUS Status indication for DMA data movement. -- Offset: `0x58` +- Offset: `0x48` - Reset default: `0x0` - Reset mask: `0x1f` @@ -659,7 +552,7 @@ Status indication for DMA data movement. ## ERROR_CODE Denotes the source of the operational error. The error is cleared by writing the RW1C STATUS.error register. -- Offset: `0x5c` +- Offset: `0x4c` - Reset default: `0x0` - Reset mask: `0xff` @@ -694,22 +587,22 @@ Depending on the used hashing mode, not all registers are used. | Name | Offset | |:---------------|:---------| -| SHA2_DIGEST_0 | 0x60 | -| SHA2_DIGEST_1 | 0x64 | -| SHA2_DIGEST_2 | 0x68 | -| SHA2_DIGEST_3 | 0x6c | -| SHA2_DIGEST_4 | 0x70 | -| SHA2_DIGEST_5 | 0x74 | -| SHA2_DIGEST_6 | 0x78 | -| SHA2_DIGEST_7 | 0x7c | -| SHA2_DIGEST_8 | 0x80 | -| SHA2_DIGEST_9 | 0x84 | -| SHA2_DIGEST_10 | 0x88 | -| SHA2_DIGEST_11 | 0x8c | -| SHA2_DIGEST_12 | 0x90 | -| SHA2_DIGEST_13 | 0x94 | -| SHA2_DIGEST_14 | 0x98 | -| SHA2_DIGEST_15 | 0x9c | +| SHA2_DIGEST_0 | 0x50 | +| SHA2_DIGEST_1 | 0x54 | +| SHA2_DIGEST_2 | 0x58 | +| SHA2_DIGEST_3 | 0x5c | +| SHA2_DIGEST_4 | 0x60 | +| SHA2_DIGEST_5 | 0x64 | +| SHA2_DIGEST_6 | 0x68 | +| SHA2_DIGEST_7 | 0x6c | +| SHA2_DIGEST_8 | 0x70 | +| SHA2_DIGEST_9 | 0x74 | +| SHA2_DIGEST_10 | 0x78 | +| SHA2_DIGEST_11 | 0x7c | +| SHA2_DIGEST_12 | 0x80 | +| SHA2_DIGEST_13 | 0x84 | +| SHA2_DIGEST_14 | 0x88 | +| SHA2_DIGEST_15 | 0x8c | ### Fields @@ -724,7 +617,7 @@ Depending on the used hashing mode, not all registers are used. ## HANDSHAKE_INTR_ENABLE Enable bits for incoming handshake interrupt wires. -- Offset: `0xa0` +- Offset: `0x90` - Reset default: `0x7ff` - Reset mask: `0x7ff` - Register enable: [`CFG_REGWEN`](#cfg_regwen) @@ -745,7 +638,7 @@ Valid bits for which interrupt sources need clearing. When HANDSHAKE_INTR_ENABLE is non-zero and corresponding lsio_trigger becomes set, DMA issues writes with address from INTR_SRC_ADDR and write value from INTR_SRC_WR_VAL corresponding to each bit set in this register. -- Offset: `0xa4` +- Offset: `0x94` - Reset default: `0x0` - Reset mask: `0x7ff` - Register enable: [`CFG_REGWEN`](#cfg_regwen) @@ -765,7 +658,7 @@ bit set in this register. Bus selection bit where the clearing command should be performed." 0: CTN/System fabric 1: OT-internal crossbar -- Offset: `0xa8` +- Offset: `0x98` - Reset default: `0x0` - Reset mask: `0x7ff` - Register enable: [`CFG_REGWEN`](#cfg_regwen) @@ -790,17 +683,17 @@ Destination address for interrupt source clearing write. | Name | Offset | |:-----------------|:---------| -| INTR_SRC_ADDR_0 | 0xac | -| INTR_SRC_ADDR_1 | 0xb0 | -| INTR_SRC_ADDR_2 | 0xb4 | -| INTR_SRC_ADDR_3 | 0xb8 | -| INTR_SRC_ADDR_4 | 0xbc | -| INTR_SRC_ADDR_5 | 0xc0 | -| INTR_SRC_ADDR_6 | 0xc4 | -| INTR_SRC_ADDR_7 | 0xc8 | -| INTR_SRC_ADDR_8 | 0xcc | -| INTR_SRC_ADDR_9 | 0xd0 | -| INTR_SRC_ADDR_10 | 0xd4 | +| INTR_SRC_ADDR_0 | 0x9c | +| INTR_SRC_ADDR_1 | 0xa0 | +| INTR_SRC_ADDR_2 | 0xa4 | +| INTR_SRC_ADDR_3 | 0xa8 | +| INTR_SRC_ADDR_4 | 0xac | +| INTR_SRC_ADDR_5 | 0xb0 | +| INTR_SRC_ADDR_6 | 0xb4 | +| INTR_SRC_ADDR_7 | 0xb8 | +| INTR_SRC_ADDR_8 | 0xbc | +| INTR_SRC_ADDR_9 | 0xc0 | +| INTR_SRC_ADDR_10 | 0xc4 | ### Fields @@ -822,17 +715,17 @@ Write value for interrupt clearing write. | Name | Offset | |:-------------------|:---------| -| INTR_SRC_WR_VAL_0 | 0x12c | -| INTR_SRC_WR_VAL_1 | 0x130 | -| INTR_SRC_WR_VAL_2 | 0x134 | -| INTR_SRC_WR_VAL_3 | 0x138 | -| INTR_SRC_WR_VAL_4 | 0x13c | -| INTR_SRC_WR_VAL_5 | 0x140 | -| INTR_SRC_WR_VAL_6 | 0x144 | -| INTR_SRC_WR_VAL_7 | 0x148 | -| INTR_SRC_WR_VAL_8 | 0x14c | -| INTR_SRC_WR_VAL_9 | 0x150 | -| INTR_SRC_WR_VAL_10 | 0x154 | +| INTR_SRC_WR_VAL_0 | 0x11c | +| INTR_SRC_WR_VAL_1 | 0x120 | +| INTR_SRC_WR_VAL_2 | 0x124 | +| INTR_SRC_WR_VAL_3 | 0x128 | +| INTR_SRC_WR_VAL_4 | 0x12c | +| INTR_SRC_WR_VAL_5 | 0x130 | +| INTR_SRC_WR_VAL_6 | 0x134 | +| INTR_SRC_WR_VAL_7 | 0x138 | +| INTR_SRC_WR_VAL_8 | 0x13c | +| INTR_SRC_WR_VAL_9 | 0x140 | +| INTR_SRC_WR_VAL_10 | 0x144 | ### Fields diff --git a/hw/ip/dma/doc/theory_of_operation.md b/hw/ip/dma/doc/theory_of_operation.md index 810c19e5b5c9c3..4000734a05a7bc 100644 --- a/hw/ip/dma/doc/theory_of_operation.md +++ b/hw/ip/dma/doc/theory_of_operation.md @@ -134,10 +134,6 @@ hardware handshake DMA operation. interrupt times the FIFO read data width). - [*Transfer Width*](../data/dma.hjson#transfer_width): Width of each transaction (equivalent to FIFO read data width). -- [*Limit register*](../data/dma.hjson#dst_addr_limit_lo): Marks the end of the buffer used - to write 'total size' worth of data payloads if memory buffer - auto-increment feature is used. DMAC shall set an overflow - indication if the buffer limit is reached. - [*DMAC Control register*](../data/dma.hjson#control): - Opcode: Type of operation requested. Typically set to copy @@ -197,10 +193,6 @@ hardware handshake DMA operation. into the FIFO. - [*Transfer Width*](../data/dma.hjson#transfer_width): Write Data width of the LSIO FIFO register. Each write transaction is equal to this size. -- [*Limit register*](../data/dma.hjson#dst_addr_limit_lo): Marks the end of the memory - buffer used to read 'total size' worth of data segments if - auto-increment feature is used. DMAC shall set an overflow - indication if the buffer limit is reached. - [*DMAC Control register*](../data/dma.hjson#control) - Opcode: Type of operation requested. Typically set to copy diff --git a/hw/ip/dma/dv/dma_sim_cfg.hjson b/hw/ip/dma/dv/dma_sim_cfg.hjson index 102081393a3d2e..1f9dc7a43dcd7e 100644 --- a/hw/ip/dma/dv/dma_sim_cfg.hjson +++ b/hw/ip/dma/dv/dma_sim_cfg.hjson @@ -86,12 +86,6 @@ run_opts: ["+dma_dv_waive_system_bus=1", "+test_timeout_ns=300_000_000_000"] reseed: 5 } - { - name: dma_mem_limit - uvm_test_seq: dma_mem_limit_vseq - run_opts: ["+dma_dv_waive_system_bus=1"] - reseed: 5 - } { name: dma_mem_enabled uvm_test_seq: dma_mem_enabled_vseq diff --git a/hw/ip/dma/dv/env/dma_env.core b/hw/ip/dma/dv/env/dma_env.core index fc878520cf1dfc..9fec7f024d6b58 100644 --- a/hw/ip/dma/dv/env/dma_env.core +++ b/hw/ip/dma/dv/env/dma_env.core @@ -35,7 +35,6 @@ filesets: - seq_lib/dma_abort_vseq.sv: {is_include_file: true} - seq_lib/dma_short_transfer_vseq.sv: {is_include_file: true} - seq_lib/dma_longer_transfer_vseq.sv: {is_include_file: true} - - seq_lib/dma_mem_limit_vseq.sv: {is_include_file: true} - seq_lib/dma_mem_enabled_vseq.sv: {is_include_file: true} - seq_lib/dma_intr_vseq.sv: {is_include_file: true} - seq_lib/dma_generic_stress_vseq.sv: {is_include_file: true} diff --git a/hw/ip/dma/dv/env/dma_env_cov.sv b/hw/ip/dma/dv/env/dma_env_cov.sv index 0e518e59f3d0f4..9be5e5f3dff902 100644 --- a/hw/ip/dma/dv/env/dma_env_cov.sv +++ b/hw/ip/dma/dv/env/dma_env_cov.sv @@ -96,22 +96,6 @@ covergroup dma_config_cg with function sample(dma_seq_item dma_config, `DMA_ENV_COV_32B_ADDR_BINS } - cp_dst_addr_limit: coverpoint dma_config.dst_addr_limit { - `DMA_ENV_COV_64B_ADDR_BINS - } - - cp_dst_addr_limit_exceeded: coverpoint ( - dma_config.dst_addr + dma_config.total_data_size >= dma_config.dst_addr_limit - ); - - cp_dst_addr_almost_limit: coverpoint dma_config.dst_addr_almost_limit { - `DMA_ENV_COV_64B_ADDR_BINS - } - - cp_dst_addr_almost_limit_exceeded: coverpoint ( - dma_config.dst_addr + dma_config.total_data_size >= dma_config.dst_addr_almost_limit - ); - cp_handshake: coverpoint dma_config.handshake; cp_data_direction: coverpoint dma_config.direction { @@ -188,12 +172,6 @@ covergroup dma_config_cg with function sample(dma_seq_item dma_config, cp_total_data_size_alignment, cp_transfer_width; - cr_mem_buffer_auto_inc_X_data_direction_X_address_limits_exceeded: cross - cp_mem_buffer_auto_inc, - cp_data_direction, - cp_dst_addr_limit_exceeded, - cp_dst_addr_almost_limit_exceeded; - endgroup covergroup dma_tlul_error_cg with function sample(dma_seq_item dma_config, diff --git a/hw/ip/dma/dv/env/dma_env_pkg.sv b/hw/ip/dma/dv/env/dma_env_pkg.sv index 9e732572782109..f94a13e8441059 100644 --- a/hw/ip/dma/dv/env/dma_env_pkg.sv +++ b/hw/ip/dma/dv/env/dma_env_pkg.sv @@ -35,7 +35,6 @@ package dma_env_pkg; // Index of interrupt in intf_vif parameter uint DMA_DONE = 0; parameter uint DMA_ERROR = 1; - parameter uint DMA_MEM_LIMIT = 2; // Completion status bits (DV-internal) typedef enum { diff --git a/hw/ip/dma/dv/env/dma_scoreboard.sv b/hw/ip/dma/dv/env/dma_scoreboard.sv index c73b52fa433837..6aa99e3f2bcd37 100644 --- a/hw/ip/dma/dv/env/dma_scoreboard.sv +++ b/hw/ip/dma/dv/env/dma_scoreboard.sv @@ -356,22 +356,6 @@ class dma_scoreboard extends cip_base_scoreboard #( $sformatf("Unexpected opcode : %d on %s", a_opcode.name(), if_name)) end - // Update the expected value of destination address limit interrupt for this address; - // applicable only to reading from FIFO hardware when auto-incrementing is enabled for the - // memory address. - if ((dma_config.handshake & dma_config.direction == DmaRcvData && - dma_config.auto_inc_buffer) && - (a_addr >= dma_config.dst_addr_limit || - a_addr >= dma_config.dst_addr_almost_limit)) begin - `uvm_info(`gfn, - $sformatf("Memory address: 0x%0x crosses almost limit: 0x%0x limit: 0x%0x", - a_addr, dma_config.dst_addr_almost_limit, dma_config.dst_addr_limit), - UVM_HIGH) - - // Interrupt is expected only if enabled. - predict_interrupts(MemLimitToIntrLatency, 1 << DMA_MEM_LIMIT, intr_enable); - end - // Update number of bytes transferred only in case of write txn - refer #338 num_bytes_transferred += num_bytes_this_txn; @@ -623,7 +607,6 @@ class dma_scoreboard extends cip_base_scoreboard #( unique case (i) DMA_DONE: rsn = {rsn, "Done "}; DMA_ERROR: rsn = {rsn, "Error "}; - DMA_MEM_LIMIT: rsn = {rsn, "Mem limit"}; default: rsn = {rsn, "Unknown intr"}; endcase end @@ -912,18 +895,6 @@ class dma_scoreboard extends cip_base_scoreboard #( `uvm_info(`gfn, $sformatf("Got transfer_width = %s", dma_config.per_transfer_width.name()), UVM_HIGH) end - "dst_addr_limit_lo": begin - dma_config.dst_addr_limit[31:0] = `gmv(ral.dst_addr_limit_lo.addr_limit_lo); - end - "dst_addr_limit_hi": begin - dma_config.dst_addr_limit[63:32] = `gmv(ral.dst_addr_limit_hi.addr_limit_hi); - end - "dst_addr_almost_limit_lo": begin - dma_config.dst_addr_almost_limit[31:0] = `gmv(ral.dst_addr_almost_limit_lo.addr_limit_lo); - end - "dst_addr_almost_limit_hi": begin - dma_config.dst_addr_almost_limit[63:32] = `gmv(ral.dst_addr_almost_limit_hi.addr_limit_hi); - end "clear_intr_bus": begin dma_config.clear_intr_bus = `gmv(ral.clear_intr_bus.bus); end diff --git a/hw/ip/dma/dv/env/dma_seq_item.sv b/hw/ip/dma/dv/env/dma_seq_item.sv index ebb9dfaaa5abac..9335a83ba6abb9 100644 --- a/hw/ip/dma/dv/env/dma_seq_item.sv +++ b/hw/ip/dma/dv/env/dma_seq_item.sv @@ -38,8 +38,6 @@ class dma_seq_item extends uvm_sequence_item; rand bit handshake; rand bit [63:0] src_addr; rand bit [63:0] dst_addr; - rand bit [63:0] dst_addr_almost_limit; - rand bit [63:0] dst_addr_limit; rand bit mem_range_valid; rand bit [31:0] mem_range_base; rand bit [31:0] mem_range_limit; @@ -107,8 +105,6 @@ class dma_seq_item extends uvm_sequence_item; `uvm_field_int(auto_inc_fifo, UVM_DEFAULT) `uvm_field_int(handshake, UVM_DEFAULT) `uvm_field_int(is_valid_config, UVM_DEFAULT) - `uvm_field_int(dst_addr_almost_limit, UVM_DEFAULT) - `uvm_field_int(dst_addr_limit, UVM_DEFAULT) `uvm_field_int(handshake_intr_en, UVM_DEFAULT) `uvm_field_int(clear_intr_src, UVM_DEFAULT) `uvm_field_int(clear_intr_bus, UVM_DEFAULT) @@ -342,63 +338,6 @@ class dma_seq_item extends uvm_sequence_item; } } - // Add a (normally disabled) constraint to exercise 'memory buffer limit' values that are - // close to the transferred destination buffer (exercising both 1. within it and 2. outside it), - // because otherwise randomizing them within even a 32-bit address space has a low probability of - // coincidence. - constraint dst_addr_limit_nearby_c { - if (valid_dma_config) { - (dst_addr >= dst_addr_limit && dst_addr - dst_addr_limit < total_data_size) || - (dst_addr_limit >= dst_addr && dst_addr_limit - dst_addr < 2 * total_data_size); - } - } - - constraint dst_addr_limit_c { - // Set solver order to make sure mem buffer limit is randomized correctly in case - // valid_dma_config is set - solve dst_addr_almost_limit before dst_addr_limit; - // For valid dma config, mem buffer limit must be greater than destination address - // in order to detect passing the limit - if (valid_dma_config) { - if (handshake && direction == DmaRcvData) { - dst_addr_limit >= dst_addr_almost_limit; - // When full testing of the SoC System bus has been waived, testing is restricted to a - // 4GiB address window but we can vary the address window for each transfer. - if (dma_dv_waive_system_bus && dst_asid == SocSystemAddr) { - // Destination address range must lie within the selected 4GiB window and not spill - // over. Since dst_addr <= dst_addr_almost_limit <= dst_addr_limit, we do not need to - // constrain `dst_addr_almost_limit` further. - dst_addr_limit[63:32] == soc_system_hi_addr; - dst_addr_limit[31:0] <= ~total_data_size; // == 32'hFFFF_FFFF - total_data_size. - } - } - } - } - - // Add a (normally disabled) constraint to exercise 'memory buffer almost limit' values that are - // close to the transferred destination buffer (exercising both 1. within it and 2. outside it), - // because otherwise randomizing them within even a 32-bit address space has a low probability of - // coincidence. - constraint dst_addr_almost_limit_nearby_c { - if (valid_dma_config) { - (dst_addr >= dst_addr_almost_limit && dst_addr - dst_addr_almost_limit < total_data_size) || - (dst_addr_almost_limit >= dst_addr && dst_addr_almost_limit - dst_addr < 2 * total_data_size); - } - } - - constraint dst_addr_almost_limit_c { - // Set solver order to make sure mem buffer almost limit is randomized correctly - // in case valid_dma_config is set - solve dst_addr before dst_addr_almost_limit; - // For valid dma config, mem buffer almost limit must not be - // less than destination address - if (valid_dma_config) { - if (handshake && direction == DmaRcvData) { - dst_addr_almost_limit >= dst_addr; - } - } - } - constraint range_regwen_c { // For valid DMA configurations, the memory range registers _may_ be locked but this is not // obligatory. Having the separate 'RANGE_VALID' bit affords the opportunity for FW at @@ -474,8 +413,6 @@ class dma_seq_item extends uvm_sequence_item; $sformatf("\n\tmem_range_valid : %0d", mem_range_valid), $sformatf("\n\tmem_range_base : 0x%08x", mem_range_base), $sformatf("\n\tmem_range_limit : 0x%08x", mem_range_limit), - $sformatf("\n\tdst_addr_almost_limit : 0x%16x", dst_addr_almost_limit), - $sformatf("\n\tdst_addr_limit : 0x%16x", dst_addr_limit), $sformatf("\n\tclear_intr_src : 0x%8x", clear_intr_src), $sformatf("\n\tclear_intr_bus : 0x%8x", clear_intr_bus), $sformatf("\n\thandshake_intr_en : 0x%08x", handshake_intr_en), diff --git a/hw/ip/dma/dv/env/seq_lib/dma_base_vseq.sv b/hw/ip/dma/dv/env/seq_lib/dma_base_vseq.sv index 9d310de98e6406..54ad02362a8937 100644 --- a/hw/ip/dma/dv/env/seq_lib/dma_base_vseq.sv +++ b/hw/ip/dma/dv/env/seq_lib/dma_base_vseq.sv @@ -301,16 +301,6 @@ class dma_base_vseq extends cip_base_vseq #( `uvm_info(`gfn, $sformatf("DMA: Destination Address = 0x%016h", dst_addr), UVM_HIGH) endtask : set_dst_addr - task set_dst_addr_range(bit[63:0] almost_limit, - bit[63:0] limit); - csr_wr(ral.dst_addr_limit_lo, limit[31:0]); - csr_wr(ral.dst_addr_limit_hi, limit[63:32]); - `uvm_info(`gfn, $sformatf("DMA: Destination Limit = 0x%016h", limit), UVM_HIGH) - csr_wr(ral.dst_addr_almost_limit_lo, almost_limit[31:0]); - csr_wr(ral.dst_addr_almost_limit_hi, almost_limit[63:32]); - `uvm_info(`gfn, $sformatf("DMA: Destination Almost Limit = 0x%016h", almost_limit), UVM_HIGH) - endtask : set_dst_addr_range - // Task: Set DMA Enabled Memory base and limit task set_dma_enabled_memory_range(bit [32:0] base, bit [31:0] limit, bit valid, mubi4_t lock); csr_wr(ral.enabled_memory_range_base, base); @@ -374,7 +364,6 @@ class dma_base_vseq extends cip_base_vseq #( abort_pending = 1'b0; set_src_addr(dma_config.src_addr); set_dst_addr(dma_config.dst_addr); - set_dst_addr_range(dma_config.dst_addr_almost_limit, dma_config.dst_addr_limit); set_addr_space_id(dma_config.src_asid, dma_config.dst_asid); set_total_size(dma_config.total_data_size); set_chunk_data_size(dma_config.chunk_data_size); diff --git a/hw/ip/dma/dv/env/seq_lib/dma_generic_vseq.sv b/hw/ip/dma/dv/env/seq_lib/dma_generic_vseq.sv index 40250a9b143743..cea9bb75921f3b 100644 --- a/hw/ip/dma/dv/env/seq_lib/dma_generic_vseq.sv +++ b/hw/ip/dma/dv/env/seq_lib/dma_generic_vseq.sv @@ -124,22 +124,9 @@ class dma_generic_vseq extends dma_base_vseq; clear_interrupts(1 << DMA_ERROR); endtask - // A small number of constraints are disabled by default to allow greater variability in the - // configuration; they may be enabled in specific derived sequences to ensure collisions between - // - say - a couple of 32-bit address ranges which would ordinarily be very unlikely to - // coincide. - virtual function void set_default_constraints(); - dma_config.dst_addr_limit_nearby_c.constraint_mode(0); - dma_config.dst_addr_almost_limit_nearby_c.constraint_mode(0); - endfunction - virtual task body(); super.body(); - // The majority of constraints on the DMA configuration are enabled in all sequences, but a - // small number need to be disabled in normal operation. - set_default_constraints(); - for (uint i = 0; i < num_iters; i++) begin randomize_iter_config(dma_config); @@ -160,8 +147,7 @@ class dma_generic_vseq extends dma_base_vseq; // Set the Interrupt Enables appropriately for this transfer; DONE and ERROR - which // terminate the test - must be enabled if this transfer is to be interrupt-driven. - // They may optionally be exercised when using polling. The MEM_LIMIT interrupt is always - // optional. + // They may optionally be exercised when using polling. intr_enables = $urandom; if (intr_driven) begin intr_enables[DMA_DONE] = 1'b1; @@ -308,8 +294,6 @@ class dma_generic_vseq extends dma_base_vseq; `uvm_fatal(`gfn, $sformatf("FATAL: Unexpected/unrecognised completion status 0x%0x", int'(status))) end - // Clear 'memory limit' interrupt to prevent it interfering with subsequent transfers. - clear_interrupts(1 << DMA_MEM_LIMIT); // Now that we've finished all DUT accesses for his iteration... stop_device(); diff --git a/hw/ip/dma/dv/env/seq_lib/dma_mem_limit_vseq.sv b/hw/ip/dma/dv/env/seq_lib/dma_mem_limit_vseq.sv deleted file mode 100644 index ef600d6ee8745a..00000000000000 --- a/hw/ip/dma/dv/env/seq_lib/dma_mem_limit_vseq.sv +++ /dev/null @@ -1,63 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// This sequence is specifically to ensure that the 'limit' and 'almost limit' addresses stand -// a much higher chance of being near the destination address range, whilst permitting them to be -// either inside or just outside that range. - -class dma_mem_limit_vseq extends dma_generic_vseq; - `uvm_object_utils(dma_mem_limit_vseq) - `uvm_object_new - - constraint iters_c {num_iters inside {[2:4]};} - constraint transactions_c {num_txns == 16;} - - // Permit only valid configurations for this test; invalid configurations are generated by stress - // sequences. - virtual function bit pick_if_config_valid(); - return 1'b1; - endfunction - - // Randomization of DMA configuration and transfer properties; constraints are set to ensure that - // the memory limit addresses shall be used, and we shall usually want them to be close to the - // destination address range of the transfer because otherwise the 32- or 64-bit address range - // is too large make collisions probable. - virtual function void randomize_item(ref dma_seq_item dma_config); - bit almost_nearby; - bit limit_nearby; - // Decide whether we want the 'limit' threshold to lie within the transfer - `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(limit_nearby, limit_nearby dist { 0 := 20, 1 := 80};) - // Decide whether we want the 'almost limit' threshold to lie within the transfer - `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(almost_nearby, almost_nearby dist { 0 := 20, 1 := 80};) - `uvm_info(`gfn, $sformatf("DMA: Choosing limit nearby = %d almost_limit nearby = %d", - limit_nearby, almost_nearby), UVM_MEDIUM) - - dma_config.dst_addr_limit_nearby_c.constraint_mode(limit_nearby); - dma_config.dst_addr_almost_limit_nearby_c.constraint_mode(almost_nearby); - - // Allow only valid DMA configurations - dma_config.valid_dma_config = 1; - `DV_CHECK_RANDOMIZE_WITH_FATAL( - dma_config, - direction == DmaRcvData; // Receive from FIFO (otherwise mem limit not used) - per_transfer_width == DmaXfer4BperTxn; // Limit to only 4B transfers - handshake == 1'b1; // Enable hardware handshake mode - handshake_intr_en != 0;) // At least one handshake interrupt signal must be enabled - `uvm_info(`gfn, $sformatf("DMA: Randomized a new transaction:%s", - dma_config.convert2string()), UVM_MEDIUM) - // Report the decisions here; the configuration shall always be valid (see above). - `uvm_info(`gfn, $sformatf("DMA: Destination range [0x%0x,0x%0x) limit 0x%0x almost_limit 0x%0x", - dma_config.dst_addr, - dma_config.dst_addr + dma_config.total_data_size, - dma_config.dst_addr_limit, dma_config.dst_addr_almost_limit), - UVM_MEDIUM) - endfunction - - // The functionality of this vseq is implemented in `dma_generic_vseq` - virtual task body(); - `uvm_info(`gfn, "DMA: Starting mem limit Sequence", UVM_LOW) - super.body(); - `uvm_info(`gfn, "DMA: Completed mem limit Sequence", UVM_LOW) - endtask : body -endclass diff --git a/hw/ip/dma/dv/env/seq_lib/dma_vseq_list.sv b/hw/ip/dma/dv/env/seq_lib/dma_vseq_list.sv index f76a2875b97420..3c420180b500a2 100644 --- a/hw/ip/dma/dv/env/seq_lib/dma_vseq_list.sv +++ b/hw/ip/dma/dv/env/seq_lib/dma_vseq_list.sv @@ -18,6 +18,5 @@ `include "dma_stress_all_vseq.sv" `include "dma_short_transfer_vseq.sv" `include "dma_longer_transfer_vseq.sv" -`include "dma_mem_limit_vseq.sv" `include "dma_mem_enabled_vseq.sv" //`include "dma_intr_vseq.sv" diff --git a/hw/ip/dma/dv/tb/tb.sv b/hw/ip/dma/dv/tb/tb.sv index bc0f639ef662cd..6f88fad6d218b1 100644 --- a/hw/ip/dma/dv/tb/tb.sv +++ b/hw/ip/dma/dv/tb/tb.sv @@ -56,7 +56,6 @@ module tb; .lsio_trigger_i (handshake_i), .intr_dma_done_o (interrupts[DMA_DONE]), .intr_dma_error_o (interrupts[DMA_ERROR]), - .intr_dma_memory_buffer_limit_o (interrupts[DMA_MEM_LIMIT]), .alert_rx_i (alert_rx), .alert_tx_o (alert_tx), // TL Interface to OT Internal address space diff --git a/hw/ip/dma/rtl/dma.sv b/hw/ip/dma/rtl/dma.sv index c74aab6292b92a..0e1817f0064acb 100644 --- a/hw/ip/dma/rtl/dma.sv +++ b/hw/ip/dma/rtl/dma.sv @@ -22,7 +22,6 @@ module dma // DMA interrupts and incoming LSIO triggers output logic intr_dma_done_o, output logic intr_dma_error_o, - output logic intr_dma_memory_buffer_limit_o, input lsio_trigger_t lsio_trigger_i, // Alerts input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, @@ -1083,85 +1082,15 @@ module dma // Interrupt logic logic test_done_interrupt; logic test_error_interrupt; - logic test_memory_buffer_limit_interrupt; - logic send_memory_buffer_limit_interrupt; - logic sent_almost_limit_interrupt_d, sent_almost_limit_interrupt_q; - logic send_almost_limit_interrupt; - logic sent_limit_interrupt_d, sent_limit_interrupt_q; - logic send_limit_interrupt; - logic data_move_state, data_move_state_valid; logic update_dst_addr_reg, update_src_addr_reg; assign test_done_interrupt = reg2hw.intr_test.dma_done.q && reg2hw.intr_test.dma_done.qe; assign test_error_interrupt = reg2hw.intr_test.dma_error.q && reg2hw.intr_test.dma_error.qe; - assign test_memory_buffer_limit_interrupt = - reg2hw.intr_test.dma_memory_buffer_limit.q && - reg2hw.intr_test.dma_memory_buffer_limit.qe; // Signal interrupt controller whenever an enabled interrupt info bit is set assign intr_dma_done_o = reg2hw.intr_state.dma_done.q && reg2hw.intr_enable.dma_done.q; assign intr_dma_error_o = reg2hw.intr_state.dma_error.q && reg2hw.intr_enable.dma_error.q; - assign intr_dma_memory_buffer_limit_o = reg2hw.intr_state.dma_memory_buffer_limit.q && - reg2hw.intr_enable.dma_memory_buffer_limit.q; - - always_comb begin - sent_almost_limit_interrupt_d = sent_almost_limit_interrupt_q; - - if (send_almost_limit_interrupt) begin - sent_almost_limit_interrupt_d = 1'b1; - end else if ((ctrl_state_q == DmaIdle) && handshake_interrupt) begin - sent_almost_limit_interrupt_d = 1'b0; - end - end - - prim_flop #( - .Width(1) - ) aff_send_almost_limit_interrupt ( - .clk_i ( gated_clk ), - .rst_ni( rst_ni ), - .d_i ( sent_almost_limit_interrupt_d ), - .q_o ( sent_almost_limit_interrupt_q ) - ); - - assign send_almost_limit_interrupt = - (!sent_almost_limit_interrupt_q) && // only want to send once - data_move_state_valid && // only trigger for single cycle when data has moved - control_q.cfg_handshake_en && - control_q.cfg_memory_buffer_auto_increment_en && - (!control_q.cfg_data_direction) && - (dst_addr_q >= {reg2hw.dst_addr_almost_limit_hi.q, reg2hw.dst_addr_almost_limit_lo.q}); - - always_comb begin - sent_limit_interrupt_d = sent_limit_interrupt_q; - - if (send_limit_interrupt) begin - sent_limit_interrupt_d = 1'b1; - end else if ((ctrl_state_q == DmaIdle) && handshake_interrupt) begin - sent_limit_interrupt_d = 1'b0; - end - end - - prim_flop #( - .Width(1) - ) aff_send_limit_interrupt ( - .clk_i ( gated_clk ), - .rst_ni( rst_ni ), - .d_i ( sent_limit_interrupt_d ), - .q_o ( sent_limit_interrupt_q ) - ); - - assign send_limit_interrupt = - (!sent_limit_interrupt_q) && // only want to send once - data_move_state_valid && // only trigger for single cycle when data has moved - control_q.cfg_handshake_en && - control_q.cfg_memory_buffer_auto_increment_en && - (!control_q.cfg_data_direction) && - (dst_addr_q >= {reg2hw.dst_addr_limit_hi.q, reg2hw.dst_addr_limit_lo.q}); - - // Send out an interrupt when reaching almost the buffer limit or when really reaching the limit - // Ensures that all data until the IRQ is transferred. - assign send_memory_buffer_limit_interrupt = send_almost_limit_interrupt || send_limit_interrupt; // Data was moved if we get a write valid response assign data_move_state_valid = (write_rsp_valid && (ctrl_state_q == DmaSendWrite || @@ -1327,10 +1256,6 @@ module dma hw2reg.intr_state.dma_error.de = reg2hw.status.error.q | test_error_interrupt; hw2reg.intr_state.dma_error.d = 1'b1; - hw2reg.intr_state.dma_memory_buffer_limit.de = send_memory_buffer_limit_interrupt | - test_memory_buffer_limit_interrupt; - hw2reg.intr_state.dma_memory_buffer_limit.d = 1'b1; - // Clear the SHA2 digests if the SHA2 valid flag is cleared (RW1C) if (reg2hw.status.sha2_digest_valid.qe & reg2hw.status.sha2_digest_valid.q) begin for (int i = 0; i < NR_SHA_DIGEST_ELEMENTS; i++) begin diff --git a/hw/ip/dma/rtl/dma_reg_pkg.sv b/hw/ip/dma/rtl/dma_reg_pkg.sv index 93e0b555b17ec5..0dca94a3d60f55 100644 --- a/hw/ip/dma/rtl/dma_reg_pkg.sv +++ b/hw/ip/dma/rtl/dma_reg_pkg.sv @@ -24,9 +24,6 @@ package dma_reg_pkg; struct packed { logic q; } dma_error; - struct packed { - logic q; - } dma_memory_buffer_limit; } dma_reg2hw_intr_state_reg_t; typedef struct packed { @@ -36,9 +33,6 @@ package dma_reg_pkg; struct packed { logic q; } dma_error; - struct packed { - logic q; - } dma_memory_buffer_limit; } dma_reg2hw_intr_enable_reg_t; typedef struct packed { @@ -50,10 +44,6 @@ package dma_reg_pkg; logic q; logic qe; } dma_error; - struct packed { - logic q; - logic qe; - } dma_memory_buffer_limit; } dma_reg2hw_intr_test_reg_t; typedef struct packed { @@ -116,22 +106,6 @@ package dma_reg_pkg; logic [1:0] q; } dma_reg2hw_transfer_width_reg_t; - typedef struct packed { - logic [31:0] q; - } dma_reg2hw_dst_addr_limit_lo_reg_t; - - typedef struct packed { - logic [31:0] q; - } dma_reg2hw_dst_addr_limit_hi_reg_t; - - typedef struct packed { - logic [31:0] q; - } dma_reg2hw_dst_addr_almost_limit_lo_reg_t; - - typedef struct packed { - logic [31:0] q; - } dma_reg2hw_dst_addr_almost_limit_hi_reg_t; - typedef struct packed { struct packed { logic [3:0] q; @@ -206,10 +180,6 @@ package dma_reg_pkg; logic d; logic de; } dma_error; - struct packed { - logic d; - logic de; - } dma_memory_buffer_limit; } dma_hw2reg_intr_state_reg_t; typedef struct packed { @@ -316,26 +286,22 @@ package dma_reg_pkg; // Register -> HW type typedef struct packed { - dma_reg2hw_intr_state_reg_t intr_state; // [1169:1167] - dma_reg2hw_intr_enable_reg_t intr_enable; // [1166:1164] - dma_reg2hw_intr_test_reg_t intr_test; // [1163:1158] - dma_reg2hw_alert_test_reg_t alert_test; // [1157:1156] - dma_reg2hw_src_addr_lo_reg_t src_addr_lo; // [1155:1124] - dma_reg2hw_src_addr_hi_reg_t src_addr_hi; // [1123:1092] - dma_reg2hw_dst_addr_lo_reg_t dst_addr_lo; // [1091:1060] - dma_reg2hw_dst_addr_hi_reg_t dst_addr_hi; // [1059:1028] - dma_reg2hw_addr_space_id_reg_t addr_space_id; // [1027:1020] - dma_reg2hw_enabled_memory_range_base_reg_t enabled_memory_range_base; // [1019:987] - dma_reg2hw_enabled_memory_range_limit_reg_t enabled_memory_range_limit; // [986:954] - dma_reg2hw_range_valid_reg_t range_valid; // [953:953] - dma_reg2hw_range_regwen_reg_t range_regwen; // [952:949] - dma_reg2hw_total_data_size_reg_t total_data_size; // [948:917] - dma_reg2hw_chunk_data_size_reg_t chunk_data_size; // [916:885] - dma_reg2hw_transfer_width_reg_t transfer_width; // [884:883] - dma_reg2hw_dst_addr_limit_lo_reg_t dst_addr_limit_lo; // [882:851] - dma_reg2hw_dst_addr_limit_hi_reg_t dst_addr_limit_hi; // [850:819] - dma_reg2hw_dst_addr_almost_limit_lo_reg_t dst_addr_almost_limit_lo; // [818:787] - dma_reg2hw_dst_addr_almost_limit_hi_reg_t dst_addr_almost_limit_hi; // [786:755] + dma_reg2hw_intr_state_reg_t intr_state; // [1037:1036] + dma_reg2hw_intr_enable_reg_t intr_enable; // [1035:1034] + dma_reg2hw_intr_test_reg_t intr_test; // [1033:1030] + dma_reg2hw_alert_test_reg_t alert_test; // [1029:1028] + dma_reg2hw_src_addr_lo_reg_t src_addr_lo; // [1027:996] + dma_reg2hw_src_addr_hi_reg_t src_addr_hi; // [995:964] + dma_reg2hw_dst_addr_lo_reg_t dst_addr_lo; // [963:932] + dma_reg2hw_dst_addr_hi_reg_t dst_addr_hi; // [931:900] + dma_reg2hw_addr_space_id_reg_t addr_space_id; // [899:892] + dma_reg2hw_enabled_memory_range_base_reg_t enabled_memory_range_base; // [891:859] + dma_reg2hw_enabled_memory_range_limit_reg_t enabled_memory_range_limit; // [858:826] + dma_reg2hw_range_valid_reg_t range_valid; // [825:825] + dma_reg2hw_range_regwen_reg_t range_regwen; // [824:821] + dma_reg2hw_total_data_size_reg_t total_data_size; // [820:789] + dma_reg2hw_chunk_data_size_reg_t chunk_data_size; // [788:757] + dma_reg2hw_transfer_width_reg_t transfer_width; // [756:755] dma_reg2hw_control_reg_t control; // [754:743] dma_reg2hw_status_reg_t status; // [742:737] dma_reg2hw_handshake_intr_enable_reg_t handshake_intr_enable; // [736:726] @@ -347,7 +313,7 @@ package dma_reg_pkg; // HW -> register type typedef struct packed { - dma_hw2reg_intr_state_reg_t intr_state; // [701:696] + dma_hw2reg_intr_state_reg_t intr_state; // [699:696] dma_hw2reg_src_addr_lo_reg_t src_addr_lo; // [695:663] dma_hw2reg_src_addr_hi_reg_t src_addr_hi; // [662:630] dma_hw2reg_dst_addr_lo_reg_t dst_addr_lo; // [629:597] @@ -377,60 +343,55 @@ package dma_reg_pkg; parameter logic [BlockAw-1:0] DMA_TOTAL_DATA_SIZE_OFFSET = 9'h 38; parameter logic [BlockAw-1:0] DMA_CHUNK_DATA_SIZE_OFFSET = 9'h 3c; parameter logic [BlockAw-1:0] DMA_TRANSFER_WIDTH_OFFSET = 9'h 40; - parameter logic [BlockAw-1:0] DMA_DST_ADDR_LIMIT_LO_OFFSET = 9'h 44; - parameter logic [BlockAw-1:0] DMA_DST_ADDR_LIMIT_HI_OFFSET = 9'h 48; - parameter logic [BlockAw-1:0] DMA_DST_ADDR_ALMOST_LIMIT_LO_OFFSET = 9'h 4c; - parameter logic [BlockAw-1:0] DMA_DST_ADDR_ALMOST_LIMIT_HI_OFFSET = 9'h 50; - parameter logic [BlockAw-1:0] DMA_CONTROL_OFFSET = 9'h 54; - parameter logic [BlockAw-1:0] DMA_STATUS_OFFSET = 9'h 58; - parameter logic [BlockAw-1:0] DMA_ERROR_CODE_OFFSET = 9'h 5c; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_0_OFFSET = 9'h 60; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_1_OFFSET = 9'h 64; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_2_OFFSET = 9'h 68; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_3_OFFSET = 9'h 6c; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_4_OFFSET = 9'h 70; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_5_OFFSET = 9'h 74; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_6_OFFSET = 9'h 78; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_7_OFFSET = 9'h 7c; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_8_OFFSET = 9'h 80; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_9_OFFSET = 9'h 84; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_10_OFFSET = 9'h 88; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_11_OFFSET = 9'h 8c; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_12_OFFSET = 9'h 90; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_13_OFFSET = 9'h 94; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_14_OFFSET = 9'h 98; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_15_OFFSET = 9'h 9c; - parameter logic [BlockAw-1:0] DMA_HANDSHAKE_INTR_ENABLE_OFFSET = 9'h a0; - parameter logic [BlockAw-1:0] DMA_CLEAR_INTR_SRC_OFFSET = 9'h a4; - parameter logic [BlockAw-1:0] DMA_CLEAR_INTR_BUS_OFFSET = 9'h a8; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_0_OFFSET = 9'h ac; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_1_OFFSET = 9'h b0; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_2_OFFSET = 9'h b4; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_3_OFFSET = 9'h b8; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_4_OFFSET = 9'h bc; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_5_OFFSET = 9'h c0; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_6_OFFSET = 9'h c4; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_7_OFFSET = 9'h c8; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_8_OFFSET = 9'h cc; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_9_OFFSET = 9'h d0; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_10_OFFSET = 9'h d4; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_0_OFFSET = 9'h 12c; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_1_OFFSET = 9'h 130; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_2_OFFSET = 9'h 134; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_3_OFFSET = 9'h 138; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_4_OFFSET = 9'h 13c; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_5_OFFSET = 9'h 140; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_6_OFFSET = 9'h 144; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_7_OFFSET = 9'h 148; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_8_OFFSET = 9'h 14c; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_9_OFFSET = 9'h 150; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_10_OFFSET = 9'h 154; + parameter logic [BlockAw-1:0] DMA_CONTROL_OFFSET = 9'h 44; + parameter logic [BlockAw-1:0] DMA_STATUS_OFFSET = 9'h 48; + parameter logic [BlockAw-1:0] DMA_ERROR_CODE_OFFSET = 9'h 4c; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_0_OFFSET = 9'h 50; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_1_OFFSET = 9'h 54; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_2_OFFSET = 9'h 58; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_3_OFFSET = 9'h 5c; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_4_OFFSET = 9'h 60; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_5_OFFSET = 9'h 64; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_6_OFFSET = 9'h 68; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_7_OFFSET = 9'h 6c; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_8_OFFSET = 9'h 70; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_9_OFFSET = 9'h 74; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_10_OFFSET = 9'h 78; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_11_OFFSET = 9'h 7c; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_12_OFFSET = 9'h 80; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_13_OFFSET = 9'h 84; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_14_OFFSET = 9'h 88; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_15_OFFSET = 9'h 8c; + parameter logic [BlockAw-1:0] DMA_HANDSHAKE_INTR_ENABLE_OFFSET = 9'h 90; + parameter logic [BlockAw-1:0] DMA_CLEAR_INTR_SRC_OFFSET = 9'h 94; + parameter logic [BlockAw-1:0] DMA_CLEAR_INTR_BUS_OFFSET = 9'h 98; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_0_OFFSET = 9'h 9c; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_1_OFFSET = 9'h a0; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_2_OFFSET = 9'h a4; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_3_OFFSET = 9'h a8; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_4_OFFSET = 9'h ac; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_5_OFFSET = 9'h b0; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_6_OFFSET = 9'h b4; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_7_OFFSET = 9'h b8; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_8_OFFSET = 9'h bc; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_9_OFFSET = 9'h c0; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_10_OFFSET = 9'h c4; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_0_OFFSET = 9'h 11c; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_1_OFFSET = 9'h 120; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_2_OFFSET = 9'h 124; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_3_OFFSET = 9'h 128; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_4_OFFSET = 9'h 12c; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_5_OFFSET = 9'h 130; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_6_OFFSET = 9'h 134; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_7_OFFSET = 9'h 138; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_8_OFFSET = 9'h 13c; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_9_OFFSET = 9'h 140; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_10_OFFSET = 9'h 144; // Reset values for hwext registers and their fields - parameter logic [2:0] DMA_INTR_TEST_RESVAL = 3'h 0; + parameter logic [1:0] DMA_INTR_TEST_RESVAL = 2'h 0; parameter logic [0:0] DMA_INTR_TEST_DMA_DONE_RESVAL = 1'h 0; parameter logic [0:0] DMA_INTR_TEST_DMA_ERROR_RESVAL = 1'h 0; - parameter logic [0:0] DMA_INTR_TEST_DMA_MEMORY_BUFFER_LIMIT_RESVAL = 1'h 0; parameter logic [0:0] DMA_ALERT_TEST_RESVAL = 1'h 0; parameter logic [0:0] DMA_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; parameter logic [3:0] DMA_CFG_REGWEN_RESVAL = 4'h 6; @@ -455,10 +416,6 @@ package dma_reg_pkg; DMA_TOTAL_DATA_SIZE, DMA_CHUNK_DATA_SIZE, DMA_TRANSFER_WIDTH, - DMA_DST_ADDR_LIMIT_LO, - DMA_DST_ADDR_LIMIT_HI, - DMA_DST_ADDR_ALMOST_LIMIT_LO, - DMA_DST_ADDR_ALMOST_LIMIT_HI, DMA_CONTROL, DMA_STATUS, DMA_ERROR_CODE, @@ -506,7 +463,7 @@ package dma_reg_pkg; } dma_id_e; // Register width information to check illegal writes - parameter logic [3:0] DMA_PERMIT [65] = '{ + parameter logic [3:0] DMA_PERMIT [61] = '{ 4'b 0001, // index[ 0] DMA_INTR_STATE 4'b 0001, // index[ 1] DMA_INTR_ENABLE 4'b 0001, // index[ 2] DMA_INTR_TEST @@ -524,54 +481,50 @@ package dma_reg_pkg; 4'b 1111, // index[14] DMA_TOTAL_DATA_SIZE 4'b 1111, // index[15] DMA_CHUNK_DATA_SIZE 4'b 0001, // index[16] DMA_TRANSFER_WIDTH - 4'b 1111, // index[17] DMA_DST_ADDR_LIMIT_LO - 4'b 1111, // index[18] DMA_DST_ADDR_LIMIT_HI - 4'b 1111, // index[19] DMA_DST_ADDR_ALMOST_LIMIT_LO - 4'b 1111, // index[20] DMA_DST_ADDR_ALMOST_LIMIT_HI - 4'b 1111, // index[21] DMA_CONTROL - 4'b 0001, // index[22] DMA_STATUS - 4'b 0001, // index[23] DMA_ERROR_CODE - 4'b 1111, // index[24] DMA_SHA2_DIGEST_0 - 4'b 1111, // index[25] DMA_SHA2_DIGEST_1 - 4'b 1111, // index[26] DMA_SHA2_DIGEST_2 - 4'b 1111, // index[27] DMA_SHA2_DIGEST_3 - 4'b 1111, // index[28] DMA_SHA2_DIGEST_4 - 4'b 1111, // index[29] DMA_SHA2_DIGEST_5 - 4'b 1111, // index[30] DMA_SHA2_DIGEST_6 - 4'b 1111, // index[31] DMA_SHA2_DIGEST_7 - 4'b 1111, // index[32] DMA_SHA2_DIGEST_8 - 4'b 1111, // index[33] DMA_SHA2_DIGEST_9 - 4'b 1111, // index[34] DMA_SHA2_DIGEST_10 - 4'b 1111, // index[35] DMA_SHA2_DIGEST_11 - 4'b 1111, // index[36] DMA_SHA2_DIGEST_12 - 4'b 1111, // index[37] DMA_SHA2_DIGEST_13 - 4'b 1111, // index[38] DMA_SHA2_DIGEST_14 - 4'b 1111, // index[39] DMA_SHA2_DIGEST_15 - 4'b 0011, // index[40] DMA_HANDSHAKE_INTR_ENABLE - 4'b 0011, // index[41] DMA_CLEAR_INTR_SRC - 4'b 0011, // index[42] DMA_CLEAR_INTR_BUS - 4'b 1111, // index[43] DMA_INTR_SRC_ADDR_0 - 4'b 1111, // index[44] DMA_INTR_SRC_ADDR_1 - 4'b 1111, // index[45] DMA_INTR_SRC_ADDR_2 - 4'b 1111, // index[46] DMA_INTR_SRC_ADDR_3 - 4'b 1111, // index[47] DMA_INTR_SRC_ADDR_4 - 4'b 1111, // index[48] DMA_INTR_SRC_ADDR_5 - 4'b 1111, // index[49] DMA_INTR_SRC_ADDR_6 - 4'b 1111, // index[50] DMA_INTR_SRC_ADDR_7 - 4'b 1111, // index[51] DMA_INTR_SRC_ADDR_8 - 4'b 1111, // index[52] DMA_INTR_SRC_ADDR_9 - 4'b 1111, // index[53] DMA_INTR_SRC_ADDR_10 - 4'b 1111, // index[54] DMA_INTR_SRC_WR_VAL_0 - 4'b 1111, // index[55] DMA_INTR_SRC_WR_VAL_1 - 4'b 1111, // index[56] DMA_INTR_SRC_WR_VAL_2 - 4'b 1111, // index[57] DMA_INTR_SRC_WR_VAL_3 - 4'b 1111, // index[58] DMA_INTR_SRC_WR_VAL_4 - 4'b 1111, // index[59] DMA_INTR_SRC_WR_VAL_5 - 4'b 1111, // index[60] DMA_INTR_SRC_WR_VAL_6 - 4'b 1111, // index[61] DMA_INTR_SRC_WR_VAL_7 - 4'b 1111, // index[62] DMA_INTR_SRC_WR_VAL_8 - 4'b 1111, // index[63] DMA_INTR_SRC_WR_VAL_9 - 4'b 1111 // index[64] DMA_INTR_SRC_WR_VAL_10 + 4'b 1111, // index[17] DMA_CONTROL + 4'b 0001, // index[18] DMA_STATUS + 4'b 0001, // index[19] DMA_ERROR_CODE + 4'b 1111, // index[20] DMA_SHA2_DIGEST_0 + 4'b 1111, // index[21] DMA_SHA2_DIGEST_1 + 4'b 1111, // index[22] DMA_SHA2_DIGEST_2 + 4'b 1111, // index[23] DMA_SHA2_DIGEST_3 + 4'b 1111, // index[24] DMA_SHA2_DIGEST_4 + 4'b 1111, // index[25] DMA_SHA2_DIGEST_5 + 4'b 1111, // index[26] DMA_SHA2_DIGEST_6 + 4'b 1111, // index[27] DMA_SHA2_DIGEST_7 + 4'b 1111, // index[28] DMA_SHA2_DIGEST_8 + 4'b 1111, // index[29] DMA_SHA2_DIGEST_9 + 4'b 1111, // index[30] DMA_SHA2_DIGEST_10 + 4'b 1111, // index[31] DMA_SHA2_DIGEST_11 + 4'b 1111, // index[32] DMA_SHA2_DIGEST_12 + 4'b 1111, // index[33] DMA_SHA2_DIGEST_13 + 4'b 1111, // index[34] DMA_SHA2_DIGEST_14 + 4'b 1111, // index[35] DMA_SHA2_DIGEST_15 + 4'b 0011, // index[36] DMA_HANDSHAKE_INTR_ENABLE + 4'b 0011, // index[37] DMA_CLEAR_INTR_SRC + 4'b 0011, // index[38] DMA_CLEAR_INTR_BUS + 4'b 1111, // index[39] DMA_INTR_SRC_ADDR_0 + 4'b 1111, // index[40] DMA_INTR_SRC_ADDR_1 + 4'b 1111, // index[41] DMA_INTR_SRC_ADDR_2 + 4'b 1111, // index[42] DMA_INTR_SRC_ADDR_3 + 4'b 1111, // index[43] DMA_INTR_SRC_ADDR_4 + 4'b 1111, // index[44] DMA_INTR_SRC_ADDR_5 + 4'b 1111, // index[45] DMA_INTR_SRC_ADDR_6 + 4'b 1111, // index[46] DMA_INTR_SRC_ADDR_7 + 4'b 1111, // index[47] DMA_INTR_SRC_ADDR_8 + 4'b 1111, // index[48] DMA_INTR_SRC_ADDR_9 + 4'b 1111, // index[49] DMA_INTR_SRC_ADDR_10 + 4'b 1111, // index[50] DMA_INTR_SRC_WR_VAL_0 + 4'b 1111, // index[51] DMA_INTR_SRC_WR_VAL_1 + 4'b 1111, // index[52] DMA_INTR_SRC_WR_VAL_2 + 4'b 1111, // index[53] DMA_INTR_SRC_WR_VAL_3 + 4'b 1111, // index[54] DMA_INTR_SRC_WR_VAL_4 + 4'b 1111, // index[55] DMA_INTR_SRC_WR_VAL_5 + 4'b 1111, // index[56] DMA_INTR_SRC_WR_VAL_6 + 4'b 1111, // index[57] DMA_INTR_SRC_WR_VAL_7 + 4'b 1111, // index[58] DMA_INTR_SRC_WR_VAL_8 + 4'b 1111, // index[59] DMA_INTR_SRC_WR_VAL_9 + 4'b 1111 // index[60] DMA_INTR_SRC_WR_VAL_10 }; endpackage diff --git a/hw/ip/dma/rtl/dma_reg_top.sv b/hw/ip/dma/rtl/dma_reg_top.sv index 094acf3250ba8f..561aef1d4ab9c7 100644 --- a/hw/ip/dma/rtl/dma_reg_top.sv +++ b/hw/ip/dma/rtl/dma_reg_top.sv @@ -55,9 +55,9 @@ module dma_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [64:0] reg_we_check; + logic [60:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(65) + .OneHotWidth(61) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -129,19 +129,14 @@ module dma_reg_top ( logic intr_state_dma_done_wd; logic intr_state_dma_error_qs; logic intr_state_dma_error_wd; - logic intr_state_dma_memory_buffer_limit_qs; - logic intr_state_dma_memory_buffer_limit_wd; logic intr_enable_we; logic intr_enable_dma_done_qs; logic intr_enable_dma_done_wd; logic intr_enable_dma_error_qs; logic intr_enable_dma_error_wd; - logic intr_enable_dma_memory_buffer_limit_qs; - logic intr_enable_dma_memory_buffer_limit_wd; logic intr_test_we; logic intr_test_dma_done_wd; logic intr_test_dma_error_wd; - logic intr_test_dma_memory_buffer_limit_wd; logic alert_test_we; logic alert_test_wd; logic src_addr_lo_we; @@ -184,18 +179,6 @@ module dma_reg_top ( logic transfer_width_we; logic [1:0] transfer_width_qs; logic [1:0] transfer_width_wd; - logic dst_addr_limit_lo_we; - logic [31:0] dst_addr_limit_lo_qs; - logic [31:0] dst_addr_limit_lo_wd; - logic dst_addr_limit_hi_we; - logic [31:0] dst_addr_limit_hi_qs; - logic [31:0] dst_addr_limit_hi_wd; - logic dst_addr_almost_limit_lo_we; - logic [31:0] dst_addr_almost_limit_lo_qs; - logic [31:0] dst_addr_almost_limit_lo_wd; - logic dst_addr_almost_limit_hi_we; - logic [31:0] dst_addr_almost_limit_hi_qs; - logic [31:0] dst_addr_almost_limit_hi_wd; logic control_we; logic [3:0] control_opcode_qs; logic [3:0] control_opcode_wd; @@ -377,33 +360,6 @@ module dma_reg_top ( .qs (intr_state_dma_error_qs) ); - // F[dma_memory_buffer_limit]: 2:2 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW1C), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_intr_state_dma_memory_buffer_limit ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (intr_state_we), - .wd (intr_state_dma_memory_buffer_limit_wd), - - // from internal hardware - .de (hw2reg.intr_state.dma_memory_buffer_limit.de), - .d (hw2reg.intr_state.dma_memory_buffer_limit.d), - - // to internal hardware - .qe (), - .q (reg2hw.intr_state.dma_memory_buffer_limit.q), - .ds (), - - // to register interface (read) - .qs (intr_state_dma_memory_buffer_limit_qs) - ); - // R[intr_enable]: V(False) // F[dma_done]: 0:0 @@ -460,37 +416,10 @@ module dma_reg_top ( .qs (intr_enable_dma_error_qs) ); - // F[dma_memory_buffer_limit]: 2:2 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_intr_enable_dma_memory_buffer_limit ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (intr_enable_we), - .wd (intr_enable_dma_memory_buffer_limit_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.intr_enable.dma_memory_buffer_limit.q), - .ds (), - - // to register interface (read) - .qs (intr_enable_dma_memory_buffer_limit_qs) - ); - // R[intr_test]: V(True) logic intr_test_qe; - logic [2:0] intr_test_flds_we; + logic [1:0] intr_test_flds_we; assign intr_test_qe = &intr_test_flds_we; // F[dma_done]: 0:0 prim_subreg_ext #( @@ -524,22 +453,6 @@ module dma_reg_top ( ); assign reg2hw.intr_test.dma_error.qe = intr_test_qe; - // F[dma_memory_buffer_limit]: 2:2 - prim_subreg_ext #( - .DW (1) - ) u_intr_test_dma_memory_buffer_limit ( - .re (1'b0), - .we (intr_test_we), - .wd (intr_test_dma_memory_buffer_limit_wd), - .d ('0), - .qre (), - .qe (intr_test_flds_we[2]), - .q (reg2hw.intr_test.dma_memory_buffer_limit.q), - .ds (), - .qs () - ); - assign reg2hw.intr_test.dma_memory_buffer_limit.qe = intr_test_qe; - // R[alert_test]: V(True) logic alert_test_qe; @@ -1020,138 +933,6 @@ module dma_reg_top ( ); - // R[dst_addr_limit_lo]: V(False) - // Create REGWEN-gated WE signal - logic dst_addr_limit_lo_gated_we; - assign dst_addr_limit_lo_gated_we = - dst_addr_limit_lo_we & - prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(cfg_regwen_qs)); - prim_subreg #( - .DW (32), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (32'h0), - .Mubi (1'b0) - ) u_dst_addr_limit_lo ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (dst_addr_limit_lo_gated_we), - .wd (dst_addr_limit_lo_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.dst_addr_limit_lo.q), - .ds (), - - // to register interface (read) - .qs (dst_addr_limit_lo_qs) - ); - - - // R[dst_addr_limit_hi]: V(False) - // Create REGWEN-gated WE signal - logic dst_addr_limit_hi_gated_we; - assign dst_addr_limit_hi_gated_we = - dst_addr_limit_hi_we & - prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(cfg_regwen_qs)); - prim_subreg #( - .DW (32), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (32'h0), - .Mubi (1'b0) - ) u_dst_addr_limit_hi ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (dst_addr_limit_hi_gated_we), - .wd (dst_addr_limit_hi_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.dst_addr_limit_hi.q), - .ds (), - - // to register interface (read) - .qs (dst_addr_limit_hi_qs) - ); - - - // R[dst_addr_almost_limit_lo]: V(False) - // Create REGWEN-gated WE signal - logic dst_addr_almost_limit_lo_gated_we; - assign dst_addr_almost_limit_lo_gated_we = - dst_addr_almost_limit_lo_we & - prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(cfg_regwen_qs)); - prim_subreg #( - .DW (32), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (32'h0), - .Mubi (1'b0) - ) u_dst_addr_almost_limit_lo ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (dst_addr_almost_limit_lo_gated_we), - .wd (dst_addr_almost_limit_lo_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.dst_addr_almost_limit_lo.q), - .ds (), - - // to register interface (read) - .qs (dst_addr_almost_limit_lo_qs) - ); - - - // R[dst_addr_almost_limit_hi]: V(False) - // Create REGWEN-gated WE signal - logic dst_addr_almost_limit_hi_gated_we; - assign dst_addr_almost_limit_hi_gated_we = - dst_addr_almost_limit_hi_we & - prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(cfg_regwen_qs)); - prim_subreg #( - .DW (32), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (32'h0), - .Mubi (1'b0) - ) u_dst_addr_almost_limit_hi ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (dst_addr_almost_limit_hi_gated_we), - .wd (dst_addr_almost_limit_hi_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.dst_addr_almost_limit_hi.q), - .ds (), - - // to register interface (read) - .qs (dst_addr_almost_limit_hi_qs) - ); - - // R[control]: V(False) logic control_qe; logic [7:0] control_flds_we; @@ -3062,7 +2843,7 @@ module dma_reg_top ( - logic [64:0] addr_hit; + logic [60:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == DMA_INTR_STATE_OFFSET); @@ -3082,54 +2863,50 @@ module dma_reg_top ( addr_hit[14] = (reg_addr == DMA_TOTAL_DATA_SIZE_OFFSET); addr_hit[15] = (reg_addr == DMA_CHUNK_DATA_SIZE_OFFSET); addr_hit[16] = (reg_addr == DMA_TRANSFER_WIDTH_OFFSET); - addr_hit[17] = (reg_addr == DMA_DST_ADDR_LIMIT_LO_OFFSET); - addr_hit[18] = (reg_addr == DMA_DST_ADDR_LIMIT_HI_OFFSET); - addr_hit[19] = (reg_addr == DMA_DST_ADDR_ALMOST_LIMIT_LO_OFFSET); - addr_hit[20] = (reg_addr == DMA_DST_ADDR_ALMOST_LIMIT_HI_OFFSET); - addr_hit[21] = (reg_addr == DMA_CONTROL_OFFSET); - addr_hit[22] = (reg_addr == DMA_STATUS_OFFSET); - addr_hit[23] = (reg_addr == DMA_ERROR_CODE_OFFSET); - addr_hit[24] = (reg_addr == DMA_SHA2_DIGEST_0_OFFSET); - addr_hit[25] = (reg_addr == DMA_SHA2_DIGEST_1_OFFSET); - addr_hit[26] = (reg_addr == DMA_SHA2_DIGEST_2_OFFSET); - addr_hit[27] = (reg_addr == DMA_SHA2_DIGEST_3_OFFSET); - addr_hit[28] = (reg_addr == DMA_SHA2_DIGEST_4_OFFSET); - addr_hit[29] = (reg_addr == DMA_SHA2_DIGEST_5_OFFSET); - addr_hit[30] = (reg_addr == DMA_SHA2_DIGEST_6_OFFSET); - addr_hit[31] = (reg_addr == DMA_SHA2_DIGEST_7_OFFSET); - addr_hit[32] = (reg_addr == DMA_SHA2_DIGEST_8_OFFSET); - addr_hit[33] = (reg_addr == DMA_SHA2_DIGEST_9_OFFSET); - addr_hit[34] = (reg_addr == DMA_SHA2_DIGEST_10_OFFSET); - addr_hit[35] = (reg_addr == DMA_SHA2_DIGEST_11_OFFSET); - addr_hit[36] = (reg_addr == DMA_SHA2_DIGEST_12_OFFSET); - addr_hit[37] = (reg_addr == DMA_SHA2_DIGEST_13_OFFSET); - addr_hit[38] = (reg_addr == DMA_SHA2_DIGEST_14_OFFSET); - addr_hit[39] = (reg_addr == DMA_SHA2_DIGEST_15_OFFSET); - addr_hit[40] = (reg_addr == DMA_HANDSHAKE_INTR_ENABLE_OFFSET); - addr_hit[41] = (reg_addr == DMA_CLEAR_INTR_SRC_OFFSET); - addr_hit[42] = (reg_addr == DMA_CLEAR_INTR_BUS_OFFSET); - addr_hit[43] = (reg_addr == DMA_INTR_SRC_ADDR_0_OFFSET); - addr_hit[44] = (reg_addr == DMA_INTR_SRC_ADDR_1_OFFSET); - addr_hit[45] = (reg_addr == DMA_INTR_SRC_ADDR_2_OFFSET); - addr_hit[46] = (reg_addr == DMA_INTR_SRC_ADDR_3_OFFSET); - addr_hit[47] = (reg_addr == DMA_INTR_SRC_ADDR_4_OFFSET); - addr_hit[48] = (reg_addr == DMA_INTR_SRC_ADDR_5_OFFSET); - addr_hit[49] = (reg_addr == DMA_INTR_SRC_ADDR_6_OFFSET); - addr_hit[50] = (reg_addr == DMA_INTR_SRC_ADDR_7_OFFSET); - addr_hit[51] = (reg_addr == DMA_INTR_SRC_ADDR_8_OFFSET); - addr_hit[52] = (reg_addr == DMA_INTR_SRC_ADDR_9_OFFSET); - addr_hit[53] = (reg_addr == DMA_INTR_SRC_ADDR_10_OFFSET); - addr_hit[54] = (reg_addr == DMA_INTR_SRC_WR_VAL_0_OFFSET); - addr_hit[55] = (reg_addr == DMA_INTR_SRC_WR_VAL_1_OFFSET); - addr_hit[56] = (reg_addr == DMA_INTR_SRC_WR_VAL_2_OFFSET); - addr_hit[57] = (reg_addr == DMA_INTR_SRC_WR_VAL_3_OFFSET); - addr_hit[58] = (reg_addr == DMA_INTR_SRC_WR_VAL_4_OFFSET); - addr_hit[59] = (reg_addr == DMA_INTR_SRC_WR_VAL_5_OFFSET); - addr_hit[60] = (reg_addr == DMA_INTR_SRC_WR_VAL_6_OFFSET); - addr_hit[61] = (reg_addr == DMA_INTR_SRC_WR_VAL_7_OFFSET); - addr_hit[62] = (reg_addr == DMA_INTR_SRC_WR_VAL_8_OFFSET); - addr_hit[63] = (reg_addr == DMA_INTR_SRC_WR_VAL_9_OFFSET); - addr_hit[64] = (reg_addr == DMA_INTR_SRC_WR_VAL_10_OFFSET); + addr_hit[17] = (reg_addr == DMA_CONTROL_OFFSET); + addr_hit[18] = (reg_addr == DMA_STATUS_OFFSET); + addr_hit[19] = (reg_addr == DMA_ERROR_CODE_OFFSET); + addr_hit[20] = (reg_addr == DMA_SHA2_DIGEST_0_OFFSET); + addr_hit[21] = (reg_addr == DMA_SHA2_DIGEST_1_OFFSET); + addr_hit[22] = (reg_addr == DMA_SHA2_DIGEST_2_OFFSET); + addr_hit[23] = (reg_addr == DMA_SHA2_DIGEST_3_OFFSET); + addr_hit[24] = (reg_addr == DMA_SHA2_DIGEST_4_OFFSET); + addr_hit[25] = (reg_addr == DMA_SHA2_DIGEST_5_OFFSET); + addr_hit[26] = (reg_addr == DMA_SHA2_DIGEST_6_OFFSET); + addr_hit[27] = (reg_addr == DMA_SHA2_DIGEST_7_OFFSET); + addr_hit[28] = (reg_addr == DMA_SHA2_DIGEST_8_OFFSET); + addr_hit[29] = (reg_addr == DMA_SHA2_DIGEST_9_OFFSET); + addr_hit[30] = (reg_addr == DMA_SHA2_DIGEST_10_OFFSET); + addr_hit[31] = (reg_addr == DMA_SHA2_DIGEST_11_OFFSET); + addr_hit[32] = (reg_addr == DMA_SHA2_DIGEST_12_OFFSET); + addr_hit[33] = (reg_addr == DMA_SHA2_DIGEST_13_OFFSET); + addr_hit[34] = (reg_addr == DMA_SHA2_DIGEST_14_OFFSET); + addr_hit[35] = (reg_addr == DMA_SHA2_DIGEST_15_OFFSET); + addr_hit[36] = (reg_addr == DMA_HANDSHAKE_INTR_ENABLE_OFFSET); + addr_hit[37] = (reg_addr == DMA_CLEAR_INTR_SRC_OFFSET); + addr_hit[38] = (reg_addr == DMA_CLEAR_INTR_BUS_OFFSET); + addr_hit[39] = (reg_addr == DMA_INTR_SRC_ADDR_0_OFFSET); + addr_hit[40] = (reg_addr == DMA_INTR_SRC_ADDR_1_OFFSET); + addr_hit[41] = (reg_addr == DMA_INTR_SRC_ADDR_2_OFFSET); + addr_hit[42] = (reg_addr == DMA_INTR_SRC_ADDR_3_OFFSET); + addr_hit[43] = (reg_addr == DMA_INTR_SRC_ADDR_4_OFFSET); + addr_hit[44] = (reg_addr == DMA_INTR_SRC_ADDR_5_OFFSET); + addr_hit[45] = (reg_addr == DMA_INTR_SRC_ADDR_6_OFFSET); + addr_hit[46] = (reg_addr == DMA_INTR_SRC_ADDR_7_OFFSET); + addr_hit[47] = (reg_addr == DMA_INTR_SRC_ADDR_8_OFFSET); + addr_hit[48] = (reg_addr == DMA_INTR_SRC_ADDR_9_OFFSET); + addr_hit[49] = (reg_addr == DMA_INTR_SRC_ADDR_10_OFFSET); + addr_hit[50] = (reg_addr == DMA_INTR_SRC_WR_VAL_0_OFFSET); + addr_hit[51] = (reg_addr == DMA_INTR_SRC_WR_VAL_1_OFFSET); + addr_hit[52] = (reg_addr == DMA_INTR_SRC_WR_VAL_2_OFFSET); + addr_hit[53] = (reg_addr == DMA_INTR_SRC_WR_VAL_3_OFFSET); + addr_hit[54] = (reg_addr == DMA_INTR_SRC_WR_VAL_4_OFFSET); + addr_hit[55] = (reg_addr == DMA_INTR_SRC_WR_VAL_5_OFFSET); + addr_hit[56] = (reg_addr == DMA_INTR_SRC_WR_VAL_6_OFFSET); + addr_hit[57] = (reg_addr == DMA_INTR_SRC_WR_VAL_7_OFFSET); + addr_hit[58] = (reg_addr == DMA_INTR_SRC_WR_VAL_8_OFFSET); + addr_hit[59] = (reg_addr == DMA_INTR_SRC_WR_VAL_9_OFFSET); + addr_hit[60] = (reg_addr == DMA_INTR_SRC_WR_VAL_10_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -3197,11 +2974,7 @@ module dma_reg_top ( (addr_hit[57] & (|(DMA_PERMIT[57] & ~reg_be))) | (addr_hit[58] & (|(DMA_PERMIT[58] & ~reg_be))) | (addr_hit[59] & (|(DMA_PERMIT[59] & ~reg_be))) | - (addr_hit[60] & (|(DMA_PERMIT[60] & ~reg_be))) | - (addr_hit[61] & (|(DMA_PERMIT[61] & ~reg_be))) | - (addr_hit[62] & (|(DMA_PERMIT[62] & ~reg_be))) | - (addr_hit[63] & (|(DMA_PERMIT[63] & ~reg_be))) | - (addr_hit[64] & (|(DMA_PERMIT[64] & ~reg_be))))); + (addr_hit[60] & (|(DMA_PERMIT[60] & ~reg_be))))); end // Generate write-enables @@ -3210,22 +2983,16 @@ module dma_reg_top ( assign intr_state_dma_done_wd = reg_wdata[0]; assign intr_state_dma_error_wd = reg_wdata[1]; - - assign intr_state_dma_memory_buffer_limit_wd = reg_wdata[2]; assign intr_enable_we = addr_hit[1] & reg_we & !reg_error; assign intr_enable_dma_done_wd = reg_wdata[0]; assign intr_enable_dma_error_wd = reg_wdata[1]; - - assign intr_enable_dma_memory_buffer_limit_wd = reg_wdata[2]; assign intr_test_we = addr_hit[2] & reg_we & !reg_error; assign intr_test_dma_done_wd = reg_wdata[0]; assign intr_test_dma_error_wd = reg_wdata[1]; - - assign intr_test_dma_memory_buffer_limit_wd = reg_wdata[2]; assign alert_test_we = addr_hit[3] & reg_we & !reg_error; assign alert_test_wd = reg_wdata[0]; @@ -3268,19 +3035,7 @@ module dma_reg_top ( assign transfer_width_we = addr_hit[16] & reg_we & !reg_error; assign transfer_width_wd = reg_wdata[1:0]; - assign dst_addr_limit_lo_we = addr_hit[17] & reg_we & !reg_error; - - assign dst_addr_limit_lo_wd = reg_wdata[31:0]; - assign dst_addr_limit_hi_we = addr_hit[18] & reg_we & !reg_error; - - assign dst_addr_limit_hi_wd = reg_wdata[31:0]; - assign dst_addr_almost_limit_lo_we = addr_hit[19] & reg_we & !reg_error; - - assign dst_addr_almost_limit_lo_wd = reg_wdata[31:0]; - assign dst_addr_almost_limit_hi_we = addr_hit[20] & reg_we & !reg_error; - - assign dst_addr_almost_limit_hi_wd = reg_wdata[31:0]; - assign control_we = addr_hit[21] & reg_we & !reg_error; + assign control_we = addr_hit[17] & reg_we & !reg_error; assign control_opcode_wd = reg_wdata[3:0]; @@ -3297,86 +3052,86 @@ module dma_reg_top ( assign control_abort_wd = reg_wdata[27]; assign control_go_wd = reg_wdata[31]; - assign status_we = addr_hit[22] & reg_we & !reg_error; + assign status_we = addr_hit[18] & reg_we & !reg_error; assign status_done_wd = reg_wdata[1]; assign status_aborted_wd = reg_wdata[2]; assign status_error_wd = reg_wdata[3]; - assign handshake_intr_enable_we = addr_hit[40] & reg_we & !reg_error; + assign handshake_intr_enable_we = addr_hit[36] & reg_we & !reg_error; assign handshake_intr_enable_wd = reg_wdata[10:0]; - assign clear_intr_src_we = addr_hit[41] & reg_we & !reg_error; + assign clear_intr_src_we = addr_hit[37] & reg_we & !reg_error; assign clear_intr_src_wd = reg_wdata[10:0]; - assign clear_intr_bus_we = addr_hit[42] & reg_we & !reg_error; + assign clear_intr_bus_we = addr_hit[38] & reg_we & !reg_error; assign clear_intr_bus_wd = reg_wdata[10:0]; - assign intr_src_addr_0_we = addr_hit[43] & reg_we & !reg_error; + assign intr_src_addr_0_we = addr_hit[39] & reg_we & !reg_error; assign intr_src_addr_0_wd = reg_wdata[31:0]; - assign intr_src_addr_1_we = addr_hit[44] & reg_we & !reg_error; + assign intr_src_addr_1_we = addr_hit[40] & reg_we & !reg_error; assign intr_src_addr_1_wd = reg_wdata[31:0]; - assign intr_src_addr_2_we = addr_hit[45] & reg_we & !reg_error; + assign intr_src_addr_2_we = addr_hit[41] & reg_we & !reg_error; assign intr_src_addr_2_wd = reg_wdata[31:0]; - assign intr_src_addr_3_we = addr_hit[46] & reg_we & !reg_error; + assign intr_src_addr_3_we = addr_hit[42] & reg_we & !reg_error; assign intr_src_addr_3_wd = reg_wdata[31:0]; - assign intr_src_addr_4_we = addr_hit[47] & reg_we & !reg_error; + assign intr_src_addr_4_we = addr_hit[43] & reg_we & !reg_error; assign intr_src_addr_4_wd = reg_wdata[31:0]; - assign intr_src_addr_5_we = addr_hit[48] & reg_we & !reg_error; + assign intr_src_addr_5_we = addr_hit[44] & reg_we & !reg_error; assign intr_src_addr_5_wd = reg_wdata[31:0]; - assign intr_src_addr_6_we = addr_hit[49] & reg_we & !reg_error; + assign intr_src_addr_6_we = addr_hit[45] & reg_we & !reg_error; assign intr_src_addr_6_wd = reg_wdata[31:0]; - assign intr_src_addr_7_we = addr_hit[50] & reg_we & !reg_error; + assign intr_src_addr_7_we = addr_hit[46] & reg_we & !reg_error; assign intr_src_addr_7_wd = reg_wdata[31:0]; - assign intr_src_addr_8_we = addr_hit[51] & reg_we & !reg_error; + assign intr_src_addr_8_we = addr_hit[47] & reg_we & !reg_error; assign intr_src_addr_8_wd = reg_wdata[31:0]; - assign intr_src_addr_9_we = addr_hit[52] & reg_we & !reg_error; + assign intr_src_addr_9_we = addr_hit[48] & reg_we & !reg_error; assign intr_src_addr_9_wd = reg_wdata[31:0]; - assign intr_src_addr_10_we = addr_hit[53] & reg_we & !reg_error; + assign intr_src_addr_10_we = addr_hit[49] & reg_we & !reg_error; assign intr_src_addr_10_wd = reg_wdata[31:0]; - assign intr_src_wr_val_0_we = addr_hit[54] & reg_we & !reg_error; + assign intr_src_wr_val_0_we = addr_hit[50] & reg_we & !reg_error; assign intr_src_wr_val_0_wd = reg_wdata[31:0]; - assign intr_src_wr_val_1_we = addr_hit[55] & reg_we & !reg_error; + assign intr_src_wr_val_1_we = addr_hit[51] & reg_we & !reg_error; assign intr_src_wr_val_1_wd = reg_wdata[31:0]; - assign intr_src_wr_val_2_we = addr_hit[56] & reg_we & !reg_error; + assign intr_src_wr_val_2_we = addr_hit[52] & reg_we & !reg_error; assign intr_src_wr_val_2_wd = reg_wdata[31:0]; - assign intr_src_wr_val_3_we = addr_hit[57] & reg_we & !reg_error; + assign intr_src_wr_val_3_we = addr_hit[53] & reg_we & !reg_error; assign intr_src_wr_val_3_wd = reg_wdata[31:0]; - assign intr_src_wr_val_4_we = addr_hit[58] & reg_we & !reg_error; + assign intr_src_wr_val_4_we = addr_hit[54] & reg_we & !reg_error; assign intr_src_wr_val_4_wd = reg_wdata[31:0]; - assign intr_src_wr_val_5_we = addr_hit[59] & reg_we & !reg_error; + assign intr_src_wr_val_5_we = addr_hit[55] & reg_we & !reg_error; assign intr_src_wr_val_5_wd = reg_wdata[31:0]; - assign intr_src_wr_val_6_we = addr_hit[60] & reg_we & !reg_error; + assign intr_src_wr_val_6_we = addr_hit[56] & reg_we & !reg_error; assign intr_src_wr_val_6_wd = reg_wdata[31:0]; - assign intr_src_wr_val_7_we = addr_hit[61] & reg_we & !reg_error; + assign intr_src_wr_val_7_we = addr_hit[57] & reg_we & !reg_error; assign intr_src_wr_val_7_wd = reg_wdata[31:0]; - assign intr_src_wr_val_8_we = addr_hit[62] & reg_we & !reg_error; + assign intr_src_wr_val_8_we = addr_hit[58] & reg_we & !reg_error; assign intr_src_wr_val_8_wd = reg_wdata[31:0]; - assign intr_src_wr_val_9_we = addr_hit[63] & reg_we & !reg_error; + assign intr_src_wr_val_9_we = addr_hit[59] & reg_we & !reg_error; assign intr_src_wr_val_9_wd = reg_wdata[31:0]; - assign intr_src_wr_val_10_we = addr_hit[64] & reg_we & !reg_error; + assign intr_src_wr_val_10_we = addr_hit[60] & reg_we & !reg_error; assign intr_src_wr_val_10_wd = reg_wdata[31:0]; @@ -3400,12 +3155,12 @@ module dma_reg_top ( reg_we_check[14] = total_data_size_gated_we; reg_we_check[15] = chunk_data_size_gated_we; reg_we_check[16] = transfer_width_gated_we; - reg_we_check[17] = dst_addr_limit_lo_gated_we; - reg_we_check[18] = dst_addr_limit_hi_gated_we; - reg_we_check[19] = dst_addr_almost_limit_lo_gated_we; - reg_we_check[20] = dst_addr_almost_limit_hi_gated_we; - reg_we_check[21] = control_we; - reg_we_check[22] = status_we; + reg_we_check[17] = control_we; + reg_we_check[18] = status_we; + reg_we_check[19] = 1'b0; + reg_we_check[20] = 1'b0; + reg_we_check[21] = 1'b0; + reg_we_check[22] = 1'b0; reg_we_check[23] = 1'b0; reg_we_check[24] = 1'b0; reg_we_check[25] = 1'b0; @@ -3419,35 +3174,31 @@ module dma_reg_top ( reg_we_check[33] = 1'b0; reg_we_check[34] = 1'b0; reg_we_check[35] = 1'b0; - reg_we_check[36] = 1'b0; - reg_we_check[37] = 1'b0; - reg_we_check[38] = 1'b0; - reg_we_check[39] = 1'b0; - reg_we_check[40] = handshake_intr_enable_gated_we; - reg_we_check[41] = clear_intr_src_gated_we; - reg_we_check[42] = clear_intr_bus_gated_we; - reg_we_check[43] = intr_src_addr_0_gated_we; - reg_we_check[44] = intr_src_addr_1_gated_we; - reg_we_check[45] = intr_src_addr_2_gated_we; - reg_we_check[46] = intr_src_addr_3_gated_we; - reg_we_check[47] = intr_src_addr_4_gated_we; - reg_we_check[48] = intr_src_addr_5_gated_we; - reg_we_check[49] = intr_src_addr_6_gated_we; - reg_we_check[50] = intr_src_addr_7_gated_we; - reg_we_check[51] = intr_src_addr_8_gated_we; - reg_we_check[52] = intr_src_addr_9_gated_we; - reg_we_check[53] = intr_src_addr_10_gated_we; - reg_we_check[54] = intr_src_wr_val_0_gated_we; - reg_we_check[55] = intr_src_wr_val_1_gated_we; - reg_we_check[56] = intr_src_wr_val_2_gated_we; - reg_we_check[57] = intr_src_wr_val_3_gated_we; - reg_we_check[58] = intr_src_wr_val_4_gated_we; - reg_we_check[59] = intr_src_wr_val_5_gated_we; - reg_we_check[60] = intr_src_wr_val_6_gated_we; - reg_we_check[61] = intr_src_wr_val_7_gated_we; - reg_we_check[62] = intr_src_wr_val_8_gated_we; - reg_we_check[63] = intr_src_wr_val_9_gated_we; - reg_we_check[64] = intr_src_wr_val_10_gated_we; + reg_we_check[36] = handshake_intr_enable_gated_we; + reg_we_check[37] = clear_intr_src_gated_we; + reg_we_check[38] = clear_intr_bus_gated_we; + reg_we_check[39] = intr_src_addr_0_gated_we; + reg_we_check[40] = intr_src_addr_1_gated_we; + reg_we_check[41] = intr_src_addr_2_gated_we; + reg_we_check[42] = intr_src_addr_3_gated_we; + reg_we_check[43] = intr_src_addr_4_gated_we; + reg_we_check[44] = intr_src_addr_5_gated_we; + reg_we_check[45] = intr_src_addr_6_gated_we; + reg_we_check[46] = intr_src_addr_7_gated_we; + reg_we_check[47] = intr_src_addr_8_gated_we; + reg_we_check[48] = intr_src_addr_9_gated_we; + reg_we_check[49] = intr_src_addr_10_gated_we; + reg_we_check[50] = intr_src_wr_val_0_gated_we; + reg_we_check[51] = intr_src_wr_val_1_gated_we; + reg_we_check[52] = intr_src_wr_val_2_gated_we; + reg_we_check[53] = intr_src_wr_val_3_gated_we; + reg_we_check[54] = intr_src_wr_val_4_gated_we; + reg_we_check[55] = intr_src_wr_val_5_gated_we; + reg_we_check[56] = intr_src_wr_val_6_gated_we; + reg_we_check[57] = intr_src_wr_val_7_gated_we; + reg_we_check[58] = intr_src_wr_val_8_gated_we; + reg_we_check[59] = intr_src_wr_val_9_gated_we; + reg_we_check[60] = intr_src_wr_val_10_gated_we; end // Read data return @@ -3457,19 +3208,16 @@ module dma_reg_top ( addr_hit[0]: begin reg_rdata_next[0] = intr_state_dma_done_qs; reg_rdata_next[1] = intr_state_dma_error_qs; - reg_rdata_next[2] = intr_state_dma_memory_buffer_limit_qs; end addr_hit[1]: begin reg_rdata_next[0] = intr_enable_dma_done_qs; reg_rdata_next[1] = intr_enable_dma_error_qs; - reg_rdata_next[2] = intr_enable_dma_memory_buffer_limit_qs; end addr_hit[2]: begin reg_rdata_next[0] = '0; reg_rdata_next[1] = '0; - reg_rdata_next[2] = '0; end addr_hit[3]: begin @@ -3530,22 +3278,6 @@ module dma_reg_top ( end addr_hit[17]: begin - reg_rdata_next[31:0] = dst_addr_limit_lo_qs; - end - - addr_hit[18]: begin - reg_rdata_next[31:0] = dst_addr_limit_hi_qs; - end - - addr_hit[19]: begin - reg_rdata_next[31:0] = dst_addr_almost_limit_lo_qs; - end - - addr_hit[20]: begin - reg_rdata_next[31:0] = dst_addr_almost_limit_hi_qs; - end - - addr_hit[21]: begin reg_rdata_next[3:0] = control_opcode_qs; reg_rdata_next[4] = control_hardware_handshake_enable_qs; reg_rdata_next[5] = control_memory_buffer_auto_increment_enable_qs; @@ -3556,7 +3288,7 @@ module dma_reg_top ( reg_rdata_next[31] = control_go_qs; end - addr_hit[22]: begin + addr_hit[18]: begin reg_rdata_next[0] = status_busy_qs; reg_rdata_next[1] = status_done_qs; reg_rdata_next[2] = status_aborted_qs; @@ -3564,7 +3296,7 @@ module dma_reg_top ( reg_rdata_next[4] = status_sha2_digest_valid_qs; end - addr_hit[23]: begin + addr_hit[19]: begin reg_rdata_next[0] = error_code_src_addr_error_qs; reg_rdata_next[1] = error_code_dst_addr_error_qs; reg_rdata_next[2] = error_code_opcode_error_qs; @@ -3575,167 +3307,167 @@ module dma_reg_top ( reg_rdata_next[7] = error_code_asid_error_qs; end - addr_hit[24]: begin + addr_hit[20]: begin reg_rdata_next[31:0] = sha2_digest_0_qs; end - addr_hit[25]: begin + addr_hit[21]: begin reg_rdata_next[31:0] = sha2_digest_1_qs; end - addr_hit[26]: begin + addr_hit[22]: begin reg_rdata_next[31:0] = sha2_digest_2_qs; end - addr_hit[27]: begin + addr_hit[23]: begin reg_rdata_next[31:0] = sha2_digest_3_qs; end - addr_hit[28]: begin + addr_hit[24]: begin reg_rdata_next[31:0] = sha2_digest_4_qs; end - addr_hit[29]: begin + addr_hit[25]: begin reg_rdata_next[31:0] = sha2_digest_5_qs; end - addr_hit[30]: begin + addr_hit[26]: begin reg_rdata_next[31:0] = sha2_digest_6_qs; end - addr_hit[31]: begin + addr_hit[27]: begin reg_rdata_next[31:0] = sha2_digest_7_qs; end - addr_hit[32]: begin + addr_hit[28]: begin reg_rdata_next[31:0] = sha2_digest_8_qs; end - addr_hit[33]: begin + addr_hit[29]: begin reg_rdata_next[31:0] = sha2_digest_9_qs; end - addr_hit[34]: begin + addr_hit[30]: begin reg_rdata_next[31:0] = sha2_digest_10_qs; end - addr_hit[35]: begin + addr_hit[31]: begin reg_rdata_next[31:0] = sha2_digest_11_qs; end - addr_hit[36]: begin + addr_hit[32]: begin reg_rdata_next[31:0] = sha2_digest_12_qs; end - addr_hit[37]: begin + addr_hit[33]: begin reg_rdata_next[31:0] = sha2_digest_13_qs; end - addr_hit[38]: begin + addr_hit[34]: begin reg_rdata_next[31:0] = sha2_digest_14_qs; end - addr_hit[39]: begin + addr_hit[35]: begin reg_rdata_next[31:0] = sha2_digest_15_qs; end - addr_hit[40]: begin + addr_hit[36]: begin reg_rdata_next[10:0] = handshake_intr_enable_qs; end - addr_hit[41]: begin + addr_hit[37]: begin reg_rdata_next[10:0] = clear_intr_src_qs; end - addr_hit[42]: begin + addr_hit[38]: begin reg_rdata_next[10:0] = clear_intr_bus_qs; end - addr_hit[43]: begin + addr_hit[39]: begin reg_rdata_next[31:0] = intr_src_addr_0_qs; end - addr_hit[44]: begin + addr_hit[40]: begin reg_rdata_next[31:0] = intr_src_addr_1_qs; end - addr_hit[45]: begin + addr_hit[41]: begin reg_rdata_next[31:0] = intr_src_addr_2_qs; end - addr_hit[46]: begin + addr_hit[42]: begin reg_rdata_next[31:0] = intr_src_addr_3_qs; end - addr_hit[47]: begin + addr_hit[43]: begin reg_rdata_next[31:0] = intr_src_addr_4_qs; end - addr_hit[48]: begin + addr_hit[44]: begin reg_rdata_next[31:0] = intr_src_addr_5_qs; end - addr_hit[49]: begin + addr_hit[45]: begin reg_rdata_next[31:0] = intr_src_addr_6_qs; end - addr_hit[50]: begin + addr_hit[46]: begin reg_rdata_next[31:0] = intr_src_addr_7_qs; end - addr_hit[51]: begin + addr_hit[47]: begin reg_rdata_next[31:0] = intr_src_addr_8_qs; end - addr_hit[52]: begin + addr_hit[48]: begin reg_rdata_next[31:0] = intr_src_addr_9_qs; end - addr_hit[53]: begin + addr_hit[49]: begin reg_rdata_next[31:0] = intr_src_addr_10_qs; end - addr_hit[54]: begin + addr_hit[50]: begin reg_rdata_next[31:0] = intr_src_wr_val_0_qs; end - addr_hit[55]: begin + addr_hit[51]: begin reg_rdata_next[31:0] = intr_src_wr_val_1_qs; end - addr_hit[56]: begin + addr_hit[52]: begin reg_rdata_next[31:0] = intr_src_wr_val_2_qs; end - addr_hit[57]: begin + addr_hit[53]: begin reg_rdata_next[31:0] = intr_src_wr_val_3_qs; end - addr_hit[58]: begin + addr_hit[54]: begin reg_rdata_next[31:0] = intr_src_wr_val_4_qs; end - addr_hit[59]: begin + addr_hit[55]: begin reg_rdata_next[31:0] = intr_src_wr_val_5_qs; end - addr_hit[60]: begin + addr_hit[56]: begin reg_rdata_next[31:0] = intr_src_wr_val_6_qs; end - addr_hit[61]: begin + addr_hit[57]: begin reg_rdata_next[31:0] = intr_src_wr_val_7_qs; end - addr_hit[62]: begin + addr_hit[58]: begin reg_rdata_next[31:0] = intr_src_wr_val_8_qs; end - addr_hit[63]: begin + addr_hit[59]: begin reg_rdata_next[31:0] = intr_src_wr_val_9_qs; end - addr_hit[64]: begin + addr_hit[60]: begin reg_rdata_next[31:0] = intr_src_wr_val_10_qs; end diff --git a/sw/ip/dma/dif/autogen/dif_dma_autogen.c b/sw/ip/dma/dif/autogen/dif_dma_autogen.c index 81a86a35bf2064..e17010dd974eab 100644 --- a/sw/ip/dma/dif/autogen/dif_dma_autogen.c +++ b/sw/ip/dma/dif/autogen/dif_dma_autogen.c @@ -57,9 +57,6 @@ static bool dma_get_irq_bit_index(dif_dma_irq_t irq, case kDifDmaIrqDmaError: *index_out = DMA_INTR_COMMON_DMA_ERROR_BIT; break; - case kDifDmaIrqDmaMemoryBufferLimit: - *index_out = DMA_INTR_COMMON_DMA_MEMORY_BUFFER_LIMIT_BIT; - break; default: return false; } @@ -70,14 +67,12 @@ static bool dma_get_irq_bit_index(dif_dma_irq_t irq, static dif_irq_type_t irq_types[] = { kDifIrqTypeEvent, kDifIrqTypeEvent, - kDifIrqTypeEvent, }; OT_WARN_UNUSED_RESULT dif_result_t dif_dma_irq_get_type(const dif_dma_t *dma, dif_dma_irq_t irq, dif_irq_type_t *type) { - if (dma == NULL || type == NULL || - irq == kDifDmaIrqDmaMemoryBufferLimit + 1) { + if (dma == NULL || type == NULL || irq == kDifDmaIrqDmaError + 1) { return kDifBadArg; } diff --git a/sw/ip/dma/dif/autogen/dif_dma_autogen.h b/sw/ip/dma/dif/autogen/dif_dma_autogen.h index ddb34525303959..7637a9d9d81542 100644 --- a/sw/ip/dma/dif/autogen/dif_dma_autogen.h +++ b/sw/ip/dma/dif/autogen/dif_dma_autogen.h @@ -82,10 +82,6 @@ typedef enum dif_dma_irq { * DMA error has occurred. DMA_STATUS.error_code register shows the details. */ kDifDmaIrqDmaError = 1, - /** - * Memory buffer limit address reached. - */ - kDifDmaIrqDmaMemoryBufferLimit = 2, } dif_dma_irq_t; /** diff --git a/sw/ip/dma/dif/autogen/dif_dma_autogen_unittest.cc b/sw/ip/dma/dif/autogen/dif_dma_autogen_unittest.cc index 0489632d7be181..7d814e966c2fb4 100644 --- a/sw/ip/dma/dif/autogen/dif_dma_autogen_unittest.cc +++ b/sw/ip/dma/dif/autogen/dif_dma_autogen_unittest.cc @@ -70,8 +70,7 @@ TEST_F(IrqGetTypeTest, BadIrq) { dif_irq_type_t type; EXPECT_DIF_BADARG(dif_dma_irq_get_type( - &dma_, static_cast(kDifDmaIrqDmaMemoryBufferLimit + 1), - &type)); + &dma_, static_cast(kDifDmaIrqDmaError + 1), &type)); } TEST_F(IrqGetTypeTest, Success) { @@ -144,9 +143,8 @@ TEST_F(IrqIsPendingTest, Success) { // Get the last IRQ state. irq_state = true; EXPECT_READ32(DMA_INTR_STATE_REG_OFFSET, - {{DMA_INTR_STATE_DMA_MEMORY_BUFFER_LIMIT_BIT, false}}); - EXPECT_DIF_OK(dif_dma_irq_is_pending(&dma_, kDifDmaIrqDmaMemoryBufferLimit, - &irq_state)); + {{DMA_INTR_STATE_DMA_ERROR_BIT, false}}); + EXPECT_DIF_OK(dif_dma_irq_is_pending(&dma_, kDifDmaIrqDmaError, &irq_state)); EXPECT_FALSE(irq_state); } @@ -158,7 +156,7 @@ TEST_F(AcknowledgeStateTest, NullArgs) { } TEST_F(AcknowledgeStateTest, AckSnapshot) { - const uint32_t num_irqs = 3; + const uint32_t num_irqs = 2; const uint32_t irq_mask = (1u << num_irqs) - 1; dif_dma_irq_state_snapshot_t irq_snapshot = 1; @@ -211,8 +209,8 @@ TEST_F(IrqAcknowledgeTest, Success) { // Clear the last IRQ state. EXPECT_WRITE32(DMA_INTR_STATE_REG_OFFSET, - {{DMA_INTR_STATE_DMA_MEMORY_BUFFER_LIMIT_BIT, true}}); - EXPECT_DIF_OK(dif_dma_irq_acknowledge(&dma_, kDifDmaIrqDmaMemoryBufferLimit)); + {{DMA_INTR_STATE_DMA_ERROR_BIT, true}}); + EXPECT_DIF_OK(dif_dma_irq_acknowledge(&dma_, kDifDmaIrqDmaError)); } class IrqForceTest : public DmaTest {}; @@ -234,8 +232,8 @@ TEST_F(IrqForceTest, Success) { // Force last IRQ. EXPECT_WRITE32(DMA_INTR_TEST_REG_OFFSET, - {{DMA_INTR_TEST_DMA_MEMORY_BUFFER_LIMIT_BIT, true}}); - EXPECT_DIF_OK(dif_dma_irq_force(&dma_, kDifDmaIrqDmaMemoryBufferLimit, true)); + {{DMA_INTR_TEST_DMA_ERROR_BIT, true}}); + EXPECT_DIF_OK(dif_dma_irq_force(&dma_, kDifDmaIrqDmaError, true)); } class IrqGetEnabledTest : public DmaTest {}; @@ -272,9 +270,8 @@ TEST_F(IrqGetEnabledTest, Success) { // Last IRQ is disabled. irq_state = kDifToggleEnabled; EXPECT_READ32(DMA_INTR_ENABLE_REG_OFFSET, - {{DMA_INTR_ENABLE_DMA_MEMORY_BUFFER_LIMIT_BIT, false}}); - EXPECT_DIF_OK(dif_dma_irq_get_enabled(&dma_, kDifDmaIrqDmaMemoryBufferLimit, - &irq_state)); + {{DMA_INTR_ENABLE_DMA_ERROR_BIT, false}}); + EXPECT_DIF_OK(dif_dma_irq_get_enabled(&dma_, kDifDmaIrqDmaError, &irq_state)); EXPECT_EQ(irq_state, kDifToggleDisabled); } @@ -306,9 +303,8 @@ TEST_F(IrqSetEnabledTest, Success) { // Disable last IRQ. irq_state = kDifToggleDisabled; EXPECT_MASK32(DMA_INTR_ENABLE_REG_OFFSET, - {{DMA_INTR_ENABLE_DMA_MEMORY_BUFFER_LIMIT_BIT, 0x1, false}}); - EXPECT_DIF_OK(dif_dma_irq_set_enabled(&dma_, kDifDmaIrqDmaMemoryBufferLimit, - irq_state)); + {{DMA_INTR_ENABLE_DMA_ERROR_BIT, 0x1, false}}); + EXPECT_DIF_OK(dif_dma_irq_set_enabled(&dma_, kDifDmaIrqDmaError, irq_state)); } class IrqDisableAllTest : public DmaTest {}; diff --git a/sw/ip/dma/dif/dif_dma.c b/sw/ip/dma/dif/dif_dma.c index 9f070f5ba1b06a..364faac3371b56 100644 --- a/sw/ip/dma/dif/dif_dma.c +++ b/sw/ip/dma/dif/dif_dma.c @@ -176,45 +176,6 @@ dif_result_t dif_dma_is_memory_range_valid(const dif_dma_t *dma, return kDifOk; } -dif_result_t dif_dma_irq_thresholds_set(const dif_dma_t *dma, - uint64_t almost_limit, uint64_t limit) { - if (dma == NULL || almost_limit > limit) { - return kDifBadArg; - } - - mmio_region_write32(dma->base_addr, DMA_DST_ADDR_ALMOST_LIMIT_LO_REG_OFFSET, - almost_limit & UINT32_MAX); - mmio_region_write32(dma->base_addr, DMA_DST_ADDR_ALMOST_LIMIT_HI_REG_OFFSET, - almost_limit >> (sizeof(uint32_t) * 8)); - - mmio_region_write32(dma->base_addr, DMA_DST_ADDR_LIMIT_LO_REG_OFFSET, - limit & UINT32_MAX); - mmio_region_write32(dma->base_addr, DMA_DST_ADDR_LIMIT_HI_REG_OFFSET, - limit >> (sizeof(uint32_t) * 8)); - - return kDifOk; -} - -dif_result_t dif_dma_irq_thresholds_get(const dif_dma_t *dma, - uint64_t *almost_limit, - uint64_t *limit) { - if (dma == NULL || almost_limit == NULL || limit == NULL) { - return kDifBadArg; - } - - uint64_t val_lo = mmio_region_read32(dma->base_addr, - DMA_DST_ADDR_ALMOST_LIMIT_LO_REG_OFFSET); - uint64_t val_hi = mmio_region_read32(dma->base_addr, - DMA_DST_ADDR_ALMOST_LIMIT_HI_REG_OFFSET); - *almost_limit = val_lo | (val_hi << (sizeof(uint32_t) * 8)); - - val_lo = mmio_region_read32(dma->base_addr, DMA_DST_ADDR_LIMIT_LO_REG_OFFSET); - val_hi = mmio_region_read32(dma->base_addr, DMA_DST_ADDR_LIMIT_HI_REG_OFFSET); - *limit = val_lo | (val_hi << (sizeof(uint32_t) * 8)); - - return kDifOk; -} - dif_result_t dif_dma_status_get(const dif_dma_t *dma, dif_dma_status_t *status) { if (dma == NULL || status == NULL) { diff --git a/sw/ip/dma/dif/dif_dma.h b/sw/ip/dma/dif/dif_dma.h index fa0ed05d3fc531..bf58bad4096ab4 100644 --- a/sw/ip/dma/dif/dif_dma.h +++ b/sw/ip/dma/dif/dif_dma.h @@ -94,11 +94,7 @@ dif_result_t dif_dma_configure(const dif_dma_t *dma, */ typedef struct dif_dma_handshake { /* Auto Increments the memory buffer address register by total data size to - * point to the next memory buffer address. Generate a warning (assert - * interrupt) if the auto-incremented address reaches the threshold set in - * DMAC Memory Buffer Almost Limit Threshold Register to prevent destination - * buffer overflow. Enables firmware to take appropriate action prior to - * reaching the limit */ + * point to the next memory buffer address.*/ bool memory_auto_increment; /* If `true`, reads/writes from/to incremental addresses for FIFO data @@ -217,42 +213,6 @@ OT_WARN_UNUSED_RESULT dif_result_t dif_dma_is_memory_range_valid(const dif_dma_t *dma, bool *is_valid); -/** - * Set thresholds for detecting the level of the buffer.Used in conjunction with - * the address auto-increment mode for hardware handshake operation to generate - * an interrupt when the buffer address approaches to the buffer address limit. - * - * This function is expected to be called when `memory_auto_increment` is - * enabled via the function `dif_dma_handshake_enable`. - * - * @param dma A DMA Controller handle. - * @param almost_limit Threshold for detecting that the buffer limit is - * approaching to prevent destination buffer overflow. - * @param limit Threshold for detecting the buffer limit. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_result_t dif_dma_irq_thresholds_set(const dif_dma_t *dma, - uint64_t almost_limit, uint64_t limit); - -/** - * Set thresholds for detecting the level of the buffer.Used in conjunction with - * the address auto-increment mode for hardware handshake operation to generate - * an interrupt when the buffer address approaches to the buffer address limit. - * - * This function is expected to be called when `memory_auto_increment` is - * enabled via the function `dif_dma_handshake_enable`. - * - * @param dma A DMA Controller handle. - * @param[out] almost_limit Out-param for the almost limit address. - * @param[out] limit Out-param for the limit address. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_result_t dif_dma_irq_thresholds_get(const dif_dma_t *dma, - uint64_t *almost_limit, - uint64_t *limit); - typedef enum dif_dma_status_code { // DMA operation is active. kDifDmaStatusBusy = 0x01 << DMA_STATUS_BUSY_BIT, diff --git a/sw/ip/dma/dif/dif_dma_unittest.cc b/sw/ip/dma/dif/dif_dma_unittest.cc index 18393aa11d2978..84535fe021d6d5 100644 --- a/sw/ip/dma/dif/dif_dma_unittest.cc +++ b/sw/ip/dma/dif/dif_dma_unittest.cc @@ -297,46 +297,7 @@ TEST_F(MemoryRangeLockTest, GetBadArg) { EXPECT_DIF_BADARG(dif_dma_is_memory_range_locked(&dma_, nullptr)); } -// DMA thresholds tests -class IrqThresholdsTest : public DmaTestInitialized {}; - -TEST_F(IrqThresholdsTest, SetSuccess) { - EXPECT_WRITE32(DMA_DST_ADDR_ALMOST_LIMIT_LO_REG_OFFSET, 0x9000F000); - EXPECT_WRITE32(DMA_DST_ADDR_ALMOST_LIMIT_HI_REG_OFFSET, 0x80001000); - EXPECT_WRITE32(DMA_DST_ADDR_LIMIT_LO_REG_OFFSET, 0xE0005000); - EXPECT_WRITE32(DMA_DST_ADDR_LIMIT_HI_REG_OFFSET, 0xF0001000); - - EXPECT_DIF_OK(dif_dma_irq_thresholds_set(&dma_, 0x800010009000F000, - 0xF0001000E0005000)); -} - -TEST_F(IrqThresholdsTest, GetSuccess) { - EXPECT_READ32(DMA_DST_ADDR_ALMOST_LIMIT_LO_REG_OFFSET, 0x9000F000); - EXPECT_READ32(DMA_DST_ADDR_ALMOST_LIMIT_HI_REG_OFFSET, 0x80001000); - EXPECT_READ32(DMA_DST_ADDR_LIMIT_LO_REG_OFFSET, 0xE0005000); - EXPECT_READ32(DMA_DST_ADDR_LIMIT_HI_REG_OFFSET, 0xF0001000); - - uint64_t almost = 0; - uint64_t limit = 0; - - EXPECT_DIF_OK(dif_dma_irq_thresholds_get(&dma_, &almost, &limit)); - EXPECT_EQ(almost, 0x800010009000F000); - EXPECT_EQ(limit, 0xF0001000E0005000); -} - -TEST_F(IrqThresholdsTest, SetBadArg) { - EXPECT_DIF_BADARG(dif_dma_irq_thresholds_set(nullptr, 0, 0)); - EXPECT_DIF_BADARG(dif_dma_irq_thresholds_set(&dma_, 1, 0)); -} - -TEST_F(IrqThresholdsTest, GetBadArg) { - uint64_t dummy; - EXPECT_DIF_BADARG(dif_dma_irq_thresholds_get(nullptr, &dummy, &dummy)); - EXPECT_DIF_BADARG(dif_dma_irq_thresholds_get(&dma_, nullptr, &dummy)); - EXPECT_DIF_BADARG(dif_dma_irq_thresholds_get(&dma_, &dummy, nullptr)); -} - -// DMA thresholds tests +// DMA status tests typedef struct status_reg { uint32_t reg; dif_dma_status_t status;