diff --git a/azure-pipelines.yml b/azure-pipelines.yml
index 282766edc4bba4..eb36283f6e44b0 100644
--- a/azure-pipelines.yml
+++ b/azure-pipelines.yml
@@ -306,6 +306,12 @@ jobs:
     displayName: Display environment
   - bash: ci/scripts/build-chip-verilator.sh englishbreakfast
     displayName: Build simulation with Verilator
+  - bash: |
+      tar -C $OBJ_DIR -czf $(Pipeline.Workspace)/obj_dir.tar.gz .
+      displayName: Pack up obj_dir
+  - publish: $(Pipeline.Workspace)/obj_dir.tar.gz .
+    artifact: obj-dir
+    displayName: Upload obj_dir
   - template: ci/upload-artifacts-template.yml
     parameters:
       includePatterns:
diff --git a/ci/scripts/build-chip-verilator.sh b/ci/scripts/build-chip-verilator.sh
index 1d6d374b2b880d..dc6088855d7e52 100755
--- a/ci/scripts/build-chip-verilator.sh
+++ b/ci/scripts/build-chip-verilator.sh
@@ -20,14 +20,14 @@ case "$tl" in
     earlgrey)
         fileset=fileset_top
         fusesoc_core=lowrisc:dv:chip_verilator_sim
-        vname=Vchip_sim_tb
+#        vname=Vchip_sim_tb
         verilator_options="--threads 4"
         make_options="-j 4"
         ;;
     englishbreakfast)
         fileset=fileset_topgen
         fusesoc_core=lowrisc:systems:chip_englishbreakfast_verilator
-        vname=Vchip_englishbreakfast_verilator
+#        vname=Vchip_englishbreakfast_verilator
         # Englishbreakfast on CI runs on a 2-core CPU
         verilator_options="--threads 2"
         make_options="-j 2"
@@ -48,12 +48,14 @@ set -x
 mkdir -p "$OBJ_DIR/hw"
 mkdir -p "$BIN_DIR/hw/top_${tl}"
 
+# Remove --build to capture the generated artifacts, or just set default target
 fusesoc --cores-root=. \
-  run --flag=$fileset --target=sim --setup --build \
+  run --flag=$fileset --target=default --setup --build \
   --build-root="$OBJ_DIR/hw" \
+  --tool verilator \
   $fusesoc_core \
   --verilator_options="${verilator_options}" \
   --make_options="${make_options}"
 
-cp "$OBJ_DIR/hw/sim-verilator/${vname}" \
-   "$BIN_DIR/hw/top_${tl}/Vchip_${tl}_verilator"
+#cp "$OBJ_DIR/hw/sim-verilator/${vname}" \
+#   "$BIN_DIR/hw/top_${tl}/Vchip_${tl}_verilator"
diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
index b5aae5dd471a02..769e184d1a2615 100644
--- a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
+++ b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
@@ -257,7 +257,7 @@
       param_decl: {
         SecCheck: "0",
       }
-      attr: "templated",
+      attr: "ipgen",
     },
     { name: "clkmgr_aon",
       type: "clkmgr",
diff --git a/hw/top_englishbreakfast/util/prepare_sw.py b/hw/top_englishbreakfast/util/prepare_sw.py
index f5c3451f599a78..a55c7903741dce 100755
--- a/hw/top_englishbreakfast/util/prepare_sw.py
+++ b/hw/top_englishbreakfast/util/prepare_sw.py
@@ -145,7 +145,7 @@ def main():
         'ip/clkmgr/data/autogen/clkmgr.hjson',
         'ip/flash_ctrl/data/autogen/flash_ctrl.hjson',
         'ip_autogen/pwrmgr/data/pwrmgr.hjson',
-        'ip/rstmgr/data/autogen/rstmgr.hjson',
+        'ip_autogen/rstmgr/data/rstmgr.hjson',
         'ip/pinmux/data/autogen/pinmux.hjson',
         'ip_autogen/rv_plic/data/rv_plic.hjson',
         'ip/ast/data/ast.hjson',
diff --git a/topgen-reg-only.core b/topgen-reg-only.core
index b9853b19f2be43..d0c80452e3e802 100644
--- a/topgen-reg-only.core
+++ b/topgen-reg-only.core
@@ -11,7 +11,6 @@ filesets:
       - lowrisc:ip:clkmgr_reggen
       - lowrisc:ip:flash_ctrl_reggen
       - lowrisc:ip:pinmux_reggen
-      - lowrisc:ip:rstmgr_reggen
 
 targets:
   default: &default
diff --git a/util/topgen-fusesoc.py b/util/topgen-fusesoc.py
index 61114341d8104e..367b1fe13f1d52 100755
--- a/util/topgen-fusesoc.py
+++ b/util/topgen-fusesoc.py
@@ -75,11 +75,10 @@ def main():
         'clkmgr': '',
         'flash_ctrl': '_core',
         'pinmux': '',
-        'rstmgr': '',
     }
 
     # reg-only
-    for ip in ['clkmgr', 'flash_ctrl', 'pinmux', 'rstmgr']:
+    for ip in ['clkmgr', 'flash_ctrl', 'pinmux']:
         core_filepath = os.path.abspath(os.path.join(files_out, 'generated-%s.core' % ip))
         name = 'lowrisc:ip:%s_reggen' % ip,
         files = ['ip/%s/rtl/autogen/%s_reg_pkg.sv' % (ip, ip),
@@ -126,7 +125,7 @@ def main():
                     'lowrisc:prim:util',
                     'lowrisc:ip:lc_ctrl_pkg',
                     'lowrisc:ip:pwrmgr_pkg',
-                    # rstmgr
+                    'lowrisc:ip:rstmgr_pkg',
                     'lowrisc:prim:clock_mux2',
                     # clkmgr
                     'lowrisc:prim:all',
@@ -147,8 +146,6 @@ def main():
                     'ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv',
                     'ip/flash_ctrl/rtl/autogen/flash_ctrl.sv',
                     'ip/flash_ctrl/rtl/autogen/flash_ctrl_region_cfg.sv',
-                    'ip/rstmgr/rtl/autogen/rstmgr_pkg.sv',
-                    'ip/rstmgr/rtl/autogen/rstmgr.sv',
                     # Top
                     'rtl/autogen/%s_rnd_cnst_pkg.sv' % topname,
                     'rtl/autogen/%s_pkg.sv' % topname,