diff --git a/hw/dv/dpi/spidpi/spidpi.c b/hw/dv/dpi/spidpi/spidpi.c
index 96158b21ad506f..f31634056ff904 100644
--- a/hw/dv/dpi/spidpi/spidpi.c
+++ b/hw/dv/dpi/spidpi/spidpi.c
@@ -276,12 +276,14 @@ static void xfer_respond_next_trans(void *ctx_void) {
     char value[16];
 
     strcat(ctx->xfer_buf_out, "{\"Read\":{\"data\":[");
-    for (int i = 0; i < (ctx->nmax - 1); i++) {
-      sprintf(value, "%u,", (uint8_t)ctx->buf[i]);
+    if (ctx->nmax > 0) {
+      for (int i = 0; i < (ctx->nmax - 1); i++) {
+        sprintf(value, "%u,", (uint8_t)ctx->buf[i]);
+        strcat(ctx->xfer_buf_out, value);
+      }
+      sprintf(value, "%u", (uint8_t)ctx->buf[ctx->nmax - 1]);
       strcat(ctx->xfer_buf_out, value);
     }
-    sprintf(value, "%u", (uint8_t)ctx->buf[ctx->nmax - 1]);
-    strcat(ctx->xfer_buf_out, value);
     strcat(ctx->xfer_buf_out, "]}}");
   } else {
     assert(false && "Response to No transaction not supported.");
@@ -310,7 +312,7 @@ static void xfer_respond(void *ctx_void, bool error) {
     }
   } else {
     int rv = write(ctx->host, ctx->xfer_buf_out, count);
-    assert(rv == 1 && "write() failed.");
+    assert(rv == count && "write() failed.");
   }
 }
 
@@ -557,10 +559,14 @@ char spidpi_tick(void *ctx_void, const svLogicVecVal *d2p_data) {
         ctx->driving = set_sck | (ctx->driving & ~P2D_SCK);
         break;
       case SP_CSFALL:
-        // CSB low, drive SDI to first bit
-        ctx->driving =
-            (set_sck | (ctx->buf[ctx->nout] & ctx->bout) ? P2D_SDI : 0);
-        ctx->state = SP_DMOVE;
+        if (ctx->nmax > 0) {
+          // CSB low, drive SDI to first bit
+          ctx->driving =
+              (set_sck | (ctx->buf[ctx->nout] & ctx->bout) ? P2D_SDI : 0);
+          ctx->state = SP_DMOVE;
+        } else {
+          ctx->state = SP_CSRISE;
+        }
         break;
       case SP_CSRISE:
         xfer_respond_next_trans(ctx);
diff --git a/hw/top_darjeeling/dv/verilator/chip_sim_tb.sv b/hw/top_darjeeling/dv/verilator/chip_sim_tb.sv
index 26cfd0c1e454c4..4b9d9a4a14b0d8 100644
--- a/hw/top_darjeeling/dv/verilator/chip_sim_tb.sv
+++ b/hw/top_darjeeling/dv/verilator/chip_sim_tb.sv
@@ -63,7 +63,7 @@ module chip_sim_tb (
     .FREQ('d500_000)
   ) u_uart (
     .clk_i  (clk_i),
-    .rst_ni (rst_ni),
+    .rst_ni (cio_gpio_rst_n),
     .tx_o   (cio_uart_rx_p2d),
     .rx_i   (cio_uart_tx_d2p)
   );
diff --git a/sw/host/opentitanlib/src/transport/verilator/transport.rs b/sw/host/opentitanlib/src/transport/verilator/transport.rs
index eb2b07a1be15ba..8e26495e953346 100644
--- a/sw/host/opentitanlib/src/transport/verilator/transport.rs
+++ b/sw/host/opentitanlib/src/transport/verilator/transport.rs
@@ -12,6 +12,7 @@ use std::rc::Rc;
 use std::time::{Duration, Instant};
 
 use crate::io::gpio::{GpioError, GpioPin};
+use crate::io::jtag::{Jtag, JtagParams};
 use crate::io::spi::Target;
 use crate::io::uart::Uart;
 use crate::transport::verilator::gpio::{GpioInner, VerilatorGpioPin};
@@ -21,9 +22,8 @@ use crate::transport::verilator::uart::VerilatorUart;
 use crate::transport::{
     Capabilities, Capability, Transport, TransportError, TransportInterfaceType,
 };
-use crate::util::parse_int::ParseInt;
-use crate::io::jtag::{Jtag, JtagParams};
 use crate::util::openocd::OpenOcdServer;
+use crate::util::parse_int::ParseInt;
 
 pub(crate) struct Inner {
     uart: Option<Rc<dyn Uart>>,
diff --git a/sw/host/opentitanlib/src/transport/verilator/uart.rs b/sw/host/opentitanlib/src/transport/verilator/uart.rs
index 88673d8c257bef..7267ac98afa586 100644
--- a/sw/host/opentitanlib/src/transport/verilator/uart.rs
+++ b/sw/host/opentitanlib/src/transport/verilator/uart.rs
@@ -9,7 +9,7 @@ use std::fs::File;
 use std::fs::OpenOptions;
 use std::io;
 use std::io::{ErrorKind, Read, Write};
-use std::io::{Seek, SeekFrom};
+//use std::io::{Seek, SeekFrom};
 use std::net::TcpStream;
 use std::time::Duration;
 
@@ -290,8 +290,9 @@ impl Uart for VerilatorUart {
             } else {
                 return Err(anyhow!("TCP socket not connected")).context("UART reset error");
             }
-        } else if let Some(ref ref_pipe) = self.pipe {
-            ref_pipe.borrow_mut().seek(SeekFrom::End(0))?;
+        // TODO: Seek on pipe causes error. Find a different method for draining pipe
+        } else if let Some(ref _ref_pipe) = self.pipe {
+            //ref_pipe.borrow_mut().seek(SeekFrom::End(0))?;
         } else {
             return Err(anyhow!("Pipe not opened")).context("UART reset error");
         }