diff --git a/hw/ip/prim/rtl/prim_ram_1p_adv.sv b/hw/ip/prim/rtl/prim_ram_1p_adv.sv index 73a973e3df32b8..78afeef21aa2bb 100644 --- a/hw/ip/prim/rtl/prim_ram_1p_adv.sv +++ b/hw/ip/prim/rtl/prim_ram_1p_adv.sv @@ -17,6 +17,7 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #( parameter int Depth = 512, + parameter int InstDepth = Depth, parameter int Width = 32, parameter int DataBitsPerMask = 1, // Number of data bits per bit of write mask parameter MemInitFile = "", // VMEM file to initialize the memory with @@ -32,25 +33,27 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #( // since this results in a more compact and faster implementation. parameter bit HammingECC = 0, - localparam int Aw = prim_util_pkg::vbits(Depth) + localparam int Aw = prim_util_pkg::vbits(Depth), + // Compute RAM tiling + localparam int NumRamInst = $ceil(Depth / InstDepth) ) ( input clk_i, input rst_ni, - input req_i, - input write_i, - input [Aw-1:0] addr_i, - input [Width-1:0] wdata_i, - input [Width-1:0] wmask_i, - output logic [Width-1:0] rdata_o, - output logic rvalid_o, // read response (rdata_o) is valid - output logic [1:0] rerror_o, // Bit1: Uncorrectable, Bit0: Correctable + input req_i, + input write_i, + input [Aw-1:0] addr_i, + input [Width-1:0] wdata_i, + input [Width-1:0] wmask_i, + output logic [Width-1:0] rdata_o, + output logic rvalid_o, // read response (rdata_o) is valid + output logic [1:0] rerror_o, // Bit1: Uncorrectable, Bit0: Correctable // config - input ram_1p_cfg_t cfg_i, + input ram_1p_cfg_t [NumRamInst-1:0] cfg_i, // When detecting multi-bit encoding errors, raise alert. - output logic alert_o + output logic alert_o ); import prim_mubi_pkg::mubi4_t; diff --git a/hw/ip/prim/rtl/prim_ram_1p_scr.sv b/hw/ip/prim/rtl/prim_ram_1p_scr.sv index d31a7d5ca01c9e..cd71ced68552a0 100644 --- a/hw/ip/prim/rtl/prim_ram_1p_scr.sv +++ b/hw/ip/prim/rtl/prim_ram_1p_scr.sv @@ -25,6 +25,7 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #( parameter int Depth = 16*1024, // Needs to be a power of 2 if NumAddrScrRounds > 0. + parameter int InstDepth = Depth, parameter int Width = 32, // Needs to be byte aligned if byte parity is enabled. parameter int DataBitsPerMask = 8, // Needs to be set to 8 in case of byte parity. parameter bit EnableParity = 1, // Enable byte parity. @@ -58,39 +59,41 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #( // use the same key, but they use a different IV localparam int DataKeyWidth = 128, // Each 64 bit scrambling primitive requires a 64bit IV - localparam int NonceWidth = 64 * NumParScr + localparam int NonceWidth = 64 * NumParScr, + // Compute RAM tiling + localparam int NumRamInst = $ceil(Depth / InstDepth) ) ( - input clk_i, - input rst_ni, + input clk_i, + input rst_ni, // Key interface. Memory requests will not be granted if key_valid is set to 0. - input key_valid_i, - input [DataKeyWidth-1:0] key_i, - input [NonceWidth-1:0] nonce_i, + input key_valid_i, + input [DataKeyWidth-1:0] key_i, + input [NonceWidth-1:0] nonce_i, // Interface to TL-UL SRAM adapter - input req_i, - output logic gnt_o, - input write_i, - input [AddrWidth-1:0] addr_i, - input [Width-1:0] wdata_i, - input [Width-1:0] wmask_i, // Needs to be byte-aligned for parity + input req_i, + output logic gnt_o, + input write_i, + input [AddrWidth-1:0] addr_i, + input [Width-1:0] wdata_i, + input [Width-1:0] wmask_i, // Needs to be byte-aligned for parity // On integrity errors, the primitive surpresses any real transaction to the memory. - input intg_error_i, - output logic [Width-1:0] rdata_o, - output logic rvalid_o, // Read response (rdata_o) is valid - output logic [1:0] rerror_o, // Bit1: Uncorrectable, Bit0: Correctable - output logic [31:0] raddr_o, // Read address for error reporting. + input intg_error_i, + output logic [Width-1:0] rdata_o, + output logic rvalid_o, // Read response (rdata_o) is valid + output logic [1:0] rerror_o, // Bit1: Uncorrectable, Bit0: Correctable + output logic [31:0] raddr_o, // Read address for error reporting. // config - input ram_1p_cfg_t cfg_i, + input ram_1p_cfg_t [NumRamInst-1:0] cfg_i, // Write currently pending inside this module. - output logic wr_collision_o, - output logic write_pending_o, + output logic wr_collision_o, + output logic write_pending_o, // When detecting multi-bit encoding errors, raise alert. - output logic alert_o + output logic alert_o ); import prim_mubi_pkg::mubi4_t; @@ -481,6 +484,7 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #( prim_ram_1p_adv #( .Depth(Depth), + .InstDepth(InstDepth), .Width(Width), .DataBitsPerMask(DataBitsPerMask), .EnableECC(1'b0), diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv b/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv index d2e835ac339156..71915ef121cf62 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv @@ -9,20 +9,24 @@ module prim_generic_ram_1p import prim_ram_1p_pkg::*; #( parameter int Width = 32, // bit parameter int Depth = 128, + parameter int InstDepth = Depth, parameter int DataBitsPerMask = 1, // Number of data bits per bit of write mask parameter MemInitFile = "", // VMEM file to initialize the memory with - localparam int Aw = $clog2(Depth) // derived parameter + localparam int Aw = $clog2(Depth), // derived parameter + // Compute RAM tiling + localparam int NumRamInst = $ceil(Depth / InstDepth) ) ( - input logic clk_i, + input logic clk_i, - input logic req_i, - input logic write_i, - input logic [Aw-1:0] addr_i, - input logic [Width-1:0] wdata_i, - input logic [Width-1:0] wmask_i, - output logic [Width-1:0] rdata_o, // Read data. Data is returned one cycle after req_i is high. - input ram_1p_cfg_t cfg_i + input logic req_i, + input logic write_i, + input logic [Aw-1:0] addr_i, + input logic [Width-1:0] wdata_i, + input logic [Width-1:0] wmask_i, + output logic [Width-1:0] rdata_o, // Read data. Data is returned one cycle after req_i + // is high. + input ram_1p_cfg_t [NumRamInst-1:0] cfg_i ); // For certain synthesis experiments we compile the design with generic models to get an unmapped diff --git a/hw/ip/sram_ctrl/data/sram_ctrl.hjson b/hw/ip/sram_ctrl/data/sram_ctrl.hjson index d31d144388bd4d..424c83ddb1c878 100644 --- a/hw/ip/sram_ctrl/data/sram_ctrl.hjson +++ b/hw/ip/sram_ctrl/data/sram_ctrl.hjson @@ -79,6 +79,11 @@ type: "int", default: "0x1000" }, + { name: "InstSize", + desc: "Memory size of a single RAM tile (in bytes).", + type: "int", + default: "0x1000" + }, { name: "InstrExec", desc: "Support execution from SRAM", type: "bit", diff --git a/hw/ip/sram_ctrl/rtl/sram_ctrl.sv b/hw/ip/sram_ctrl/rtl/sram_ctrl.sv index 788e18f534442c..68e8f4d0133c65 100644 --- a/hw/ip/sram_ctrl/rtl/sram_ctrl.sv +++ b/hw/ip/sram_ctrl/rtl/sram_ctrl.sv @@ -13,6 +13,7 @@ module sram_ctrl #( // Number of words stored in the SRAM. parameter int MemSizeRam = 32'h1000, + parameter int InstSize = MemSizeRam, // Enable asynchronous transitions on alerts. parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, // Enables the execute from SRAM feature. @@ -23,40 +24,41 @@ module sram_ctrl // Setting this to 3 lowers this to approximately 7 effective rounds. parameter int NumPrinceRoundsHalf = 3, // Random netlist constants - parameter otp_ctrl_pkg::sram_key_t RndCnstSramKey = RndCnstSramKeyDefault, - parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramNonce = RndCnstSramNonceDefault, - parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, - parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault + parameter otp_ctrl_pkg::sram_key_t RndCnstSramKey = RndCnstSramKeyDefault, + parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramNonce = RndCnstSramNonceDefault, + parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, + parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault, + localparam int NumRamInst = $ceil(MemSizeRam / InstSize) ) ( // SRAM Clock - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // OTP Clock (for key interface) - input logic clk_otp_i, - input logic rst_otp_ni, + input logic clk_otp_i, + input logic rst_otp_ni, // Bus Interface (device) for SRAM - input tlul_pkg::tl_h2d_t ram_tl_i, - output tlul_pkg::tl_d2h_t ram_tl_o, + input tlul_pkg::tl_h2d_t ram_tl_i, + output tlul_pkg::tl_d2h_t ram_tl_o, // Bus Interface (device) for CSRs - input tlul_pkg::tl_h2d_t regs_tl_i, - output tlul_pkg::tl_d2h_t regs_tl_o, + input tlul_pkg::tl_h2d_t regs_tl_i, + output tlul_pkg::tl_d2h_t regs_tl_o, // Alert outputs. - input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, - output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, // Life-cycle escalation input (scraps the scrambling keys) // SEC_CM: LC_ESCALATE_EN.INTERSIG.MUBI - input lc_ctrl_pkg::lc_tx_t lc_escalate_en_i, + input lc_ctrl_pkg::lc_tx_t lc_escalate_en_i, // SEC_CM: LC_HW_DEBUG_EN.INTERSIG.MUBI - input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, + input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, // Otp configuration for sram execution // SEC_CM: EXEC.INTERSIG.MUBI - input prim_mubi_pkg::mubi8_t otp_en_sram_ifetch_i, + input prim_mubi_pkg::mubi8_t otp_en_sram_ifetch_i, // Key request to OTP (running on clk_fixed) // SEC_CM: SCRAMBLE.KEY.SIDELOAD - output otp_ctrl_pkg::sram_otp_key_req_t sram_otp_key_o, - input otp_ctrl_pkg::sram_otp_key_rsp_t sram_otp_key_i, + output otp_ctrl_pkg::sram_otp_key_req_t sram_otp_key_o, + input otp_ctrl_pkg::sram_otp_key_rsp_t sram_otp_key_i, // config - input prim_ram_1p_pkg::ram_1p_cfg_t cfg_i + input prim_ram_1p_pkg::ram_1p_cfg_t [NumRamInst-1:0] cfg_i ); import lc_ctrl_pkg::lc_tx_t; @@ -73,6 +75,7 @@ module sram_ctrl // This is later on pruned to the correct width at the SRAM wrapper interface. parameter int unsigned Depth = MemSizeRam >> 2; + parameter int unsigned InstDepth = InstSize >> 2; parameter int unsigned AddrWidth = prim_util_pkg::vbits(Depth); `ASSERT_INIT(NonceWidthsLessThanSource_A, NonceWidth + LfsrWidth <= otp_ctrl_pkg::SramNonceWidth) @@ -541,6 +544,7 @@ module sram_ctrl prim_ram_1p_scr #( .Width(DataWidth), .Depth(Depth), + .InstDepth(InstDepth), .EnableParity(0), .DataBitsPerMask(DataWidth), .NumPrinceRoundsHalf(NumPrinceRoundsHalf)