From 40ea13c6efcda449226cf615ae74c9a0f70e5f1c Mon Sep 17 00:00:00 2001 From: Neeraj Upasani Date: Tue, 16 Apr 2024 18:09:17 -0700 Subject: [PATCH] [hw,topgen] regenerated regs and top Signed-off-by: Neeraj Upasani --- .bazelrc | 3 ++ .../rtl/autogen/chip_darjeeling_asic.sv | 26 +++++++++- .../rtl/autogen/chip_darjeeling_cw310.sv | 23 --------- util/topgen/templates/chiplevel.sv.tpl | 51 +++++++++---------- 4 files changed, 53 insertions(+), 50 deletions(-) diff --git a/.bazelrc b/.bazelrc index 8404a82154a9fd..cb3c3d44ec1012 100644 --- a/.bazelrc +++ b/.bazelrc @@ -139,6 +139,9 @@ build:ubsan --linkopt -fsanitize=undefined # Enable the rust nightly toolchain build --@rules_rust//rust/toolchain/channel=nightly +#Add Centos bin link +build --@rules_rust//:extra_rustc_toolchain_dirs=/tools/foss/llvm/13.0.1/x86_64/centos.7/bin + # Configure the rust 'clippy' linter. build --aspects=@rules_rust//rust:defs.bzl%rust_clippy_aspect build --output_groups=+clippy_checks diff --git a/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv index b865840d5f9b12..afaa723a42da9d 100644 --- a/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv +++ b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv @@ -1515,6 +1515,30 @@ module chip_darjeeling_asic #( assign soc_recov_alert_req = {soc_proxy_pkg::NumRecovExternalAlerts{soc_proxy_pkg::SOC_ALERT_REQ_DEFAULT}}; + logic internal_request_d, internal_request_q; + logic external_reset, count_up; + logic [3:0] count; + assign internal_request_d = pwrmgr_boot_status.light_reset_req; + always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin : extrst + if (!por_n[0]) begin + external_reset <= 1'b0; + internal_request_q <= 1'b0; + count_up <= '0; + count <= '0; + end else begin + internal_request_q <= internal_request_d; + if (!internal_request_q && internal_request_d) begin + count_up <= 1'b1; + external_reset <= 1; + end else if (count == 'd8) begin + count_up <= 0; + external_reset <= 0; + count <= '0; + end else if (count_up) + count <= count + 1; + end + end : extrst + ////////////////////// // Top-level design // ////////////////////// @@ -1565,7 +1589,7 @@ module chip_darjeeling_asic #( .soc_intr_async_i ( '0 ), .soc_wkup_async_i ( 1'b0 ), // FIXME: Needs better loopback fix - .soc_rst_req_async_i ( pwrmgr_boot_status.light_reset_req), + .soc_rst_req_async_i ( external_reset ), // FIXME_END .soc_lsio_trigger_i ( '0 ), .entropy_src_hw_if_req_o ( entropy_src_hw_if_req ), diff --git a/hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv index a67bea62f417c2..9b28f0721dd118 100644 --- a/hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv +++ b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv @@ -1363,29 +1363,6 @@ module chip_darjeeling_cw310 #( assign srst_n = manual_in_por_button_n; - logic internal_request_d, internal_request_q; - logic external_reset, count_up; - logic [3:0] count; - assign internal_request_d = pwrmgr_boot_status.light_reset_req; - always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin : extrst - if (!por_n[0]) begin - external_reset <= 1'b0; - internal_request_q <= 1'b0; - count_up <= '0; - count <= '0; - end else begin - internal_request_q <= internal_request_d; - if (!internal_request_q && internal_request_d) begin - count_up <= 1'b1; - external_reset <= 1; - end else if (count == 'd8) begin - count_up <= 0; - external_reset <= 0; - count <= '0; - end else if (count_up) - count <= count + 1; - end - end : extrst ////////////////////// // Top-level design // diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl index d660f8c8c9fd40..5e793154d6f707 100644 --- a/util/topgen/templates/chiplevel.sv.tpl +++ b/util/topgen/templates/chiplevel.sv.tpl @@ -1223,6 +1223,30 @@ module chip_${top["name"]}_${target["name"]} #( {soc_proxy_pkg::NumFatalExternalAlerts{soc_proxy_pkg::SOC_ALERT_REQ_DEFAULT}}; assign soc_recov_alert_req = {soc_proxy_pkg::NumRecovExternalAlerts{soc_proxy_pkg::SOC_ALERT_REQ_DEFAULT}}; + + logic internal_request_d, internal_request_q; + logic external_reset, count_up; + logic [3:0] count; + assign internal_request_d = pwrmgr_boot_status.light_reset_req; + always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin : extrst + if (!por_n[0]) begin + external_reset <= 1'b0; + internal_request_q <= 1'b0; + count_up <= '0; + count <= '0; + end else begin + internal_request_q <= internal_request_d; + if (!internal_request_q && internal_request_d) begin + count_up <= 1'b1; + external_reset <= 1; + end else if (count == 'd8) begin + count_up <= 0; + external_reset <= 0; + count <= '0; + end else if (count_up) + count <= count + 1; + end + end : extrst % endif ////////////////////// @@ -1297,7 +1321,7 @@ module chip_${top["name"]}_${target["name"]} #( .soc_intr_async_i ( '0 ), .soc_wkup_async_i ( 1'b0 ), // FIXME: Needs better loopback fix - .soc_rst_req_async_i ( pwrmgr_boot_status.light_reset_req), + .soc_rst_req_async_i ( external_reset ), // FIXME_END .soc_lsio_trigger_i ( '0 ), .entropy_src_hw_if_req_o ( entropy_src_hw_if_req ), @@ -1442,31 +1466,6 @@ module chip_${top["name"]}_${target["name"]} #( assign otp_obs_o = '0; % endif - % if top["name"] == "darjeeling": - logic internal_request_d, internal_request_q; - logic external_reset, count_up; - logic [3:0] count; - assign internal_request_d = pwrmgr_boot_status.light_reset_req; - always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin : extrst - if (!por_n[0]) begin - external_reset <= 1'b0; - internal_request_q <= 1'b0; - count_up <= '0; - count <= '0; - end else begin - internal_request_q <= internal_request_d; - if (!internal_request_q && internal_request_d) begin - count_up <= 1'b1; - external_reset <= 1; - end else if (count == 'd8) begin - count_up <= 0; - external_reset <= 0; - count <= '0; - end else if (count_up) - count <= count + 1; - end - end : extrst - % endif ////////////////////// // Top-level design //