From 3c455ebafdc68a7b6ea67470968b303e5af2e86a Mon Sep 17 00:00:00 2001 From: Guillermo Maturana Date: Thu, 31 Oct 2024 15:30:22 -0700 Subject: [PATCH] [doc,cmdgen] Remove text bracketed by BEGIN and END CMDGEN I verified the resulting generated md files are unchanged. This requires running make -C hw, followed by cmdgen.py for the affected generated files. Signed-off-by: Guillermo Maturana --- hw/ip_templates/clkmgr/doc/interfaces.md.tpl | 55 - hw/ip_templates/clkmgr/doc/registers.md.tpl | 506 ---- .../flash_ctrl/doc/interfaces.md.tpl | 100 - .../flash_ctrl/doc/registers.md.tpl | 2107 ----------------- hw/ip_templates/pwrmgr/doc/interfaces.md.tpl | 63 - hw/ip_templates/pwrmgr/doc/registers.md.tpl | 431 ---- hw/ip_templates/rstmgr/doc/interfaces.md.tpl | 41 - hw/ip_templates/rstmgr/doc/registers.md.tpl | 332 --- 8 files changed, 3635 deletions(-) diff --git a/hw/ip_templates/clkmgr/doc/interfaces.md.tpl b/hw/ip_templates/clkmgr/doc/interfaces.md.tpl index c2af68209224c7..5933ea916b0adf 100644 --- a/hw/ip_templates/clkmgr/doc/interfaces.md.tpl +++ b/hw/ip_templates/clkmgr/doc/interfaces.md.tpl @@ -1,59 +1,4 @@ # Hardware Interfaces -Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`clkmgr`** has the following hardware interfaces defined -- Primary Clock: **`clk_i`** -- Other Clocks: **`clk_main_i`**, **`clk_io_i`**, **`clk_usb_i`**, **`clk_aon_i`**, **`clk_io_div2_i`**, **`clk_io_div4_i`** -- Bus Device Interfaces (TL-UL): **`tl`** -- Bus Host Interfaces (TL-UL): *none* -- Peripheral Pins for Chip IO: *none* -- Interrupts: *none* - -${"##"} [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) - -| Port Name | Package::Struct | Type | Act | Width | Description | -|:------------------|:-------------------------|:--------|:------|--------:|:---------------------------------------------------------| -| clocks | clkmgr_pkg::clkmgr_out | uni | req | 1 | | -| cg_en | clkmgr_pkg::clkmgr_cg_en | uni | req | 1 | | -| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| io_clk_byp_req | prim_mubi_pkg::mubi4 | uni | req | 1 | | -| io_clk_byp_ack | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | -| all_clk_byp_req | prim_mubi_pkg::mubi4 | uni | req | 1 | | -| all_clk_byp_ack | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | -| hi_speed_sel | prim_mubi_pkg::mubi4 | uni | req | 1 | | -| div_step_down_req | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | -| lc_clk_byp_req | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_clk_byp_ack | lc_ctrl_pkg::lc_tx | uni | req | 1 | | -| jitter_en | prim_mubi_pkg::mubi4 | uni | req | 1 | | -| pwr | pwr_clk | req_rsp | rsp | 1 | | -| idle | prim_mubi_pkg::mubi4 | uni | rcv | 4 | | -| calib_rdy | prim_mubi_pkg::mubi4 | uni | rcv | 1 | Indicates clocks are calibrated and frequencies accurate | -| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | - -${"##"} Security Alerts - -| Alert Name | Description | -|:-------------|:----------------------------------------------------------------------------------| -| recov_fault | This recoverable alert is triggered when there are measurement errors. | -| fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. | - -${"##"} Security Countermeasures - -| Countermeasure ID | Description | -|:-------------------------------------------|:-------------------------------------------------------------| -| CLKMGR.BUS.INTEGRITY | End-to-end bus integrity scheme. | -| CLKMGR.TIMEOUT.CLK.BKGN_CHK | Background check for clock timeout. | -| CLKMGR.MEAS.CLK.BKGN_CHK | Background check for clock frequency. | -| CLKMGR.MEAS.CONFIG.SHADOW | Measurement configurations are shadowed. | -| CLKMGR.IDLE.INTERSIG.MUBI | Idle inputs are multibit encoded. | -| CLKMGR.LC_CTRL.INTERSIG.MUBI | The life cycle control signals are multibit encoded. | -| CLKMGR.LC_CTRL_CLK_HANDSHAKE.INTERSIG.MUBI | The life cycle clock req/ack signals are multibit encoded. | -| CLKMGR.CLK_HANDSHAKE.INTERSIG.MUBI | The external clock req/ack signals are multibit encoded. | -| CLKMGR.DIV.INTERSIG.MUBI | Divider step down request is multibit encoded. | -| CLKMGR.JITTER.CONFIG.MUBI | The jitter enable configuration is multibit encoded. | -| CLKMGR.IDLE.CTR.REDUN | Idle counter is duplicated. | -| CLKMGR.MEAS.CONFIG.REGWEN | The measurement controls protected with regwen. | -| CLKMGR.CLK_CTRL.CONFIG.REGWEN | Software controlled clock requests are proteced with regwen. | - - diff --git a/hw/ip_templates/clkmgr/doc/registers.md.tpl b/hw/ip_templates/clkmgr/doc/registers.md.tpl index 97acd1e8857d0a..d0d335bd759510 100644 --- a/hw/ip_templates/clkmgr/doc/registers.md.tpl +++ b/hw/ip_templates/clkmgr/doc/registers.md.tpl @@ -1,510 +1,4 @@ # Registers -${"##"} Summary - -| Name | Offset | Length | Description | -|:-------------------------------------------------------------------|:---------|---------:|:---------------------------------------------------------------------------| -| clkmgr.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register | -| clkmgr.[`EXTCLK_CTRL_REGWEN`](#extclk_ctrl_regwen) | 0x4 | 4 | External clock control write enable | -| clkmgr.[`EXTCLK_CTRL`](#extclk_ctrl) | 0x8 | 4 | Select external clock | -| clkmgr.[`EXTCLK_STATUS`](#extclk_status) | 0xc | 4 | Status of requested external clock switch | -| clkmgr.[`JITTER_REGWEN`](#jitter_regwen) | 0x10 | 4 | Jitter write enable | -| clkmgr.[`JITTER_ENABLE`](#jitter_enable) | 0x14 | 4 | Enable jittery clock | -| clkmgr.[`CLK_ENABLES`](#clk_enables) | 0x18 | 4 | Clock enable for software gateable clocks. | -| clkmgr.[`CLK_HINTS`](#clk_hints) | 0x1c | 4 | Clock hint for software gateable transactional clocks during active mode. | -| clkmgr.[`CLK_HINTS_STATUS`](#clk_hints_status) | 0x20 | 4 | Since the final state of !!CLK_HINTS is not always determined by software, | -| clkmgr.[`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) | 0x24 | 4 | Measurement control write enable | -| clkmgr.[`IO_MEAS_CTRL_EN`](#io_meas_ctrl_en) | 0x28 | 4 | Enable for measurement control | -| clkmgr.[`IO_MEAS_CTRL_SHADOWED`](#io_meas_ctrl_shadowed) | 0x2c | 4 | Configuration controls for io measurement. | -| clkmgr.[`IO_DIV2_MEAS_CTRL_EN`](#io_div2_meas_ctrl_en) | 0x30 | 4 | Enable for measurement control | -| clkmgr.[`IO_DIV2_MEAS_CTRL_SHADOWED`](#io_div2_meas_ctrl_shadowed) | 0x34 | 4 | Configuration controls for io_div2 measurement. | -| clkmgr.[`IO_DIV4_MEAS_CTRL_EN`](#io_div4_meas_ctrl_en) | 0x38 | 4 | Enable for measurement control | -| clkmgr.[`IO_DIV4_MEAS_CTRL_SHADOWED`](#io_div4_meas_ctrl_shadowed) | 0x3c | 4 | Configuration controls for io_div4 measurement. | -| clkmgr.[`MAIN_MEAS_CTRL_EN`](#main_meas_ctrl_en) | 0x40 | 4 | Enable for measurement control | -| clkmgr.[`MAIN_MEAS_CTRL_SHADOWED`](#main_meas_ctrl_shadowed) | 0x44 | 4 | Configuration controls for main measurement. | -| clkmgr.[`USB_MEAS_CTRL_EN`](#usb_meas_ctrl_en) | 0x48 | 4 | Enable for measurement control | -| clkmgr.[`USB_MEAS_CTRL_SHADOWED`](#usb_meas_ctrl_shadowed) | 0x4c | 4 | Configuration controls for usb measurement. | -| clkmgr.[`RECOV_ERR_CODE`](#recov_err_code) | 0x50 | 4 | Recoverable Error code | -| clkmgr.[`FATAL_ERR_CODE`](#fatal_err_code) | 0x54 | 4 | Error code | - -${"##"} ALERT_TEST -Alert Test Register -- Offset: `0x0` -- Reset default: `0x0` -- Reset mask: `0x3` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "recov_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------|:-------------------------------------------------| -| 31:2 | | | | Reserved | -| 1 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. | -| 0 | wo | 0x0 | recov_fault | Write 1 to trigger one alert event of this kind. | - -${"##"} EXTCLK_CTRL_REGWEN -External clock control write enable -- Offset: `0x4` -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | rw0c | 0x1 | EN | When 1, the value of [`EXTCLK_CTRL`](#extclk_ctrl) can be set. When 0, writes to [`EXTCLK_CTRL`](#extclk_ctrl) have no effect. | - -${"##"} EXTCLK_CTRL -Select external clock -- Offset: `0x8` -- Reset default: `0x99` -- Reset mask: `0xff` -- Register enable: [`EXTCLK_CTRL_REGWEN`](#extclk_ctrl_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "SEL", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HI_SPEED_SEL", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------------------------| -| 31:8 | | | Reserved | -| 7:4 | rw | 0x9 | [HI_SPEED_SEL](#extclk_ctrl--hi_speed_sel) | -| 3:0 | rw | 0x9 | [SEL](#extclk_ctrl--sel) | - -${"###"} EXTCLK_CTRL . HI_SPEED_SEL -A value of kMultiBitBool4True selects nominal speed external clock. -All other values selects low speed clocks. - -Note this field only has an effect when the [`EXTCLK_CTRL.SEL`](#extclk_ctrl) field is set to -kMultiBitBool4True. - -Nominal speed means the external clock is approximately the same frequency as -the internal oscillator source. When this option is used, all clocks operate -at roughly the nominal frequency. - -Low speed means the external clock is approximately half the frequency of the -internal oscillator source. When this option is used, the internal dividers are -stepped down. As a result, previously undivided clocks now run at half frequency, -while previously divided clocks run at roughly the nominal frequency. - -See external clock switch support in documentation for more details. - -${"###"} EXTCLK_CTRL . SEL -When the current value is not kMultiBitBool4True, writing a value of kMultiBitBool4True -selects external clock as clock for the system. Writing any other value has -no impact. - -When the current value is kMultiBitBool4True, writing a value of kMultiBitBool4False -selects internal clock as clock for the system. Writing any other value during this stage -has no impact. - -While this register can always be programmed, it only takes effect when debug functions are enabled -in life cycle TEST, DEV or RMA states. - -${"##"} EXTCLK_STATUS -Status of requested external clock switch -- Offset: `0xc` -- Reset default: `0x9` -- Reset mask: `0xf` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "ACK", "bits": 4, "attr": ["ro"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:---------------------------| -| 31:4 | | | Reserved | -| 3:0 | ro | 0x9 | [ACK](#extclk_status--ack) | - -${"###"} EXTCLK_STATUS . ACK -When [`EXTCLK_CTRL.SEL`](#extclk_ctrl) is set to kMultiBitBool4True, this field reflects -whether the clock has been switched the external source. - -kMultiBitBool4True indicates the switch is complete. -kMultiBitBool4False indicates the switch is either not possible or still ongoing. - -${"##"} JITTER_REGWEN -Jitter write enable -- Offset: `0x10` -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | rw0c | 0x1 | EN | When 1, the value of [`JITTER_ENABLE`](#jitter_enable) can be changed. When 0, writes have no effect. | - -${"##"} JITTER_ENABLE -Enable jittery clock -- Offset: `0x14` -- Reset default: `0x9` -- Reset mask: `0xf` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "VAL", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------| -| 31:4 | | | | Reserved | -| 3:0 | rw | 0x9 | VAL | Enable jittery clock. A value of kMultiBitBool4False disables the jittery clock, while all other values enable jittery clock. | - -${"##"} CLK_ENABLES -Clock enable for software gateable clocks. -These clocks are directly controlled by software. -- Offset: `0x18` -- Reset default: `0xf` -- Reset mask: `0xf` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "CLK_IO_DIV4_PERI_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_IO_DIV2_PERI_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_IO_PERI_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_USB_PERI_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:--------------------|:---------------------------------------------------------------| -| 31:4 | | | | Reserved | -| 3 | rw | 0x1 | CLK_USB_PERI_EN | 0 CLK_USB_PERI is disabled. 1 CLK_USB_PERI is enabled. | -| 2 | rw | 0x1 | CLK_IO_PERI_EN | 0 CLK_IO_PERI is disabled. 1 CLK_IO_PERI is enabled. | -| 1 | rw | 0x1 | CLK_IO_DIV2_PERI_EN | 0 CLK_IO_DIV2_PERI is disabled. 1 CLK_IO_DIV2_PERI is enabled. | -| 0 | rw | 0x1 | CLK_IO_DIV4_PERI_EN | 0 CLK_IO_DIV4_PERI is disabled. 1 CLK_IO_DIV4_PERI is enabled. | - -${"##"} CLK_HINTS -Clock hint for software gateable transactional clocks during active mode. -During low power mode, all clocks are gated off regardless of the software hint. - -Transactional clocks are not fully controlled by software. Instead software provides only a disable hint. - -When software provides a disable hint, the clock manager checks to see if the associated hardware block is idle. -If the hardware block is idle, then the clock is disabled. -If the hardware block is not idle, the clock is kept on. - -For the enable case, the software hint is immediately honored and the clock turned on. Hardware does not provide any -feedback in this case. -- Offset: `0x1c` -- Reset default: `0xf` -- Reset mask: `0xf` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "CLK_MAIN_AES_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_OTBN_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------------------|:-------------------------------------------------------------| -| 31:4 | | | | Reserved | -| 3 | rw | 0x1 | CLK_MAIN_OTBN_HINT | 0 CLK_MAIN_OTBN can be disabled. 1 CLK_MAIN_OTBN is enabled. | -| 2 | rw | 0x1 | CLK_MAIN_KMAC_HINT | 0 CLK_MAIN_KMAC can be disabled. 1 CLK_MAIN_KMAC is enabled. | -| 1 | rw | 0x1 | CLK_MAIN_HMAC_HINT | 0 CLK_MAIN_HMAC can be disabled. 1 CLK_MAIN_HMAC is enabled. | -| 0 | rw | 0x1 | CLK_MAIN_AES_HINT | 0 CLK_MAIN_AES can be disabled. 1 CLK_MAIN_AES is enabled. | - -${"##"} CLK_HINTS_STATUS -Since the final state of [`CLK_HINTS`](#clk_hints) is not always determined by software, -this register provides read feedback for the current clock state. - -- Offset: `0x20` -- Reset default: `0xf` -- Reset mask: `0xf` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "CLK_MAIN_AES_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_OTBN_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------------|:---------------------------------------------------------| -| 31:4 | | | | Reserved | -| 3 | ro | 0x1 | CLK_MAIN_OTBN_VAL | 0 CLK_MAIN_OTBN is disabled. 1 CLK_MAIN_OTBN is enabled. | -| 2 | ro | 0x1 | CLK_MAIN_KMAC_VAL | 0 CLK_MAIN_KMAC is disabled. 1 CLK_MAIN_KMAC is enabled. | -| 1 | ro | 0x1 | CLK_MAIN_HMAC_VAL | 0 CLK_MAIN_HMAC is disabled. 1 CLK_MAIN_HMAC is enabled. | -| 0 | ro | 0x1 | CLK_MAIN_AES_VAL | 0 CLK_MAIN_AES is disabled. 1 CLK_MAIN_AES is enabled. | - -${"##"} MEASURE_CTRL_REGWEN -Measurement control write enable -- Offset: `0x24` -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | rw0c | 0x1 | EN | When 1, the value of the measurement control can be set. When 0, writes have no effect. | - -${"##"} IO_MEAS_CTRL_EN -Enable for measurement control -- Offset: `0x28` -- Reset default: `0x9` -- Reset mask: `0xf` -- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:--------------------------| -| 31:4 | | | | Reserved | -| 3:0 | rw | 0x9 | EN | Enable measurement for io | - -${"##"} IO_MEAS_CTRL_SHADOWED -Configuration controls for io measurement. - -The threshold fields are made wider than required (by 1 bit) to ensure -there is room to adjust for measurement inaccuracies. -- Offset: `0x2c` -- Reset default: `0x759ea` -- Reset mask: `0xfffff` -- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "HI", "bits": 10, "attr": ["rw"], "rotate": 0}, {"name": "LO", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:---------------------------------| -| 31:20 | | | | Reserved | -| 19:10 | rw | 0x1d6 | LO | Min threshold for io measurement | -| 9:0 | rw | 0x1ea | HI | Max threshold for io measurement | - -${"##"} IO_DIV2_MEAS_CTRL_EN -Enable for measurement control -- Offset: `0x30` -- Reset default: `0x9` -- Reset mask: `0xf` -- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:-------------------------------| -| 31:4 | | | | Reserved | -| 3:0 | rw | 0x9 | EN | Enable measurement for io_div2 | - -${"##"} IO_DIV2_MEAS_CTRL_SHADOWED -Configuration controls for io_div2 measurement. - -The threshold fields are made wider than required (by 1 bit) to ensure -there is room to adjust for measurement inaccuracies. -- Offset: `0x34` -- Reset default: `0x1ccfa` -- Reset mask: `0x3ffff` -- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "HI", "bits": 9, "attr": ["rw"], "rotate": 0}, {"name": "LO", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 14}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:--------------------------------------| -| 31:18 | | | | Reserved | -| 17:9 | rw | 0xe6 | LO | Min threshold for io_div2 measurement | -| 8:0 | rw | 0xfa | HI | Max threshold for io_div2 measurement | - -${"##"} IO_DIV4_MEAS_CTRL_EN -Enable for measurement control -- Offset: `0x38` -- Reset default: `0x9` -- Reset mask: `0xf` -- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:-------------------------------| -| 31:4 | | | | Reserved | -| 3:0 | rw | 0x9 | EN | Enable measurement for io_div4 | - -${"##"} IO_DIV4_MEAS_CTRL_SHADOWED -Configuration controls for io_div4 measurement. - -The threshold fields are made wider than required (by 1 bit) to ensure -there is room to adjust for measurement inaccuracies. -- Offset: `0x3c` -- Reset default: `0x6e82` -- Reset mask: `0xffff` -- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "HI", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "LO", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:--------------------------------------| -| 31:16 | | | | Reserved | -| 15:8 | rw | 0x6e | LO | Min threshold for io_div4 measurement | -| 7:0 | rw | 0x82 | HI | Max threshold for io_div4 measurement | - -${"##"} MAIN_MEAS_CTRL_EN -Enable for measurement control -- Offset: `0x40` -- Reset default: `0x9` -- Reset mask: `0xf` -- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:----------------------------| -| 31:4 | | | | Reserved | -| 3:0 | rw | 0x9 | EN | Enable measurement for main | - -${"##"} MAIN_MEAS_CTRL_SHADOWED -Configuration controls for main measurement. - -The threshold fields are made wider than required (by 1 bit) to ensure -there is room to adjust for measurement inaccuracies. -- Offset: `0x44` -- Reset default: `0x7a9fe` -- Reset mask: `0xfffff` -- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "HI", "bits": 10, "attr": ["rw"], "rotate": 0}, {"name": "LO", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:-----------------------------------| -| 31:20 | | | | Reserved | -| 19:10 | rw | 0x1ea | LO | Min threshold for main measurement | -| 9:0 | rw | 0x1fe | HI | Max threshold for main measurement | - -${"##"} USB_MEAS_CTRL_EN -Enable for measurement control -- Offset: `0x48` -- Reset default: `0x9` -- Reset mask: `0xf` -- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:---------------------------| -| 31:4 | | | | Reserved | -| 3:0 | rw | 0x9 | EN | Enable measurement for usb | - -${"##"} USB_MEAS_CTRL_SHADOWED -Configuration controls for usb measurement. - -The threshold fields are made wider than required (by 1 bit) to ensure -there is room to adjust for measurement inaccuracies. -- Offset: `0x4c` -- Reset default: `0x1ccfa` -- Reset mask: `0x3ffff` -- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "HI", "bits": 9, "attr": ["rw"], "rotate": 0}, {"name": "LO", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 14}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:----------------------------------| -| 31:18 | | | | Reserved | -| 17:9 | rw | 0xe6 | LO | Min threshold for usb measurement | -| 8:0 | rw | 0xfa | HI | Max threshold for usb measurement | - -${"##"} RECOV_ERR_CODE -Recoverable Error code -- Offset: `0x50` -- Reset default: `0x0` -- Reset mask: `0x7ff` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "SHADOW_UPDATE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "IO_MEASURE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "IO_DIV2_MEASURE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "IO_DIV4_MEASURE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "MAIN_MEASURE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "USB_MEASURE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "IO_TIMEOUT_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "IO_DIV2_TIMEOUT_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "IO_DIV4_TIMEOUT_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "MAIN_TIMEOUT_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "USB_TIMEOUT_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:--------------------|:---------------------------------------------------------| -| 31:11 | | | | Reserved | -| 10 | rw1c | 0x0 | USB_TIMEOUT_ERR | usb has timed out. | -| 9 | rw1c | 0x0 | MAIN_TIMEOUT_ERR | main has timed out. | -| 8 | rw1c | 0x0 | IO_DIV4_TIMEOUT_ERR | io_div4 has timed out. | -| 7 | rw1c | 0x0 | IO_DIV2_TIMEOUT_ERR | io_div2 has timed out. | -| 6 | rw1c | 0x0 | IO_TIMEOUT_ERR | io has timed out. | -| 5 | rw1c | 0x0 | USB_MEASURE_ERR | usb has encountered a measurement error. | -| 4 | rw1c | 0x0 | MAIN_MEASURE_ERR | main has encountered a measurement error. | -| 3 | rw1c | 0x0 | IO_DIV4_MEASURE_ERR | io_div4 has encountered a measurement error. | -| 2 | rw1c | 0x0 | IO_DIV2_MEASURE_ERR | io_div2 has encountered a measurement error. | -| 1 | rw1c | 0x0 | IO_MEASURE_ERR | io has encountered a measurement error. | -| 0 | rw1c | 0x0 | SHADOW_UPDATE_ERR | One of the shadow registers encountered an update error. | - -${"##"} FATAL_ERR_CODE -Error code -- Offset: `0x54` -- Reset default: `0x0` -- Reset mask: `0x7` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "REG_INTG", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "IDLE_CNT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SHADOW_STORAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------------------|:---------------------------------------------------------| -| 31:3 | | | | Reserved | -| 2 | ro | 0x0 | SHADOW_STORAGE_ERR | One of the shadow registers encountered a storage error. | -| 1 | ro | 0x0 | IDLE_CNT | One of the idle counts encountered a duplicate error. | -| 0 | ro | 0x0 | REG_INTG | Register file has experienced a fatal integrity error. | - - diff --git a/hw/ip_templates/flash_ctrl/doc/interfaces.md.tpl b/hw/ip_templates/flash_ctrl/doc/interfaces.md.tpl index 4dc8a088602d75..0a344705863cad 100644 --- a/hw/ip_templates/flash_ctrl/doc/interfaces.md.tpl +++ b/hw/ip_templates/flash_ctrl/doc/interfaces.md.tpl @@ -1,106 +1,6 @@ # Interfaces -Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`flash_ctrl`** has the following hardware interfaces defined -- Primary Clock: **`clk_i`** -- Other Clocks: **`clk_otp_i`** -- Bus Device Interfaces (TL-UL): **`core_tl`**, **`prim_tl`**, **`mem_tl`** -- Bus Host Interfaces (TL-UL): *none* - -${"##"} Peripheral Pins for Chip IO - -| Pin name | Direction | Description | -|:-----------|:------------|:--------------| -| tck | input | jtag clock | -| tms | input | jtag tms | -| tdi | input | jtag input | -| tdo | output | jtag output | - -${"##"} [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) - -| Port Name | Package::Struct | Type | Act | Width | Description | -|:-------------------------|:-------------------------------|:--------|:------|--------:|:--------------| -| otp | otp_ctrl_pkg::flash_otp_key | req_rsp | req | 1 | | -| lc_nvm_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| flash_bist_enable | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | -| flash_power_down_h | logic | uni | rcv | 1 | | -| flash_power_ready_h | logic | uni | rcv | 1 | | -| flash_test_mode_a | | io | none | 2 | | -| flash_test_voltage_h | | io | none | 1 | | -| lc_creator_seed_sw_rw_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_owner_seed_sw_rw_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_iso_part_sw_rd_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_iso_part_sw_wr_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_seed_hw_rd_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| rma_req | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| rma_ack | lc_ctrl_pkg::lc_tx | uni | req | 1 | | -| rma_seed | lc_ctrl_pkg::lc_flash_rma_seed | uni | rcv | 1 | | -| pwrmgr | pwrmgr_pkg::pwr_flash | uni | req | 1 | | -| keymgr | flash_ctrl_pkg::keymgr_flash | uni | req | 1 | | -| obs_ctrl | ast_pkg::ast_obs_ctrl | uni | rcv | 1 | | -| fla_obs | logic | uni | req | 8 | | -| core_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | -| prim_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | -| mem_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | - -${"##"} Interrupts - -| Interrupt Name | Type | Description | -|:-----------------|:-------|:------------------------------| -| prog_empty | Status | Program FIFO empty | -| prog_lvl | Status | Program FIFO drained to level | -| rd_full | Status | Read FIFO full | -| rd_lvl | Status | Read FIFO filled to level | -| op_done | Event | Operation complete | -| corr_err | Event | Correctable error encountered | - -${"##"} Security Alerts - -| Alert Name | Description | -|:-----------------------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| recov_err | flash recoverable errors | -| fatal_std_err | flash standard fatal errors | -| fatal_err | Flash fatal errors including uncorrectable ECC errors. Note that this alert is not always fatal. The underlying error bits in the [`FAULT_STATUS`](registers.md#fault_status) register remain set until reset, meaning the alert keeps firing. This doesn't hold for [`FAULT_STATUS.PHY_RELBL_ERR`](registers.md#fault_status) and [`FAULT_STATUS.PHY_STORAGE_ERR.`](registers.md#fault_status) To enable firmware dealing with multi-bit ECC and ICV errors during firmware selection and verification, these error bits can be cleared. After passing this stage, it is recommended that firmware classifies the corresponding alert as fatal on the receiver end, i.e, inside the alert handler. | -| fatal_prim_flash_alert | Fatal alert triggered inside the flash primitive, including fatal TL-UL bus integrity faults of the test interface. | -| recov_prim_flash_alert | Recoverable alert triggered inside the flash primitive. | - -${"##"} Security Countermeasures - -| Countermeasure ID | Description | -|:-------------------------------------------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| FLASH_CTRL.REG.BUS.INTEGRITY | End-to-end bus integrity scheme. Since there are multiple access points for flash, please see Transmission Integrity Faults in the documentation for more details. The bus integrity scheme for flash is different from other comportable modules. | -| FLASH_CTRL.HOST.BUS.INTEGRITY | End-to-end bus integrity scheme. Since there are multiple access points for flash, please see Transmission Integrity Faults in the documentation for more details. The bus integrity scheme for flash is different from other comportable modules. | -| FLASH_CTRL.MEM.BUS.INTEGRITY | End-to-end bus integrity scheme. Since there are multiple access points for flash, please see Transmission Integrity Faults in the documentation for more details. The bus integrity scheme for flash is different from other comportable modules. | -| FLASH_CTRL.MEM.ADDR_INFECTION | On host reads, the address of the request is XORed with the data inside the read pipeline. The request address is removed from the data before returning the data over TL-UL. A mismatch triggers a data integrity error. | -| FLASH_CTRL.SCRAMBLE.KEY.SIDELOAD | The scrambling key is sideloaded from OTP and thus unreadable by SW. | -| FLASH_CTRL.LC_CTRL.INTERSIG.MUBI | Life cycle control signals are used control information partition access and flash debug access. See secret information partition, isolated information partitions and jtag connection in documentation for more details. | -| FLASH_CTRL.CTRL.CONFIG.REGWEN | Configurations cannot be changed when an operation is ongoing. | -| FLASH_CTRL.DATA_REGIONS.CONFIG.REGWEN | Each data region has a configurable regwen. | -| FLASH_CTRL.DATA_REGIONS.CONFIG.SHADOW | Data region configuration is shadowed. | -| FLASH_CTRL.INFO_REGIONS.CONFIG.REGWEN | Each info page of each type in each bank has separate regwen. | -| FLASH_CTRL.INFO_REGIONS.CONFIG.SHADOW | Each info page is shadowed. | -| FLASH_CTRL.BANK.CONFIG.REGWEN | Each bank has separate regwen for bank erase. | -| FLASH_CTRL.BANK.CONFIG.SHADOW | Each bank has separate regwen for bank erase. | -| FLASH_CTRL.MEM.CTRL.GLOBAL_ESC | Global escalation causes memory to no longer be accessible. | -| FLASH_CTRL.MEM.CTRL.LOCAL_ESC | A subset of fatal errors cause memory to no longer be accessible. This subset is defined in [`STD_FAULT_STATUS.`](registers.md#std_fault_status) | -| FLASH_CTRL.MEM_DISABLE.CONFIG.MUBI | Software control for flash disable is multibit. The register is [`DIS.`](registers.md#dis) | -| FLASH_CTRL.EXEC.CONFIG.REDUN | Software control for flash enable is 32-bit constant. The register is [`EXEC.`](registers.md#exec) | -| FLASH_CTRL.MEM.SCRAMBLE | The flash supports XEX scrambling. The cipher used is PRINCE. The scrambling scheme is enabled by software, please see flash scrambling in documentation for more details. | -| FLASH_CTRL.MEM.INTEGRITY | The flash supports two layers of ECC integrity: one layer is for integrity, and the other layer is for reliability. These ECCs are enabled and disabled together by software. Please see Flash ECC in the documentation for more details. | -| FLASH_CTRL.RMA_ENTRY.MEM.SEC_WIPE | RMA entry entry wipes flash memory with random data. | -| FLASH_CTRL.CTRL.FSM.SPARSE | RMA handling FSMs in flash_ctrl_lcmgr are sparsely encoded. FSM in flash_ctrl_arb is sparsely encoded. | -| FLASH_CTRL.PHY.FSM.SPARSE | PHY FSMs are sparsely encoded. | -| FLASH_CTRL.PHY_PROG.FSM.SPARSE | PHY program FSMs are sparsely encoded. | -| FLASH_CTRL.CTR.REDUN | flash_ctrl_lcmgr handling counters are redundantly encoded. This includes seed count and address count used during seed reading phase, as well as word count, page count and wipe index in RMA entry phase. | -| FLASH_CTRL.PHY_ARBITER.CTRL.REDUN | The phy arbiters for controller/host arbitration and in the shared scrambling module are redundant. The arbiters have two instances underneath that are constantly compared to each other. | -| FLASH_CTRL.PHY_HOST_GRANT.CTRL.CONSISTENCY | The host grant is consistency checked. If the host is ever granted with info partition access, it is an error. If the host is ever granted at the same time as a program/erase operation, it is an error. | -| FLASH_CTRL.PHY_ACK.CTRL.CONSISTENCY | If the host or controller ever receive an unexpeced transaction acknowledge, it is an error. | -| FLASH_CTRL.FIFO.CTR.REDUN | The FIFO pointers of several FIFOs are implemented with duplicate counters. | -| FLASH_CTRL.MEM_TL_LC_GATE.FSM.SPARSE | The control FSM inside the TL-UL gating primitive is sparsely encoded. | -| FLASH_CTRL.PROG_TL_LC_GATE.FSM.SPARSE | The control FSM inside the TL-UL gating primitive is sparsely encoded. | - - ${"##"} Signals diff --git a/hw/ip_templates/flash_ctrl/doc/registers.md.tpl b/hw/ip_templates/flash_ctrl/doc/registers.md.tpl index 0f763dfab2fd3a..42b7d76743aecc 100644 --- a/hw/ip_templates/flash_ctrl/doc/registers.md.tpl +++ b/hw/ip_templates/flash_ctrl/doc/registers.md.tpl @@ -4,2111 +4,4 @@ The flash protocol controller maintains two separate access windows for the FIFO It is implemented this way because the access window supports transaction back-pressure should the FIFO become full (in case of write) or empty (in case of read). -${"##"} Summary of the **`core`** interface's registers - -| Name | Offset | Length | Description | -|:-------------------------------------------------------------|:---------|---------:|:--------------------------------------------------------------| -| flash_ctrl.[`INTR_STATE`](#intr_state) | 0x0 | 4 | Interrupt State Register | -| flash_ctrl.[`INTR_ENABLE`](#intr_enable) | 0x4 | 4 | Interrupt Enable Register | -| flash_ctrl.[`INTR_TEST`](#intr_test) | 0x8 | 4 | Interrupt Test Register | -| flash_ctrl.[`ALERT_TEST`](#alert_test) | 0xc | 4 | Alert Test Register | -| flash_ctrl.[`DIS`](#dis) | 0x10 | 4 | Disable flash functionality | -| flash_ctrl.[`EXEC`](#exec) | 0x14 | 4 | Controls whether flash can be used for code execution fetches | -| flash_ctrl.[`INIT`](#init) | 0x18 | 4 | Controller init register | -| flash_ctrl.[`CTRL_REGWEN`](#ctrl_regwen) | 0x1c | 4 | Controls the configurability of the !!CONTROL register. | -| flash_ctrl.[`CONTROL`](#control) | 0x20 | 4 | Control register | -| flash_ctrl.[`ADDR`](#addr) | 0x24 | 4 | Address for flash operation | -| flash_ctrl.[`PROG_TYPE_EN`](#prog_type_en) | 0x28 | 4 | Enable different program types | -| flash_ctrl.[`ERASE_SUSPEND`](#erase_suspend) | 0x2c | 4 | Suspend erase | -| flash_ctrl.[`REGION_CFG_REGWEN_0`](#region_cfg_regwen) | 0x30 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`REGION_CFG_REGWEN_1`](#region_cfg_regwen) | 0x34 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`REGION_CFG_REGWEN_2`](#region_cfg_regwen) | 0x38 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`REGION_CFG_REGWEN_3`](#region_cfg_regwen) | 0x3c | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`REGION_CFG_REGWEN_4`](#region_cfg_regwen) | 0x40 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`REGION_CFG_REGWEN_5`](#region_cfg_regwen) | 0x44 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`REGION_CFG_REGWEN_6`](#region_cfg_regwen) | 0x48 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`REGION_CFG_REGWEN_7`](#region_cfg_regwen) | 0x4c | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`MP_REGION_CFG_0`](#mp_region_cfg) | 0x50 | 4 | Memory property configuration for data partition | -| flash_ctrl.[`MP_REGION_CFG_1`](#mp_region_cfg) | 0x54 | 4 | Memory property configuration for data partition | -| flash_ctrl.[`MP_REGION_CFG_2`](#mp_region_cfg) | 0x58 | 4 | Memory property configuration for data partition | -| flash_ctrl.[`MP_REGION_CFG_3`](#mp_region_cfg) | 0x5c | 4 | Memory property configuration for data partition | -| flash_ctrl.[`MP_REGION_CFG_4`](#mp_region_cfg) | 0x60 | 4 | Memory property configuration for data partition | -| flash_ctrl.[`MP_REGION_CFG_5`](#mp_region_cfg) | 0x64 | 4 | Memory property configuration for data partition | -| flash_ctrl.[`MP_REGION_CFG_6`](#mp_region_cfg) | 0x68 | 4 | Memory property configuration for data partition | -| flash_ctrl.[`MP_REGION_CFG_7`](#mp_region_cfg) | 0x6c | 4 | Memory property configuration for data partition | -| flash_ctrl.[`MP_REGION_0`](#mp_region) | 0x70 | 4 | Memory base and size configuration for data partition | -| flash_ctrl.[`MP_REGION_1`](#mp_region) | 0x74 | 4 | Memory base and size configuration for data partition | -| flash_ctrl.[`MP_REGION_2`](#mp_region) | 0x78 | 4 | Memory base and size configuration for data partition | -| flash_ctrl.[`MP_REGION_3`](#mp_region) | 0x7c | 4 | Memory base and size configuration for data partition | -| flash_ctrl.[`MP_REGION_4`](#mp_region) | 0x80 | 4 | Memory base and size configuration for data partition | -| flash_ctrl.[`MP_REGION_5`](#mp_region) | 0x84 | 4 | Memory base and size configuration for data partition | -| flash_ctrl.[`MP_REGION_6`](#mp_region) | 0x88 | 4 | Memory base and size configuration for data partition | -| flash_ctrl.[`MP_REGION_7`](#mp_region) | 0x8c | 4 | Memory base and size configuration for data partition | -| flash_ctrl.[`DEFAULT_REGION`](#default_region) | 0x90 | 4 | Default region properties | -| flash_ctrl.[`BANK0_INFO0_REGWEN_0`](#bank0_info0_regwen) | 0x94 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK0_INFO0_REGWEN_1`](#bank0_info0_regwen) | 0x98 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK0_INFO0_REGWEN_2`](#bank0_info0_regwen) | 0x9c | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK0_INFO0_REGWEN_3`](#bank0_info0_regwen) | 0xa0 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK0_INFO0_REGWEN_4`](#bank0_info0_regwen) | 0xa4 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK0_INFO0_REGWEN_5`](#bank0_info0_regwen) | 0xa8 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK0_INFO0_REGWEN_6`](#bank0_info0_regwen) | 0xac | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK0_INFO0_REGWEN_7`](#bank0_info0_regwen) | 0xb0 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK0_INFO0_REGWEN_8`](#bank0_info0_regwen) | 0xb4 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK0_INFO0_REGWEN_9`](#bank0_info0_regwen) | 0xb8 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK0_INFO0_PAGE_CFG_0`](#bank0_info0_page_cfg) | 0xbc | 4 | Memory property configuration for info partition in bank0, | -| flash_ctrl.[`BANK0_INFO0_PAGE_CFG_1`](#bank0_info0_page_cfg) | 0xc0 | 4 | Memory property configuration for info partition in bank0, | -| flash_ctrl.[`BANK0_INFO0_PAGE_CFG_2`](#bank0_info0_page_cfg) | 0xc4 | 4 | Memory property configuration for info partition in bank0, | -| flash_ctrl.[`BANK0_INFO0_PAGE_CFG_3`](#bank0_info0_page_cfg) | 0xc8 | 4 | Memory property configuration for info partition in bank0, | -| flash_ctrl.[`BANK0_INFO0_PAGE_CFG_4`](#bank0_info0_page_cfg) | 0xcc | 4 | Memory property configuration for info partition in bank0, | -| flash_ctrl.[`BANK0_INFO0_PAGE_CFG_5`](#bank0_info0_page_cfg) | 0xd0 | 4 | Memory property configuration for info partition in bank0, | -| flash_ctrl.[`BANK0_INFO0_PAGE_CFG_6`](#bank0_info0_page_cfg) | 0xd4 | 4 | Memory property configuration for info partition in bank0, | -| flash_ctrl.[`BANK0_INFO0_PAGE_CFG_7`](#bank0_info0_page_cfg) | 0xd8 | 4 | Memory property configuration for info partition in bank0, | -| flash_ctrl.[`BANK0_INFO0_PAGE_CFG_8`](#bank0_info0_page_cfg) | 0xdc | 4 | Memory property configuration for info partition in bank0, | -| flash_ctrl.[`BANK0_INFO0_PAGE_CFG_9`](#bank0_info0_page_cfg) | 0xe0 | 4 | Memory property configuration for info partition in bank0, | -| flash_ctrl.[`BANK0_INFO1_REGWEN`](#bank0_info1_regwen) | 0xe4 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK0_INFO1_PAGE_CFG`](#bank0_info1_page_cfg) | 0xe8 | 4 | Memory property configuration for info partition in bank0, | -| flash_ctrl.[`BANK0_INFO2_REGWEN_0`](#bank0_info2_regwen) | 0xec | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK0_INFO2_REGWEN_1`](#bank0_info2_regwen) | 0xf0 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK0_INFO2_PAGE_CFG_0`](#bank0_info2_page_cfg) | 0xf4 | 4 | Memory property configuration for info partition in bank0, | -| flash_ctrl.[`BANK0_INFO2_PAGE_CFG_1`](#bank0_info2_page_cfg) | 0xf8 | 4 | Memory property configuration for info partition in bank0, | -| flash_ctrl.[`BANK1_INFO0_REGWEN_0`](#bank1_info0_regwen) | 0xfc | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK1_INFO0_REGWEN_1`](#bank1_info0_regwen) | 0x100 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK1_INFO0_REGWEN_2`](#bank1_info0_regwen) | 0x104 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK1_INFO0_REGWEN_3`](#bank1_info0_regwen) | 0x108 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK1_INFO0_REGWEN_4`](#bank1_info0_regwen) | 0x10c | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK1_INFO0_REGWEN_5`](#bank1_info0_regwen) | 0x110 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK1_INFO0_REGWEN_6`](#bank1_info0_regwen) | 0x114 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK1_INFO0_REGWEN_7`](#bank1_info0_regwen) | 0x118 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK1_INFO0_REGWEN_8`](#bank1_info0_regwen) | 0x11c | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK1_INFO0_REGWEN_9`](#bank1_info0_regwen) | 0x120 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK1_INFO0_PAGE_CFG_0`](#bank1_info0_page_cfg) | 0x124 | 4 | Memory property configuration for info partition in bank1, | -| flash_ctrl.[`BANK1_INFO0_PAGE_CFG_1`](#bank1_info0_page_cfg) | 0x128 | 4 | Memory property configuration for info partition in bank1, | -| flash_ctrl.[`BANK1_INFO0_PAGE_CFG_2`](#bank1_info0_page_cfg) | 0x12c | 4 | Memory property configuration for info partition in bank1, | -| flash_ctrl.[`BANK1_INFO0_PAGE_CFG_3`](#bank1_info0_page_cfg) | 0x130 | 4 | Memory property configuration for info partition in bank1, | -| flash_ctrl.[`BANK1_INFO0_PAGE_CFG_4`](#bank1_info0_page_cfg) | 0x134 | 4 | Memory property configuration for info partition in bank1, | -| flash_ctrl.[`BANK1_INFO0_PAGE_CFG_5`](#bank1_info0_page_cfg) | 0x138 | 4 | Memory property configuration for info partition in bank1, | -| flash_ctrl.[`BANK1_INFO0_PAGE_CFG_6`](#bank1_info0_page_cfg) | 0x13c | 4 | Memory property configuration for info partition in bank1, | -| flash_ctrl.[`BANK1_INFO0_PAGE_CFG_7`](#bank1_info0_page_cfg) | 0x140 | 4 | Memory property configuration for info partition in bank1, | -| flash_ctrl.[`BANK1_INFO0_PAGE_CFG_8`](#bank1_info0_page_cfg) | 0x144 | 4 | Memory property configuration for info partition in bank1, | -| flash_ctrl.[`BANK1_INFO0_PAGE_CFG_9`](#bank1_info0_page_cfg) | 0x148 | 4 | Memory property configuration for info partition in bank1, | -| flash_ctrl.[`BANK1_INFO1_REGWEN`](#bank1_info1_regwen) | 0x14c | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK1_INFO1_PAGE_CFG`](#bank1_info1_page_cfg) | 0x150 | 4 | Memory property configuration for info partition in bank1, | -| flash_ctrl.[`BANK1_INFO2_REGWEN_0`](#bank1_info2_regwen) | 0x154 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK1_INFO2_REGWEN_1`](#bank1_info2_regwen) | 0x158 | 4 | Memory region registers configuration enable. | -| flash_ctrl.[`BANK1_INFO2_PAGE_CFG_0`](#bank1_info2_page_cfg) | 0x15c | 4 | Memory property configuration for info partition in bank1, | -| flash_ctrl.[`BANK1_INFO2_PAGE_CFG_1`](#bank1_info2_page_cfg) | 0x160 | 4 | Memory property configuration for info partition in bank1, | -| flash_ctrl.[`HW_INFO_CFG_OVERRIDE`](#hw_info_cfg_override) | 0x164 | 4 | HW interface info configuration rule overrides | -| flash_ctrl.[`BANK_CFG_REGWEN`](#bank_cfg_regwen) | 0x168 | 4 | Bank configuration registers configuration enable. | -| flash_ctrl.[`MP_BANK_CFG_SHADOWED`](#MP_BANK_CFG_SHADOWED) | 0x16c | 4 | Memory properties bank configuration | -| flash_ctrl.[`OP_STATUS`](#op_status) | 0x170 | 4 | Flash Operation Status | -| flash_ctrl.[`STATUS`](#status) | 0x174 | 4 | Flash Controller Status | -| flash_ctrl.[`DEBUG_STATE`](#debug_state) | 0x178 | 4 | Current flash fsm state | -| flash_ctrl.[`ERR_CODE`](#err_code) | 0x17c | 4 | Flash error code register. | -| flash_ctrl.[`STD_FAULT_STATUS`](#std_fault_status) | 0x180 | 4 | This register tabulates standard fault status of the flash. | -| flash_ctrl.[`FAULT_STATUS`](#fault_status) | 0x184 | 4 | This register tabulates customized fault status of the flash. | -| flash_ctrl.[`ERR_ADDR`](#err_addr) | 0x188 | 4 | Synchronous error address | -| flash_ctrl.[`ECC_SINGLE_ERR_CNT`](#ECC_SINGLE_ERR_CNT) | 0x18c | 4 | Total number of single bit ECC error count | -| flash_ctrl.[`ECC_SINGLE_ERR_ADDR_0`](#ecc_single_err_addr) | 0x190 | 4 | Latest address of ECC single err | -| flash_ctrl.[`ECC_SINGLE_ERR_ADDR_1`](#ecc_single_err_addr) | 0x194 | 4 | Latest address of ECC single err | -| flash_ctrl.[`PHY_ALERT_CFG`](#phy_alert_cfg) | 0x198 | 4 | Phy alert configuration | -| flash_ctrl.[`PHY_STATUS`](#phy_status) | 0x19c | 4 | Flash Phy Status | -| flash_ctrl.[`Scratch`](#scratch) | 0x1a0 | 4 | Flash Controller Scratch | -| flash_ctrl.[`FIFO_LVL`](#fifo_lvl) | 0x1a4 | 4 | Programmable depth where FIFOs should generate interrupts | -| flash_ctrl.[`FIFO_RST`](#fifo_rst) | 0x1a8 | 4 | Reset for flash controller FIFOs | -| flash_ctrl.[`CURR_FIFO_LVL`](#curr_fifo_lvl) | 0x1ac | 4 | Current program and read fifo depth | -| flash_ctrl.[`prog_fifo`](#prog_fifo) | 0x1b0 | 4 | Flash program FIFO. | -| flash_ctrl.[`rd_fifo`](#rd_fifo) | 0x1b4 | 4 | Flash read FIFO. | - -${"##"} INTR_STATE -Interrupt State Register -- Offset: `0x0` -- Reset default: `0x3` -- Reset mask: `0x3f` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "prog_empty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_lvl", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rd_full", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rd_lvl", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "op_done", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "corr_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-----------|:------------------------------| -| 31:6 | | | | Reserved | -| 5 | rw1c | 0x0 | corr_err | Correctable error encountered | -| 4 | rw1c | 0x0 | op_done | Operation complete | -| 3 | ro | 0x0 | rd_lvl | Read FIFO filled to level | -| 2 | ro | 0x0 | rd_full | Read FIFO full | -| 1 | ro | 0x1 | prog_lvl | Program FIFO drained to level | -| 0 | ro | 0x1 | prog_empty | Program FIFO empty | - -${"##"} INTR_ENABLE -Interrupt Enable Register -- Offset: `0x4` -- Reset default: `0x0` -- Reset mask: `0x3f` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "prog_empty", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "prog_lvl", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rd_full", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rd_lvl", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "op_done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "corr_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-----------|:---------------------------------------------------------------------| -| 31:6 | | | | Reserved | -| 5 | rw | 0x0 | corr_err | Enable interrupt when [`INTR_STATE.corr_err`](#intr_state) is set. | -| 4 | rw | 0x0 | op_done | Enable interrupt when [`INTR_STATE.op_done`](#intr_state) is set. | -| 3 | rw | 0x0 | rd_lvl | Enable interrupt when [`INTR_STATE.rd_lvl`](#intr_state) is set. | -| 2 | rw | 0x0 | rd_full | Enable interrupt when [`INTR_STATE.rd_full`](#intr_state) is set. | -| 1 | rw | 0x0 | prog_lvl | Enable interrupt when [`INTR_STATE.prog_lvl`](#intr_state) is set. | -| 0 | rw | 0x0 | prog_empty | Enable interrupt when [`INTR_STATE.prog_empty`](#intr_state) is set. | - -${"##"} INTR_TEST -Interrupt Test Register -- Offset: `0x8` -- Reset default: `0x0` -- Reset mask: `0x3f` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "prog_empty", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "prog_lvl", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rd_full", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rd_lvl", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "op_done", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "corr_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-----------|:--------------------------------------------------------------| -| 31:6 | | | | Reserved | -| 5 | wo | 0x0 | corr_err | Write 1 to force [`INTR_STATE.corr_err`](#intr_state) to 1. | -| 4 | wo | 0x0 | op_done | Write 1 to force [`INTR_STATE.op_done`](#intr_state) to 1. | -| 3 | wo | 0x0 | rd_lvl | Write 1 to force [`INTR_STATE.rd_lvl`](#intr_state) to 1. | -| 2 | wo | 0x0 | rd_full | Write 1 to force [`INTR_STATE.rd_full`](#intr_state) to 1. | -| 1 | wo | 0x0 | prog_lvl | Write 1 to force [`INTR_STATE.prog_lvl`](#intr_state) to 1. | -| 0 | wo | 0x0 | prog_empty | Write 1 to force [`INTR_STATE.prog_empty`](#intr_state) to 1. | - -${"##"} ALERT_TEST -Alert Test Register -- Offset: `0xc` -- Reset default: `0x0` -- Reset mask: `0x1f` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "recov_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_std_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_prim_flash_alert", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "recov_prim_flash_alert", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-----------------------|:-------------------------------------------------| -| 31:5 | | | | Reserved | -| 4 | wo | 0x0 | recov_prim_flash_alert | Write 1 to trigger one alert event of this kind. | -| 3 | wo | 0x0 | fatal_prim_flash_alert | Write 1 to trigger one alert event of this kind. | -| 2 | wo | 0x0 | fatal_err | Write 1 to trigger one alert event of this kind. | -| 1 | wo | 0x0 | fatal_std_err | Write 1 to trigger one alert event of this kind. | -| 0 | wo | 0x0 | recov_err | Write 1 to trigger one alert event of this kind. | - -${"##"} DIS -Disable flash functionality -- Offset: `0x10` -- Reset default: `0x9` -- Reset mask: `0xf` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "VAL", "bits": 4, "attr": ["rw1s"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-----------------| -| 31:4 | | | Reserved | -| 3:0 | rw1s | 0x9 | [VAL](#dis--val) | - -${"###"} DIS . VAL -Disables flash functionality completely. -This is a shortcut mechanism used by the software to completely -kill flash in case of emergency. - -Since this register is rw1s instead of rw, to disable, write the value kMuBi4True -to the register to disable the flash. - -${"##"} EXEC -Controls whether flash can be used for code execution fetches -- Offset: `0x14` -- Reset default: `0x0` -- Reset mask: `0xffffffff` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------------| -| 31:0 | rw | 0x0 | EN | A value of 0xa26a38f7 allows flash to be used for code execution. Any other value prevents code execution. | - -${"##"} INIT -Controller init register -- Offset: `0x18` -- Reset default: `0x0` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "VAL", "bits": 1, "attr": ["rw1s"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------| -| 31:1 | | | Reserved | -| 0 | rw1s | 0x0 | [VAL](#init--val) | - -${"###"} INIT . VAL -Initializes the flash controller. - -During the initialization process, the flash controller requests the address and data -scramble keys and reads out the root seeds stored in flash before allowing other usage -of the flash controller. - -When the initialization sequence is complete, the flash read buffers are enabled -and turned on. - -${"##"} CTRL_REGWEN -Controls the configurability of the [`CONTROL`](#control) register. - -This register ensures the contents of [`CONTROL`](#control) cannot be changed by software once a flash -operation has begun. - -It unlocks whenever the existing flash operation completes, regardless of success or error. -- Offset: `0x1c` -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | ro | 0x1 | EN | Configuration enable. This bit defaults to 1 and is set to 0 by hardware when flash operation is initiated. When the controller completes the flash operation, this bit is set back to 1 to allow software configuration of [`CONTROL`](#control) | - -${"##"} CONTROL -Control register -- Offset: `0x20` -- Reset default: `0x0` -- Reset mask: `0xfff07f1` -- Register enable: [`CTRL_REGWEN`](#ctrl_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "START", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "OP", "bits": 2, "attr": ["rw"], "rotate": 0}, {"name": "PROG_SEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_SEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PARTITION_SEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "INFO_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 5}, {"name": "NUM", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-----------------------------------------| -| 31:28 | | | Reserved | -| 27:16 | rw | 0x0 | [NUM](#control--num) | -| 15:11 | | | Reserved | -| 10:9 | rw | 0x0 | [INFO_SEL](#control--info_sel) | -| 8 | rw | 0x0 | [PARTITION_SEL](#control--partition_sel) | -| 7 | rw | 0x0 | [ERASE_SEL](#control--erase_sel) | -| 6 | rw | 0x0 | [PROG_SEL](#control--prog_sel) | -| 5:4 | rw | 0x0 | [OP](#control--op) | -| 3:1 | | | Reserved | -| 0 | rw | 0x0 | [START](#control--start) | - -${"###"} CONTROL . NUM -One fewer than the number of bus words the flash operation should read or program. -For example, to read 10 words, software should program this field with the value 9. - -${"###"} CONTROL . INFO_SEL -Informational partions can have multiple types. - -This field selects the info type to be accessed. - -${"###"} CONTROL . PARTITION_SEL -When doing a read, program or page erase operation, selects either info or data partition for operation. -When 0, select data partition - this is the portion of flash that is accessible both by the host and by the controller. -When 1, select info partition - this is the portion of flash that is only accessible by the controller. - -When doing a bank erase operation, selects info partition also for erase. -When 0, bank erase only erases data partition. -When 1, bank erase erases data partition and info partition. - -${"###"} CONTROL . ERASE_SEL -Flash erase operation type selection - -| Value | Name | Description | -|:--------|:-----------|:----------------------| -| 0x0 | Page Erase | Erase 1 page of flash | -| 0x1 | Bank Erase | Erase 1 bank of flash | - - -${"###"} CONTROL . PROG_SEL -Flash program operation type selection - -| Value | Name | Description | -|:--------|:---------------|:-------------------------------------------------------------------------------------------------------------------| -| 0x0 | Normal program | Normal program operation to the flash | -| 0x1 | Program repair | Repair program operation to the flash. Whether this is actually supported depends on the underlying flash memory. | - - -${"###"} CONTROL . OP -Flash operation selection - -| Value | Name | Description | -|:--------|:-------|:--------------------------------------------------------------------| -| 0x0 | Read | Flash Read. Read desired number of flash words | -| 0x1 | Prog | Flash Program. Program desired number of flash words | -| 0x2 | Erase | Flash Erase Operation. See ERASE_SEL for details on erase operation | - -Other values are reserved. - -${"###"} CONTROL . START -Start flash transaction. This bit shall only be set at the same time or after the other -fields of the [`CONTROL`](#control) register and [`ADDR`](#addr) have been programmed. - -${"##"} ADDR -Address for flash operation -- Offset: `0x24` -- Reset default: `0x0` -- Reset mask: `0xfffff` -- Register enable: [`CTRL_REGWEN`](#ctrl_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "START", "bits": 20, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:----------------------| -| 31:20 | | | Reserved | -| 19:0 | rw | 0x0 | [START](#addr--start) | - -${"###"} ADDR . START -Start address of a flash transaction. This is a byte address relative to the flash -only. Ie, an address of 0 will access address 0 of the requested partition. - -For read operations, the flash controller will truncate to the closest, lower word -aligned address. For example, if 0x13 is supplied, the controller will perform a -read at address 0x10. - -Program operations behave similarly, the controller does not have read modified write -support. - -For page erases, the controller will truncate to the closest lower page aligned -address. Similarly for bank erases, the controller will truncate to the closest -lower bank aligned address. - -${"##"} PROG_TYPE_EN -Enable different program types -- Offset: `0x28` -- Reset default: `0x3` -- Reset mask: `0x3` -- Register enable: [`CTRL_REGWEN`](#ctrl_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "NORMAL", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "REPAIR", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:---------------------------| -| 31:2 | | | | Reserved | -| 1 | rw0c | 0x1 | REPAIR | Repair prog type available | -| 0 | rw0c | 0x1 | NORMAL | Normal prog type available | - -${"##"} ERASE_SUSPEND -Suspend erase -- Offset: `0x2c` -- Reset default: `0x0` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "REQ", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | rw | 0x0 | REQ | When 1, request erase suspend. If no erase ongoing, the request is immediately cleared by hardware If erase ongoing, the request is fed to the flash_phy and cleared when the suspend is handled. | - -${"##"} REGION_CFG_REGWEN -Memory region registers configuration enable. -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Instances - -| Name | Offset | -|:--------------------|:---------| -| REGION_CFG_REGWEN_0 | 0x30 | -| REGION_CFG_REGWEN_1 | 0x34 | -| REGION_CFG_REGWEN_2 | 0x38 | -| REGION_CFG_REGWEN_3 | 0x3c | -| REGION_CFG_REGWEN_4 | 0x40 | -| REGION_CFG_REGWEN_5 | 0x44 | -| REGION_CFG_REGWEN_6 | 0x48 | -| REGION_CFG_REGWEN_7 | 0x4c | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------------------| -| 31:1 | | | Reserved | -| 0 | rw0c | 0x1 | [REGION](#region_cfg_regwen--region) | - -${"###"} REGION_CFG_REGWEN . REGION -Region register write enable. Once set to 0, it can longer be configured to 1 - -| Value | Name | Description | -|:--------|:---------------|:----------------------------------------------------| -| 0x0 | Region locked | Region can no longer be configured until next reset | -| 0x1 | Region enabled | Region can be configured | - - -${"##"} MP_REGION_CFG -Memory property configuration for data partition -- Reset default: `0x9999999` -- Reset mask: `0xfffffff` - -${"###"} Instances - -| Name | Offset | -|:----------------|:---------| -| MP_REGION_CFG_0 | 0x50 | -| MP_REGION_CFG_1 | 0x54 | -| MP_REGION_CFG_2 | 0x58 | -| MP_REGION_CFG_3 | 0x5c | -| MP_REGION_CFG_4 | 0x60 | -| MP_REGION_CFG_5 | 0x64 | -| MP_REGION_CFG_6 | 0x68 | -| MP_REGION_CFG_7 | 0x6c | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "PROG_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HE_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------|:-------------------------------------------------------------------------------------------------------------------| -| 31:28 | | | | Reserved | -| 27:24 | rw | 0x9 | HE_EN | Region is high endurance enabled. | -| 23:20 | rw | 0x9 | ECC_EN | Region is integrity checked and reliability ECC enabled. | -| 19:16 | rw | 0x9 | SCRAMBLE_EN | Region is scramble enabled. | -| 15:12 | rw | 0x9 | ERASE_EN | Region can be erased | -| 11:8 | rw | 0x9 | PROG_EN | Region can be programmed | -| 7:4 | rw | 0x9 | RD_EN | Region can be read | -| 3:0 | rw | 0x9 | EN | Region enabled, following fields apply. If region is disabled, it is not matched against any incoming transaction. | - -${"##"} MP_REGION -Memory base and size configuration for data partition -- Reset default: `0x0` -- Reset mask: `0x7ffff` - -${"###"} Instances - -| Name | Offset | -|:------------|:---------| -| MP_REGION_0 | 0x70 | -| MP_REGION_1 | 0x74 | -| MP_REGION_2 | 0x78 | -| MP_REGION_3 | 0x7c | -| MP_REGION_4 | 0x80 | -| MP_REGION_5 | 0x84 | -| MP_REGION_6 | 0x88 | -| MP_REGION_7 | 0x8c | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "BASE", "bits": 9, "attr": ["rw"], "rotate": 0}, {"name": "SIZE", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| 31:19 | | | | Reserved | -| 18:9 | rw | 0x0 | SIZE | Region size in number of pages. For example, if base is 0 and size is 1, then the region is defined by page 0. If base is 0 and size is 2, then the region is defined by pages 0 and 1. | -| 8:0 | rw | 0x0 | BASE | Region base page. Note the granularity is page, not byte or word | - -${"##"} DEFAULT_REGION -Default region properties -- Offset: `0x90` -- Reset default: `0x999999` -- Reset mask: `0xffffff` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "PROG_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HE_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------|:------------------------------------------------------------| -| 31:24 | | | | Reserved | -| 23:20 | rw | 0x9 | HE_EN | Region is high endurance enabled. | -| 19:16 | rw | 0x9 | ECC_EN | Region is ECC enabled (both integrity and reliability ECC). | -| 15:12 | rw | 0x9 | SCRAMBLE_EN | Region is scramble enabled. | -| 11:8 | rw | 0x9 | ERASE_EN | Region can be erased | -| 7:4 | rw | 0x9 | PROG_EN | Region can be programmed | -| 3:0 | rw | 0x9 | RD_EN | Region can be read | - -${"##"} BANK0_INFO0_REGWEN -Memory region registers configuration enable. -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Instances - -| Name | Offset | -|:---------------------|:---------| -| BANK0_INFO0_REGWEN_0 | 0x94 | -| BANK0_INFO0_REGWEN_1 | 0x98 | -| BANK0_INFO0_REGWEN_2 | 0x9c | -| BANK0_INFO0_REGWEN_3 | 0xa0 | -| BANK0_INFO0_REGWEN_4 | 0xa4 | -| BANK0_INFO0_REGWEN_5 | 0xa8 | -| BANK0_INFO0_REGWEN_6 | 0xac | -| BANK0_INFO0_REGWEN_7 | 0xb0 | -| BANK0_INFO0_REGWEN_8 | 0xb4 | -| BANK0_INFO0_REGWEN_9 | 0xb8 | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:--------------------------------------| -| 31:1 | | | Reserved | -| 0 | rw0c | 0x1 | [REGION](#bank0_info0_regwen--region) | - -${"###"} BANK0_INFO0_REGWEN . REGION -Info0 page write enable. Once set to 0, it can longer be configured to 1 - -| Value | Name | Description | -|:--------|:-------------|:----------------------------------------------------| -| 0x0 | Page locked | Region can no longer be configured until next reset | -| 0x1 | Page enabled | Region can be configured | - - -${"##"} BANK0_INFO0_PAGE_CFG - Memory property configuration for info partition in bank0, - Unlike data partition, each page is individually configured. -- Reset default: `0x9999999` -- Reset mask: `0xfffffff` - -${"###"} Instances - -| Name | Offset | -|:-----------------------|:---------| -| BANK0_INFO0_PAGE_CFG_0 | 0xbc | -| BANK0_INFO0_PAGE_CFG_1 | 0xc0 | -| BANK0_INFO0_PAGE_CFG_2 | 0xc4 | -| BANK0_INFO0_PAGE_CFG_3 | 0xc8 | -| BANK0_INFO0_PAGE_CFG_4 | 0xcc | -| BANK0_INFO0_PAGE_CFG_5 | 0xd0 | -| BANK0_INFO0_PAGE_CFG_6 | 0xd4 | -| BANK0_INFO0_PAGE_CFG_7 | 0xd8 | -| BANK0_INFO0_PAGE_CFG_8 | 0xdc | -| BANK0_INFO0_PAGE_CFG_9 | 0xe0 | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "PROG_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HE_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------|:------------------------------------------------------------| -| 31:28 | | | | Reserved | -| 27:24 | rw | 0x9 | HE_EN | Region is high endurance enabled. | -| 23:20 | rw | 0x9 | ECC_EN | Region is ECC enabled (both integrity and reliability ECC). | -| 19:16 | rw | 0x9 | SCRAMBLE_EN | Region is scramble enabled. | -| 15:12 | rw | 0x9 | ERASE_EN | Region can be erased | -| 11:8 | rw | 0x9 | PROG_EN | Region can be programmed | -| 7:4 | rw | 0x9 | RD_EN | Region can be read | -| 3:0 | rw | 0x9 | EN | Region enabled, following fields apply | - -${"##"} BANK0_INFO1_REGWEN -Memory region registers configuration enable. -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Instances - -| Name | Offset | -|:-------------------|:---------| -| BANK0_INFO1_REGWEN | 0xe4 | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:--------------------------------------| -| 31:1 | | | Reserved | -| 0 | rw0c | 0x1 | [REGION](#bank0_info1_regwen--region) | - -${"###"} BANK0_INFO1_REGWEN . REGION -Info1 page write enable. Once set to 0, it can longer be configured to 1 - -| Value | Name | Description | -|:--------|:-------------|:----------------------------------------------------| -| 0x0 | Page locked | Region can no longer be configured until next reset | -| 0x1 | Page enabled | Region can be configured | - - -${"##"} BANK0_INFO1_PAGE_CFG - Memory property configuration for info partition in bank0, - Unlike data partition, each page is individually configured. -- Reset default: `0x9999999` -- Reset mask: `0xfffffff` - -${"###"} Instances - -| Name | Offset | -|:---------------------|:---------| -| BANK0_INFO1_PAGE_CFG | 0xe8 | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "PROG_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HE_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------|:------------------------------------------------------------| -| 31:28 | | | | Reserved | -| 27:24 | rw | 0x9 | HE_EN | Region is high endurance enabled. | -| 23:20 | rw | 0x9 | ECC_EN | Region is ECC enabled (both integrity and reliability ECC). | -| 19:16 | rw | 0x9 | SCRAMBLE_EN | Region is scramble enabled. | -| 15:12 | rw | 0x9 | ERASE_EN | Region can be erased | -| 11:8 | rw | 0x9 | PROG_EN | Region can be programmed | -| 7:4 | rw | 0x9 | RD_EN | Region can be read | -| 3:0 | rw | 0x9 | EN | Region enabled, following fields apply | - -${"##"} BANK0_INFO2_REGWEN -Memory region registers configuration enable. -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Instances - -| Name | Offset | -|:---------------------|:---------| -| BANK0_INFO2_REGWEN_0 | 0xec | -| BANK0_INFO2_REGWEN_1 | 0xf0 | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:--------------------------------------| -| 31:1 | | | Reserved | -| 0 | rw0c | 0x1 | [REGION](#bank0_info2_regwen--region) | - -${"###"} BANK0_INFO2_REGWEN . REGION -Info2 page write enable. Once set to 0, it can longer be configured to 1 - -| Value | Name | Description | -|:--------|:-------------|:----------------------------------------------------| -| 0x0 | Page locked | Region can no longer be configured until next reset | -| 0x1 | Page enabled | Region can be configured | - - -${"##"} BANK0_INFO2_PAGE_CFG - Memory property configuration for info partition in bank0, - Unlike data partition, each page is individually configured. -- Reset default: `0x9999999` -- Reset mask: `0xfffffff` - -${"###"} Instances - -| Name | Offset | -|:-----------------------|:---------| -| BANK0_INFO2_PAGE_CFG_0 | 0xf4 | -| BANK0_INFO2_PAGE_CFG_1 | 0xf8 | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "PROG_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HE_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------|:------------------------------------------------------------| -| 31:28 | | | | Reserved | -| 27:24 | rw | 0x9 | HE_EN | Region is high endurance enabled. | -| 23:20 | rw | 0x9 | ECC_EN | Region is ECC enabled (both integrity and reliability ECC). | -| 19:16 | rw | 0x9 | SCRAMBLE_EN | Region is scramble enabled. | -| 15:12 | rw | 0x9 | ERASE_EN | Region can be erased | -| 11:8 | rw | 0x9 | PROG_EN | Region can be programmed | -| 7:4 | rw | 0x9 | RD_EN | Region can be read | -| 3:0 | rw | 0x9 | EN | Region enabled, following fields apply | - -${"##"} BANK1_INFO0_REGWEN -Memory region registers configuration enable. -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Instances - -| Name | Offset | -|:---------------------|:---------| -| BANK1_INFO0_REGWEN_0 | 0xfc | -| BANK1_INFO0_REGWEN_1 | 0x100 | -| BANK1_INFO0_REGWEN_2 | 0x104 | -| BANK1_INFO0_REGWEN_3 | 0x108 | -| BANK1_INFO0_REGWEN_4 | 0x10c | -| BANK1_INFO0_REGWEN_5 | 0x110 | -| BANK1_INFO0_REGWEN_6 | 0x114 | -| BANK1_INFO0_REGWEN_7 | 0x118 | -| BANK1_INFO0_REGWEN_8 | 0x11c | -| BANK1_INFO0_REGWEN_9 | 0x120 | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:--------------------------------------| -| 31:1 | | | Reserved | -| 0 | rw0c | 0x1 | [REGION](#bank1_info0_regwen--region) | - -${"###"} BANK1_INFO0_REGWEN . REGION -Info0 page write enable. Once set to 0, it can longer be configured to 1 - -| Value | Name | Description | -|:--------|:-------------|:----------------------------------------------------| -| 0x0 | Page locked | Region can no longer be configured until next reset | -| 0x1 | Page enabled | Region can be configured | - - -${"##"} BANK1_INFO0_PAGE_CFG - Memory property configuration for info partition in bank1, - Unlike data partition, each page is individually configured. -- Reset default: `0x9999999` -- Reset mask: `0xfffffff` - -${"###"} Instances - -| Name | Offset | -|:-----------------------|:---------| -| BANK1_INFO0_PAGE_CFG_0 | 0x124 | -| BANK1_INFO0_PAGE_CFG_1 | 0x128 | -| BANK1_INFO0_PAGE_CFG_2 | 0x12c | -| BANK1_INFO0_PAGE_CFG_3 | 0x130 | -| BANK1_INFO0_PAGE_CFG_4 | 0x134 | -| BANK1_INFO0_PAGE_CFG_5 | 0x138 | -| BANK1_INFO0_PAGE_CFG_6 | 0x13c | -| BANK1_INFO0_PAGE_CFG_7 | 0x140 | -| BANK1_INFO0_PAGE_CFG_8 | 0x144 | -| BANK1_INFO0_PAGE_CFG_9 | 0x148 | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "PROG_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HE_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------|:------------------------------------------------------------| -| 31:28 | | | | Reserved | -| 27:24 | rw | 0x9 | HE_EN | Region is high endurance enabled. | -| 23:20 | rw | 0x9 | ECC_EN | Region is ECC enabled (both integrity and reliability ECC). | -| 19:16 | rw | 0x9 | SCRAMBLE_EN | Region is scramble enabled. | -| 15:12 | rw | 0x9 | ERASE_EN | Region can be erased | -| 11:8 | rw | 0x9 | PROG_EN | Region can be programmed | -| 7:4 | rw | 0x9 | RD_EN | Region can be read | -| 3:0 | rw | 0x9 | EN | Region enabled, following fields apply | - -${"##"} BANK1_INFO1_REGWEN -Memory region registers configuration enable. -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Instances - -| Name | Offset | -|:-------------------|:---------| -| BANK1_INFO1_REGWEN | 0x14c | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:--------------------------------------| -| 31:1 | | | Reserved | -| 0 | rw0c | 0x1 | [REGION](#bank1_info1_regwen--region) | - -${"###"} BANK1_INFO1_REGWEN . REGION -Info1 page write enable. Once set to 0, it can longer be configured to 1 - -| Value | Name | Description | -|:--------|:-------------|:----------------------------------------------------| -| 0x0 | Page locked | Region can no longer be configured until next reset | -| 0x1 | Page enabled | Region can be configured | - - -${"##"} BANK1_INFO1_PAGE_CFG - Memory property configuration for info partition in bank1, - Unlike data partition, each page is individually configured. -- Reset default: `0x9999999` -- Reset mask: `0xfffffff` - -${"###"} Instances - -| Name | Offset | -|:---------------------|:---------| -| BANK1_INFO1_PAGE_CFG | 0x150 | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "PROG_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HE_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------|:------------------------------------------------------------| -| 31:28 | | | | Reserved | -| 27:24 | rw | 0x9 | HE_EN | Region is high endurance enabled. | -| 23:20 | rw | 0x9 | ECC_EN | Region is ECC enabled (both integrity and reliability ECC). | -| 19:16 | rw | 0x9 | SCRAMBLE_EN | Region is scramble enabled. | -| 15:12 | rw | 0x9 | ERASE_EN | Region can be erased | -| 11:8 | rw | 0x9 | PROG_EN | Region can be programmed | -| 7:4 | rw | 0x9 | RD_EN | Region can be read | -| 3:0 | rw | 0x9 | EN | Region enabled, following fields apply | - -${"##"} BANK1_INFO2_REGWEN -Memory region registers configuration enable. -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Instances - -| Name | Offset | -|:---------------------|:---------| -| BANK1_INFO2_REGWEN_0 | 0x154 | -| BANK1_INFO2_REGWEN_1 | 0x158 | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:--------------------------------------| -| 31:1 | | | Reserved | -| 0 | rw0c | 0x1 | [REGION](#bank1_info2_regwen--region) | - -${"###"} BANK1_INFO2_REGWEN . REGION -Info2 page write enable. Once set to 0, it can longer be configured to 1 - -| Value | Name | Description | -|:--------|:-------------|:----------------------------------------------------| -| 0x0 | Page locked | Region can no longer be configured until next reset | -| 0x1 | Page enabled | Region can be configured | - - -${"##"} BANK1_INFO2_PAGE_CFG - Memory property configuration for info partition in bank1, - Unlike data partition, each page is individually configured. -- Reset default: `0x9999999` -- Reset mask: `0xfffffff` - -${"###"} Instances - -| Name | Offset | -|:-----------------------|:---------| -| BANK1_INFO2_PAGE_CFG_0 | 0x15c | -| BANK1_INFO2_PAGE_CFG_1 | 0x160 | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "PROG_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HE_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------|:------------------------------------------------------------| -| 31:28 | | | | Reserved | -| 27:24 | rw | 0x9 | HE_EN | Region is high endurance enabled. | -| 23:20 | rw | 0x9 | ECC_EN | Region is ECC enabled (both integrity and reliability ECC). | -| 19:16 | rw | 0x9 | SCRAMBLE_EN | Region is scramble enabled. | -| 15:12 | rw | 0x9 | ERASE_EN | Region can be erased | -| 11:8 | rw | 0x9 | PROG_EN | Region can be programmed | -| 7:4 | rw | 0x9 | RD_EN | Region can be read | -| 3:0 | rw | 0x9 | EN | Region enabled, following fields apply | - -${"##"} HW_INFO_CFG_OVERRIDE -HW interface info configuration rule overrides -- Offset: `0x164` -- Reset default: `0x99` -- Reset mask: `0xff` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "SCRAMBLE_DIS", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_DIS", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| 31:8 | | | | Reserved | -| 7:4 | rw | 0x9 | ECC_DIS | The hardwired hardware info configuration rules for ECC enable are logically AND'd with this field. If the hardware rules hardwires ECC to enable, we can disable via software if needed. By default this field is false. | -| 3:0 | rw | 0x9 | SCRAMBLE_DIS | The hardwired hardware info configuration rules for scramble enable are logically AND'd with this field. If the hardware rules hardwires scramble to enable, we can disable via software if needed. By default this field is false. | - -${"##"} BANK_CFG_REGWEN -Bank configuration registers configuration enable. -- Offset: `0x168` -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "BANK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------------| -| 31:1 | | | Reserved | -| 0 | rw0c | 0x1 | [BANK](#bank_cfg_regwen--bank) | - -${"###"} BANK_CFG_REGWEN . BANK -Bank register write enable. Once set to 0, it can longer be configured to 1 - -| Value | Name | Description | -|:--------|:-------------|:--------------------------------------------------| -| 0x0 | Bank locked | Bank can no longer be configured until next reset | -| 0x1 | Bank enabled | Bank can be configured | - - -${"##"} MP_BANK_CFG_SHADOWED -Memory properties bank configuration -- Offset: `0x16c` -- Reset default: `0x0` -- Reset mask: `0x3` -- Register enable: [`BANK_CFG_REGWEN`](#bank_cfg_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "ERASE_EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-----------|:-----------------------| -| 31:2 | | | | Reserved | -| 1 | rw | 0x0 | ERASE_EN_1 | Bank wide erase enable | -| 0 | rw | 0x0 | ERASE_EN_0 | Bank wide erase enable | - -${"##"} OP_STATUS -Flash Operation Status -- Offset: `0x170` -- Reset default: `0x0` -- Reset mask: `0x3` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------| -| 31:2 | | | | Reserved | -| 1 | rw | 0x0 | err | Flash operation error. Set by HW, cleared by SW. See [`ERR_CODE`](#err_code) for more details. | -| 0 | rw | 0x0 | done | Flash operation done. Set by HW, cleared by SW | - -${"##"} STATUS -Flash Controller Status -- Offset: `0x174` -- Reset default: `0xa` -- Reset mask: `0x3f` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "rd_full", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rd_empty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_full", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_empty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "init_wip", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "initialized", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------|:--------------------------------------------------------| -| 31:6 | | | | Reserved | -| 5 | ro | 0x0 | initialized | Flash controller initialized | -| 4 | ro | 0x0 | init_wip | Flash controller undergoing init, inclusive of phy init | -| 3 | ro | 0x1 | prog_empty | Flash program FIFO empty, software must provide data | -| 2 | ro | 0x0 | prog_full | Flash program FIFO full | -| 1 | ro | 0x1 | rd_empty | Flash read FIFO empty | -| 0 | ro | 0x0 | rd_full | Flash read FIFO full, software must consume data | - -${"##"} DEBUG_STATE -Current flash fsm state -- Offset: `0x178` -- Reset default: `0x0` -- Reset mask: `0x7ff` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "lcmgr_state", "bits": 11, "attr": ["ro"], "rotate": 0}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------|:------------------------------| -| 31:11 | | | | Reserved | -| 10:0 | ro | x | lcmgr_state | Current lcmgr interface staet | - -${"##"} ERR_CODE -Flash error code register. -This register tabulates detailed error status of the flash. -This is separate from [`OP_STATUS`](#op_status), which is used to indicate the current state of the software initiated -flash operation. - -Note, all errors in this register are considered recoverable errors, ie, errors that could have been -generated by software. -- Offset: `0x17c` -- Reset default: `0x0` -- Reset mask: `0xff` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "op_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "mp_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rd_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "prog_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "prog_win_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "prog_type_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "update_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "macro_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:--------------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| 31:8 | | | | Reserved | -| 7 | rw1c | 0x0 | macro_err | A recoverable error has been encountered in the flash macro. Please read the flash macro status registers for more details. | -| 6 | rw1c | 0x0 | update_err | A shadow register encountered an update error. This is an asynchronous error. | -| 5 | rw1c | 0x0 | prog_type_err | Flash program selected unavailable type, see [`PROG_TYPE_EN.`](#prog_type_en) This is a synchronous error. | -| 4 | rw1c | 0x0 | prog_win_err | Flash program has a window resolution error. Ie, the start of program and end of program are in different windows. Please check [`ERR_ADDR.`](#err_addr) This is a synchronous error. | -| 3 | rw1c | 0x0 | prog_err | Flash program has an error. This could be a program integrity error, see [`STD_FAULT_STATUS.`](#std_fault_status) This is a synchronous error. | -| 2 | rw1c | 0x0 | rd_err | Flash read has an error. This could be a reliability ECC error or an storage integrity error encountered during a software issued controller read, see [`STD_FAULT_STATUS.`](#std_fault_status) See [`ERR_ADDR`](#err_addr) for exact address. This is a synchronous error. | -| 1 | rw1c | 0x0 | mp_err | Flash access has encountered an access permission error. Please see [`ERR_ADDR`](#err_addr) for exact address. This is a synchronous error. | -| 0 | rw1c | 0x0 | op_err | Software has supplied an undefined operation. See [`CONTROL.OP`](#control) for list of valid operations. | - -${"##"} STD_FAULT_STATUS -This register tabulates standard fault status of the flash. - -These represent errors that occur in the standard structures of the design. -For example fsm integrity, counter integrity and tlul integrity. -- Offset: `0x180` -- Reset default: `0x0` -- Reset mask: `0x1ff` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "reg_intg_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_intg_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "lcmgr_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "lcmgr_intg_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "arb_fsm_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "storage_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "phy_fsm_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ctrl_cnt_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "fifo_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:---------------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| 31:9 | | | | Reserved | -| 8 | ro | 0x0 | fifo_err | Flash primitive fifo's have encountered a count error. | -| 7 | ro | 0x0 | ctrl_cnt_err | Flash ctrl read/prog has encountered a count error. | -| 6 | ro | 0x0 | phy_fsm_err | A flash phy fsm has encountered a sparse encoding error. | -| 5 | ro | 0x0 | storage_err | A shadow register encountered a storage error. | -| 4 | ro | 0x0 | arb_fsm_err | The arbiter fsm has encountered a sparse encoding error. | -| 3 | ro | 0x0 | lcmgr_intg_err | The life cycle management interface has encountered a transmission integrity error. This is an integrity error on the generated integrity during a life cycle management interface read. | -| 2 | ro | 0x0 | lcmgr_err | The life cycle management interface has encountered a fatal error. The error is either an FSM sparse encoding error or a count error. | -| 1 | ro | 0x0 | prog_intg_err | The flash controller encountered a program data transmission integrity error. | -| 0 | ro | 0x0 | reg_intg_err | The flash controller encountered a register integrity error. | - -${"##"} FAULT_STATUS -This register tabulates customized fault status of the flash. - -These are errors that are impossible to have been caused by software or unrecoverable in nature. - -All errors except for multi-bit ECC errors ([`FAULT_STATUS.PHY_RELBL_ERR`](#fault_status)) and ICV ([`FAULT_STATUS.PHY_STORAGE_ERR`](#fault_status)) trigger a fatal alert. -Once set, they remain set until reset. -- Offset: `0x184` -- Reset default: `0x0` -- Reset mask: `0xfff` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "op_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "mp_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rd_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_win_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_type_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "seed_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "phy_relbl_err", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "phy_storage_err", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "spurious_ack", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "arb_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "host_gnt_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:--------------------------------------------------| -| 31:12 | | | Reserved | -| 11 | ro | 0x0 | [host_gnt_err](#fault_status--host_gnt_err) | -| 10 | ro | 0x0 | [arb_err](#fault_status--arb_err) | -| 9 | ro | 0x0 | [spurious_ack](#fault_status--spurious_ack) | -| 8 | rw0c | 0x0 | [phy_storage_err](#fault_status--phy_storage_err) | -| 7 | rw0c | 0x0 | [phy_relbl_err](#fault_status--phy_relbl_err) | -| 6 | ro | 0x0 | [seed_err](#fault_status--seed_err) | -| 5 | ro | 0x0 | [prog_type_err](#fault_status--prog_type_err) | -| 4 | ro | 0x0 | [prog_win_err](#fault_status--prog_win_err) | -| 3 | ro | 0x0 | [prog_err](#fault_status--prog_err) | -| 2 | ro | 0x0 | [rd_err](#fault_status--rd_err) | -| 1 | ro | 0x0 | [mp_err](#fault_status--mp_err) | -| 0 | ro | 0x0 | [op_err](#fault_status--op_err) | - -${"###"} FAULT_STATUS . host_gnt_err -A host transaction was granted with illegal properties. - -${"###"} FAULT_STATUS . arb_err -The phy arbiter encountered inconsistent results. - -${"###"} FAULT_STATUS . spurious_ack -The flash emitted an unexpected acknowledgement. - -${"###"} FAULT_STATUS . phy_storage_err -The flash macro encountered a storage integrity ECC error. - -Note that this error bit can be cleared to allow firmware dealing with ICV errors during firmware selection and verification. -After passing this stage, it is recommended that firmware classifies the corresponding alert as fatal on the receiver end, i.e, inside the alert handler. - -${"###"} FAULT_STATUS . phy_relbl_err -The flash macro encountered a storage reliability ECC error. - -Note that this error bit can be cleared to allow firmware dealing with multi-bit ECC errors during firmware selection and verification. -After passing this stage, it is recommended that firmware classifies the corresponding alert as fatal on the receiver end, i.e, inside the alert handler. - -${"###"} FAULT_STATUS . seed_err -The seed reading process encountered an unexpected error. - -${"###"} FAULT_STATUS . prog_type_err -The flash life cycle management interface encountered a program type error. -A program type not supported by the flash macro was issued. - -${"###"} FAULT_STATUS . prog_win_err -The flash life cycle management interface encountered a program resolution error. - -${"###"} FAULT_STATUS . prog_err -The flash life cycle management interface encountered a program error. -This could be a program integirty eror, see [`STD_FAULT_STATUS`](#std_fault_status) for more details. - -${"###"} FAULT_STATUS . rd_err -The flash life cycle management interface encountered a read error. -This could be a reliability ECC error or an integrity ECC error -encountered during a read, see [`STD_FAULT_STATUS`](#std_fault_status) for more details. - -${"###"} FAULT_STATUS . mp_err -The flash life cycle management interface encountered a memory permission error. - -${"###"} FAULT_STATUS . op_err -The flash life cycle management interface has supplied an undefined operation. -See [`CONTROL.OP`](#control) for list of valid operations. - -${"##"} ERR_ADDR -Synchronous error address -- Offset: `0x188` -- Reset default: `0x0` -- Reset mask: `0xfffff` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "ERR_ADDR", "bits": 20, "attr": ["ro"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:---------|:--------------| -| 31:20 | | | | Reserved | -| 19:0 | ro | 0x0 | ERR_ADDR | | - -${"##"} ECC_SINGLE_ERR_CNT -Total number of single bit ECC error count -- Offset: `0x18c` -- Reset default: `0x0` -- Reset mask: `0xffff` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "ECC_SINGLE_ERR_CNT_0", "bits": 8, "attr": ["rw"], "rotate": -90}, {"name": "ECC_SINGLE_ERR_CNT_1", "bits": 8, "attr": ["rw"], "rotate": -90}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:---------------------|:----------------------------------------| -| 31:16 | | | | Reserved | -| 15:8 | rw | 0x0 | ECC_SINGLE_ERR_CNT_1 | This count will not wrap when saturated | -| 7:0 | rw | 0x0 | ECC_SINGLE_ERR_CNT_0 | This count will not wrap when saturated | - -${"##"} ECC_SINGLE_ERR_ADDR -Latest address of ECC single err -- Reset default: `0x0` -- Reset mask: `0xfffff` - -${"###"} Instances - -| Name | Offset | -|:----------------------|:---------| -| ECC_SINGLE_ERR_ADDR_0 | 0x190 | -| ECC_SINGLE_ERR_ADDR_1 | 0x194 | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "ECC_SINGLE_ERR_ADDR", "bits": 20, "attr": ["ro"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:--------------------|:------------------------------------------| -| 31:20 | | | | Reserved | -| 19:0 | ro | 0x0 | ECC_SINGLE_ERR_ADDR | Latest single error address for this bank | - -${"##"} PHY_ALERT_CFG -Phy alert configuration -- Offset: `0x198` -- Reset default: `0x0` -- Reset mask: `0x3` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "alert_ack", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "alert_trig", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-----------|:----------------------------| -| 31:2 | | | | Reserved | -| 1 | rw | 0x0 | alert_trig | Trigger flash phy alert | -| 0 | rw | 0x0 | alert_ack | Acknowledge flash phy alert | - -${"##"} PHY_STATUS -Flash Phy Status -- Offset: `0x19c` -- Reset default: `0x6` -- Reset mask: `0x7` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "init_wip", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_normal_avail", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_repair_avail", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------------|:----------------------------------| -| 31:3 | | | | Reserved | -| 2 | ro | 0x1 | prog_repair_avail | Program repair supported | -| 1 | ro | 0x1 | prog_normal_avail | Normal program supported | -| 0 | ro | 0x0 | init_wip | Flash phy controller initializing | - -${"##"} Scratch -Flash Controller Scratch -- Offset: `0x1a0` -- Reset default: `0x0` -- Reset mask: `0xffffffff` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "data", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:----------------------------| -| 31:0 | rw | 0x0 | data | Flash ctrl scratch register | - -${"##"} FIFO_LVL -Programmable depth where FIFOs should generate interrupts -- Offset: `0x1a4` -- Reset default: `0xf0f` -- Reset mask: `0x1f1f` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "PROG", "bits": 5, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "RD", "bits": 5, "attr": ["rw"], "rotate": 0}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------| -| 31:13 | | | | Reserved | -| 12:8 | rw | 0xf | RD | When the read FIFO fills to this level, trigger an interrupt. Default value is set such that interrupt does not trigger at reset. | -| 7:5 | | | | Reserved | -| 4:0 | rw | 0xf | PROG | When the program FIFO drains to this level, trigger an interrupt. Default value is set such that interrupt does not trigger at reset. | - -${"##"} FIFO_RST -Reset for flash controller FIFOs -- Offset: `0x1a8` -- Reset default: `0x0` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | rw | 0x0 | EN | Active high resets for both program and read FIFOs. This is especially useful after the controller encounters an error of some kind. This bit will hold the FIFO in reset as long as it is set. | - -${"##"} CURR_FIFO_LVL -Current program and read fifo depth -- Offset: `0x1ac` -- Reset default: `0x0` -- Reset mask: `0x1f1f` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "PROG", "bits": 5, "attr": ["ro"], "rotate": 0}, {"bits": 3}, {"name": "RD", "bits": 5, "attr": ["ro"], "rotate": 0}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:---------------------------| -| 31:13 | | | | Reserved | -| 12:8 | ro | 0x0 | RD | Current read fifo depth | -| 7:5 | | | | Reserved | -| 4:0 | ro | 0x0 | PROG | Current program fifo depth | - -${"##"} prog_fifo -Flash program FIFO. - -The FIFO is 16 entries of 4B flash words. This FIFO can only be programmed -by software after a program operation has been initiated via the !!CONTROL register. -This ensures accidental programming of the program FIFO cannot lock up the system. - -- Word Aligned Offset Range: `0x1b0`to`0x1b0` -- Size (words): `1` -- Access: `wo` -- Byte writes are *not* supported. - -${"##"} rd_fifo -Flash read FIFO. - -The FIFO is 16 entries of 4B flash words - -- Word Aligned Offset Range: `0x1b4`to`0x1b4` -- Size (words): `1` -- Access: `ro` -- Byte writes are *not* supported. - -${"##"} Summary of the **`prim`** interface's registers - -| Name | Offset | Length | Description | -|:-----------------------------------------|:---------|---------:|:--------------| -| flash_ctrl.[`CSR0_REGWEN`](#csr0_regwen) | 0x0 | 4 | | -| flash_ctrl.[`CSR1`](#csr1) | 0x4 | 4 | | -| flash_ctrl.[`CSR2`](#csr2) | 0x8 | 4 | | -| flash_ctrl.[`CSR3`](#csr3) | 0xc | 4 | | -| flash_ctrl.[`CSR4`](#csr4) | 0x10 | 4 | | -| flash_ctrl.[`CSR5`](#csr5) | 0x14 | 4 | | -| flash_ctrl.[`CSR6`](#csr6) | 0x18 | 4 | | -| flash_ctrl.[`CSR7`](#csr7) | 0x1c | 4 | | -| flash_ctrl.[`CSR8`](#csr8) | 0x20 | 4 | | -| flash_ctrl.[`CSR9`](#csr9) | 0x24 | 4 | | -| flash_ctrl.[`CSR10`](#csr10) | 0x28 | 4 | | -| flash_ctrl.[`CSR11`](#csr11) | 0x2c | 4 | | -| flash_ctrl.[`CSR12`](#csr12) | 0x30 | 4 | | -| flash_ctrl.[`CSR13`](#csr13) | 0x34 | 4 | | -| flash_ctrl.[`CSR14`](#csr14) | 0x38 | 4 | | -| flash_ctrl.[`CSR15`](#csr15) | 0x3c | 4 | | -| flash_ctrl.[`CSR16`](#csr16) | 0x40 | 4 | | -| flash_ctrl.[`CSR17`](#csr17) | 0x44 | 4 | | -| flash_ctrl.[`CSR18`](#csr18) | 0x48 | 4 | | -| flash_ctrl.[`CSR19`](#csr19) | 0x4c | 4 | | -| flash_ctrl.[`CSR20`](#csr20) | 0x50 | 4 | | - -${"##"} CSR0_REGWEN - -- Offset: `0x0` -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------------| -| 31:1 | | | Reserved | -| 0 | rw0c | 0x1 | [field0](#csr0_regwen--field0) | - -${"###"} CSR0_REGWEN . field0 - -All values are reserved. - -${"##"} CSR1 - -- Offset: `0x4` -- Reset default: `0x0` -- Reset mask: `0x1fff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 5, "attr": ["rw"], "rotate": 0}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:13 | | | Reserved | -| 12:8 | rw | 0x0 | [field1](#csr1--field1) | -| 7:0 | rw | 0x0 | [field0](#csr1--field0) | - -${"###"} CSR1 . field1 - -All values are reserved. - -${"###"} CSR1 . field0 - -All values are reserved. - -${"##"} CSR2 - -- Offset: `0x8` -- Reset default: `0x0` -- Reset mask: `0xff` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field1", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field2", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field4", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field5", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field6", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:8 | | | Reserved | -| 7 | rw | 0x0 | [field7](#csr2--field7) | -| 6 | rw1c | 0x0 | [field6](#csr2--field6) | -| 5 | rw1c | 0x0 | [field5](#csr2--field5) | -| 4 | rw1c | 0x0 | [field4](#csr2--field4) | -| 3 | rw | 0x0 | [field3](#csr2--field3) | -| 2 | rw1c | 0x0 | [field2](#csr2--field2) | -| 1 | rw1c | 0x0 | [field1](#csr2--field1) | -| 0 | rw1c | 0x0 | [field0](#csr2--field0) | - -${"###"} CSR2 . field7 - -All values are reserved. - -${"###"} CSR2 . field6 - -All values are reserved. - -${"###"} CSR2 . field5 - -All values are reserved. - -${"###"} CSR2 . field4 - -All values are reserved. - -${"###"} CSR2 . field3 - -All values are reserved. - -${"###"} CSR2 . field2 - -All values are reserved. - -${"###"} CSR2 . field1 - -All values are reserved. - -${"###"} CSR2 . field0 - -All values are reserved. - -${"##"} CSR3 - -- Offset: `0xc` -- Reset default: `0x0` -- Reset mask: `0xfffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "field2", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field3", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field4", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field5", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field7", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field8", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field9", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:28 | | | Reserved | -| 27:26 | rw | 0x0 | [field9](#csr3--field9) | -| 25:24 | rw | 0x0 | [field8](#csr3--field8) | -| 23:21 | rw | 0x0 | [field7](#csr3--field7) | -| 20 | rw | 0x0 | [field6](#csr3--field6) | -| 19:17 | rw | 0x0 | [field5](#csr3--field5) | -| 16:14 | rw | 0x0 | [field4](#csr3--field4) | -| 13:11 | rw | 0x0 | [field3](#csr3--field3) | -| 10:8 | rw | 0x0 | [field2](#csr3--field2) | -| 7:4 | rw | 0x0 | [field1](#csr3--field1) | -| 3:0 | rw | 0x0 | [field0](#csr3--field0) | - -${"###"} CSR3 . field9 - -All values are reserved. - -${"###"} CSR3 . field8 - -All values are reserved. - -${"###"} CSR3 . field7 - -All values are reserved. - -${"###"} CSR3 . field6 - -All values are reserved. - -${"###"} CSR3 . field5 - -All values are reserved. - -${"###"} CSR3 . field4 - -All values are reserved. - -${"###"} CSR3 . field3 - -All values are reserved. - -${"###"} CSR3 . field2 - -All values are reserved. - -${"###"} CSR3 . field1 - -All values are reserved. - -${"###"} CSR3 . field0 - -All values are reserved. - -${"##"} CSR4 - -- Offset: `0x10` -- Reset default: `0x0` -- Reset mask: `0xfff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field1", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field2", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field3", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:12 | | | Reserved | -| 11:9 | rw | 0x0 | [field3](#csr4--field3) | -| 8:6 | rw | 0x0 | [field2](#csr4--field2) | -| 5:3 | rw | 0x0 | [field1](#csr4--field1) | -| 2:0 | rw | 0x0 | [field0](#csr4--field0) | - -${"###"} CSR4 . field3 - -All values are reserved. - -${"###"} CSR4 . field2 - -All values are reserved. - -${"###"} CSR4 . field1 - -All values are reserved. - -${"###"} CSR4 . field0 - -All values are reserved. - -${"##"} CSR5 - -- Offset: `0x14` -- Reset default: `0x0` -- Reset mask: `0x7fffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field1", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field2", "bits": 9, "attr": ["rw"], "rotate": 0}, {"name": "field3", "bits": 5, "attr": ["rw"], "rotate": 0}, {"name": "field4", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 9}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:23 | | | Reserved | -| 22:19 | rw | 0x0 | [field4](#csr5--field4) | -| 18:14 | rw | 0x0 | [field3](#csr5--field3) | -| 13:5 | rw | 0x0 | [field2](#csr5--field2) | -| 4:3 | rw | 0x0 | [field1](#csr5--field1) | -| 2:0 | rw | 0x0 | [field0](#csr5--field0) | - -${"###"} CSR5 . field4 - -All values are reserved. - -${"###"} CSR5 . field3 - -All values are reserved. - -${"###"} CSR5 . field2 - -All values are reserved. - -${"###"} CSR5 . field1 - -All values are reserved. - -${"###"} CSR5 . field0 - -All values are reserved. - -${"##"} CSR6 - -- Offset: `0x18` -- Reset default: `0x0` -- Reset mask: `0x1ffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field1", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field2", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field3", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field4", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field5", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field6", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:25 | | | Reserved | -| 24 | rw | 0x0 | [field8](#csr6--field8) | -| 23 | rw | 0x0 | [field7](#csr6--field7) | -| 22:21 | rw | 0x0 | [field6](#csr6--field6) | -| 20:19 | rw | 0x0 | [field5](#csr6--field5) | -| 18:17 | rw | 0x0 | [field4](#csr6--field4) | -| 16:14 | rw | 0x0 | [field3](#csr6--field3) | -| 13:6 | rw | 0x0 | [field2](#csr6--field2) | -| 5:3 | rw | 0x0 | [field1](#csr6--field1) | -| 2:0 | rw | 0x0 | [field0](#csr6--field0) | - -${"###"} CSR6 . field8 - -All values are reserved. - -${"###"} CSR6 . field7 - -All values are reserved. - -${"###"} CSR6 . field6 - -All values are reserved. - -${"###"} CSR6 . field5 - -All values are reserved. - -${"###"} CSR6 . field4 - -All values are reserved. - -${"###"} CSR6 . field3 - -All values are reserved. - -${"###"} CSR6 . field2 - -All values are reserved. - -${"###"} CSR6 . field1 - -All values are reserved. - -${"###"} CSR6 . field0 - -All values are reserved. - -${"##"} CSR7 - -- Offset: `0x1c` -- Reset default: `0x0` -- Reset mask: `0x1ffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 15}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:17 | | | Reserved | -| 16:8 | rw | 0x0 | [field1](#csr7--field1) | -| 7:0 | rw | 0x0 | [field0](#csr7--field0) | - -${"###"} CSR7 . field1 - -All values are reserved. - -${"###"} CSR7 . field0 - -All values are reserved. - -${"##"} CSR8 - -- Offset: `0x20` -- Reset default: `0x0` -- Reset mask: `0xffffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:0 | rw | 0x0 | [field0](#csr8--field0) | - -${"###"} CSR8 . field0 - -All values are reserved. - -${"##"} CSR9 - -- Offset: `0x24` -- Reset default: `0x0` -- Reset mask: `0xffffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:0 | rw | 0x0 | [field0](#csr9--field0) | - -${"###"} CSR9 . field0 - -All values are reserved. - -${"##"} CSR10 - -- Offset: `0x28` -- Reset default: `0x0` -- Reset mask: `0xffffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:0 | rw | 0x0 | [field0](#csr10--field0) | - -${"###"} CSR10 . field0 - -All values are reserved. - -${"##"} CSR11 - -- Offset: `0x2c` -- Reset default: `0x0` -- Reset mask: `0xffffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:0 | rw | 0x0 | [field0](#csr11--field0) | - -${"###"} CSR11 . field0 - -All values are reserved. - -${"##"} CSR12 - -- Offset: `0x30` -- Reset default: `0x0` -- Reset mask: `0x3ff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 22}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:10 | | | Reserved | -| 9:0 | rw | 0x0 | [field0](#csr12--field0) | - -${"###"} CSR12 . field0 - -All values are reserved. - -${"##"} CSR13 - -- Offset: `0x34` -- Reset default: `0x0` -- Reset mask: `0x1fffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 20, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 11}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:21 | | | Reserved | -| 20 | rw | 0x0 | [field1](#csr13--field1) | -| 19:0 | rw | 0x0 | [field0](#csr13--field0) | - -${"###"} CSR13 . field1 - -All values are reserved. - -${"###"} CSR13 . field0 - -All values are reserved. - -${"##"} CSR14 - -- Offset: `0x38` -- Reset default: `0x0` -- Reset mask: `0x1ff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:9 | | | Reserved | -| 8 | rw | 0x0 | [field1](#csr14--field1) | -| 7:0 | rw | 0x0 | [field0](#csr14--field0) | - -${"###"} CSR14 . field1 - -All values are reserved. - -${"###"} CSR14 . field0 - -All values are reserved. - -${"##"} CSR15 - -- Offset: `0x3c` -- Reset default: `0x0` -- Reset mask: `0x1ff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:9 | | | Reserved | -| 8 | rw | 0x0 | [field1](#csr15--field1) | -| 7:0 | rw | 0x0 | [field0](#csr15--field0) | - -${"###"} CSR15 . field1 - -All values are reserved. - -${"###"} CSR15 . field0 - -All values are reserved. - -${"##"} CSR16 - -- Offset: `0x40` -- Reset default: `0x0` -- Reset mask: `0x1ff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:9 | | | Reserved | -| 8 | rw | 0x0 | [field1](#csr16--field1) | -| 7:0 | rw | 0x0 | [field0](#csr16--field0) | - -${"###"} CSR16 . field1 - -All values are reserved. - -${"###"} CSR16 . field0 - -All values are reserved. - -${"##"} CSR17 - -- Offset: `0x44` -- Reset default: `0x0` -- Reset mask: `0x1ff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:9 | | | Reserved | -| 8 | rw | 0x0 | [field1](#csr17--field1) | -| 7:0 | rw | 0x0 | [field0](#csr17--field0) | - -${"###"} CSR17 . field1 - -All values are reserved. - -${"###"} CSR17 . field0 - -All values are reserved. - -${"##"} CSR18 - -- Offset: `0x48` -- Reset default: `0x0` -- Reset mask: `0x1` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:1 | | | Reserved | -| 0 | rw | 0x0 | [field0](#csr18--field0) | - -${"###"} CSR18 . field0 - -All values are reserved. - -${"##"} CSR19 - -- Offset: `0x4c` -- Reset default: `0x0` -- Reset mask: `0x1` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:1 | | | Reserved | -| 0 | rw | 0x0 | [field0](#csr19--field0) | - -${"###"} CSR19 . field0 - -All values are reserved. - -${"##"} CSR20 - -- Offset: `0x50` -- Reset default: `0x0` -- Reset mask: `0x7` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field1", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:3 | | | Reserved | -| 2 | ro | 0x0 | [field2](#csr20--field2) | -| 1 | rw1c | 0x0 | [field1](#csr20--field1) | -| 0 | rw1c | 0x0 | [field0](#csr20--field0) | - -${"###"} CSR20 . field2 - -All values are reserved. - -${"###"} CSR20 . field1 - -All values are reserved. - -${"###"} CSR20 . field0 - -All values are reserved. - -This interface does not expose any registers. diff --git a/hw/ip_templates/pwrmgr/doc/interfaces.md.tpl b/hw/ip_templates/pwrmgr/doc/interfaces.md.tpl index 34a228c54563e0..f02bb8f32791dd 100644 --- a/hw/ip_templates/pwrmgr/doc/interfaces.md.tpl +++ b/hw/ip_templates/pwrmgr/doc/interfaces.md.tpl @@ -1,67 +1,4 @@ # Hardware Interfaces -Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`pwrmgr`** has the following hardware interfaces defined -- Primary Clock: **`clk_i`** -- Other Clocks: **`clk_slow_i`**, **`clk_lc_i`**, **`clk_esc_i`** -- Bus Device Interfaces (TL-UL): **`tl`** -- Bus Host Interfaces (TL-UL): *none* -- Peripheral Pins for Chip IO: *none* - -${"##"} [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) - -| Port Name | Package::Struct | Type | Act | Width | Description | -|:---------------|:--------------------------|:--------|:------|--------:|:--------------| -| pwr_ast | pwrmgr_pkg::pwr_ast | req_rsp | req | 1 | | -| pwr_rst | pwrmgr_pkg::pwr_rst | req_rsp | req | 1 | | -| pwr_clk | pwrmgr_pkg::pwr_clk | req_rsp | req | 1 | | -| pwr_otp | pwrmgr_pkg::pwr_otp | req_rsp | req | 1 | | -| pwr_lc | pwrmgr_pkg::pwr_lc | req_rsp | req | 1 | | -| pwr_flash | pwrmgr_pkg::pwr_flash | uni | rcv | 1 | | -| esc_rst_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | | -| esc_rst_rx | prim_esc_pkg::esc_rx | uni | req | 1 | | -| pwr_cpu | pwrmgr_pkg::pwr_cpu | uni | rcv | 1 | | -| wakeups | logic | uni | rcv | 6 | | -| rstreqs | logic | uni | rcv | 2 | | -| ndmreset_req | logic | uni | rcv | 1 | | -| strap | logic | uni | req | 1 | | -| low_power | logic | uni | req | 1 | | -| rom_ctrl | rom_ctrl_pkg::pwrmgr_data | uni | rcv | 1 | | -| fetch_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | | -| lc_dft_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| sw_rst_req | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | -| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | - -${"##"} Interrupts - -| Interrupt Name | Type | Description | -|:-----------------|:-------|:----------------------------------------------------------| -| wakeup | Event | Wake from low power state. See wake info for more details | - -${"##"} Security Alerts - -| Alert Name | Description | -|:-------------|:----------------------------------------------------------------------------------| -| fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. | - -${"##"} Security Countermeasures - -| Countermeasure ID | Description | -|:------------------------------|:-------------------------------------------------------------------------------------------------------------------------| -| PWRMGR.BUS.INTEGRITY | End-to-end bus integrity scheme. | -| PWRMGR.LC_CTRL.INTERSIG.MUBI | life cycle control / debug signals are multibit. | -| PWRMGR.ROM_CTRL.INTERSIG.MUBI | rom control done/good signals are multibit. | -| PWRMGR.RSTMGR.INTERSIG.MUBI | reset manager software request is multibit. | -| PWRMGR.ESC_RX.CLK.BKGN_CHK | Escalation receiver has a background timeout check | -| PWRMGR.ESC_RX.CLK.LOCAL_ESC | Escalation receiver clock timeout has a local reset escalation | -| PWRMGR.FSM.SPARSE | Sparse encoding for slow and fast state machines. | -| PWRMGR.FSM.TERMINAL | When FSMs reach a bad state, go into a terminate state that does not recover without user or external host intervention. | -| PWRMGR.CTRL_FLOW.GLOBAL_ESC | When global escalation is received, proceed directly to reset. | -| PWRMGR.MAIN_PD.RST.LOCAL_ESC | When main power domain reset glitches, proceed directly to reset. | -| PWRMGR.CTRL.CONFIG.REGWEN | Main control protected by regwen. | -| PWRMGR.WAKEUP.CONFIG.REGWEN | Wakeup configuration protected by regwen. | -| PWRMGR.RESET.CONFIG.REGWEN | Reset configuration protected by regwen. | - - diff --git a/hw/ip_templates/pwrmgr/doc/registers.md.tpl b/hw/ip_templates/pwrmgr/doc/registers.md.tpl index 3b252c7dffdaa0..8f776282a4cf6b 100644 --- a/hw/ip_templates/pwrmgr/doc/registers.md.tpl +++ b/hw/ip_templates/pwrmgr/doc/registers.md.tpl @@ -1,435 +1,4 @@ # Registers -${"##"} Summary - -| Name | Offset | Length | Description | -|:---------------------------------------------------------|:---------|---------:|:--------------------------------------------------------------------------------| -| pwrmgr.[`INTR_STATE`](#intr_state) | 0x0 | 4 | Interrupt State Register | -| pwrmgr.[`INTR_ENABLE`](#intr_enable) | 0x4 | 4 | Interrupt Enable Register | -| pwrmgr.[`INTR_TEST`](#intr_test) | 0x8 | 4 | Interrupt Test Register | -| pwrmgr.[`ALERT_TEST`](#alert_test) | 0xc | 4 | Alert Test Register | -| pwrmgr.[`CTRL_CFG_REGWEN`](#ctrl_cfg_regwen) | 0x10 | 4 | Controls the configurability of the !!CONTROL register. | -| pwrmgr.[`CONTROL`](#control) | 0x14 | 4 | Control register | -| pwrmgr.[`CFG_CDC_SYNC`](#cfg_cdc_sync) | 0x18 | 4 | The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the | -| pwrmgr.[`WAKEUP_EN_REGWEN`](#wakeup_en_regwen) | 0x1c | 4 | Configuration enable for wakeup_en register | -| pwrmgr.[`WAKEUP_EN`](#WAKEUP_EN) | 0x20 | 4 | Bit mask for enabled wakeups | -| pwrmgr.[`WAKE_STATUS`](#WAKE_STATUS) | 0x24 | 4 | A read only register of all current wake requests post enable mask | -| pwrmgr.[`RESET_EN_REGWEN`](#reset_en_regwen) | 0x28 | 4 | Configuration enable for reset_en register | -| pwrmgr.[`RESET_EN`](#RESET_EN) | 0x2c | 4 | Bit mask for enabled reset requests | -| pwrmgr.[`RESET_STATUS`](#RESET_STATUS) | 0x30 | 4 | A read only register of all current reset requests post enable mask | -| pwrmgr.[`ESCALATE_RESET_STATUS`](#escalate_reset_status) | 0x34 | 4 | A read only register of escalation reset request | -| pwrmgr.[`WAKE_INFO_CAPTURE_DIS`](#wake_info_capture_dis) | 0x38 | 4 | Indicates which functions caused the chip to wakeup | -| pwrmgr.[`WAKE_INFO`](#wake_info) | 0x3c | 4 | Indicates which functions caused the chip to wakeup. | -| pwrmgr.[`FAULT_STATUS`](#fault_status) | 0x40 | 4 | A read only register that shows the existing faults | - -${"##"} INTR_STATE -Interrupt State Register -- Offset: `0x0` -- Reset default: `0x0` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "wakeup", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:----------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | rw1c | 0x0 | wakeup | Wake from low power state. See wake info for more details | - -${"##"} INTR_ENABLE -Interrupt Enable Register -- Offset: `0x4` -- Reset default: `0x0` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "wakeup", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | rw | 0x0 | wakeup | Enable interrupt when [`INTR_STATE.wakeup`](#intr_state) is set. | - -${"##"} INTR_TEST -Interrupt Test Register -- Offset: `0x8` -- Reset default: `0x0` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "wakeup", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:----------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | wo | 0x0 | wakeup | Write 1 to force [`INTR_STATE.wakeup`](#intr_state) to 1. | - -${"##"} ALERT_TEST -Alert Test Register -- Offset: `0xc` -- Reset default: `0x0` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------|:-------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. | - -${"##"} CTRL_CFG_REGWEN -Controls the configurability of the [`CONTROL`](#control) register. - -This register ensures the contents do not change once a low power hint and -WFI has occurred. - -It unlocks whenever a low power transition has completed (transition back to the -ACTIVE state) for any reason. -- Offset: `0x10` -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | ro | 0x1 | EN | Configuration enable. This bit defaults to 1 and is set to 0 by hardware when low power entry is initiated. When the device transitions back from low power state to active state, this bit is set back to 1 to allow software configuration of [`CONTROL`](#control) | - -${"##"} CONTROL -Control register -- Offset: `0x14` -- Reset default: `0x180` -- Reset mask: `0x1f1` -- Register enable: [`CTRL_CFG_REGWEN`](#ctrl_cfg_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "LOW_POWER_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "CORE_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IO_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "USB_CLK_EN_LP", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "USB_CLK_EN_ACTIVE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MAIN_PD_N", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------------------------------| -| 31:9 | | | Reserved | -| 8 | rw | 0x1 | [MAIN_PD_N](#control--main_pd_n) | -| 7 | rw | 0x1 | [USB_CLK_EN_ACTIVE](#control--usb_clk_en_active) | -| 6 | rw | 0x0 | [USB_CLK_EN_LP](#control--usb_clk_en_lp) | -| 5 | rw | 0x0 | [IO_CLK_EN](#control--io_clk_en) | -| 4 | rw | 0x0 | [CORE_CLK_EN](#control--core_clk_en) | -| 3:1 | | | Reserved | -| 0 | rw | 0x0 | [LOW_POWER_HINT](#control--low_power_hint) | - -${"###"} CONTROL . MAIN_PD_N -Active low, main power domain power down - -| Value | Name | Description | -|:--------|:-----------|:----------------------------------------------------------| -| 0x0 | Power down | Main power domain is powered down during low power state. | -| 0x1 | Power up | Main power domain is kept powered during low power state | - - -${"###"} CONTROL . USB_CLK_EN_ACTIVE -USB clock enable during active power state - -| Value | Name | Description | -|:--------|:---------|:---------------------------------------------| -| 0x0 | Disabled | USB clock disabled during active power state | -| 0x1 | Enabled | USB clock enabled during active power state | - - -${"###"} CONTROL . USB_CLK_EN_LP -USB clock enable during low power state - -| Value | Name | Description | -|:--------|:---------|:------------------------------------------------------------------------------------------------------------------------------| -| 0x0 | Disabled | USB clock disabled during low power state | -| 0x1 | Enabled | USB clock enabled during low power state. However, if !!CONTROL.MAIN_PD_N is 0, USB clock is disabled during low power state. | - - -${"###"} CONTROL . IO_CLK_EN -IO clock enable during low power state - -| Value | Name | Description | -|:--------|:---------|:-----------------------------------------| -| 0x0 | Disabled | IO clock disabled during low power state | -| 0x1 | Enabled | IO clock enabled during low power state | - - -${"###"} CONTROL . CORE_CLK_EN -core clock enable during low power state - -| Value | Name | Description | -|:--------|:---------|:-------------------------------------------| -| 0x0 | Disabled | Core clock disabled during low power state | -| 0x1 | Enabled | Core clock enabled during low power state | - - -${"###"} CONTROL . LOW_POWER_HINT -The low power hint to power manager. -The hint is an indication for how the manager should treat the next WFI. -Once the power manager begins a low power transition, or if a valid reset request is registered, -this bit is automatically cleared by HW. - -| Value | Name | Description | -|:--------|:----------|:----------------------------------------| -| 0x0 | None | No low power intent | -| 0x1 | Low Power | Next WFI should trigger low power entry | - - -${"##"} CFG_CDC_SYNC -The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the -fast clock domain but used in the slow clock domain. - -The configuration are not propagated across the clock boundary until this -register is triggered and read. See fields below for more details -- Offset: `0x18` -- Reset default: `0x0` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "SYNC", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:----------------------------| -| 31:1 | | | Reserved | -| 0 | rw | 0x0 | [SYNC](#cfg_cdc_sync--sync) | - -${"###"} CFG_CDC_SYNC . SYNC -Configuration sync. When this bit is written to 1, a sync pulse is generated. When -the sync completes, this bit then self clears. - -Software should write this bit to 1, wait for it to clear, before assuming the slow clock -domain has accepted the programmed values. - -${"##"} WAKEUP_EN_REGWEN -Configuration enable for wakeup_en register -- Offset: `0x1c` -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | rw0c | 0x1 | EN | When 1, WAKEUP_EN register can be configured. When 0, WAKEUP_EN register cannot be configured. | - -${"##"} WAKEUP_EN -Bit mask for enabled wakeups -- Offset: `0x20` -- Reset default: `0x0` -- Reset mask: `0x3f` -- Register enable: [`WAKEUP_EN_REGWEN`](#wakeup_en_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------| -| 31:6 | | | | Reserved | -| 5 | rw | 0x0 | EN_5 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | -| 4 | rw | 0x0 | EN_4 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | -| 3 | rw | 0x0 | EN_3 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | -| 2 | rw | 0x0 | EN_2 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | -| 1 | rw | 0x0 | EN_1 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | -| 0 | rw | 0x0 | EN_0 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | - -${"##"} WAKE_STATUS -A read only register of all current wake requests post enable mask -- Offset: `0x24` -- Reset default: `0x0` -- Reset mask: `0x3f` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "VAL_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:-------------------------------| -| 31:6 | | | | Reserved | -| 5 | ro | 0x0 | VAL_5 | Current value of wake requests | -| 4 | ro | 0x0 | VAL_4 | Current value of wake requests | -| 3 | ro | 0x0 | VAL_3 | Current value of wake requests | -| 2 | ro | 0x0 | VAL_2 | Current value of wake requests | -| 1 | ro | 0x0 | VAL_1 | Current value of wake requests | -| 0 | ro | 0x0 | VAL_0 | Current value of wake requests | - -${"##"} RESET_EN_REGWEN -Configuration enable for reset_en register -- Offset: `0x28` -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | rw0c | 0x1 | EN | When 1, RESET_EN register can be configured. When 0, RESET_EN register cannot be configured. | - -${"##"} RESET_EN -Bit mask for enabled reset requests -- Offset: `0x2c` -- Reset default: `0x0` -- Reset mask: `0x3` -- Register enable: [`RESET_EN_REGWEN`](#reset_en_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------| -| 31:2 | | | | Reserved | -| 1 | rw | 0x0 | EN_1 | Whenever a particular bit is set to 1, that reset request is enabled. Whenever a particular bit is set to 0, that reset request cannot reset the device. | -| 0 | rw | 0x0 | EN_0 | Whenever a particular bit is set to 1, that reset request is enabled. Whenever a particular bit is set to 0, that reset request cannot reset the device. | - -${"##"} RESET_STATUS -A read only register of all current reset requests post enable mask -- Offset: `0x30` -- Reset default: `0x0` -- Reset mask: `0x3` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "VAL_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:-------------------------------| -| 31:2 | | | | Reserved | -| 1 | ro | 0x0 | VAL_1 | Current value of reset request | -| 0 | ro | 0x0 | VAL_0 | Current value of reset request | - -${"##"} ESCALATE_RESET_STATUS -A read only register of escalation reset request -- Offset: `0x34` -- Reset default: `0x0` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | ro | 0x0 | VAL | When 1, an escalation reset has been seen. When 0, there is no escalation reset. | - -${"##"} WAKE_INFO_CAPTURE_DIS -Indicates which functions caused the chip to wakeup -- Offset: `0x38` -- Reset default: `0x0` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "VAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | rw | 0x0 | VAL | When written to 1, this actively suppresses the wakeup info capture. When written to 0, wakeup info capture timing is controlled by HW. | - -${"##"} WAKE_INFO -Indicates which functions caused the chip to wakeup. -The wake info recording begins whenever the device begins a valid low power entry. - -This capture is continued until it is explicitly disabled through WAKE_INFO_CAPTURE_DIS. -This means it is possible to capture multiple wakeup reasons. -- Offset: `0x3c` -- Reset default: `0x0` -- Reset mask: `0xff` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "REASONS", "bits": 6, "attr": ["rw1c"], "rotate": 0}, {"name": "FALL_THROUGH", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ABORT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-----------------------------------------| -| 31:8 | | | Reserved | -| 7 | rw1c | 0x0 | [ABORT](#wake_info--abort) | -| 6 | rw1c | 0x0 | [FALL_THROUGH](#wake_info--fall_through) | -| 5:0 | rw1c | 0x0 | [REASONS](#wake_info--reasons) | - -${"###"} WAKE_INFO . ABORT -The abort wakeup reason indicates that despite setting a WFI and providing a low power -hint, an active flash / lifecycle / otp transaction was ongoing when the power controller -attempted to initiate low power entry. - -The power manager detects this condition, halts low power entry and reports as a wakeup reason - -${"###"} WAKE_INFO . FALL_THROUGH -The fall through wakeup reason indicates that despite setting a WFI and providing a low power -hint, an interrupt arrived at just the right time to break the executing core out of WFI. - -The power manager detects this condition, halts low power entry and reports as a wakeup reason - -${"###"} WAKE_INFO . REASONS -Various peripheral wake reasons - -${"##"} FAULT_STATUS -A read only register that shows the existing faults -- Offset: `0x40` -- Reset default: `0x0` -- Reset mask: `0x7` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "REG_INTG_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ESC_TIMEOUT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_PD_GLITCH", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:---------------|:----------------------------------------------------------| -| 31:3 | | | | Reserved | -| 2 | ro | 0x0 | MAIN_PD_GLITCH | When 1, unexpected power glitch was observed on main PD. | -| 1 | ro | 0x0 | ESC_TIMEOUT | When 1, an escalation clock / reset timeout has occurred. | -| 0 | ro | 0x0 | REG_INTG_ERR | When 1, an integrity error has occurred. | - - diff --git a/hw/ip_templates/rstmgr/doc/interfaces.md.tpl b/hw/ip_templates/rstmgr/doc/interfaces.md.tpl index 1f3784c284bdee..ad5fb6104d98fe 100644 --- a/hw/ip_templates/rstmgr/doc/interfaces.md.tpl +++ b/hw/ip_templates/rstmgr/doc/interfaces.md.tpl @@ -13,45 +13,4 @@ Parameter | Default | Description ## Signals -Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`rstmgr`** has the following hardware interfaces defined -- Primary Clock: **`clk_i`** -- Other Clocks: **`clk_aon_i`**, **`clk_io_div4_i`**, **`clk_main_i`**, **`clk_io_i`**, **`clk_io_div2_i`**, **`clk_usb_i`**, **`clk_por_i`** -- Bus Device Interfaces (TL-UL): **`tl`** -- Bus Host Interfaces (TL-UL): *none* -- Peripheral Pins for Chip IO: *none* -- Interrupts: *none* - -${"##"} [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) - -| Port Name | Package::Struct | Type | Act | Width | Description | -|:------------|:---------------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------| -| por_n | logic | uni | rcv | 2 | Root power on reset signals from ast. There is one root reset signal for each core power domain. | -| pwr | pwr_rst | req_rsp | rsp | 1 | Reset request signals from power manager. Power manager can request for specific domains of the lc/sys reset tree to assert. | -| resets | rstmgr_pkg::rstmgr_out | uni | req | 1 | Leaf resets fed to the system. | -| rst_en | rstmgr_pkg::rstmgr_rst_en | uni | req | 1 | Low-power-group outputs used by alert handler. | -| alert_dump | alert_pkg::alert_crashdump | uni | rcv | 1 | Alert handler crash dump information. | -| cpu_dump | rv_core_ibex_pkg::cpu_crash_dump | uni | rcv | 1 | Main processing element crash dump information. | -| sw_rst_req | prim_mubi_pkg::mubi4 | uni | req | 1 | Software requested system reset to pwrmgr. | -| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | - -${"##"} Security Alerts - -| Alert Name | Description | -|:------------------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------| -| fatal_fault | This fatal alert is triggered when a fatal structural fault is detected. Structural faults include errors such as sparse fsm errors and tlul integrity errors. | -| fatal_cnsty_fault | This fatal alert is triggered when a reset consistency fault is detected. It is separated from the category above for clearer error collection and debug. | - -${"##"} Security Countermeasures - -| Countermeasure ID | Description | -|:-------------------------------|:---------------------------------------------------------------------------------------------------------------------------| -| RSTMGR.BUS.INTEGRITY | End-to-end bus integrity scheme. | -| RSTMGR.SCAN.INTERSIG.MUBI | scan control signals are multibit | -| RSTMGR.LEAF.RST.BKGN_CHK | Background consistency checks for each leaf reset. | -| RSTMGR.LEAF.RST.SHADOW | Leaf resets to blocks containing shadow registers are shadowed | -| RSTMGR.LEAF.FSM.SPARSE | Sparsely encoded fsm for each leaf rst check. The Hamming delta is only 3 as there are a significant number of leaf resets | -| RSTMGR.SW_RST.CONFIG.REGWEN | Software reset controls are protected by regwen | -| RSTMGR.DUMP_CTRL.CONFIG.REGWEN | Crash dump controls are protected by regwen | - - diff --git a/hw/ip_templates/rstmgr/doc/registers.md.tpl b/hw/ip_templates/rstmgr/doc/registers.md.tpl index 607ccf28a7dd67..2cc3445b2dd6d9 100644 --- a/hw/ip_templates/rstmgr/doc/registers.md.tpl +++ b/hw/ip_templates/rstmgr/doc/registers.md.tpl @@ -1,336 +1,4 @@ # Registers -${"##"} Summary - -| Name | Offset | Length | Description | -|:---------------------------------------------|:---------|---------:|:-------------------------------------------------------------------| -| rstmgr.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register | -| rstmgr.[`RESET_REQ`](#reset_req) | 0x4 | 4 | Software requested system reset. | -| rstmgr.[`RESET_INFO`](#reset_info) | 0x8 | 4 | Device reset reason. | -| rstmgr.[`ALERT_REGWEN`](#alert_regwen) | 0xc | 4 | Alert write enable | -| rstmgr.[`ALERT_INFO_CTRL`](#alert_info_ctrl) | 0x10 | 4 | Alert info dump controls. | -| rstmgr.[`ALERT_INFO_ATTR`](#alert_info_attr) | 0x14 | 4 | Alert info dump attributes. | -| rstmgr.[`ALERT_INFO`](#alert_info) | 0x18 | 4 | Alert dump information prior to last reset. | -| rstmgr.[`CPU_REGWEN`](#cpu_regwen) | 0x1c | 4 | Cpu write enable | -| rstmgr.[`CPU_INFO_CTRL`](#cpu_info_ctrl) | 0x20 | 4 | Cpu info dump controls. | -| rstmgr.[`CPU_INFO_ATTR`](#cpu_info_attr) | 0x24 | 4 | Cpu info dump attributes. | -| rstmgr.[`CPU_INFO`](#cpu_info) | 0x28 | 4 | Cpu dump information prior to last reset. | -| rstmgr.[`SW_RST_REGWEN_0`](#sw_rst_regwen) | 0x2c | 4 | Register write enable for software controllable resets. | -| rstmgr.[`SW_RST_REGWEN_1`](#sw_rst_regwen) | 0x30 | 4 | Register write enable for software controllable resets. | -| rstmgr.[`SW_RST_REGWEN_2`](#sw_rst_regwen) | 0x34 | 4 | Register write enable for software controllable resets. | -| rstmgr.[`SW_RST_REGWEN_3`](#sw_rst_regwen) | 0x38 | 4 | Register write enable for software controllable resets. | -| rstmgr.[`SW_RST_REGWEN_4`](#sw_rst_regwen) | 0x3c | 4 | Register write enable for software controllable resets. | -| rstmgr.[`SW_RST_REGWEN_5`](#sw_rst_regwen) | 0x40 | 4 | Register write enable for software controllable resets. | -| rstmgr.[`SW_RST_REGWEN_6`](#sw_rst_regwen) | 0x44 | 4 | Register write enable for software controllable resets. | -| rstmgr.[`SW_RST_REGWEN_7`](#sw_rst_regwen) | 0x48 | 4 | Register write enable for software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_0`](#sw_rst_ctrl_n) | 0x4c | 4 | Software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_1`](#sw_rst_ctrl_n) | 0x50 | 4 | Software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_2`](#sw_rst_ctrl_n) | 0x54 | 4 | Software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_3`](#sw_rst_ctrl_n) | 0x58 | 4 | Software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_4`](#sw_rst_ctrl_n) | 0x5c | 4 | Software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_5`](#sw_rst_ctrl_n) | 0x60 | 4 | Software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_6`](#sw_rst_ctrl_n) | 0x64 | 4 | Software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_7`](#sw_rst_ctrl_n) | 0x68 | 4 | Software controllable resets. | -| rstmgr.[`ERR_CODE`](#err_code) | 0x6c | 4 | A bit vector of all the errors that have occurred in reset manager | - -${"##"} ALERT_TEST -Alert Test Register -- Offset: `0x0` -- Reset default: `0x0` -- Reset mask: `0x3` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_cnsty_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:------------------|:-------------------------------------------------| -| 31:2 | | | | Reserved | -| 1 | wo | 0x0 | fatal_cnsty_fault | Write 1 to trigger one alert event of this kind. | -| 0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. | - -${"##"} RESET_REQ -Software requested system reset. -- Offset: `0x4` -- Reset default: `0x9` -- Reset mask: `0xf` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "VAL", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------| -| 31:4 | | | | Reserved | -| 3:0 | rw | 0x9 | VAL | When set to kMultiBitBool4True, a reset to power manager is requested. Upon completion of reset, this bit is automatically cleared by hardware. | - -${"##"} RESET_INFO -Device reset reason. -- Offset: `0x8` -- Reset default: `0x1` -- Reset mask: `0xff` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "POR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "LOW_POWER_EXIT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "SW_RESET", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "HW_REQ", "bits": 5, "attr": ["rw1c"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:----------------------------------------------| -| 31:8 | | | Reserved | -| 7:3 | rw1c | 0x0 | [HW_REQ](#reset_info--hw_req) | -| 2 | rw1c | 0x0 | [SW_RESET](#reset_info--sw_reset) | -| 1 | rw1c | 0x0 | [LOW_POWER_EXIT](#reset_info--low_power_exit) | -| 0 | rw1c | 0x1 | [POR](#reset_info--por) | - -${"###"} RESET_INFO . HW_REQ -Indicates when a device has reset due to a hardware requested reset. -The bit mapping is as follows: -b3: sysrst_ctrl_aon: OpenTitan reset request to `rstmgr` (running on AON clock). -b4: aon_timer_aon: watchdog reset requestt -b5: pwrmgr_aon: main power glitch reset request -b6: alert_handler: escalation reset request -b7: rv_dm: non-debug-module reset request - -${"###"} RESET_INFO . SW_RESET -Indicates when a device has reset due to [`RESET_REQ.`](#reset_req) - -${"###"} RESET_INFO . LOW_POWER_EXIT -Indicates when a device has reset due low power exit. - -${"###"} RESET_INFO . POR -Indicates when a device has reset due to power up. - -${"##"} ALERT_REGWEN -Alert write enable -- Offset: `0xc` -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | rw0c | 0x1 | EN | When 1, [`ALERT_INFO_CTRL`](#alert_info_ctrl) can be modified. | - -${"##"} ALERT_INFO_CTRL -Alert info dump controls. -- Offset: `0x10` -- Reset default: `0x0` -- Reset mask: `0xf1` -- Register enable: [`ALERT_REGWEN`](#alert_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "INDEX", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------| -| 31:8 | | | | Reserved | -| 7:4 | rw | 0x0 | INDEX | Controls which 32-bit value to read. | -| 3:1 | | | | Reserved | -| 0 | rw | 0x0 | EN | Enable alert dump to capture new information. This field is automatically set to 0 upon system reset (even if rstmgr is not reset). | - -${"##"} ALERT_INFO_ATTR -Alert info dump attributes. -- Offset: `0x14` -- Reset default: `0x0` -- Reset mask: `0xf` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "CNT_AVAIL", "bits": 4, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------| -| 31:4 | | | | Reserved | -| 3:0 | ro | 0x0 | CNT_AVAIL | The number of 32-bit values contained in the alert info dump. | - -${"##"} ALERT_INFO - Alert dump information prior to last reset. - Which value read is controlled by the [`ALERT_INFO_CTRL`](#alert_info_ctrl) register. -- Offset: `0x18` -- Reset default: `0x0` -- Reset mask: `0xffffffff` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "VALUE", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:----------------------------------------| -| 31:0 | ro | 0x0 | VALUE | The current 32-bit value of crash dump. | - -${"##"} CPU_REGWEN -Cpu write enable -- Offset: `0x1c` -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | rw0c | 0x1 | EN | When 1, [`CPU_INFO_CTRL`](#cpu_info_ctrl) can be modified. | - -${"##"} CPU_INFO_CTRL -Cpu info dump controls. -- Offset: `0x20` -- Reset default: `0x0` -- Reset mask: `0xf1` -- Register enable: [`CPU_REGWEN`](#cpu_regwen) - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "INDEX", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------| -| 31:8 | | | | Reserved | -| 7:4 | rw | 0x0 | INDEX | Controls which 32-bit value to read. | -| 3:1 | | | | Reserved | -| 0 | rw | 0x0 | EN | Enable cpu dump to capture new information. This field is automatically set to 0 upon system reset (even if rstmgr is not reset). | - -${"##"} CPU_INFO_ATTR -Cpu info dump attributes. -- Offset: `0x24` -- Reset default: `0x0` -- Reset mask: `0xf` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "CNT_AVAIL", "bits": 4, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:----------|:------------------------------------------------------------| -| 31:4 | | | | Reserved | -| 3:0 | ro | 0x0 | CNT_AVAIL | The number of 32-bit values contained in the cpu info dump. | - -${"##"} CPU_INFO - Cpu dump information prior to last reset. - Which value read is controlled by the [`CPU_INFO_CTRL`](#cpu_info_ctrl) register. -- Offset: `0x28` -- Reset default: `0x0` -- Reset mask: `0xffffffff` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "VALUE", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:----------------------------------------| -| 31:0 | ro | 0x0 | VALUE | The current 32-bit value of crash dump. | - -${"##"} SW_RST_REGWEN -Register write enable for software controllable resets. -When a particular bit value is 0, the corresponding value in [`SW_RST_CTRL_N`](#sw_rst_ctrl_n) can no longer be changed. -When a particular bit value is 1, the corresponding value in [`SW_RST_CTRL_N`](#sw_rst_ctrl_n) can be changed. -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Instances - -| Name | Offset | -|:----------------|:---------| -| SW_RST_REGWEN_0 | 0x2c | -| SW_RST_REGWEN_1 | 0x30 | -| SW_RST_REGWEN_2 | 0x34 | -| SW_RST_REGWEN_3 | 0x38 | -| SW_RST_REGWEN_4 | 0x3c | -| SW_RST_REGWEN_5 | 0x40 | -| SW_RST_REGWEN_6 | 0x44 | -| SW_RST_REGWEN_7 | 0x48 | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:-------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | rw0c | 0x1 | EN | Register write enable for software controllable resets | - -${"##"} SW_RST_CTRL_N -Software controllable resets. -When a particular bit value is 0, the corresponding module is held in reset. -When a particular bit value is 1, the corresponding module is not held in reset. -- Reset default: `0x1` -- Reset mask: `0x1` - -${"###"} Instances - -| Name | Offset | -|:----------------|:---------| -| SW_RST_CTRL_N_0 | 0x4c | -| SW_RST_CTRL_N_1 | 0x50 | -| SW_RST_CTRL_N_2 | 0x54 | -| SW_RST_CTRL_N_3 | 0x58 | -| SW_RST_CTRL_N_4 | 0x5c | -| SW_RST_CTRL_N_5 | 0x60 | -| SW_RST_CTRL_N_6 | 0x64 | -| SW_RST_CTRL_N_7 | 0x68 | - - -${"###"} Fields - -```wavejson -{"reg": [{"name": "VAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:---------------------| -| 31:1 | | | | Reserved | -| 0 | rw | 0x1 | VAL | Software reset value | - -${"##"} ERR_CODE -A bit vector of all the errors that have occurred in reset manager -- Offset: `0x6c` -- Reset default: `0x0` -- Reset mask: `0x7` - -${"###"} Fields - -```wavejson -{"reg": [{"name": "REG_INTG_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RESET_CONSISTENCY_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FSM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:----------------------|:------------------------------------------------------| -| 31:3 | | | | Reserved | -| 2 | ro | 0x0 | FSM_ERR | Sparsely encoded fsm error. | -| 1 | ro | 0x0 | RESET_CONSISTENCY_ERR | A inconsistent parent / child reset was observed. | -| 0 | ro | 0x0 | REG_INTG_ERR | The register file has experienced an integrity error. | - -