diff --git a/hw/dv/sv/cip_lib/cip_base_env_cfg.sv b/hw/dv/sv/cip_lib/cip_base_env_cfg.sv
index 979b6223a80298..c8cb6c8d53d10d 100644
--- a/hw/dv/sv/cip_lib/cip_base_env_cfg.sv
+++ b/hw/dv/sv/cip_lib/cip_base_env_cfg.sv
@@ -32,6 +32,9 @@ class cip_base_env_cfg #(type RAL_T = dv_base_reg_block) extends dv_base_env_cfg
   // Flag to indicate if it is an IP or chip level testbench.
   bit                 is_chip;
 
+  //Default timeout of 10ms on TL accesses
+  uint tl_access_timeout_ns = 10_000_000; // 10ms
+  
   // Similar to the associative array above, if DUT has shadow registers, these two associative
   // arrays contains register fields related to shadow register's update and storage error status.
   uvm_reg_data_t      shadow_update_err_status_fields[dv_base_reg_field];
diff --git a/hw/ip/rom_ctrl/dv/env/rom_ctrl_env_cfg.sv b/hw/ip/rom_ctrl/dv/env/rom_ctrl_env_cfg.sv
index 72aa22b8f66c43..908dd4c74b9505 100644
--- a/hw/ip/rom_ctrl/dv/env/rom_ctrl_env_cfg.sv
+++ b/hw/ip/rom_ctrl/dv/env/rom_ctrl_env_cfg.sv
@@ -16,11 +16,6 @@ class rom_ctrl_env_cfg extends cip_base_env_cfg #(.RAL_T(rom_ctrl_regs_reg_block
   // Enables/disable all protocol delays.
   rand bit zero_delays;
 
-  // Default is 10ms (see default_spinwait_timeout_ns in csr_utils_pkg.sv)
-  // We have to increase this here since the ROM check may actually take longer than that,
-  // which sometimes causes blocked TL accesses to time out.
-  uint tl_access_timeout_ns = 40_000_000; // 40ms
-
   // Bias randomization in favor of enabling zero delays less often.
   constraint zero_delays_c {
     zero_delays dist { 0 := 8,
@@ -70,6 +65,12 @@ class rom_ctrl_env_cfg extends cip_base_env_cfg #(.RAL_T(rom_ctrl_regs_reg_block
     // Tell the CIP base code what bit gets set if we see a TL fault.
     tl_intg_alert_fields[ral.fatal_alert_cause.integrity_error] = 1;
     sec_cm_alert_name = "fatal";
+
+    // Default is 10ms (see default_spinwait_timeout_ns in csr_utils_pkg.sv)
+    // We have to increase this here since the ROM check may actually take longer than that,
+    // which sometimes causes blocked TL accesses to time out.
+    tl_access_timeout_ns = 40_000_000; // 40ms
+
   endfunction
 
 endclass