diff --git a/hw/top_darjeeling/data/top_darjeeling.hjson b/hw/top_darjeeling/data/top_darjeeling.hjson
index ec2c11cc675a83..9b1dca9f197bd8 100644
--- a/hw/top_darjeeling/data/top_darjeeling.hjson
+++ b/hw/top_darjeeling/data/top_darjeeling.hjson
@@ -562,7 +562,7 @@
           data_intg_passthru: "true",
           exec:       "True",
           byte_write: "True",
-          size:     "0x1000"
+          size:     "0x1000",
         }
       }
     },
diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv
index f180d07875f9c7..e6425d5fe3ec83 100644
--- a/hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv
+++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv
@@ -91,6 +91,16 @@ package top_darjeeling_pkg;
    */
   parameter int unsigned TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES = 32'h100;
 
+  /**
+   * Peripheral base address for dmi device on lc_ctrl in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR = 32'h20000;
+
+  /**
+   * Peripheral size in bytes for dmi device on lc_ctrl in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES = 32'h1000;
+
   /**
    * Peripheral base address for alert_handler in top darjeeling.
    */
@@ -241,6 +251,16 @@ package top_darjeeling_pkg;
    */
   parameter int unsigned TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES = 32'h1000;
 
+  /**
+   * Peripheral base address for dbg device on rv_dm in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_RV_DM_DBG_BASE_ADDR = 32'h0;
+
+  /**
+   * Peripheral size in bytes for dbg device on rv_dm in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES = 32'h200;
+
   /**
    * Peripheral base address for rv_plic in top darjeeling.
    */
@@ -431,6 +451,16 @@ package top_darjeeling_pkg;
    */
   parameter int unsigned TOP_DARJEELING_MBX0_CORE_SIZE_BYTES = 32'h80;
 
+  /**
+   * Peripheral base address for soc device on mbx0 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX0_SOC_BASE_ADDR = 32'h1465000;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx0 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX0_SOC_SIZE_BYTES = 32'h20;
+
   /**
    * Peripheral base address for core device on mbx1 in top darjeeling.
    */
@@ -441,6 +471,16 @@ package top_darjeeling_pkg;
    */
   parameter int unsigned TOP_DARJEELING_MBX1_CORE_SIZE_BYTES = 32'h80;
 
+  /**
+   * Peripheral base address for soc device on mbx1 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX1_SOC_BASE_ADDR = 32'h1465100;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx1 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX1_SOC_SIZE_BYTES = 32'h20;
+
   /**
    * Peripheral base address for core device on mbx2 in top darjeeling.
    */
@@ -451,6 +491,16 @@ package top_darjeeling_pkg;
    */
   parameter int unsigned TOP_DARJEELING_MBX2_CORE_SIZE_BYTES = 32'h80;
 
+  /**
+   * Peripheral base address for soc device on mbx2 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX2_SOC_BASE_ADDR = 32'h1465200;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx2 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX2_SOC_SIZE_BYTES = 32'h20;
+
   /**
    * Peripheral base address for core device on mbx3 in top darjeeling.
    */
@@ -461,6 +511,16 @@ package top_darjeeling_pkg;
    */
   parameter int unsigned TOP_DARJEELING_MBX3_CORE_SIZE_BYTES = 32'h80;
 
+  /**
+   * Peripheral base address for soc device on mbx3 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX3_SOC_BASE_ADDR = 32'h1465300;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx3 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX3_SOC_SIZE_BYTES = 32'h20;
+
   /**
    * Peripheral base address for core device on mbx4 in top darjeeling.
    */
@@ -471,6 +531,16 @@ package top_darjeeling_pkg;
    */
   parameter int unsigned TOP_DARJEELING_MBX4_CORE_SIZE_BYTES = 32'h80;
 
+  /**
+   * Peripheral base address for soc device on mbx4 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX4_SOC_BASE_ADDR = 32'h1465400;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx4 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX4_SOC_SIZE_BYTES = 32'h20;
+
   /**
    * Peripheral base address for core device on mbx5 in top darjeeling.
    */
@@ -481,6 +551,16 @@ package top_darjeeling_pkg;
    */
   parameter int unsigned TOP_DARJEELING_MBX5_CORE_SIZE_BYTES = 32'h80;
 
+  /**
+   * Peripheral base address for soc device on mbx5 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX5_SOC_BASE_ADDR = 32'h1465500;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx5 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX5_SOC_SIZE_BYTES = 32'h20;
+
   /**
    * Peripheral base address for core device on mbx6 in top darjeeling.
    */
@@ -491,6 +571,16 @@ package top_darjeeling_pkg;
    */
   parameter int unsigned TOP_DARJEELING_MBX6_CORE_SIZE_BYTES = 32'h80;
 
+  /**
+   * Peripheral base address for soc device on mbx6 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX6_SOC_BASE_ADDR = 32'h1465600;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx6 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX6_SOC_SIZE_BYTES = 32'h20;
+
   /**
    * Peripheral base address for core device on mbx_jtag in top darjeeling.
    */
@@ -501,6 +591,16 @@ package top_darjeeling_pkg;
    */
   parameter int unsigned TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES = 32'h80;
 
+  /**
+   * Peripheral base address for soc device on mbx_jtag in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR = 32'h1000;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx_jtag in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES = 32'h20;
+
   /**
    * Peripheral base address for core device on mbx_pcie0 in top darjeeling.
    */
@@ -511,6 +611,16 @@ package top_darjeeling_pkg;
    */
   parameter int unsigned TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES = 32'h80;
 
+  /**
+   * Peripheral base address for soc device on mbx_pcie0 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR = 32'h1460100;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx_pcie0 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES = 32'h20;
+
   /**
    * Peripheral base address for core device on mbx_pcie1 in top darjeeling.
    */
@@ -521,6 +631,16 @@ package top_darjeeling_pkg;
    */
   parameter int unsigned TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES = 32'h80;
 
+  /**
+   * Peripheral base address for soc device on mbx_pcie1 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR = 32'h1460200;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx_pcie1 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES = 32'h20;
+
   /**
    * Peripheral base address for cfg device on rv_core_ibex in top darjeeling.
    */
diff --git a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs
index 2798bf4982658f..a0b76da041d301 100644
--- a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs
+++ b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs
@@ -125,6 +125,19 @@ pub const TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR: usize = 0x30140000;
 /// address between #TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR and
 /// `TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR + TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES`.
 pub const TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES: usize = 0x100;
+/// Peripheral base address for dmi device on lc_ctrl in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR: usize = 0x20000;
+
+/// Peripheral size for dmi device on lc_ctrl in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR and
+/// `TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR + TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES`.
+pub const TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES: usize = 0x1000;
 /// Peripheral base address for alert_handler in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -320,6 +333,19 @@ pub const TOP_DARJEELING_RV_DM_MEM_BASE_ADDR: usize = 0x40000;
 /// address between #TOP_DARJEELING_RV_DM_MEM_BASE_ADDR and
 /// `TOP_DARJEELING_RV_DM_MEM_BASE_ADDR + TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES`.
 pub const TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES: usize = 0x1000;
+/// Peripheral base address for dbg device on rv_dm in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_RV_DM_DBG_BASE_ADDR: usize = 0x0;
+
+/// Peripheral size for dbg device on rv_dm in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_RV_DM_DBG_BASE_ADDR and
+/// `TOP_DARJEELING_RV_DM_DBG_BASE_ADDR + TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES`.
+pub const TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES: usize = 0x200;
 /// Peripheral base address for rv_plic in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -567,6 +593,19 @@ pub const TOP_DARJEELING_MBX0_CORE_BASE_ADDR: usize = 0x22000000;
 /// address between #TOP_DARJEELING_MBX0_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX0_CORE_BASE_ADDR + TOP_DARJEELING_MBX0_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX0_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx0 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX0_SOC_BASE_ADDR: usize = 0x1465000;
+
+/// Peripheral size for soc device on mbx0 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX0_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX0_SOC_BASE_ADDR + TOP_DARJEELING_MBX0_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX0_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx1 in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -580,6 +619,19 @@ pub const TOP_DARJEELING_MBX1_CORE_BASE_ADDR: usize = 0x22000100;
 /// address between #TOP_DARJEELING_MBX1_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX1_CORE_BASE_ADDR + TOP_DARJEELING_MBX1_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX1_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx1 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX1_SOC_BASE_ADDR: usize = 0x1465100;
+
+/// Peripheral size for soc device on mbx1 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX1_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX1_SOC_BASE_ADDR + TOP_DARJEELING_MBX1_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX1_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx2 in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -593,6 +645,19 @@ pub const TOP_DARJEELING_MBX2_CORE_BASE_ADDR: usize = 0x22000200;
 /// address between #TOP_DARJEELING_MBX2_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX2_CORE_BASE_ADDR + TOP_DARJEELING_MBX2_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX2_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx2 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX2_SOC_BASE_ADDR: usize = 0x1465200;
+
+/// Peripheral size for soc device on mbx2 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX2_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX2_SOC_BASE_ADDR + TOP_DARJEELING_MBX2_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX2_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx3 in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -606,6 +671,19 @@ pub const TOP_DARJEELING_MBX3_CORE_BASE_ADDR: usize = 0x22000300;
 /// address between #TOP_DARJEELING_MBX3_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX3_CORE_BASE_ADDR + TOP_DARJEELING_MBX3_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX3_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx3 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX3_SOC_BASE_ADDR: usize = 0x1465300;
+
+/// Peripheral size for soc device on mbx3 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX3_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX3_SOC_BASE_ADDR + TOP_DARJEELING_MBX3_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX3_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx4 in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -619,6 +697,19 @@ pub const TOP_DARJEELING_MBX4_CORE_BASE_ADDR: usize = 0x22000400;
 /// address between #TOP_DARJEELING_MBX4_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX4_CORE_BASE_ADDR + TOP_DARJEELING_MBX4_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX4_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx4 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX4_SOC_BASE_ADDR: usize = 0x1465400;
+
+/// Peripheral size for soc device on mbx4 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX4_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX4_SOC_BASE_ADDR + TOP_DARJEELING_MBX4_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX4_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx5 in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -632,6 +723,19 @@ pub const TOP_DARJEELING_MBX5_CORE_BASE_ADDR: usize = 0x22000500;
 /// address between #TOP_DARJEELING_MBX5_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX5_CORE_BASE_ADDR + TOP_DARJEELING_MBX5_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX5_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx5 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX5_SOC_BASE_ADDR: usize = 0x1465500;
+
+/// Peripheral size for soc device on mbx5 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX5_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX5_SOC_BASE_ADDR + TOP_DARJEELING_MBX5_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX5_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx6 in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -645,6 +749,19 @@ pub const TOP_DARJEELING_MBX6_CORE_BASE_ADDR: usize = 0x22000600;
 /// address between #TOP_DARJEELING_MBX6_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX6_CORE_BASE_ADDR + TOP_DARJEELING_MBX6_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX6_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx6 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX6_SOC_BASE_ADDR: usize = 0x1465600;
+
+/// Peripheral size for soc device on mbx6 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX6_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX6_SOC_BASE_ADDR + TOP_DARJEELING_MBX6_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX6_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx_jtag in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -658,6 +775,19 @@ pub const TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR: usize = 0x22000800;
 /// address between #TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx_jtag in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR: usize = 0x1000;
+
+/// Peripheral size for soc device on mbx_jtag in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx_pcie0 in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -671,6 +801,19 @@ pub const TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR: usize = 0x22040000;
 /// address between #TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR + TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx_pcie0 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR: usize = 0x1460100;
+
+/// Peripheral size for soc device on mbx_pcie0 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR + TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx_pcie1 in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -684,6 +827,19 @@ pub const TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR: usize = 0x22040100;
 /// address between #TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR + TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx_pcie1 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR: usize = 0x1460200;
+
+/// Peripheral size for soc device on mbx_pcie1 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR + TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for cfg device on rv_core_ibex in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -2742,10 +2898,10 @@ pub enum TopDarjeelingHintableClocks {
     MainOtbn = 3,
 }
 
-/// MMIO Region
+/// MMIO Region for `hart`
 ///
 /// MMIO region excludes any memory that is separate from the module
 /// configuration space, i.e. ROM, main SRAM, and flash are excluded but
 /// retention SRAM, spi_device memory, or usbdev memory are included.
 pub const TOP_DARJEELING_MMIO_BASE_ADDR: usize = 0x21100000;
-pub const TOP_DARJEELING_MMIO_SIZE_BYTES: usize = 0xF400020;
+pub const TOP_DARJEELING_MMIO_SIZE_BYTES: usize = 0xF501000;
diff --git a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_memory.rs b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_memory.rs
index 1216ec9816016f..6948fd839a5f94 100644
--- a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_memory.rs
+++ b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_memory.rs
@@ -158,6 +158,19 @@ pub const TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR: usize = 0x30140000;
 /// address between #TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR and
 /// `TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR + TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES`.
 pub const TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES: usize = 0x100;
+/// Peripheral base address for dmi device on lc_ctrl in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR: usize = 0x20000;
+
+/// Peripheral size for dmi device on lc_ctrl in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR and
+/// `TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR + TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES`.
+pub const TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES: usize = 0x1000;
 /// Peripheral base address for alert_handler in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -353,6 +366,19 @@ pub const TOP_DARJEELING_RV_DM_MEM_BASE_ADDR: usize = 0x40000;
 /// address between #TOP_DARJEELING_RV_DM_MEM_BASE_ADDR and
 /// `TOP_DARJEELING_RV_DM_MEM_BASE_ADDR + TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES`.
 pub const TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES: usize = 0x1000;
+/// Peripheral base address for dbg device on rv_dm in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_RV_DM_DBG_BASE_ADDR: usize = 0x0;
+
+/// Peripheral size for dbg device on rv_dm in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_RV_DM_DBG_BASE_ADDR and
+/// `TOP_DARJEELING_RV_DM_DBG_BASE_ADDR + TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES`.
+pub const TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES: usize = 0x200;
 /// Peripheral base address for rv_plic in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -600,6 +626,19 @@ pub const TOP_DARJEELING_MBX0_CORE_BASE_ADDR: usize = 0x22000000;
 /// address between #TOP_DARJEELING_MBX0_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX0_CORE_BASE_ADDR + TOP_DARJEELING_MBX0_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX0_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx0 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX0_SOC_BASE_ADDR: usize = 0x1465000;
+
+/// Peripheral size for soc device on mbx0 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX0_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX0_SOC_BASE_ADDR + TOP_DARJEELING_MBX0_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX0_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx1 in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -613,6 +652,19 @@ pub const TOP_DARJEELING_MBX1_CORE_BASE_ADDR: usize = 0x22000100;
 /// address between #TOP_DARJEELING_MBX1_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX1_CORE_BASE_ADDR + TOP_DARJEELING_MBX1_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX1_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx1 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX1_SOC_BASE_ADDR: usize = 0x1465100;
+
+/// Peripheral size for soc device on mbx1 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX1_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX1_SOC_BASE_ADDR + TOP_DARJEELING_MBX1_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX1_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx2 in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -626,6 +678,19 @@ pub const TOP_DARJEELING_MBX2_CORE_BASE_ADDR: usize = 0x22000200;
 /// address between #TOP_DARJEELING_MBX2_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX2_CORE_BASE_ADDR + TOP_DARJEELING_MBX2_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX2_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx2 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX2_SOC_BASE_ADDR: usize = 0x1465200;
+
+/// Peripheral size for soc device on mbx2 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX2_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX2_SOC_BASE_ADDR + TOP_DARJEELING_MBX2_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX2_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx3 in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -639,6 +704,19 @@ pub const TOP_DARJEELING_MBX3_CORE_BASE_ADDR: usize = 0x22000300;
 /// address between #TOP_DARJEELING_MBX3_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX3_CORE_BASE_ADDR + TOP_DARJEELING_MBX3_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX3_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx3 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX3_SOC_BASE_ADDR: usize = 0x1465300;
+
+/// Peripheral size for soc device on mbx3 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX3_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX3_SOC_BASE_ADDR + TOP_DARJEELING_MBX3_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX3_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx4 in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -652,6 +730,19 @@ pub const TOP_DARJEELING_MBX4_CORE_BASE_ADDR: usize = 0x22000400;
 /// address between #TOP_DARJEELING_MBX4_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX4_CORE_BASE_ADDR + TOP_DARJEELING_MBX4_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX4_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx4 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX4_SOC_BASE_ADDR: usize = 0x1465400;
+
+/// Peripheral size for soc device on mbx4 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX4_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX4_SOC_BASE_ADDR + TOP_DARJEELING_MBX4_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX4_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx5 in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -665,6 +756,19 @@ pub const TOP_DARJEELING_MBX5_CORE_BASE_ADDR: usize = 0x22000500;
 /// address between #TOP_DARJEELING_MBX5_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX5_CORE_BASE_ADDR + TOP_DARJEELING_MBX5_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX5_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx5 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX5_SOC_BASE_ADDR: usize = 0x1465500;
+
+/// Peripheral size for soc device on mbx5 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX5_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX5_SOC_BASE_ADDR + TOP_DARJEELING_MBX5_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX5_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx6 in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -678,6 +782,19 @@ pub const TOP_DARJEELING_MBX6_CORE_BASE_ADDR: usize = 0x22000600;
 /// address between #TOP_DARJEELING_MBX6_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX6_CORE_BASE_ADDR + TOP_DARJEELING_MBX6_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX6_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx6 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX6_SOC_BASE_ADDR: usize = 0x1465600;
+
+/// Peripheral size for soc device on mbx6 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX6_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX6_SOC_BASE_ADDR + TOP_DARJEELING_MBX6_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX6_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx_jtag in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -691,6 +808,19 @@ pub const TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR: usize = 0x22000800;
 /// address between #TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx_jtag in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR: usize = 0x1000;
+
+/// Peripheral size for soc device on mbx_jtag in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx_pcie0 in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -704,6 +834,19 @@ pub const TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR: usize = 0x22040000;
 /// address between #TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR + TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx_pcie0 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR: usize = 0x1460100;
+
+/// Peripheral size for soc device on mbx_pcie0 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR + TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for core device on mbx_pcie1 in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -717,6 +860,19 @@ pub const TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR: usize = 0x22040100;
 /// address between #TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR and
 /// `TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR + TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES`.
 pub const TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES: usize = 0x80;
+/// Peripheral base address for soc device on mbx_pcie1 in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR: usize = 0x1460200;
+
+/// Peripheral size for soc device on mbx_pcie1 in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR + TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES: usize = 0x20;
 /// Peripheral base address for cfg device on rv_core_ibex in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -731,10 +887,10 @@ pub const TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR: usize = 0x211F0000;
 /// `TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_DARJEELING_RV_CORE_IBEX_CFG_SIZE_BYTES`.
 pub const TOP_DARJEELING_RV_CORE_IBEX_CFG_SIZE_BYTES: usize = 0x800;
 
-/// MMIO Region
+/// MMIO Region for `hart`
 ///
 /// MMIO region excludes any memory that is separate from the module
 /// configuration space, i.e. ROM, main SRAM, and flash are excluded but
 /// retention SRAM, spi_device memory, or usbdev memory are included.
 pub const TOP_DARJEELING_MMIO_BASE_ADDR: usize = 0x21100000;
-pub const TOP_DARJEELING_MMIO_SIZE_BYTES: usize = 0xF400020;
+pub const TOP_DARJEELING_MMIO_SIZE_BYTES: usize = 0xF501000;
diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling.h b/hw/top_darjeeling/sw/autogen/top_darjeeling.h
index 391c067a9445f8..bfa997e8386d51 100644
--- a/hw/top_darjeeling/sw/autogen/top_darjeeling.h
+++ b/hw/top_darjeeling/sw/autogen/top_darjeeling.h
@@ -172,6 +172,24 @@ extern "C" {
  */
 #define TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES 0x100u
 
+/**
+ * Peripheral base address for dmi device on lc_ctrl in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR 0x20000u
+
+/**
+ * Peripheral size for dmi device on lc_ctrl in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR and
+ * `TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR + TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES 0x1000u
+
 /**
  * Peripheral base address for alert_handler in top darjeeling.
  *
@@ -442,6 +460,24 @@ extern "C" {
  */
 #define TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES 0x1000u
 
+/**
+ * Peripheral base address for dbg device on rv_dm in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_RV_DM_DBG_BASE_ADDR 0x0u
+
+/**
+ * Peripheral size for dbg device on rv_dm in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_RV_DM_DBG_BASE_ADDR and
+ * `TOP_DARJEELING_RV_DM_DBG_BASE_ADDR + TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES 0x200u
+
 /**
  * Peripheral base address for rv_plic in top darjeeling.
  *
@@ -784,6 +820,24 @@ extern "C" {
  */
 #define TOP_DARJEELING_MBX0_CORE_SIZE_BYTES 0x80u
 
+/**
+ * Peripheral base address for soc device on mbx0 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX0_SOC_BASE_ADDR 0x1465000u
+
+/**
+ * Peripheral size for soc device on mbx0 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX0_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX0_SOC_BASE_ADDR + TOP_DARJEELING_MBX0_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX0_SOC_SIZE_BYTES 0x20u
+
 /**
  * Peripheral base address for core device on mbx1 in top darjeeling.
  *
@@ -802,6 +856,24 @@ extern "C" {
  */
 #define TOP_DARJEELING_MBX1_CORE_SIZE_BYTES 0x80u
 
+/**
+ * Peripheral base address for soc device on mbx1 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX1_SOC_BASE_ADDR 0x1465100u
+
+/**
+ * Peripheral size for soc device on mbx1 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX1_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX1_SOC_BASE_ADDR + TOP_DARJEELING_MBX1_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX1_SOC_SIZE_BYTES 0x20u
+
 /**
  * Peripheral base address for core device on mbx2 in top darjeeling.
  *
@@ -820,6 +892,24 @@ extern "C" {
  */
 #define TOP_DARJEELING_MBX2_CORE_SIZE_BYTES 0x80u
 
+/**
+ * Peripheral base address for soc device on mbx2 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX2_SOC_BASE_ADDR 0x1465200u
+
+/**
+ * Peripheral size for soc device on mbx2 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX2_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX2_SOC_BASE_ADDR + TOP_DARJEELING_MBX2_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX2_SOC_SIZE_BYTES 0x20u
+
 /**
  * Peripheral base address for core device on mbx3 in top darjeeling.
  *
@@ -838,6 +928,24 @@ extern "C" {
  */
 #define TOP_DARJEELING_MBX3_CORE_SIZE_BYTES 0x80u
 
+/**
+ * Peripheral base address for soc device on mbx3 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX3_SOC_BASE_ADDR 0x1465300u
+
+/**
+ * Peripheral size for soc device on mbx3 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX3_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX3_SOC_BASE_ADDR + TOP_DARJEELING_MBX3_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX3_SOC_SIZE_BYTES 0x20u
+
 /**
  * Peripheral base address for core device on mbx4 in top darjeeling.
  *
@@ -856,6 +964,24 @@ extern "C" {
  */
 #define TOP_DARJEELING_MBX4_CORE_SIZE_BYTES 0x80u
 
+/**
+ * Peripheral base address for soc device on mbx4 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX4_SOC_BASE_ADDR 0x1465400u
+
+/**
+ * Peripheral size for soc device on mbx4 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX4_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX4_SOC_BASE_ADDR + TOP_DARJEELING_MBX4_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX4_SOC_SIZE_BYTES 0x20u
+
 /**
  * Peripheral base address for core device on mbx5 in top darjeeling.
  *
@@ -874,6 +1000,24 @@ extern "C" {
  */
 #define TOP_DARJEELING_MBX5_CORE_SIZE_BYTES 0x80u
 
+/**
+ * Peripheral base address for soc device on mbx5 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX5_SOC_BASE_ADDR 0x1465500u
+
+/**
+ * Peripheral size for soc device on mbx5 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX5_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX5_SOC_BASE_ADDR + TOP_DARJEELING_MBX5_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX5_SOC_SIZE_BYTES 0x20u
+
 /**
  * Peripheral base address for core device on mbx6 in top darjeeling.
  *
@@ -892,6 +1036,24 @@ extern "C" {
  */
 #define TOP_DARJEELING_MBX6_CORE_SIZE_BYTES 0x80u
 
+/**
+ * Peripheral base address for soc device on mbx6 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX6_SOC_BASE_ADDR 0x1465600u
+
+/**
+ * Peripheral size for soc device on mbx6 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX6_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX6_SOC_BASE_ADDR + TOP_DARJEELING_MBX6_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX6_SOC_SIZE_BYTES 0x20u
+
 /**
  * Peripheral base address for core device on mbx_jtag in top darjeeling.
  *
@@ -910,6 +1072,24 @@ extern "C" {
  */
 #define TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES 0x80u
 
+/**
+ * Peripheral base address for soc device on mbx_jtag in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR 0x1000u
+
+/**
+ * Peripheral size for soc device on mbx_jtag in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES 0x20u
+
 /**
  * Peripheral base address for core device on mbx_pcie0 in top darjeeling.
  *
@@ -928,6 +1108,24 @@ extern "C" {
  */
 #define TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES 0x80u
 
+/**
+ * Peripheral base address for soc device on mbx_pcie0 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR 0x1460100u
+
+/**
+ * Peripheral size for soc device on mbx_pcie0 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR + TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES 0x20u
+
 /**
  * Peripheral base address for core device on mbx_pcie1 in top darjeeling.
  *
@@ -946,6 +1144,24 @@ extern "C" {
  */
 #define TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES 0x80u
 
+/**
+ * Peripheral base address for soc device on mbx_pcie1 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR 0x1460200u
+
+/**
+ * Peripheral size for soc device on mbx_pcie1 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR + TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES 0x20u
+
 /**
  * Peripheral base address for cfg device on rv_core_ibex in top darjeeling.
  *
@@ -1672,7 +1888,7 @@ typedef enum top_darjeeling_hintable_clocks {
 } top_darjeeling_hintable_clocks_t;
 
 /**
- * MMIO Region
+ * MMIO Region for `hart`
  *
  * MMIO region excludes any memory that is separate from the module
  * configuration space, i.e. ROM, main SRAM, and flash are excluded but
diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h b/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h
index 552e2be44067d7..1c29b9eaf9a256 100644
--- a/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h
+++ b/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h
@@ -230,6 +230,23 @@
  * `TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR + TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES`.
  */
 #define TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for dmi device on lc_ctrl in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR 0x20000
+
+/**
+ * Peripheral size for dmi device on lc_ctrl in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR and
+ * `TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR + TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES 0x1000
 /**
  * Peripheral base address for alert_handler in top darjeeling.
  *
@@ -485,6 +502,23 @@
  * `TOP_DARJEELING_RV_DM_MEM_BASE_ADDR + TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES`.
  */
 #define TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for dbg device on rv_dm in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_RV_DM_DBG_BASE_ADDR 0x0
+
+/**
+ * Peripheral size for dbg device on rv_dm in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_RV_DM_DBG_BASE_ADDR and
+ * `TOP_DARJEELING_RV_DM_DBG_BASE_ADDR + TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES 0x200
 /**
  * Peripheral base address for rv_plic in top darjeeling.
  *
@@ -808,6 +842,23 @@
  * `TOP_DARJEELING_MBX0_CORE_BASE_ADDR + TOP_DARJEELING_MBX0_CORE_SIZE_BYTES`.
  */
 #define TOP_DARJEELING_MBX0_CORE_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for soc device on mbx0 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX0_SOC_BASE_ADDR 0x1465000
+
+/**
+ * Peripheral size for soc device on mbx0 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX0_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX0_SOC_BASE_ADDR + TOP_DARJEELING_MBX0_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX0_SOC_SIZE_BYTES 0x20
 /**
  * Peripheral base address for core device on mbx1 in top darjeeling.
  *
@@ -825,6 +876,23 @@
  * `TOP_DARJEELING_MBX1_CORE_BASE_ADDR + TOP_DARJEELING_MBX1_CORE_SIZE_BYTES`.
  */
 #define TOP_DARJEELING_MBX1_CORE_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for soc device on mbx1 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX1_SOC_BASE_ADDR 0x1465100
+
+/**
+ * Peripheral size for soc device on mbx1 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX1_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX1_SOC_BASE_ADDR + TOP_DARJEELING_MBX1_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX1_SOC_SIZE_BYTES 0x20
 /**
  * Peripheral base address for core device on mbx2 in top darjeeling.
  *
@@ -842,6 +910,23 @@
  * `TOP_DARJEELING_MBX2_CORE_BASE_ADDR + TOP_DARJEELING_MBX2_CORE_SIZE_BYTES`.
  */
 #define TOP_DARJEELING_MBX2_CORE_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for soc device on mbx2 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX2_SOC_BASE_ADDR 0x1465200
+
+/**
+ * Peripheral size for soc device on mbx2 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX2_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX2_SOC_BASE_ADDR + TOP_DARJEELING_MBX2_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX2_SOC_SIZE_BYTES 0x20
 /**
  * Peripheral base address for core device on mbx3 in top darjeeling.
  *
@@ -859,6 +944,23 @@
  * `TOP_DARJEELING_MBX3_CORE_BASE_ADDR + TOP_DARJEELING_MBX3_CORE_SIZE_BYTES`.
  */
 #define TOP_DARJEELING_MBX3_CORE_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for soc device on mbx3 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX3_SOC_BASE_ADDR 0x1465300
+
+/**
+ * Peripheral size for soc device on mbx3 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX3_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX3_SOC_BASE_ADDR + TOP_DARJEELING_MBX3_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX3_SOC_SIZE_BYTES 0x20
 /**
  * Peripheral base address for core device on mbx4 in top darjeeling.
  *
@@ -876,6 +978,23 @@
  * `TOP_DARJEELING_MBX4_CORE_BASE_ADDR + TOP_DARJEELING_MBX4_CORE_SIZE_BYTES`.
  */
 #define TOP_DARJEELING_MBX4_CORE_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for soc device on mbx4 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX4_SOC_BASE_ADDR 0x1465400
+
+/**
+ * Peripheral size for soc device on mbx4 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX4_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX4_SOC_BASE_ADDR + TOP_DARJEELING_MBX4_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX4_SOC_SIZE_BYTES 0x20
 /**
  * Peripheral base address for core device on mbx5 in top darjeeling.
  *
@@ -893,6 +1012,23 @@
  * `TOP_DARJEELING_MBX5_CORE_BASE_ADDR + TOP_DARJEELING_MBX5_CORE_SIZE_BYTES`.
  */
 #define TOP_DARJEELING_MBX5_CORE_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for soc device on mbx5 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX5_SOC_BASE_ADDR 0x1465500
+
+/**
+ * Peripheral size for soc device on mbx5 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX5_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX5_SOC_BASE_ADDR + TOP_DARJEELING_MBX5_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX5_SOC_SIZE_BYTES 0x20
 /**
  * Peripheral base address for core device on mbx6 in top darjeeling.
  *
@@ -910,6 +1046,23 @@
  * `TOP_DARJEELING_MBX6_CORE_BASE_ADDR + TOP_DARJEELING_MBX6_CORE_SIZE_BYTES`.
  */
 #define TOP_DARJEELING_MBX6_CORE_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for soc device on mbx6 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX6_SOC_BASE_ADDR 0x1465600
+
+/**
+ * Peripheral size for soc device on mbx6 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX6_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX6_SOC_BASE_ADDR + TOP_DARJEELING_MBX6_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX6_SOC_SIZE_BYTES 0x20
 /**
  * Peripheral base address for core device on mbx_jtag in top darjeeling.
  *
@@ -927,6 +1080,23 @@
  * `TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES`.
  */
 #define TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for soc device on mbx_jtag in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR 0x1000
+
+/**
+ * Peripheral size for soc device on mbx_jtag in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES 0x20
 /**
  * Peripheral base address for core device on mbx_pcie0 in top darjeeling.
  *
@@ -944,6 +1114,23 @@
  * `TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR + TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES`.
  */
 #define TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for soc device on mbx_pcie0 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR 0x1460100
+
+/**
+ * Peripheral size for soc device on mbx_pcie0 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR + TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES 0x20
 /**
  * Peripheral base address for core device on mbx_pcie1 in top darjeeling.
  *
@@ -961,6 +1148,23 @@
  * `TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR + TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES`.
  */
 #define TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for soc device on mbx_pcie1 in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR 0x1460200
+
+/**
+ * Peripheral size for soc device on mbx_pcie1 in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR + TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES 0x20
 /**
  * Peripheral base address for cfg device on rv_core_ibex in top darjeeling.
  *
@@ -980,7 +1184,7 @@
 #define TOP_DARJEELING_RV_CORE_IBEX_CFG_SIZE_BYTES 0x800
 
 /**
- * MMIO Region
+ * MMIO Region for `hart`
  *
  * MMIO region excludes any memory that is separate from the module
  * configuration space, i.e. ROM, main SRAM, and flash are excluded but
diff --git a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs
index cbdd9578a8922c..428ab919204900 100644
--- a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs
+++ b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs
@@ -3178,7 +3178,7 @@ pub enum TopEarlgreyHintableClocks {
     MainOtbn = 3,
 }
 
-/// MMIO Region
+/// MMIO Region for `hart`
 ///
 /// MMIO region excludes any memory that is separate from the module
 /// configuration space, i.e. ROM, main SRAM, and flash are excluded but
diff --git a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey_memory.rs b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey_memory.rs
index cb7d88b7fe07ba..5467fec7bbaf4e 100644
--- a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey_memory.rs
+++ b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey_memory.rs
@@ -688,7 +688,7 @@ pub const TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR: usize = 0x411F0000;
 /// `TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES`.
 pub const TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES: usize = 0x800;
 
-/// MMIO Region
+/// MMIO Region for `hart`
 ///
 /// MMIO region excludes any memory that is separate from the module
 /// configuration space, i.e. ROM, main SRAM, and flash are excluded but
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index ee2efcf2926382..cf4f4872feaa10 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -1768,7 +1768,7 @@ typedef enum top_earlgrey_hintable_clocks {
 } top_earlgrey_hintable_clocks_t;
 
 /**
- * MMIO Region
+ * MMIO Region for `hart`
  *
  * MMIO region excludes any memory that is separate from the module
  * configuration space, i.e. ROM, main SRAM, and flash are excluded but
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
index ee406dedc407cd..1de2fd39313871 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
@@ -914,7 +914,7 @@
 #define TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES 0x800
 
 /**
- * MMIO Region
+ * MMIO Region for `hart`
  *
  * MMIO region excludes any memory that is separate from the module
  * configuration space, i.e. ROM, main SRAM, and flash are excluded but
diff --git a/util/topgen/c.py b/util/topgen/c.py
index ad7f1c42f49fa6..1ad28e268e3c2e 100644
--- a/util/topgen/c.py
+++ b/util/topgen/c.py
@@ -16,12 +16,13 @@
 
 
 class MemoryRegion(object):
-    def __init__(self, name: Name, base_addr: int, size_bytes: int):
+    def __init__(self, name: Name, base_addr: int, size_bytes: int, addr_space: str):
         assert isinstance(base_addr, int)
         self.name = name
         self.base_addr = base_addr
         self.size_bytes = size_bytes
         self.size_words = (size_bytes + 3) // 4
+        self.addr_space = addr_space
 
     def base_addr_name(self):
         return self.name + Name(["base", "addr"])
@@ -111,9 +112,6 @@ def __init__(self, top_info, name_to_block: Dict[str, IpBlock]):
         # The .c file needs the .h file's relative path, store it here
         self.header_path = None
 
-        # TODO: Don't hardcode the address space used for software.
-        self.addr_space = "hart"
-
         self._init_plic_targets()
         self._init_plic_mapping()
         self._init_alert_mapping()
@@ -150,10 +148,11 @@ def devices(self) -> List[Tuple[Tuple[str, Optional[str]], MemoryRegion]]:
                 name = self._top_name + full_if_name
                 base, size = get_base_and_size(self._name_to_block,
                                                inst, if_name)
-                if self.addr_space not in base:
-                    continue
 
-                region = MemoryRegion(name, base[self.addr_space], size)
+                # Return the base address and addr space value of single instance base addr dict
+                base_addr = list(base.values())[0]
+                addr_space = list(base.keys())[0]
+                region = MemoryRegion(name, base_addr, size, addr_space)
                 self.device_regions[inst['name']].update({if_name: region})
                 ret.append((full_if, region))
 
@@ -165,19 +164,22 @@ def memories(self):
             ret.append((m["name"],
                         MemoryRegion(self._top_name +
                                      Name.from_snake_case(m["name"]),
-                                     int(m["base_addr"][self.addr_space], 0),
-                                     int(m["size"], 0))))
+                                     int(m["base_addr"][m["addr_space"]], 0),
+                                     int(m["size"], 0))),
+                        m["addr_space"])
 
         for inst in self.top['module']:
             if "memory" in inst:
                 for if_name, val in inst["memory"].items():
                     base, size = get_base_and_size(self._name_to_block,
                                                    inst, if_name)
-                    if self.addr_space not in base:
-                        continue
+
+                    # Determine addr space from single-element base addrs field
+                    assert(len(inst["base_addrs"][if_name].keys()) == 1)
+                    addr_space = list(inst["base_addrs"][if_name].keys())[0]
 
                     name = self._top_name + Name.from_snake_case(val["label"])
-                    region = MemoryRegion(name, base[self.addr_space], size)
+                    region = MemoryRegion(name, base[addr_space], size, addr_space)
                     ret.append((val["label"], region))
 
         return ret
@@ -519,21 +521,48 @@ def _init_mmio_region(self):
         space, i.e. ROM, main SRAM, and flash are excluded but retention SRAM,
         spi_device memory, or usbdev memory are included.
         """
-        memories = [region.base_addr for (_, region) in self.memories()]
-        # TODO(#14345): Remove the hardcoded "rv_dm" name check below.
-        # TODO: we need a cleaner way to define which buses are visible
-        # by the CPU and which ones are not. For now, exclude every
-        # interface with the name `dbg`, since that is attached to the
-        # debug bus which is not connected to the CPU LSU.
-        regions = [
-            region for ((dev_name, if_name), region) in self.devices()
-            if (dev_name == "sram_ctrl_ret_aon" and if_name == 'ram') or
-               (region.base_addr not in memories and dev_name != "rv_dm" and
-                (if_name is None or if_name != 'dbg'))
+        excluded_addr_spaces = [
+            "soc_dbg",
+            "soc_mbx"
+        ]
+        # List of tuples(dev_name, if_name) which are included in the MMIO region
+        included_devices = [
+            ("sram_ctrl_ret_aon", 'ram'),
         ]
-        # Note: The memory interface of the retention RAM is in the MMIO address space,
-        # which we prefer since it reduces the number of ePMP regions we need.
-        mmio = range(min([r.base_addr for r in regions]),
-                     max([r.base_addr + r.size_bytes for r in regions]))
-        self.mmio = MemoryRegion(self._top_name + Name(["mmio"]), mmio.start,
-                                 mmio.stop - mmio.start)
+        # List of excluded devices by name
+        excluded_devices = [
+            "rv_dm"
+        ]
+
+        self.mmio = {}
+        all_regions = defaultdict(list)
+        memories = defaultdict(list)
+
+        for (_, region) in self.memories():
+            memories[region.addr_space].append(region.base_addr)
+
+        for ((dev_name, if_name), region) in self.devices():
+            if region.addr_space in excluded_addr_spaces:
+                continue
+            if dev_name in excluded_devices:
+                continue
+
+            # Filter for included_devices
+            dev_included = any(dev_name == tpl[0] for tpl in included_devices)
+            if_included = any(if_name == tpl[1] for tpl in included_devices)
+
+            if ((dev_included and if_included) or
+               (region.base_addr not in memories[region.addr_space])):
+                all_regions[region.addr_space].append(region)
+
+        for addr_space, regions in all_regions.items():
+            # Note: The memory interface of the retention RAM is in the MMIO address space,
+            # which we prefer since it reduces the number of ePMP regions we need.
+            mmio = range(min([r.base_addr for r in regions]),
+                         max([r.base_addr + r.size_bytes for r in regions]))
+            # Hack to keep the name of the original address space hart the same
+            name = ["mmio"]
+            if addr_space != "hart":
+                name.append(addr_space)
+            self.mmio[addr_space] = MemoryRegion(self._top_name + Name(name), mmio.start,
+                                                 mmio.stop - mmio.start, addr_space)
\ No newline at end of file
diff --git a/util/topgen/rust.py b/util/topgen/rust.py
index 6fe1e6e0fc554b..0885fef41f8fcc 100644
--- a/util/topgen/rust.py
+++ b/util/topgen/rust.py
@@ -15,12 +15,13 @@
 
 
 class MemoryRegion(object):
-    def __init__(self, name: Name, base_addr: int, size_bytes: int):
+    def __init__(self, name: Name, base_addr: int, size_bytes: int, addr_space: str):
         assert isinstance(base_addr, int)
         self.name = name
         self.base_addr = base_addr
         self.size_bytes = size_bytes
         self.size_words = (size_bytes + 3) // 4
+        self.addr_space = addr_space
 
     def base_addr_name(self):
         return self.name + Name(["base", "addr"])
@@ -202,9 +203,6 @@ def __init__(self, top_info, name_to_block: Dict[str, IpBlock], version_stamp: D
         self.regwidth = int(top_info["datawidth"])
         self.file_header = RustFileHeader("foo.tpl", version_stamp, len(version_stamp) == 0)
 
-        # TODO: Don't hardcode the address space used for software.
-        self.addr_space = "hart"
-
         self._init_plic_targets()
         self._init_plic_mapping()
         self._init_alert_mapping()
@@ -241,10 +239,11 @@ def devices(self) -> List[Tuple[Tuple[str, Optional[str]], MemoryRegion]]:
                 name = self._top_name + full_if_name
                 base, size = get_base_and_size(self._name_to_block,
                                                inst, if_name)
-                if self.addr_space not in base:
-                    continue
 
-                region = MemoryRegion(name, base[self.addr_space], size)
+                # Return the base address and addr space value of single instance base addr dict
+                base_addr = list(base.values())[0]
+                addr_space = list(base.keys())[0]
+                region = MemoryRegion(name, base_addr, size, addr_space)
                 self.device_regions[inst['name']].update({if_name: region})
                 ret.append((full_if, region))
 
@@ -256,20 +255,23 @@ def memories(self):
             ret.append((m["name"],
                         MemoryRegion(self._top_name +
                                      Name.from_snake_case(m["name"]),
-                                     int(m["base_addr"][self.addr_space], 0),
-                                     int(m["size"], 0))))
+                                     int(m["base_addr"][m["addr_space"]], 0),
+                                     int(m["size"], 0))),
+                        m["addr_space"])
 
         for inst in self.top['module']:
             if "memory" in inst:
                 for if_name, val in inst["memory"].items():
                     base, size = get_base_and_size(self._name_to_block,
                                                    inst, if_name)
-                    if self.addr_space not in base:
-                        continue
+
+                    # Determine addr space from single-element base addrs field
+                    assert(len(inst["base_addrs"][if_name].keys()) == 1)
+                    addr_space = list(inst["base_addrs"][if_name].keys())[0]
 
                     # name = self._top_name + Name.from_snake_case(val["label"])
                     name = Name.from_snake_case(val["label"])
-                    region = MemoryRegion(name, base[self.addr_space], size)
+                    region = MemoryRegion(name, base[addr_space], size, addr_space)
                     ret.append((val["label"], region))
 
         return ret
@@ -606,20 +608,48 @@ def _init_mmio_region(self):
         space, i.e. ROM, main SRAM, and flash are excluded but retention SRAM,
         spi_device memory, or usbdev memory are included.
         """
-        memories = [region.base_addr for (_, region) in self.memories()]
-        # TODO(#14345): Remove the hardcoded "rv_dm" name check below.
-        # TODO: we need a cleaner way to define which buses are visible
-        # by the CPU and which ones are not. For now, exclude every
-        # interface with the name `dbg`, since that is attached to the
-        # debug bus which is not connected to the CPU LSU.
-        regions = [
-            region for ((dev_name, if_name), region) in self.devices()
-            if region.base_addr not in memories and dev_name != "rv_dm" and
-            (if_name is None or if_name != 'dbg')
+        excluded_addr_spaces = [
+            "soc_dbg",
+            "soc_mbx"
+        ]
+        # List of tuples(dev_name, if_name) which are included in the MMIO region
+        included_devices = [
+            ("sram_ctrl_ret_aon", 'ram'),
         ]
-        # Note: The memory interface of the retention RAM is in the MMIO address space,
-        # which we prefer since it reduces the number of ePMP regions we need.
-        mmio = range(min([r.base_addr for r in regions]),
-                     max([r.base_addr + r.size_bytes for r in regions]))
-        self.mmio = MemoryRegion(self._top_name + Name(["mmio"]), mmio.start,
-                                 mmio.stop - mmio.start)
+        # List of excluded devices by name
+        excluded_devices = [
+            "rv_dm"
+        ]
+
+        self.mmio = {}
+        all_regions = defaultdict(list)
+        memories = defaultdict(list)
+
+        for (_, region) in self.memories():
+            memories[region.addr_space].append(region.base_addr)
+
+        for ((dev_name, if_name), region) in self.devices():
+            if region.addr_space in excluded_addr_spaces:
+                continue
+            if dev_name in excluded_devices:
+                continue
+
+            # Filter for included_devices
+            dev_included = any(dev_name == tpl[0] for tpl in included_devices)
+            if_included = any(if_name == tpl[1] for tpl in included_devices)
+
+            if ((dev_included and if_included) or
+               (region.base_addr not in memories[region.addr_space])):
+                all_regions[region.addr_space].append(region)
+
+        for addr_space, regions in all_regions.items():
+            # Note: The memory interface of the retention RAM is in the MMIO address space,
+            # which we prefer since it reduces the number of ePMP regions we need.
+            mmio = range(min([r.base_addr for r in regions]),
+                         max([r.base_addr + r.size_bytes for r in regions]))
+            # Hack to keep the name of the original address space hart the same
+            name = ["mmio"]
+            if addr_space != "hart":
+                name.append(addr_space)
+            self.mmio[addr_space] = MemoryRegion(self._top_name + Name(name), mmio.start,
+                                                 mmio.stop - mmio.start, addr_space)
\ No newline at end of file
diff --git a/util/topgen/templates/toplevel.h.tpl b/util/topgen/templates/toplevel.h.tpl
index 74b85614cd201b..fcbfd90b03ec40 100644
--- a/util/topgen/templates/toplevel.h.tpl
+++ b/util/topgen/templates/toplevel.h.tpl
@@ -234,15 +234,17 @@ ${helper.clkmgr_gateable_clocks.render()}
  */
 ${helper.clkmgr_hintable_clocks.render()}
 
+% for addr_space, mmio in helper.mmio.items():
 /**
- * MMIO Region
+ * MMIO Region for `${addr_space}`
  *
  * MMIO region excludes any memory that is separate from the module
  * configuration space, i.e. ROM, main SRAM, and flash are excluded but
  * retention SRAM, spi_device memory, or usbdev memory are included.
  */
-#define ${helper.mmio.base_addr_name().as_c_define()} ${"0x{:X}u".format(helper.mmio.base_addr)}
-#define ${helper.mmio.size_bytes_name().as_c_define()} ${"0x{:X}u".format(helper.mmio.size_bytes)}
+#define ${mmio.base_addr_name().as_c_define()} ${"0x{:X}u".format(mmio.base_addr)}
+#define ${mmio.size_bytes_name().as_c_define()} ${"0x{:X}u".format(mmio.size_bytes)}
+% endfor
 
 // Header Extern Guard
 #ifdef __cplusplus
diff --git a/util/topgen/templates/toplevel.rs.tpl b/util/topgen/templates/toplevel.rs.tpl
index 9971eead9efae6..d83dbb82d39c55 100644
--- a/util/topgen/templates/toplevel.rs.tpl
+++ b/util/topgen/templates/toplevel.rs.tpl
@@ -171,10 +171,12 @@ ${helper.clkmgr_gateable_clocks.render()}
 /// but the clock manager is in control of whether the clock actually is stopped.
 ${helper.clkmgr_hintable_clocks.render()}
 
-/// MMIO Region
+% for addr_space, mmio in helper.mmio.items():
+/// MMIO Region for `${addr_space}`
 ///
 /// MMIO region excludes any memory that is separate from the module
 /// configuration space, i.e. ROM, main SRAM, and flash are excluded but
 /// retention SRAM, spi_device memory, or usbdev memory are included.
-pub const ${helper.mmio.base_addr_name().as_rust_const()}: usize = ${"0x{:X}".format(helper.mmio.base_addr)};
-pub const ${helper.mmio.size_bytes_name().as_rust_const()}: usize = ${"0x{:X}".format(helper.mmio.size_bytes)};
+pub const ${mmio.base_addr_name().as_rust_const()}: usize = ${"0x{:X}".format(mmio.base_addr)};
+pub const ${mmio.size_bytes_name().as_rust_const()}: usize = ${"0x{:X}".format(mmio.size_bytes)};
+% endfor
diff --git a/util/topgen/templates/toplevel_memory.h.tpl b/util/topgen/templates/toplevel_memory.h.tpl
index bd3c73e1117dd0..d64da6263642cb 100644
--- a/util/topgen/templates/toplevel_memory.h.tpl
+++ b/util/topgen/templates/toplevel_memory.h.tpl
@@ -100,15 +100,17 @@
 #define ${size_bytes_name} ${hex_size_bytes}
 % endfor
 
+% for addr_space, mmio in helper.mmio.items():
 /**
- * MMIO Region
+ * MMIO Region for `${addr_space}`
  *
  * MMIO region excludes any memory that is separate from the module
  * configuration space, i.e. ROM, main SRAM, and flash are excluded but
  * retention SRAM, spi_device memory, or usbdev memory are included.
  */
-#define ${helper.mmio.base_addr_name().as_c_define()} ${"0x{:X}".format(helper.mmio.base_addr)}
-#define ${helper.mmio.size_bytes_name().as_c_define()} ${"0x{:X}".format(helper.mmio.size_bytes)}
+#define ${mmio.base_addr_name().as_c_define()} ${"0x{:X}".format(mmio.base_addr)}
+#define ${mmio.size_bytes_name().as_c_define()} ${"0x{:X}".format(mmio.size_bytes)}
+% endfor
 
 #endif  // __ASSEMBLER__
 
diff --git a/util/topgen/templates/toplevel_memory.ld.tpl b/util/topgen/templates/toplevel_memory.ld.tpl
index c026e3d1969a93..7da67323835ccb 100644
--- a/util/topgen/templates/toplevel_memory.ld.tpl
+++ b/util/topgen/templates/toplevel_memory.ld.tpl
@@ -60,12 +60,12 @@ MEMORY {
 % for m in top["module"]:
   % if "memory" in m:
     % for key, mem in m["memory"].items():
-  ${mem["label"]}(${flags(mem)}) : ORIGIN = ${m["base_addrs"][key][helper.addr_space]}, LENGTH = ${mem["size"]}
+  ${mem["label"]}(${flags(mem)}) : ORIGIN = ${list(m["base_addrs"][key].values())[0]}, LENGTH = ${mem["size"]}
     % endfor
   % endif
 % endfor
 % for m in top["memory"]:
-  ${m["name"]}(${memory_to_flags(m)}) : ORIGIN = ${m["base_addr"][helper.addr_space]}, LENGTH = ${m["size"]}
+  ${m["name"]}(${memory_to_flags(m)}) : ORIGIN =  ${m["base_addr"][mem["addr_space"]]}, LENGTH = ${m["size"]}
 % endfor
 ## TODO: need to find a more holistic way to define memories on the wrapper CTN crossbar.
 ## At the moment, the topgen tooling is only aware of the CTN address space as a whole.
@@ -73,7 +73,7 @@ MEMORY {
   % if "memory" in m:
     % for key, mem in m["memory"].items():
       % if mem["label"] == "ctn":
-  ram_ctn(${flags(mem)}) : ORIGIN = ${m["base_addrs"][key][helper.addr_space]} + 0x01000000, LENGTH = 0x00100000
+  ram_ctn(${flags(mem)}) : ORIGIN = ${list(m["base_addrs"][key].values())[0]} + 0x01000000, LENGTH = 0x00100000
       % endif
     % endfor
   % endif
diff --git a/util/topgen/templates/toplevel_memory.rs.tpl b/util/topgen/templates/toplevel_memory.rs.tpl
index 0bf6e3097a1890..0a4ecaeeb4bdf8 100644
--- a/util/topgen/templates/toplevel_memory.rs.tpl
+++ b/util/topgen/templates/toplevel_memory.rs.tpl
@@ -70,10 +70,12 @@ pub const ${base_addr_name}: usize = ${hex_base_addr};
 pub const ${size_bytes_name}: usize = ${hex_size_bytes};
 % endfor
 
-/// MMIO Region
+% for addr_space, mmio in helper.mmio.items():
+/// MMIO Region for `${addr_space}`
 ///
 /// MMIO region excludes any memory that is separate from the module
 /// configuration space, i.e. ROM, main SRAM, and flash are excluded but
 /// retention SRAM, spi_device memory, or usbdev memory are included.
-pub const ${helper.mmio.base_addr_name().as_c_define()}: usize = ${"0x{:X}".format(helper.mmio.base_addr)};
-pub const ${helper.mmio.size_bytes_name().as_c_define()}: usize = ${"0x{:X}".format(helper.mmio.size_bytes)};
+pub const ${mmio.base_addr_name().as_c_define()}: usize = ${"0x{:X}".format(mmio.base_addr)};
+pub const ${mmio.size_bytes_name().as_c_define()}: usize = ${"0x{:X}".format(mmio.size_bytes)};
+% endfor