From 2e69b99b5413c330369ebbf83effe706d1271782 Mon Sep 17 00:00:00 2001 From: Pirmin Vogel Date: Tue, 16 Jan 2024 17:43:38 +0100 Subject: [PATCH] Update lowrisc_ibex to lowRISC/ibex@123d46b4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update code from upstream repository https://github.com/lowRISC/ibex.git to revision 123d46b4d60068502f80c117772a279db12f5af7 * [dv] Fix paths in `merge_cov.py` (Sᴜᴘᴇʀ Lᴇᴇ) * Tweak questa timescale argument (Harry Callahan) * Fixup the questa build/sim command templates in rtl_simulation.yaml (Harry Callahan) * [rtl] Fix FI vulnerability in RF (Pascal Nasahl) * [doc] Update cosim version (Pascal Nasahl) * [util] Update check_tool_requirements.py (Gary Guo) * [rtl] Avoid name collision in ibex_pmp.sv (Rupert Swarbrick) * [dv] Fix performance counter printing in simple system (Rupert Swarbrick) * Fix spelling of separator (Rupert Swarbrick) * [dv] Add an extra key to common_project_cfg.hjson (Rupert Swarbrick) * [verilator] Slight refactor in ibex_tracer to avoid BLKSEQ warning (Rupert Swarbrick) * [verilator] Waive MULTIDRIVEN warning in ibex_tracer.sv (Rupert Swarbrick) * [ibex_pmp/lint] Declare functions before using them (Michael Schaffner) * Update google_riscv-dv to chipsalliance/riscv-dv@71666eb (Greg Chadwick) * [dv] Fix ibex_cmd.py (Greg Chadwick) * Port directed_test_schema.py to recent versions of Pydantic (Rupert Swarbrick) * Tweak ibex_cmd.py to fail more cleanly (Rupert Swarbrick) * Remove (empty) Verible waiver file (Rupert Swarbrick) * [doc] Fix background of Icache block (Marno van der Maas) * [doc] Fix background in block diagram (Marno van der Maas) * Update google_riscv-dv to chipsalliance/riscv-dv@08b1206 (Marno van der Maas) * [dv,doc] Point reference to lowRISC branch (Marno van der Maas) * [dv] Move DVSIM data structures (Marno van der Maas) * [dv] Add common_ifs_pkg.sv to DV files (Marno van der Maas) * [doc] Fix documented mstatus reset value (Greg Chadwick) * [dv] New directed test to cover some scenarios with U-mode execution (Greg Chadwick) * [dv] Fix SET_PMP_CFG macro used by directed tests (Greg Chadwick) * [dv,fcov] Add additional illegal bins to PMP fcov (Greg Chadwick) * [dv, fcov] Increase iterations of riscv_mem_intg_error_test (Greg Chadwick) * Use correct format string for $value$plusargs (Rupert Swarbrick) * Reorder classes in ibex_debug_triggers_overrides.sv (Rupert Swarbrick) * Express some coverpoint crosses in an equivalent way (Rupert Swarbrick) * Drop an import from inside of a class (Rupert Swarbrick) * Re-export imported symbols from ibex_mem_intf_pkg (Rupert Swarbrick) * Bump Spike minimum version (Rupert Swarbrick) * Correct type in scripts_lib.py's run_one (Rupert Swarbrick) * [dv] Add asserts to check alerts for memory integrity failures (Greg Chadwick) * Drop a double entry in rtl_simulation.yaml (Rupert Swarbrick) Signed-off-by: Pirmin Vogel --- hw/ip/rv_core_ibex/lint/rv_core_ibex.waiver | 3 + hw/vendor/lowrisc_ibex.lock.hjson | 2 +- .../lowrisc_ibex/doc/03_reference/cosim.rst | 2 +- .../doc/03_reference/cs_registers.rst | 2 +- .../doc/03_reference/images/blockdiagram.svg | 540 +++++++------ .../doc/03_reference/security.rst | 9 + .../doc/03_reference/verification.rst | 3 +- .../dv/uvm/common_project_cfg.hjson | 5 + .../ibex_cosim_agent/ibex_cosim_scoreboard.sv | 7 +- .../ibex_mem_intf_agent_pkg.sv | 4 + .../dv/uvm/core_ibex/common/prim/prim_and2.sv | 27 + .../dv/uvm/core_ibex/directed_tests/README.md | 2 +- .../core_ibex/directed_tests/custom_macros.h | 6 + .../directed_tests/directed_testlist.yaml | 725 +++++++++--------- .../core_ibex/directed_tests/gen_testlist.py | 7 + .../u_mode_exec_test/u_mode_exec_test.S | 71 ++ .../uvm/core_ibex/fcov/core_ibex_fcov_if.sv | 2 +- .../core_ibex/fcov/core_ibex_pmp_fcov_if.sv | 13 +- .../lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f | 5 + .../ibex_asm_program_gen.sv | 2 +- .../ibex_debug_triggers_overrides.sv | 38 +- .../riscv_dv_extension/testlist.yaml | 2 +- .../core_ibex/scripts/directed_test_schema.py | 39 +- .../dv/uvm/core_ibex/scripts/ibex_cmd.py | 17 +- .../dv/uvm/core_ibex/scripts/merge_cov.py | 8 +- .../uvm/core_ibex/scripts/report_lib/util.py | 2 +- .../dv/uvm/core_ibex/scripts/scripts_lib.py | 2 +- .../dv/uvm/core_ibex/tb/core_ibex_tb_top.sv | 8 + .../dv/uvm/core_ibex/yaml/rtl_simulation.yaml | 7 +- .../dv/verilator/pcount/cpp/ibex_pcounts.cc | 35 +- hw/vendor/lowrisc_ibex/ibex_core.core | 5 - hw/vendor/lowrisc_ibex/ibex_top.core | 7 +- .../lowrisc_ibex/lint/verible_waiver.vbw | 0 .../lowrisc_ibex/lint/verilator_waiver.vlt | 7 + hw/vendor/lowrisc_ibex/rtl/ibex_pmp.sv | 43 +- .../lowrisc_ibex/rtl/ibex_register_file_ff.sv | 111 ++- .../rtl/ibex_register_file_fpga.sv | 118 ++- .../rtl/ibex_register_file_latch.sv | 111 ++- hw/vendor/lowrisc_ibex/rtl/ibex_top.sv | 49 +- hw/vendor/lowrisc_ibex/rtl/ibex_tracer.sv | 56 +- .../util/check_tool_requirements.py | 19 +- .../.github/scripts/code_fixup.py | 106 +++ .../.github/scripts/parse_testlist.py | 26 + .../.github/workflows/build-spike.yml | 63 ++ .../.github/workflows/metrics-regress.yml | 27 - .../.github/workflows/run-tests.yml | 182 +++++ .../euvm/riscv/gen/riscv_asm_program_gen.d | 2 +- .../riscv/gen/riscv_load_store_instr_lib.d | 4 +- .../euvm/riscv/gen/riscv_page_table_entry.d | 2 +- .../riscv/gen/riscv_privileged_common_seq.d | 22 +- .../vendor/google_riscv-dv/requirements.txt | 2 +- .../vendor/google_riscv-dv/run.py | 8 +- .../vendor/google_riscv-dv/scripts/lib.py | 1 + .../scripts/renode_log_to_trace_csv.py | 156 ++++ .../google_riscv-dv/scripts/renode_wrapper.py | 106 +++ .../scripts/spike_log_to_trace_csv.py | 18 +- .../scripts/whisper_log_trace_csv.py | 1 + .../src/isa/riscv_csr_instr.sv | 2 +- .../src/riscv_page_table_list.sv | 3 + .../google_riscv-dv/src/riscv_pmp_cfg.sv | 49 +- .../vendor/google_riscv-dv/yaml/iss.yaml | 5 + .../google_riscv-dv/yaml/simulator.yaml | 3 +- 62 files changed, 2037 insertions(+), 872 deletions(-) create mode 100644 hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/prim/prim_and2.sv create mode 100644 hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/u_mode_exec_test/u_mode_exec_test.S delete mode 100644 hw/vendor/lowrisc_ibex/lint/verible_waiver.vbw create mode 100644 hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/scripts/code_fixup.py create mode 100644 hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/scripts/parse_testlist.py create mode 100644 hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/workflows/build-spike.yml delete mode 100644 hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/workflows/metrics-regress.yml create mode 100644 hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/workflows/run-tests.yml create mode 100644 hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/renode_log_to_trace_csv.py create mode 100644 hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/renode_wrapper.py diff --git a/hw/ip/rv_core_ibex/lint/rv_core_ibex.waiver b/hw/ip/rv_core_ibex/lint/rv_core_ibex.waiver index 0d4c45aa7f3204..5175b79b6d055d 100644 --- a/hw/ip/rv_core_ibex/lint/rv_core_ibex.waiver +++ b/hw/ip/rv_core_ibex/lint/rv_core_ibex.waiver @@ -120,6 +120,9 @@ waive -rules RESET_MUX -location {ibex_lockstep.sv} -regexp {Asynchro -comment "The test enable input used to control the bypass can be considered static" waive -rules RESET_USE -location {ibex_lockstep.sv} -regexp {'rst_shadow_set_q' is used for some other purpose, and as asynchronous reset 'rst_ni' at} -comment "A synchronous counter is needed to release the shadow core reset with a delay of LockstepOffset clock cycles and start the comparison logic one clock cycle later" +waive -rules {CLOCK_USE RESET_USE} -location {ibex_register_file_ff.sv} \ + -regexp {'(clk_i|rst_ni)' is connected to '(prim_onehot_mux)' port} \ + -comment {The module is fully combinatorial, clk/rst are only used for assertions.} # Highlighting my main concerns here, documenting areas to review in next dive # diff --git a/hw/vendor/lowrisc_ibex.lock.hjson b/hw/vendor/lowrisc_ibex.lock.hjson index c6cb24441c3a8b..5f599a9044ee37 100644 --- a/hw/vendor/lowrisc_ibex.lock.hjson +++ b/hw/vendor/lowrisc_ibex.lock.hjson @@ -9,6 +9,6 @@ upstream: { url: https://github.com/lowRISC/ibex.git - rev: 1120e8ddbfe39cfedabe7dda16945e7e809c8389 + rev: 123d46b4d60068502f80c117772a279db12f5af7 } } diff --git a/hw/vendor/lowrisc_ibex/doc/03_reference/cosim.rst b/hw/vendor/lowrisc_ibex/doc/03_reference/cosim.rst index 0f667539863697..d4fd9b76404b66 100644 --- a/hw/vendor/lowrisc_ibex/doc/03_reference/cosim.rst +++ b/hw/vendor/lowrisc_ibex/doc/03_reference/cosim.rst @@ -22,7 +22,7 @@ These extended signals have the prefix ``rvfi_ext`` Setup and Usage --------------- -Clone the `lowRISC fork of Spike `_ and check out the ``ibex-cosim-v0.3`` tag. +Clone the `lowRISC fork of Spike `_ and check out the ``ibex-cosim-v0.5`` tag. Other, later, versions called ``ibex-cosim-v*`` may also work but there's no guarantee of backwards compatibility. Follow the Spike build instructions to build and install Spike. The ``--enable-commitlog`` and ``--enable-misaligned`` options must be passed to ``configure``. diff --git a/hw/vendor/lowrisc_ibex/doc/03_reference/cs_registers.rst b/hw/vendor/lowrisc_ibex/doc/03_reference/cs_registers.rst index e2748ff36c1c00..3b5c07ae2c8631 100644 --- a/hw/vendor/lowrisc_ibex/doc/03_reference/cs_registers.rst +++ b/hw/vendor/lowrisc_ibex/doc/03_reference/cs_registers.rst @@ -113,7 +113,7 @@ Machine Status (mstatus) CSR Address: ``0x300`` -Reset Value: ``0x0000_1800`` +Reset Value: ``0x0000_0080`` +-------+-----+---------------------------------------------------------------------------------+ | Bit# | R/W | Description | diff --git a/hw/vendor/lowrisc_ibex/doc/03_reference/images/blockdiagram.svg b/hw/vendor/lowrisc_ibex/doc/03_reference/images/blockdiagram.svg index cee009a3dec872..16924ccffd433e 100644 --- a/hw/vendor/lowrisc_ibex/doc/03_reference/images/blockdiagram.svg +++ b/hw/vendor/lowrisc_ibex/doc/03_reference/images/blockdiagram.svg @@ -2,21 +2,21 @@ + inkscape:version="1.2.2 (732a01da63, 2022-12-09, custom)" + sodipodi:docname="blockdiagram.svg" + xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" + xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" + xmlns:xlink="http://www.w3.org/1999/xlink" + xmlns="http://www.w3.org/2000/svg" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" + xmlns:cc="http://creativecommons.org/ns#" + xmlns:dc="http://purl.org/dc/elements/1.1/"> + fit-margin-bottom="0" + inkscape:showpageshadow="2" + inkscape:pagecheckerboard="0" + inkscape:deskcolor="#d1d1d1"> + transform="translate(95.448437,-117.39207)" + style="display:inline"> + id="g1776" + inkscape:groupmode="layer" + style="display:inline" + inkscape:label="g1776" + transform="translate(4.9999998e-7)"> + style="fill:url(#linearGradient9433);fill-opacity:1;stroke:#ffe0e5;stroke-width:0.980208;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:10;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" + rx="2.9263036" /> + Ibex Core + style="fill:none;fill-opacity:1;stroke:#6c0e1d;stroke-width:0.980209;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:10;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" + id="rect4554-36-3-0" + width="233.01979" + height="171.01979" + x="-72.958336" + y="117.88216" + ry="2.7583942" + rx="2.7573464" /> + transform="rotate(90)" /> PMP Check + style="fill:#000000;fill-opacity:1;stroke-width:0.264583">PMP Check Data Memory Interface + style="stroke-width:0.264583">Data Memory Interface + style="fill:none;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> ICache + style="font-size:5.64444px;stroke-width:0.264583">ICache PrefetchPrefetchBuffer @@ -433,7 +450,8 @@ height="20" x="155" y="437.51968" />Configuration chooses ICache or Prefetch Buffer Configuration chooses ICache or Prefetch Buffer + PC + style="stroke-width:0.264583">PC Execute Execute + + style="fill:none;fill-opacity:1;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-dasharray:0.5, 0.5;stroke-dashoffset:0;stroke-opacity:1" /> ImmImmRegPCFwd Writeback + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-family:'Liberation Sans';-inkscape-font-specification:'Liberation Sans Bold';stroke-width:0.264583">Writeback Instruction Fetch + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-family:'Liberation Sans';-inkscape-font-specification:'Liberation Sans Bold';stroke-width:0.264583">Instruction Fetch Decode and Execute + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-family:'Liberation Sans';-inkscape-font-specification:'Liberation Sans Bold';stroke-width:0.264583">Decode and Execute @@ -650,9 +669,9 @@ id="text1251" y="11.084595" x="70.869095" - style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:7.05555534px;line-height:1.25;font-family:'Liberation Sans';-inkscape-font-specification:'Liberation Sans';letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.26458332" + style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:7.05556px;line-height:1.25;font-family:'Liberation Sans';-inkscape-font-specification:'Liberation Sans';letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.264583" xml:space="preserve">Register File Optional feature + style="font-style:italic;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:7.05556px;font-family:'Liberation Sans';-inkscape-font-specification:'Liberation Sans, Italic';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;writing-mode:lr-tb;text-anchor:start;stroke-width:0.264583">Optional feature + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> @@ -738,9 +757,9 @@ inkscape:connector-curvature="0" id="path1305-5-8" d="m -43.075356,172.05437 v -2.64583 h -1.322922 l -1.32292,1.32292 1.32292,1.32291 z" - style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.26458332px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> @@ -780,9 +799,9 @@ inkscape:connector-curvature="0" id="path1305-7" d="m -5.5045283,187.92937 v 2.64583 h 1.322922 l 1.322908,-1.32291 -1.322908,-1.32292 z" - style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.26458332px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> @@ -790,14 +809,14 @@ inkscape:connector-curvature="0" id="path1305-0-5-6-2" d="m -10.796198,241.11062 h -2.64583 v 1.32292 l 1.322922,1.32291 1.322908,-1.32291 z" - style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.26458332px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> @@ -805,9 +824,9 @@ inkscape:connector-curvature="0" id="path1305-7-2" d="m -5.5045283,193.22104 v 2.64583 h 1.322922 l 1.322908,-1.32292 -1.322908,-1.32291 z" - style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.26458332px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> @@ -815,9 +834,9 @@ inkscape:connector-curvature="0" id="path1305-0-2-9" d="m -16.087856,169.40854 v 2.64583 h 1.322908 l 1.32292,-1.32292 -1.32292,-1.32291 z" - style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.26458332px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> @@ -857,20 +876,20 @@ inkscape:connector-curvature="0" id="path1305-3" d="m 106.62709,148.30417 h 2.64584 v -1.32291 l -1.32293,-1.32292 -1.32291,1.32292 z" - style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.26458332px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> @@ -917,25 +936,25 @@ inkscape:connector-curvature="0" id="path1305-7-6-0-2-4-0" d="m 112.49964,210.94812 v 2.64583 h 1.32292 l 1.32291,-1.32291 -1.32291,-1.32292 z" - style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.26458332px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> @@ -943,9 +962,9 @@ inkscape:connector-curvature="0" id="path1305-7-6-0-2-4-3" d="m 125.46422,187.92937 v 2.64583 h 1.32292 l 1.32292,-1.32291 -1.32292,-1.32292 z" - style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.26458332px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> @@ -953,49 +972,49 @@ inkscape:connector-curvature="0" id="path1305-5-83" d="m 120.96631,141.62729 v -2.64583 h -1.32292 l -1.32292,1.32291 1.32292,1.32292 z" - style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.26458332px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> @@ -1003,109 +1022,64 @@ inkscape:connector-curvature="0" id="path1305-0-2-9-3" d="m -44.927448,165.43979 v 2.64583 h 1.32292 l 1.322922,-1.32292 -1.322922,-1.32291 z" - style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.26458332px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> - Ibex Core - - - - - - - @@ -1114,42 +1088,27 @@ inkscape:connector-curvature="0" id="path1305-5-0-0" d="m 75.722561,181.57928 1.32291,1.32291 1.32292,-1.32291 v -1.32292 l -1.32292,-1.32292 -1.32291,1.32292 z" - style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.26458332px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> - - - ALU + style="stroke-width:0.264583">ALU + style="fill:#f08c9b;fill-opacity:1;stroke:#000000;stroke-width:0.5;stroke-miterlimit:10;stroke-dasharray:0.5, 0.5;stroke-dashoffset:0;stroke-opacity:1" /> Mult/Div + style="stroke-width:0.264583">Mult/Div + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> @@ -1231,11 +1190,11 @@ inkscape:connector-curvature="0" id="path1305-7-6-0-7-9-1-0-7" d="m 115.54238,265.68947 h -2.64583 v 1.32291 l 1.32291,1.32292 1.32292,-1.32292 z" - style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.26458332px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" inkscape:transform-center-x="3.0153411" inkscape:transform-center-y="-0.98682538" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + id="text10113" /> debug_req_i + style="font-size:2.82222px;stroke-width:0.264583px">debug_req_i @@ -1294,7 +1248,7 @@ ry="1.0000006" /> CSRs + style="stroke-width:0.264583">CSRs + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> @@ -1350,7 +1304,7 @@ ry="1.0000006" /> Decoder + style="stroke-width:0.264583">Decoder + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> @@ -1373,19 +1327,19 @@ inkscape:connector-curvature="0" id="path1305-5-6" d="m 42.895988,197.57386 v -2.23103 h -1.32291 l -1.32292,1.1155 1.32292,1.11553 z" - style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.24296008px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.24296px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.24296px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> @@ -1394,20 +1348,20 @@ inkscape:connector-curvature="0" id="path1305-5-0-0-3" d="m 87.665279,170.00001 -1.146525,1.32291 1.146525,1.32292 h 1.146537 l 1.146525,-1.32292 -1.146525,-1.32291 z" - style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.2463139px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.246314px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.277497px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> @@ -1415,25 +1369,25 @@ inkscape:connector-curvature="0" id="path1305-7-6-0-2-4-1-2" d="m 103.18753,237.46876 h -2.64585 v 1.32291 l 1.32293,1.32292 1.32292,-1.32292 z" - style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.26458332px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> Compressed InstructionCompressed InstructionDecoder Controller + style="stroke-width:0.264583">Controller + + + + diff --git a/hw/vendor/lowrisc_ibex/doc/03_reference/security.rst b/hw/vendor/lowrisc_ibex/doc/03_reference/security.rst index a66dd709568ae4..52a62af50b2dfe 100644 --- a/hw/vendor/lowrisc_ibex/doc/03_reference/security.rst +++ b/hw/vendor/lowrisc_ibex/doc/03_reference/security.rst @@ -90,6 +90,15 @@ When Ibex is configured with the SecureIbex parameter, the write enable signal i This can be useful to detect fault injection attacks. No attempt is made to correct detected errors, but an internal major alert is signaled for the system to take action. +Register file read addresses glitch detection +------------------------------------------- + +When Ibex is configured with the SecureIbex parameter, the read addresses provided to the register file are converted to one-hot encoded signals, and a one-hot encoded MUX is used to select the register to read from. +By using one-hot encoding checkers, glitches in the one-hot encoded signals are detected. +Bit-flips inside the plain read addresses before the one-hot conversion happens are detected by the dual core lockstep. +This can be useful to detect fault injection attacks. +No attempt is made to correct detected errors, but an internal major alert is signaled for the system to take action. + ICache ECC ---------- diff --git a/hw/vendor/lowrisc_ibex/doc/03_reference/verification.rst b/hw/vendor/lowrisc_ibex/doc/03_reference/verification.rst index a4511fb3658619..361597160cd9c4 100644 --- a/hw/vendor/lowrisc_ibex/doc/03_reference/verification.rst +++ b/hw/vendor/lowrisc_ibex/doc/03_reference/verification.rst @@ -111,8 +111,7 @@ In order to run the co-simulation flow, you'll need: + Some custom CSRs + Custom NMI behavior - Ibex verification should work with the Spike version that is tagged as ``ibex-cosim-v0.3``. - Other, later, versions called ``ibex-cosim-v*`` may also work but there's no guarantee of backwards compatibility. + Ibex verification should work with the Spike version that is tagged as ``ibex-cosim-v0.5``. Spike must be built with the ``--enable-commitlog`` and ``--enable-misaligned`` options. ``--enable-commitlog`` is needed to produce log output to track the instructions that were executed. diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/common_project_cfg.hjson b/hw/vendor/lowrisc_ibex/dv/uvm/common_project_cfg.hjson index 21e296fd1c328e..ef0499fe055bf1 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/common_project_cfg.hjson +++ b/hw/vendor/lowrisc_ibex/dv/uvm/common_project_cfg.hjson @@ -5,6 +5,7 @@ project: ibex // These keys are expected by dvsim.py, so we have to set them to something. + book: bogus.book.domain doc_server: bogus.doc.server results_server: bogus.results.server results_html_name: report.html @@ -14,6 +15,10 @@ scratch_path: "{scratch_base_path}/{branch}" tool_srcs_dir: "{scratch_path}/{tool}" + // Common DVSIM data structures + build_pass_patterns: [] + build_fail_patterns: [] + // The current design level design_level: "ip" } diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv index 8123d17dcbab2b..7dca96826a6c3f 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv @@ -6,7 +6,6 @@ `include "cosim_dpi.svh" class ibex_cosim_scoreboard extends uvm_scoreboard; - import ibex_pkg::*; chandle cosim_handle; core_ibex_cosim_cfg cfg; @@ -151,8 +150,10 @@ class ibex_cosim_scoreboard extends uvm_scoreboard; // Set performance counters through a pseudo-backdoor write for (int i=0; i < 10; i++) begin - riscv_cosim_set_csr(cosim_handle, CSR_MHPMCOUNTER3 + i, rvfi_instr.mhpmcounters[i]); - riscv_cosim_set_csr(cosim_handle, CSR_MHPMCOUNTER3H + i, rvfi_instr.mhpmcountersh[i]); + riscv_cosim_set_csr(cosim_handle, + ibex_pkg::CSR_MHPMCOUNTER3 + i, rvfi_instr.mhpmcounters[i]); + riscv_cosim_set_csr(cosim_handle, + ibex_pkg::CSR_MHPMCOUNTER3H + i, rvfi_instr.mhpmcountersh[i]); end riscv_cosim_set_ic_scr_key_valid(cosim_handle, rvfi_instr.ic_scr_key_valid); diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_agent_pkg.sv b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_agent_pkg.sv index 8d21cb8b61d8d2..cde11e1ab3f514 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_agent_pkg.sv +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_agent_pkg.sv @@ -22,4 +22,8 @@ package ibex_mem_intf_agent_pkg; `include "ibex_mem_intf_request_driver.sv" `include "ibex_mem_intf_request_agent.sv" + // Re-export parameters from ibex_mem_intf_pkg so that other packages can access them through this + // package. + export ibex_mem_intf_pkg::*; + endpackage diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/prim/prim_and2.sv b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/prim/prim_and2.sv new file mode 100644 index 00000000000000..157d4dba67ee10 --- /dev/null +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/prim/prim_and2.sv @@ -0,0 +1,27 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Abstract primitives wrapper. +// +// This file is a stop-gap until the DV file list is generated by FuseSoC. +// Its contents are taken from the file which would be generated by FuseSoC. +// https://github.com/lowRISC/ibex/issues/893 + +module prim_and2 #( + parameter int Width = 1 +) ( + input [Width-1:0] in0_i, + input [Width-1:0] in1_i, + output logic [Width-1:0] out_o +); + +if (1) begin : gen_generic + prim_generic_and2 #( + .Width(Width) + ) u_impl_generic ( + .* + ); +end + +endmodule diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/README.md b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/README.md index b63b774e654814..cb82814d9e4eb3 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/README.md +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/README.md @@ -5,7 +5,7 @@ This directory contains the custom directed tests as well as scripts and headers Currently following open source test suites are vendored: - [riscv-tests](https://github.com/riscv-software-src/riscv-tests) - [riscv-arch-tests](https://github.com/riscv-non-isa/riscv-arch-test) -- epmp-tests ([fork](https://github.com/Saad525/riscv-isa-sim) from an opensource [repo](https://github.com/joxie/riscv-isa-sim)) +- epmp-tests ([fork](https://github.com/lowRISC/riscv-isa-sim/tree/mseccfg_tests) from an opensource [repo](https://github.com/joxie/riscv-isa-sim)) ## Generating test list diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/custom_macros.h b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/custom_macros.h index e4c987d40c7eba..b26f719d839b43 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/custom_macros.h +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/custom_macros.h @@ -53,11 +53,13 @@ li t1, pmp_cfg; \ sll t1, t1, t0; \ csrw pmpcfg1, t1; \ + j 4f; \ 2 : li t2, 11; \ bgt t1, t2, 3f; \ li t1, pmp_cfg; \ sll t1, t1, t0; \ csrw pmpcfg2, t1; \ + j 4f; \ 3 : li t2, 15; \ bgt t1, t2, 4f; \ li t1, pmp_cfg; \ @@ -111,6 +113,10 @@ lw s1, 0(s2); \ sw s1, 0(s2); +// This assumes a PMP access failure on the read and write where the handler +// jumps back to the failing access in M mode. If the access succeeds it remains +// in U mode and the second SWITCH_TO_U_MODE will trap (due to attempting a +// write to mstatus). #define RW_ACCESSES_IN_U_MODE(pmp_addr, gran) \ la s0, pmp_addr; \ SWITCH_TO_U_MODE_LABEL(1f); \ diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/directed_testlist.yaml b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/directed_testlist.yaml index 63cebcb283883e..2517f54a7ee4da 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/directed_testlist.yaml +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/directed_testlist.yaml @@ -379,8 +379,113 @@ test_srcs: access_pmp_overlap/access_pmp_overlap.S config: riscv-tests +- test: u_mode_exec_test + desc: > + PMP U mode exec test + iterations: 1 + test_srcs: u_mode_exec_test/u_mode_exec_test.S + config: riscv-tests + # Test-suite: riscv-tests +- test: breakpoint + desc: > + riscv test - breakpoint + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/breakpoint.S + config: riscv-tests + +- test: csr + desc: > + riscv test - csr + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/csr.S + config: riscv-tests + +- test: illegal + desc: > + riscv test - illegal + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/illegal.S + config: riscv-tests + +- test: lh-misaligned + desc: > + riscv test - lh-misaligned + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/lh-misaligned.S + config: riscv-tests + +- test: lw-misaligned + desc: > + riscv test - lw-misaligned + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/lw-misaligned.S + config: riscv-tests + +- test: ma_addr + desc: > + riscv test - ma_addr + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/ma_addr.S + config: riscv-tests + +- test: ma_fetch + desc: > + riscv test - ma_fetch + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/ma_fetch.S + config: riscv-tests + +- test: mcsr + desc: > + riscv test - mcsr + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/mcsr.S + config: riscv-tests + +- test: sbreak + desc: > + riscv test - sbreak + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/sbreak.S + config: riscv-tests + +- test: scall + desc: > + riscv test - scall + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/scall.S + config: riscv-tests + +- test: shamt + desc: > + riscv test - shamt + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/shamt.S + config: riscv-tests + +- test: sh-misaligned + desc: > + riscv test - sh-misaligned + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/sh-misaligned.S + config: riscv-tests + +- test: sw-misaligned + desc: > + riscv test - sw-misaligned + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/sw-misaligned.S + config: riscv-tests + +- test: zicntr + desc: > + riscv test - zicntr + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/zicntr.S + config: riscv-tests + - test: rvc desc: > riscv test - rvc @@ -388,6 +493,62 @@ test_srcs: ../../../../vendor/riscv-tests/isa/rv32uc/rvc.S config: riscv-tests +- test: div + desc: > + riscv test - div + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/div.S + config: riscv-tests + +- test: divu + desc: > + riscv test - divu + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/divu.S + config: riscv-tests + +- test: mulh + desc: > + riscv test - mulh + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mulh.S + config: riscv-tests + +- test: mulhsu + desc: > + riscv test - mulhsu + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mulhsu.S + config: riscv-tests + +- test: mulhu + desc: > + riscv test - mulhu + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mulhu.S + config: riscv-tests + +- test: mul + desc: > + riscv test - mul + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mul.S + config: riscv-tests + +- test: rem + desc: > + riscv test - rem + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/rem.S + config: riscv-tests + +- test: remu + desc: > + riscv test - remu + iterations: 1 + test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/remu.S + config: riscv-tests + - test: addi desc: > riscv test - addi @@ -661,384 +822,251 @@ test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/xor.S config: riscv-tests -- test: div - desc: > - riscv test - div - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/div.S - config: riscv-tests - -- test: divu - desc: > - riscv test - divu - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/divu.S - config: riscv-tests - -- test: mulh - desc: > - riscv test - mulh - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mulh.S - config: riscv-tests - -- test: mulhsu - desc: > - riscv test - mulhsu - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mulhsu.S - config: riscv-tests - -- test: mulhu - desc: > - riscv test - mulhu - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mulhu.S - config: riscv-tests - -- test: mul - desc: > - riscv test - mul - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mul.S - config: riscv-tests - -- test: rem - desc: > - riscv test - rem - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/rem.S - config: riscv-tests - -- test: remu - desc: > - riscv test - remu - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/remu.S - config: riscv-tests - -- test: breakpoint - desc: > - riscv test - breakpoint - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/breakpoint.S - config: riscv-tests - -- test: csr - desc: > - riscv test - csr - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/csr.S - config: riscv-tests - -- test: illegal - desc: > - riscv test - illegal - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/illegal.S - config: riscv-tests - -- test: lh-misaligned - desc: > - riscv test - lh-misaligned - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/lh-misaligned.S - config: riscv-tests - -- test: lw-misaligned - desc: > - riscv test - lw-misaligned - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/lw-misaligned.S - config: riscv-tests - -- test: ma_addr - desc: > - riscv test - ma_addr - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/ma_addr.S - config: riscv-tests - -- test: ma_fetch - desc: > - riscv test - ma_fetch - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/ma_fetch.S - config: riscv-tests - -- test: mcsr - desc: > - riscv test - mcsr - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/mcsr.S - config: riscv-tests - -- test: sbreak - desc: > - riscv test - sbreak - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/sbreak.S - config: riscv-tests - -- test: scall - desc: > - riscv test - scall - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/scall.S - config: riscv-tests - -- test: shamt - desc: > - riscv test - shamt - iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/shamt.S - config: riscv-tests +# Test-suite: riscv-arch-tests -- test: sh-misaligned +- test: div-01 desc: > - riscv test - sh-misaligned + riscv test - div-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/sh-misaligned.S - config: riscv-tests + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/div-01.S + config: riscv-arch-tests -- test: sw-misaligned +- test: divu-01 desc: > - riscv test - sw-misaligned + riscv test - divu-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/sw-misaligned.S - config: riscv-tests + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/divu-01.S + config: riscv-arch-tests -- test: zicntr +- test: mul-01 desc: > - riscv test - zicntr + riscv test - mul-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/zicntr.S - config: riscv-tests - -# Test-suite: riscv-arch-tests + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/mul-01.S + config: riscv-arch-tests -- test: andn-01 +- test: mulh-01 desc: > - riscv test - andn-01 + riscv test - mulh-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/andn-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/mulh-01.S config: riscv-arch-tests -- test: bclr-01 +- test: mulhsu-01 desc: > - riscv test - bclr-01 + riscv test - mulhsu-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bclr-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/mulhsu-01.S config: riscv-arch-tests -- test: bclri-01 +- test: mulhu-01 desc: > - riscv test - bclri-01 + riscv test - mulhu-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bclri-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/mulhu-01.S config: riscv-arch-tests -- test: bext-01 +- test: rem-01 desc: > - riscv test - bext-01 + riscv test - rem-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bext-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/rem-01.S config: riscv-arch-tests -- test: bexti-01 +- test: remu-01 desc: > - riscv test - bexti-01 + riscv test - remu-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bexti-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/remu-01.S config: riscv-arch-tests -- test: binv-01 +- test: cadd-01 desc: > - riscv test - binv-01 + riscv test - cadd-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/binv-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cadd-01.S config: riscv-arch-tests -- test: binvi-01 +- test: caddi-01 desc: > - riscv test - binvi-01 + riscv test - caddi-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/binvi-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/caddi-01.S config: riscv-arch-tests -- test: bset-01 +- test: caddi16sp-01 desc: > - riscv test - bset-01 + riscv test - caddi16sp-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bset-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/caddi16sp-01.S config: riscv-arch-tests -- test: bseti-01 +- test: caddi4spn-01 desc: > - riscv test - bseti-01 + riscv test - caddi4spn-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bseti-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/caddi4spn-01.S config: riscv-arch-tests -- test: clmul-01 +- test: cand-01 desc: > - riscv test - clmul-01 + riscv test - cand-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/clmul-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cand-01.S config: riscv-arch-tests -- test: clmulh-01 +- test: candi-01 desc: > - riscv test - clmulh-01 + riscv test - candi-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/clmulh-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/candi-01.S config: riscv-arch-tests -- test: clmulr-01 +- test: cbeqz-01 desc: > - riscv test - clmulr-01 + riscv test - cbeqz-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/clmulr-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cbeqz-01.S config: riscv-arch-tests -- test: clz-01 +- test: cbnez-01 desc: > - riscv test - clz-01 + riscv test - cbnez-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/clz-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cbnez-01.S config: riscv-arch-tests -- test: cpop-01 +- test: cebreak-01 desc: > - riscv test - cpop-01 + riscv test - cebreak-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/cpop-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cebreak-01.S config: riscv-arch-tests -- test: ctz-01 +- test: cj-01 desc: > - riscv test - ctz-01 + riscv test - cj-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/ctz-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cj-01.S config: riscv-arch-tests -- test: max-01 +- test: cjal-01 desc: > - riscv test - max-01 + riscv test - cjal-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/max-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cjal-01.S config: riscv-arch-tests -- test: maxu-01 +- test: cjalr-01 desc: > - riscv test - maxu-01 + riscv test - cjalr-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/maxu-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cjalr-01.S config: riscv-arch-tests -- test: min-01 +- test: cjr-01 desc: > - riscv test - min-01 + riscv test - cjr-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/min-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cjr-01.S config: riscv-arch-tests -- test: minu-01 +- test: cli-01 desc: > - riscv test - minu-01 + riscv test - cli-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/minu-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cli-01.S config: riscv-arch-tests -- test: orcb_32-01 +- test: clui-01 desc: > - riscv test - orcb_32-01 + riscv test - clui-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/orcb_32-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/clui-01.S config: riscv-arch-tests -- test: orn-01 +- test: clw-01 desc: > - riscv test - orn-01 + riscv test - clw-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/orn-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/clw-01.S config: riscv-arch-tests -- test: rev8_32-01 +- test: clwsp-01 desc: > - riscv test - rev8_32-01 + riscv test - clwsp-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/rev8_32-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/clwsp-01.S config: riscv-arch-tests -- test: rol-01 +- test: cmv-01 desc: > - riscv test - rol-01 + riscv test - cmv-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/rol-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cmv-01.S config: riscv-arch-tests -- test: ror-01 +- test: cnop-01 desc: > - riscv test - ror-01 + riscv test - cnop-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/ror-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cnop-01.S config: riscv-arch-tests -- test: rori-01 +- test: cor-01 desc: > - riscv test - rori-01 + riscv test - cor-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/rori-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cor-01.S config: riscv-arch-tests -- test: sext-b-01 +- test: cslli-01 desc: > - riscv test - sext-b-01 + riscv test - cslli-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/sext-b-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cslli-01.S config: riscv-arch-tests -- test: sext-h-01 +- test: csrai-01 desc: > - riscv test - sext-h-01 + riscv test - csrai-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/sext-h-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/csrai-01.S config: riscv-arch-tests -- test: sh1add-01 +- test: csrli-01 desc: > - riscv test - sh1add-01 + riscv test - csrli-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/sh1add-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/csrli-01.S config: riscv-arch-tests -- test: sh2add-01 +- test: csub-01 desc: > - riscv test - sh2add-01 + riscv test - csub-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/sh2add-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/csub-01.S config: riscv-arch-tests -- test: sh3add-01 +- test: csw-01 desc: > - riscv test - sh3add-01 + riscv test - csw-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/sh3add-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/csw-01.S config: riscv-arch-tests -- test: xnor-01 +- test: cswsp-01 desc: > - riscv test - xnor-01 + riscv test - cswsp-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/xnor-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cswsp-01.S config: riscv-arch-tests -- test: zext-h_32-01 +- test: cxor-01 desc: > - riscv test - zext-h_32-01 + riscv test - cxor-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/zext-h_32-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cxor-01.S config: riscv-arch-tests - test: Fencei @@ -1321,249 +1349,228 @@ test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/xori-01.S config: riscv-arch-tests -- test: cadd-01 - desc: > - riscv test - cadd-01 - iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cadd-01.S - config: riscv-arch-tests - -- test: caddi-01 - desc: > - riscv test - caddi-01 - iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/caddi-01.S - config: riscv-arch-tests - -- test: caddi16sp-01 - desc: > - riscv test - caddi16sp-01 - iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/caddi16sp-01.S - config: riscv-arch-tests - -- test: caddi4spn-01 +- test: andn-01 desc: > - riscv test - caddi4spn-01 + riscv test - andn-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/caddi4spn-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/andn-01.S config: riscv-arch-tests -- test: cand-01 +- test: bclr-01 desc: > - riscv test - cand-01 + riscv test - bclr-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cand-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bclr-01.S config: riscv-arch-tests -- test: candi-01 +- test: bclri-01 desc: > - riscv test - candi-01 + riscv test - bclri-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/candi-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bclri-01.S config: riscv-arch-tests -- test: cbeqz-01 +- test: bext-01 desc: > - riscv test - cbeqz-01 + riscv test - bext-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cbeqz-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bext-01.S config: riscv-arch-tests -- test: cbnez-01 +- test: bexti-01 desc: > - riscv test - cbnez-01 + riscv test - bexti-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cbnez-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bexti-01.S config: riscv-arch-tests -- test: cebreak-01 +- test: binv-01 desc: > - riscv test - cebreak-01 + riscv test - binv-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cebreak-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/binv-01.S config: riscv-arch-tests -- test: cj-01 +- test: binvi-01 desc: > - riscv test - cj-01 + riscv test - binvi-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cj-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/binvi-01.S config: riscv-arch-tests -- test: cjal-01 +- test: bset-01 desc: > - riscv test - cjal-01 + riscv test - bset-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cjal-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bset-01.S config: riscv-arch-tests -- test: cjalr-01 +- test: bseti-01 desc: > - riscv test - cjalr-01 + riscv test - bseti-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cjalr-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bseti-01.S config: riscv-arch-tests -- test: cjr-01 +- test: clmul-01 desc: > - riscv test - cjr-01 + riscv test - clmul-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cjr-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/clmul-01.S config: riscv-arch-tests -- test: cli-01 +- test: clmulh-01 desc: > - riscv test - cli-01 + riscv test - clmulh-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cli-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/clmulh-01.S config: riscv-arch-tests -- test: clui-01 +- test: clmulr-01 desc: > - riscv test - clui-01 + riscv test - clmulr-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/clui-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/clmulr-01.S config: riscv-arch-tests -- test: clw-01 +- test: clz-01 desc: > - riscv test - clw-01 + riscv test - clz-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/clw-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/clz-01.S config: riscv-arch-tests -- test: clwsp-01 +- test: cpop-01 desc: > - riscv test - clwsp-01 + riscv test - cpop-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/clwsp-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/cpop-01.S config: riscv-arch-tests -- test: cmv-01 +- test: ctz-01 desc: > - riscv test - cmv-01 + riscv test - ctz-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cmv-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/ctz-01.S config: riscv-arch-tests -- test: cnop-01 +- test: max-01 desc: > - riscv test - cnop-01 + riscv test - max-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cnop-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/max-01.S config: riscv-arch-tests -- test: cor-01 +- test: maxu-01 desc: > - riscv test - cor-01 + riscv test - maxu-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cor-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/maxu-01.S config: riscv-arch-tests -- test: cslli-01 +- test: min-01 desc: > - riscv test - cslli-01 + riscv test - min-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cslli-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/min-01.S config: riscv-arch-tests -- test: csrai-01 +- test: minu-01 desc: > - riscv test - csrai-01 + riscv test - minu-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/csrai-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/minu-01.S config: riscv-arch-tests -- test: csrli-01 +- test: orcb_32-01 desc: > - riscv test - csrli-01 + riscv test - orcb_32-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/csrli-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/orcb_32-01.S config: riscv-arch-tests -- test: csub-01 +- test: orn-01 desc: > - riscv test - csub-01 + riscv test - orn-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/csub-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/orn-01.S config: riscv-arch-tests -- test: csw-01 +- test: rev8_32-01 desc: > - riscv test - csw-01 + riscv test - rev8_32-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/csw-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/rev8_32-01.S config: riscv-arch-tests -- test: cswsp-01 +- test: rol-01 desc: > - riscv test - cswsp-01 + riscv test - rol-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cswsp-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/rol-01.S config: riscv-arch-tests -- test: cxor-01 +- test: ror-01 desc: > - riscv test - cxor-01 + riscv test - ror-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cxor-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/ror-01.S config: riscv-arch-tests -- test: div-01 +- test: rori-01 desc: > - riscv test - div-01 + riscv test - rori-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/div-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/rori-01.S config: riscv-arch-tests -- test: divu-01 +- test: sext-b-01 desc: > - riscv test - divu-01 + riscv test - sext-b-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/divu-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/sext-b-01.S config: riscv-arch-tests -- test: mul-01 +- test: sext-h-01 desc: > - riscv test - mul-01 + riscv test - sext-h-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/mul-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/sext-h-01.S config: riscv-arch-tests -- test: mulh-01 +- test: sh1add-01 desc: > - riscv test - mulh-01 + riscv test - sh1add-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/mulh-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/sh1add-01.S config: riscv-arch-tests -- test: mulhsu-01 +- test: sh2add-01 desc: > - riscv test - mulhsu-01 + riscv test - sh2add-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/mulhsu-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/sh2add-01.S config: riscv-arch-tests -- test: mulhu-01 +- test: sh3add-01 desc: > - riscv test - mulhu-01 + riscv test - sh3add-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/mulhu-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/sh3add-01.S config: riscv-arch-tests -- test: rem-01 +- test: xnor-01 desc: > - riscv test - rem-01 + riscv test - xnor-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/rem-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/xnor-01.S config: riscv-arch-tests -- test: remu-01 +- test: zext-h_32-01 desc: > - riscv test - remu-01 + riscv test - zext-h_32-01 iterations: 1 - test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/remu-01.S + test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/zext-h_32-01.S config: riscv-arch-tests # Test-suite: epmp-tests diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/gen_testlist.py b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/gen_testlist.py index 358469a1c27c82..209904ead2afb1 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/gen_testlist.py +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/gen_testlist.py @@ -398,6 +398,13 @@ def add_configs_and_handwritten_directed_tests(): iterations: 1 test_srcs: access_pmp_overlap/access_pmp_overlap.S config: riscv-tests + +- test: u_mode_exec_test + desc: > + PMP U mode exec test + iterations: 1 + test_srcs: u_mode_exec_test/u_mode_exec_test.S + config: riscv-tests ''' testlist_string += available_directed_tests with open('directed_testlist.yaml', "a") as f: diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/u_mode_exec_test/u_mode_exec_test.S b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/u_mode_exec_test/u_mode_exec_test.S new file mode 100644 index 00000000000000..79b18858da3256 --- /dev/null +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/directed_tests/u_mode_exec_test/u_mode_exec_test.S @@ -0,0 +1,71 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Tests U-mode execution across all of the locked non-MML PMP permission +# configurations + +#include "riscv_test.h" +#include "test_macros.h" +#include "custom_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + RESET_PMP + # Setup region that can be fully accessed by U mode + SET_PMP_NAPOT(test_code, 4096, PMP_R | PMP_W | PMP_X, 15) + + # Setup exception handler + la t0, mtvec_handler + csrw mtvec, t0 + + j test_code + +test_end: + j pass + + TEST_PASSFAIL + +.balign 4096 +test_code: + # As we cannot modify locked regions setup new regions with increase priority + # (lower numbered regions take priority). Run a U-mode execution after every + # every new region to setup to test its configuration before moving to the + # next. + SET_PMP_NAPOT(test_exec_region, 256, PMP_NAPOT, 14) + SWITCH_TO_U_MODE_LABEL(test_exec_region) + SET_PMP_NAPOT(test_exec_region, 256, PMP_L | PMP_NAPOT, 13) + SWITCH_TO_U_MODE_LABEL(test_exec_region) + SET_PMP_NAPOT(test_exec_region, 256, PMP_L | PMP_R| PMP_NAPOT, 12) + SWITCH_TO_U_MODE_LABEL(test_exec_region) + SET_PMP_NAPOT(test_exec_region, 256, PMP_L | PMP_R | PMP_W| PMP_NAPOT, 11) + SWITCH_TO_U_MODE_LABEL(test_exec_region) + SET_PMP_NAPOT(test_exec_region, 256, PMP_L | PMP_X | PMP_R | PMP_W | PMP_NAPOT, 10) + SWITCH_TO_U_MODE_LABEL(test_exec_region) + SET_PMP_NAPOT(test_exec_region, 256, PMP_L | PMP_X | PMP_R | PMP_NAPOT, 9) + SWITCH_TO_U_MODE_LABEL(test_exec_region) + SET_PMP_NAPOT(test_exec_region, 256, PMP_L | PMP_X | PMP_NAPOT, 8) + SWITCH_TO_U_MODE_LABEL(test_exec_region) + + j test_end + +.balign 256 +test_exec_region: + add t0, t0, t0 + # Jump to exception handler to return to M-mode where U mode exec succeeds + unimp + +.balign 256 +mtvec_handler: + csrw mepc, a0 + # always return to m-mode + li t0, MSTATUS_MPP + csrs mstatus, t0 + mret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + TEST_DATA +RVTEST_DATA_END diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv index ac8e515a47228d..1ef6a5e0854d7e 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv @@ -643,7 +643,7 @@ interface core_ibex_fcov_if import ibex_pkg::*; ( // No interrupt would be taken in M-mode when its mstatus.MIE = 0 unless it's an NMI illegal_bins mmode_mstatus_mie = binsof(cs_registers_i.mstatus_q.mie) intersect {1'b0} && - binsof(cp_priv_mode_id) intersect {PRIV_LVL_M} with (cp_interrupt_taken[5:4] == 2'b00); + binsof(cp_priv_mode_id) intersect {PRIV_LVL_M} with (cp_interrupt_taken >> 4 == 6'd0); } priv_mode_exception_cross: cross cp_priv_mode_id, cp_ls_pmp_exception, cp_ls_error_exception { diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/fcov/core_ibex_pmp_fcov_if.sv b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/fcov/core_ibex_pmp_fcov_if.sv index 8f2a752bd0f82c..0c024d82a1b16c 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/fcov/core_ibex_pmp_fcov_if.sv +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/fcov/core_ibex_pmp_fcov_if.sv @@ -384,7 +384,8 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #( illegal_bins illegal_machine_deny_read = // Ensuring MML is high and we are in a R allowed configuration in Machine Mode (binsof(cp_region_priv_bits) intersect {MML_WRM_RU, MML_WRM_WRU, MML_RM_RU, MML_RM, - MML_WRM, MML_XRM, MML_XRM_XU, NONE} && + MML_WRM, MML_XRM, MML_XRM_XU, NONE, + W, X, XW} && binsof(cp_priv_lvl_dside) intersect {PRIV_LVL_M} && binsof(cp_req_type_dside) intersect {PMP_ACC_READ} && binsof(pmp_dside_req_err) intersect {1}); @@ -428,7 +429,8 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #( binsof(pmp_dside_req_err) intersect {1}); illegal_bins illegal_machine_deny_write = // Ensuring MML is high and we are in a W allowed configuration in Machine Mode - (binsof(cp_region_priv_bits) intersect {MML_WRM_WRU, MML_WRM_RU, MML_WRM, NONE} && + (binsof(cp_region_priv_bits) intersect {MML_WRM_WRU, MML_WRM_RU, MML_WRM, NONE, + R, X, XR, XW} && binsof(cp_priv_lvl_dside) intersect {PRIV_LVL_M} && binsof(cp_req_type_dside) intersect {PMP_ACC_WRITE} && binsof(pmp_dside_req_err) intersect {1}); @@ -463,11 +465,12 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #( ((!pmp_region_priv_bits[2] && pmp_region_priv_bits != MML_XM_XU) || pmp_region_priv_bits inside {MML_WRM_WRU, MML_RM_RU})) { - // Only interested in MML configuration - ignore_bins non_mml_in = binsof(pmp_region_priv_bits) with (!pmp_region_priv_bits[4]); + // Only interested in MML configuration, so ignore anything where the top bit is not set + ignore_bins non_mml_in = + binsof(pmp_region_priv_bits) with (pmp_region_priv_bits >> 4 == 5'b0); ignore_bins non_mml_out = - binsof(pmp_region_priv_bits_wr) with (!pmp_region_priv_bits_wr[4]); + binsof(pmp_region_priv_bits_wr) with (pmp_region_priv_bits_wr >> 4 == 5'b0); // Only interested in starting configs that weren't executable so ignore executable // regions diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f index 177d3277aca4f8..f6c54794bd852b 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f @@ -45,6 +45,8 @@ ${PRJ_DIR}/dv/uvm/core_ibex/common/prim/prim_clock_mux2.sv ${LOWRISC_IP_DIR}/ip/prim_generic/rtl/prim_generic_flop.sv ${PRJ_DIR}/dv/uvm/core_ibex/common/prim/prim_flop.sv +${LOWRISC_IP_DIR}/ip/prim_generic/rtl/prim_generic_and2.sv +${PRJ_DIR}/dv/uvm/core_ibex/common/prim/prim_and2.sv // Shared lowRISC code ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_cipher_pkg.sv @@ -64,6 +66,8 @@ ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_72_64_enc.sv ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_72_64_dec.sv ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_onehot_check.sv +${LOWRISC_IP_DIR}/ip/prim/rtl/prim_onehot_enc.sv +${LOWRISC_IP_DIR}/ip/prim/rtl/prim_onehot_mux.sv ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_mubi_pkg.sv // ibex CORE RTL files @@ -119,6 +123,7 @@ +incdir+${PRJ_DIR}/dv/uvm/core_ibex/common/ibex_cosim_agent +incdir+${PRJ_DIR}/dv/cosim ${PRJ_DIR}/dv/uvm/bus_params_pkg/bus_params_pkg.sv +${LOWRISC_IP_DIR}/dv/sv/common_ifs/common_ifs_pkg.sv ${LOWRISC_IP_DIR}/dv/sv/common_ifs/clk_rst_if.sv ${LOWRISC_IP_DIR}/dv/sv/common_ifs/pins_if.sv ${LOWRISC_IP_DIR}/dv/sv/str_utils/str_utils_pkg.sv diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv index 6f92eaa75d86d9..23fbe8b6d96bb0 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv @@ -54,7 +54,7 @@ class ibex_asm_program_gen extends riscv_asm_program_gen; riscv_csr_instr::create_csr_filter(cfg); - if ($value$plusargs("disable_pmp_exception_handler", disable_pmp_exception_handler) && + if ($value$plusargs("disable_pmp_exception_handler=%d", disable_pmp_exception_handler) && disable_pmp_exception_handler) begin cfg.pmp_cfg.enable_pmp_exception_handler = 0; end diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_debug_triggers_overrides.sv b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_debug_triggers_overrides.sv index 130c7f842ef195..1bc53c13c06926 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_debug_triggers_overrides.sv +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_debug_triggers_overrides.sv @@ -2,25 +2,6 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class ibex_hardware_triggers_asm_program_gen extends ibex_asm_program_gen; - - `uvm_object_utils(ibex_hardware_triggers_asm_program_gen) - `uvm_object_new - - // Same implementation as the parent class, except substitute for our custom debug_rom class. - virtual function void gen_debug_rom(int hart); - `uvm_info(`gfn, "Creating debug ROM", UVM_LOW) - debug_rom = ibex_hardware_triggers_debug_rom_gen:: - type_id::create("debug_rom", , {"uvm_test_top", ".", `gfn}); - debug_rom.cfg = cfg; - debug_rom.hart = hart; - debug_rom.gen_program(); - instr_stream = {instr_stream, debug_rom.instr_stream}; - endfunction - -endclass - - class ibex_hardware_triggers_debug_rom_gen extends riscv_debug_rom_gen; `uvm_object_utils(ibex_hardware_triggers_debug_rom_gen) @@ -123,6 +104,25 @@ class ibex_hardware_triggers_debug_rom_gen extends riscv_debug_rom_gen; endclass +class ibex_hardware_triggers_asm_program_gen extends ibex_asm_program_gen; + + `uvm_object_utils(ibex_hardware_triggers_asm_program_gen) + `uvm_object_new + + // Same implementation as the parent class, except substitute for our custom debug_rom class. + virtual function void gen_debug_rom(int hart); + `uvm_info(`gfn, "Creating debug ROM", UVM_LOW) + debug_rom = ibex_hardware_triggers_debug_rom_gen:: + type_id::create("debug_rom", , {"uvm_test_top", ".", `gfn}); + debug_rom.cfg = cfg; + debug_rom.hart = hart; + debug_rom.gen_program(); + instr_stream = {instr_stream, debug_rom.instr_stream}; + endfunction + +endclass + + class ibex_hardware_triggers_illegal_instr extends riscv_illegal_instr; `uvm_object_utils(ibex_hardware_triggers_illegal_instr) diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml index e8b7b82e8ae1d5..824ba7ff7a63d2 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml @@ -606,7 +606,7 @@ - test: riscv_mem_intg_error_test description: > Normal random instruction test, but randomly insert memory load/store integrity errors - iterations: 15 + iterations: 50 gen_test: riscv_rand_instr_test gen_opts: > +require_signature_addr=1 diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/directed_test_schema.py b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/directed_test_schema.py index fdbdc754752a22..7cd4faf71f87b8 100755 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/directed_test_schema.py +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/directed_test_schema.py @@ -62,7 +62,8 @@ class Config: # noqa # DConfig.VALIDATORS # ################################## - @pydantic.validator('ld_script', 'includes', pre=True) + @pydantic.field_validator('ld_script', 'includes', mode='before') + @classmethod def _make_valid_paths(cls, v: Any) -> pathlib.Path: return make_valid_pathlib_path(cls, v) @@ -124,20 +125,20 @@ def yaml_file_must_exist(cls, v: pathlib.Path): raise ValueError(f"Path object not found in filesystem : {v}") return v - @pydantic.root_validator() - def test_config_must_exist(cls, values): - """Check that if a test specifies a common config, it exists in the list available.""" - configs = [c.config for c in values.get('configs')] - for test in values.get('tests'): - if test.config not in configs: + @pydantic.model_validator(mode='after') + def test_config_must_exist(self): + """A test may only specify common configs in the available list.""" + config_names = {c.config for c in self.configs} + for test in self.tests: + if test.config not in config_names: raise ValueError( f"Test '{test.test}' gave the config '{test.config}', but " "this config does not exist in the file " - f"'{values.get('yaml')}'. Configs detected : {configs} \n") - return values + f"'{self.yaml}'. Configs detected : {self.configs} \n") + return self - @pydantic.root_validator() - def all_paths_must_exist(cls, values): + @pydantic.model_validator(mode='after') + def all_paths_must_exist(self): """Check that all fields specifying files exist on disk. We need to check all fields recursively for pathlib.Path fields, @@ -145,18 +146,20 @@ def all_paths_must_exist(cls, values): """ def check_model_path_fields_exist(model): - for f in filter(lambda f: (f.type_ == pathlib.Path), - model.__fields__.values()): - p = validate_path_exists(getattr(model, f.name), values.get('yaml')) - setattr(model, f.name, p) + for k, f in model.__fields__.items(): + if f.annotation != pathlib.Path: + continue - for c in values.get('configs'): + p = validate_path_exists(getattr(model, k), self.yaml) + setattr(model, k, p) + + for c in self.configs: check_model_path_fields_exist(c) - for t in values.get('tests'): + for t in self.tests: check_model_path_fields_exist(t) - return values + return self def import_model(directed_test_yaml: pathlib.Path) -> dict: diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/ibex_cmd.py b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/ibex_cmd.py index 3cf163e2847e7c..0d8c5346e2a646 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/ibex_cmd.py +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/ibex_cmd.py @@ -150,13 +150,18 @@ def filter_tests_by_config(cfg: ibex_config.Config, for test in test_list: if "rtl_params" not in test: - # We currently only exclude tests by mismatching 'rtl_params', so if - # that key is missing then the test is accepted by default. + # We currently only exclude tests by mismatching 'rtl_params', so + # if that key is missing then the test is accepted by default. filtered_test_list.append(test) else: param_dict = test['rtl_params'] assert isinstance(param_dict, dict) for p, p_val in param_dict.items(): + # Parameters are strings or ints, or lists of those two. Coerce + # to the latter to make the code below simpler. + if isinstance(p_val, str) or isinstance(p_val, int): + p_val = [p_val] + config_val = cfg.params.get(p, None) # Throw an error if required RTL parameters in the testlist @@ -171,11 +176,11 @@ def filter_tests_by_config(cfg: ibex_config.Config, # bitmanipulation tests). If this is the case, the testlist # will specify all legal enum values, check if any of them # match the config. - if ((isinstance(p_val, list) and (config_val not in p_val)) or - (isinstance(p_val, str) and (config_val != p_val))): + if config_val not in p_val: logger.warning( - f"Rejecting test {test['test']}, 'rtl_params' specified " - "not compatible with ibex_config") + f"Rejecting test: {test['test']}. It specifies " + f"rtl_params of {p_val}, which doesn't contain the " + f"expected '{config_val}'.") break # The test is accepted if we got this far diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/merge_cov.py b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/merge_cov.py index 35e26fed671b68..6c58c2d2bd487e 100755 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/merge_cov.py +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/merge_cov.py @@ -42,11 +42,11 @@ def merge_cov_vcs(md: RegressionMetadata, cov_dirs: Set[pathlib.Path]) -> int: logging.info("Generating merged coverage directory") cmd = (['urg', '-full64', '-format', 'both', - '-dbname', str(md.cov_dir/'merged.vdb'), - '-report', str(md.cov_dir/'report'), - '-log', str(md.cov_dir/'merge.log'), + '-dbname', str(md.dir_cov/'merged.vdb'), + '-report', str(md.dir_cov/'report'), + '-log', str(md.dir_cov/'merge.log'), '-dir'] + - list(cov_dirs)) + [str(cov_dir) for cov_dir in list(cov_dirs)]) return run_one(md.verbose, cmd, redirect_stdstreams='/dev/null') diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/report_lib/util.py b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/report_lib/util.py index c94698d49f9838..f6a00756c2d096 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/report_lib/util.py +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/report_lib/util.py @@ -96,7 +96,7 @@ def parse_xcelium_cov_report(cov_report: str) -> Dict[str, Dict[str, Dict[str, i metric_info.append((metric_info_match.group(1), metric_info_match.group(2))) - # Skip header seperator line + # Skip header separator line metrics_start_line = line_no + 2 if metrics_start_line == -1: diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/scripts_lib.py b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/scripts_lib.py index 6c96f5f4fd5357..77eaef6f37b566 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/scripts_lib.py +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/scripts_lib.py @@ -27,7 +27,7 @@ def run_one(verbose: bool, redirect_stdstreams: Optional[Union[str, pathlib.Path, IOBase]] = None, timeout_s: Optional[int] = None, reraise: bool = False, - env: Dict[str, str] = None) -> int: + env: Optional[Dict[str, str]] = None) -> int: """Run a command, returning its retcode. If verbose is true, print the command to stderr first (a bit like bash -x). diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv index cf1f13b176e325..4e758489720673 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv @@ -336,4 +336,12 @@ module core_ibex_tb_top; assign dut.u_ibex_top.gen_regfile_ff.register_file_i.gen_wren_check.u_prim_onehot_check. unused_assert_connected = 1; end + + // Disable the assertion for onhot check in case RdataMuxCheck (set by SecureIbex) is enabled. + if (SecureIbex) begin : gen_disable_rdata_mux_check + assign dut.u_ibex_top.gen_regfile_ff.register_file_i.gen_rdata_mux_check. + u_prim_onehot_check_raddr_a.unused_assert_connected = 1; + assign dut.u_ibex_top.gen_regfile_ff.register_file_i.gen_rdata_mux_check. + u_prim_onehot_check_raddr_b.unused_assert_connected = 1; + end endmodule diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/yaml/rtl_simulation.yaml b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/yaml/rtl_simulation.yaml index 6d3d76f32a3417..a193889f0b8d09 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/yaml/rtl_simulation.yaml +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/yaml/rtl_simulation.yaml @@ -33,7 +33,6 @@ -timescale=1ns/10ps -licqueue -LDFLAGS '-Wl,--no-as-needed' - -CFLAGS '--std=c99 -fno-extended-identifiers' -Mdir=/vcs_simv.csrc -o /vcs_simv -debug_access+pp @@ -100,9 +99,9 @@ -mfcu -cuname design_cuname +define+UVM_REGEX_NO_DPI +define+UVM - -timescale \"1 ns / 1 ps \" + -timescale 1ns/1ps -writetoplevels /top.list - -l / + -l sim: cmd: @@ -119,7 +118,7 @@ +UVM_VERBOSITY=UVM_LOW +bin= +ibex_tracer_file_base= - -l /sim.log + -l cov_opts: >- -do "coverage save -onexit /cov.ucdb;" diff --git a/hw/vendor/lowrisc_ibex/dv/verilator/pcount/cpp/ibex_pcounts.cc b/hw/vendor/lowrisc_ibex/dv/verilator/pcount/cpp/ibex_pcounts.cc index 733dcf09bf100d..6924ee5261fabe 100644 --- a/hw/vendor/lowrisc_ibex/dv/verilator/pcount/cpp/ibex_pcounts.cc +++ b/hw/vendor/lowrisc_ibex/dv/verilator/pcount/cpp/ibex_pcounts.cc @@ -10,6 +10,7 @@ #include extern "C" { +extern unsigned int mhpmcounter_num(); extern unsigned long long mhpmcounter_get(int index); } @@ -32,24 +33,48 @@ const std::vector ibex_counter_names = { "Multiply Wait", "Divide Wait"}; +static bool has_hpm_counter(int index) { + // The "cycles" and "instructions retired" counters are special and always + // exist. + if (index == 0 || index == 2) + return true; + + // The "NONE" counter is a placeholder. The space reserves an index that was + // once the "MTIME" CSR, but now is unused. Return false: there's no real HPM + // counter at index 1. + if (index == 1) + return false; + + // Otherwise, a counter exists if the index is strictly less than + // the MHPMCounterNum parameter that got passed to the + // ibex_cs_registers module. + return index < mhpmcounter_num(); +} + std::string ibex_pcount_string(bool csv) { - char seperator = csv ? ',' : ':'; + char separator = csv ? ',' : ':'; std::string::size_type longest_name_length; if (!csv) { longest_name_length = 0; - for (const std::string &counter_name : ibex_counter_names) { - longest_name_length = std::max(longest_name_length, counter_name.length()); + for (int i = 0; i < ibex_counter_names.size(); ++i) { + if (has_hpm_counter(i)) { + longest_name_length = + std::max(longest_name_length, ibex_counter_names[i].length()); + } } - // Add 1 to always get at least once space after the seperator + // Add 1 to always get at least once space after the separator longest_name_length++; } std::stringstream pcount_ss; for (int i = 0; i < ibex_counter_names.size(); ++i) { - pcount_ss << ibex_counter_names[i] << seperator; + if (!has_hpm_counter(i)) + continue; + + pcount_ss << ibex_counter_names[i] << separator; if (!csv) { int padding = longest_name_length - ibex_counter_names[i].length(); diff --git a/hw/vendor/lowrisc_ibex/ibex_core.core b/hw/vendor/lowrisc_ibex/ibex_core.core index c228c1860f982b..a9fd400b41c5e6 100644 --- a/hw/vendor/lowrisc_ibex/ibex_core.core +++ b/hw/vendor/lowrisc_ibex/ibex_core.core @@ -42,10 +42,6 @@ filesets: files: - lint/verilator_waiver.vlt: {file_type: vlt} - files_lint_verible: - files: - - lint/verible_waiver.vbw: {file_type: veribleLintWaiver} - files_check_tool_requirements: depend: - lowrisc:tool:check_tool_requirements @@ -170,7 +166,6 @@ targets: default: &default_target filesets: - tool_verilator ? (files_lint_verilator) - - tool_veriblelint ? (files_lint_verible) - files_rtl - files_check_tool_requirements toplevel: ibex_core diff --git a/hw/vendor/lowrisc_ibex/ibex_top.core b/hw/vendor/lowrisc_ibex/ibex_top.core index 8adbce20c0b43b..e8e5d011e9f843 100644 --- a/hw/vendor/lowrisc_ibex/ibex_top.core +++ b/hw/vendor/lowrisc_ibex/ibex_top.core @@ -10,11 +10,13 @@ filesets: depend: - lowrisc:ibex:ibex_pkg - lowrisc:ibex:ibex_core + - lowrisc:prim:and2 - lowrisc:prim:buf - lowrisc:prim:clock_mux2 - lowrisc:prim:flop - lowrisc:prim:ram_1p_scr - lowrisc:prim:onehot_check + - lowrisc:prim:onehot files: - rtl/ibex_register_file_ff.sv # generic FF-based - rtl/ibex_register_file_fpga.sv # FPGA @@ -27,10 +29,6 @@ filesets: files: - lint/verilator_waiver.vlt: {file_type: vlt} - files_lint_verible: - files: - - lint/verible_waiver.vbw: {file_type: veribleLintWaiver} - files_check_tool_requirements: depend: - lowrisc:tool:check_tool_requirements @@ -155,7 +153,6 @@ targets: default: &default_target filesets: - tool_verilator ? (files_lint_verilator) - - tool_veriblelint ? (files_lint_verible) - files_rtl - files_check_tool_requirements toplevel: ibex_top diff --git a/hw/vendor/lowrisc_ibex/lint/verible_waiver.vbw b/hw/vendor/lowrisc_ibex/lint/verible_waiver.vbw deleted file mode 100644 index e69de29bb2d1d6..00000000000000 diff --git a/hw/vendor/lowrisc_ibex/lint/verilator_waiver.vlt b/hw/vendor/lowrisc_ibex/lint/verilator_waiver.vlt index b7c952ca746614..d03f9bcb486fe7 100644 --- a/hw/vendor/lowrisc_ibex/lint/verilator_waiver.vlt +++ b/hw/vendor/lowrisc_ibex/lint/verilator_waiver.vlt @@ -64,6 +64,13 @@ lint_off -rule UNUSED -file "*/rtl/ibex_compressed_decoder.sv" -match "*rst_ni*" lint_off -rule UNUSED -file "*/rtl/ibex_decoder.sv" -match "*rst_ni*" lint_off -rule UNUSED -file "*/rtl/ibex_branch_predict.sv" -match "*rst_ni*" +// Don't worry about the fact that decoded_str and data_accessed appear to be +// written by multiple processes that might race with each other. They can't +// race with each other (everything is a descendent of the always_comb block), +// but Verilator doesn't notice this. +lint_off -rule MULTIDRIVEN -file "*/rtl/ibex_tracer.sv" -match "*decoded_str*" +lint_off -rule MULTIDRIVEN -file "*/rtl/ibex_tracer.sv" -match "*data_accessed*" + // Temporary waivers until OpenTitan primitives are lint-clean // https://github.com/lowRISC/opentitan/issues/2313 lint_off -file "*/lowrisc_prim_*/rtl/*.sv" diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_pmp.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_pmp.sv index 74cb6a378359d7..48c3a7ed674c03 100644 --- a/hw/vendor/lowrisc_ibex/rtl/ibex_pmp.sv +++ b/hw/vendor/lowrisc_ibex/rtl/ibex_pmp.sv @@ -50,32 +50,17 @@ module ibex_pmp #( // | // \--> pmp_req_err_o - // A wrapper function in which it is decided which form of permission check function gets called - function automatic logic perm_check_wrapper(logic csr_pmp_mseccfg_mml, - ibex_pkg::pmp_cfg_t csr_pmp_cfg, - ibex_pkg::pmp_req_e pmp_req_type, - ibex_pkg::priv_lvl_e priv_mode, - logic permission_check); - return csr_pmp_mseccfg_mml ? mml_perm_check(csr_pmp_cfg, - pmp_req_type, - priv_mode, - permission_check) : - orig_perm_check(csr_pmp_cfg.lock, - priv_mode, - permission_check); - endfunction - // Compute permissions checks that apply when MSECCFG.MML is set. Added for Smepmp support. - function automatic logic mml_perm_check(ibex_pkg::pmp_cfg_t csr_pmp_cfg, + function automatic logic mml_perm_check(ibex_pkg::pmp_cfg_t region_csr_pmp_cfg, ibex_pkg::pmp_req_e pmp_req_type, ibex_pkg::priv_lvl_e priv_mode, logic permission_check); logic result = 1'b0; - logic unused_cfg = |csr_pmp_cfg.mode; + logic unused_cfg = |region_csr_pmp_cfg.mode; - if (!csr_pmp_cfg.read && csr_pmp_cfg.write) begin + if (!region_csr_pmp_cfg.read && region_csr_pmp_cfg.write) begin // Special-case shared regions where R = 0, W = 1 - unique case ({csr_pmp_cfg.lock, csr_pmp_cfg.exec}) + unique case ({region_csr_pmp_cfg.lock, region_csr_pmp_cfg.exec}) // Read/write in M, read only in S/U 2'b00: result = (pmp_req_type == PMP_ACC_READ) | @@ -92,14 +77,15 @@ module ibex_pmp #( default: ; endcase end else begin - if (csr_pmp_cfg.read & csr_pmp_cfg.write & csr_pmp_cfg.exec & csr_pmp_cfg.lock) begin + if (region_csr_pmp_cfg.read & region_csr_pmp_cfg.write & + region_csr_pmp_cfg.exec & region_csr_pmp_cfg.lock) begin // Special-case shared read only region when R = 1, W = 1, X = 1, L = 1 result = pmp_req_type == PMP_ACC_READ; end else begin // Otherwise use basic permission check. Permission is always denied if in S/U mode and // L is set or if in M mode and L is unset. result = permission_check & - (priv_mode == PRIV_LVL_M ? csr_pmp_cfg.lock : ~csr_pmp_cfg.lock); + (priv_mode == PRIV_LVL_M ? region_csr_pmp_cfg.lock : ~region_csr_pmp_cfg.lock); end end return result; @@ -118,6 +104,21 @@ module ibex_pmp #( permission_check; endfunction + // A wrapper function in which it is decided which form of permission check function gets called + function automatic logic perm_check_wrapper(logic csr_pmp_mseccfg_mml, + ibex_pkg::pmp_cfg_t region_csr_pmp_cfg, + ibex_pkg::pmp_req_e pmp_req_type, + ibex_pkg::priv_lvl_e priv_mode, + logic permission_check); + return csr_pmp_mseccfg_mml ? mml_perm_check(region_csr_pmp_cfg, + pmp_req_type, + priv_mode, + permission_check) : + orig_perm_check(region_csr_pmp_cfg.lock, + priv_mode, + permission_check); + endfunction + // Access fault determination / prioritization function automatic logic access_fault_check (logic csr_pmp_mseccfg_mmwp, logic csr_pmp_mseccfg_mml, diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_register_file_ff.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_register_file_ff.sv index 45890db88664d6..53c89e2d34190a 100644 --- a/hw/vendor/lowrisc_ibex/rtl/ibex_register_file_ff.sv +++ b/hw/vendor/lowrisc_ibex/rtl/ibex_register_file_ff.sv @@ -15,6 +15,7 @@ module ibex_register_file_ff #( parameter int unsigned DataWidth = 32, parameter bit DummyInstructions = 0, parameter bit WrenCheck = 0, + parameter bit RdataMuxCheck = 0, parameter logic [DataWidth-1:0] WordZeroVal = '0 ) ( // Clock and Reset @@ -39,7 +40,7 @@ module ibex_register_file_ff #( input logic [DataWidth-1:0] wdata_a_i, input logic we_a_i, - // This indicates whether spurious WE are detected. + // This indicates whether spurious WE or non-one-hot encoded raddr are detected. output logic err_o ); @@ -49,6 +50,8 @@ module ibex_register_file_ff #( logic [DataWidth-1:0] rf_reg [NUM_WORDS]; logic [NUM_WORDS-1:0] we_a_dec; + logic oh_raddr_a_err, oh_raddr_b_err, oh_we_err; + always_comb begin : we_a_decoder for (int unsigned i = 0; i < NUM_WORDS; i++) begin we_a_dec[i] = (waddr_a_i == 5'(i)) ? we_a_i : 1'b0; @@ -78,12 +81,12 @@ module ibex_register_file_ff #( .oh_i(we_a_dec_buf), .addr_i(waddr_a_i), .en_i(we_a_i), - .err_o + .err_o(oh_we_err) ); end else begin : gen_no_wren_check logic unused_strobe; assign unused_strobe = we_a_dec[0]; // this is never read from in this case - assign err_o = 1'b0; + assign oh_we_err = 1'b0; end // No flops for R0 as it's hard-wired to 0 @@ -130,8 +133,106 @@ module ibex_register_file_ff #( assign rf_reg[0] = WordZeroVal; end - assign rdata_a_o = rf_reg[raddr_a_i]; - assign rdata_b_o = rf_reg[raddr_b_i]; + if (RdataMuxCheck) begin : gen_rdata_mux_check + // Encode raddr_a/b into one-hot encoded signals. + logic [NUM_WORDS-1:0] raddr_onehot_a, raddr_onehot_b; + logic [NUM_WORDS-1:0] raddr_onehot_a_buf, raddr_onehot_b_buf; + prim_onehot_enc #( + .OneHotWidth(NUM_WORDS) + ) u_prim_onehot_enc_raddr_a ( + .in_i (raddr_a_i), + .en_i (1'b1), + .out_o (raddr_onehot_a) + ); + + prim_onehot_enc #( + .OneHotWidth(NUM_WORDS) + ) u_prim_onehot_enc_raddr_b ( + .in_i (raddr_b_i), + .en_i (1'b1), + .out_o (raddr_onehot_b) + ); + + // Buffer the one-hot encoded signals so that the checkers + // are not optimized. + prim_buf #( + .Width(NUM_WORDS) + ) u_prim_buf_raddr_a ( + .in_i (raddr_onehot_a), + .out_o(raddr_onehot_a_buf) + ); + + prim_buf #( + .Width(NUM_WORDS) + ) u_prim_buf_raddr_b ( + .in_i (raddr_onehot_b), + .out_o(raddr_onehot_b_buf) + ); + + // SEC_CM: DATA_REG_SW.GLITCH_DETECT + // Check the one-hot encoded signals for glitches. + prim_onehot_check #( + .AddrWidth(ADDR_WIDTH), + .OneHotWidth(NUM_WORDS), + .AddrCheck(1), + // When AddrCheck=1 also EnableCheck needs to be 1. + .EnableCheck(1) + ) u_prim_onehot_check_raddr_a ( + .clk_i, + .rst_ni, + .oh_i (raddr_onehot_a_buf), + .addr_i (raddr_a_i), + // Set enable=1 as address is always valid. + .en_i (1'b1), + .err_o (oh_raddr_a_err) + ); + + prim_onehot_check #( + .AddrWidth(ADDR_WIDTH), + .OneHotWidth(NUM_WORDS), + .AddrCheck(1), + // When AddrCheck=1 also EnableCheck needs to be 1. + .EnableCheck(1) + ) u_prim_onehot_check_raddr_b ( + .clk_i, + .rst_ni, + .oh_i (raddr_onehot_b_buf), + .addr_i (raddr_b_i), + // Set enable=1 as address is always valid. + .en_i (1'b1), + .err_o (oh_raddr_b_err) + ); + + // MUX register to rdata_a/b_o according to raddr_a/b_onehot. + prim_onehot_mux #( + .Width(DataWidth), + .Inputs(NUM_WORDS) + ) u_rdata_a_mux ( + .clk_i, + .rst_ni, + .in_i (rf_reg), + .sel_i (raddr_onehot_a), + .out_o (rdata_a_o) + ); + + prim_onehot_mux #( + .Width(DataWidth), + .Inputs(NUM_WORDS) + ) u_rdata_b_mux ( + .clk_i, + .rst_ni, + .in_i (rf_reg), + .sel_i (raddr_onehot_b), + .out_o (rdata_b_o) + ); + end else begin : gen_no_rdata_mux_check + assign rdata_a_o = rf_reg[raddr_a_i]; + assign rdata_b_o = rf_reg[raddr_b_i]; + assign oh_raddr_a_err = 1'b0; + assign oh_raddr_b_err = 1'b0; + end + + assign err_o = oh_raddr_a_err || oh_raddr_b_err || oh_we_err; // Signal not used in FF register file logic unused_test_en; diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_register_file_fpga.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_register_file_fpga.sv index 420b8fe8bc13a1..7a0ae34b151fad 100644 --- a/hw/vendor/lowrisc_ibex/rtl/ibex_register_file_fpga.sv +++ b/hw/vendor/lowrisc_ibex/rtl/ibex_register_file_fpga.sv @@ -16,6 +16,7 @@ module ibex_register_file_fpga #( parameter int unsigned DataWidth = 32, parameter bit DummyInstructions = 0, parameter bit WrenCheck = 0, + parameter bit RdataMuxCheck = 0, parameter logic [DataWidth-1:0] WordZeroVal = '0 ) ( // Clock and Reset @@ -37,7 +38,7 @@ module ibex_register_file_fpga #( input logic [DataWidth-1:0] wdata_a_i, input logic we_a_i, - // This indicates whether spurious WE are detected. + // This indicates whether spurious WE or non-one-hot encoded raddr are detected. output logic err_o ); @@ -47,11 +48,114 @@ module ibex_register_file_fpga #( logic [DataWidth-1:0] mem[NUM_WORDS]; logic we; // write enable if writing to any register other than R0 - // async_read a - assign rdata_a_o = (raddr_a_i == '0) ? '0 : mem[raddr_a_i]; + logic [DataWidth-1:0] mem_o_a, mem_o_b; - // async_read b - assign rdata_b_o = (raddr_b_i == '0) ? '0 : mem[raddr_b_i]; + // WE strobe and one-hot encoded raddr alert. + logic oh_raddr_a_err, oh_raddr_b_err, oh_we_err; + assign err_o = oh_raddr_a_err || oh_raddr_b_err || oh_we_err; + + if (RdataMuxCheck) begin : gen_rdata_mux_check + // Encode raddr_a/b into one-hot encoded signals. + logic [NUM_WORDS-1:0] raddr_onehot_a, raddr_onehot_b; + logic [NUM_WORDS-1:0] raddr_onehot_a_buf, raddr_onehot_b_buf; + prim_onehot_enc #( + .OneHotWidth(NUM_WORDS) + ) u_prim_onehot_enc_raddr_a ( + .in_i (raddr_a_i), + .en_i (1'b1), + .out_o (raddr_onehot_a) + ); + + prim_onehot_enc #( + .OneHotWidth(NUM_WORDS) + ) u_prim_onehot_enc_raddr_b ( + .in_i (raddr_b_i), + .en_i (1'b1), + .out_o (raddr_onehot_b) + ); + + // Buffer the one-hot encoded signals so that the checkers + // are not optimized. + prim_buf #( + .Width(NUM_WORDS) + ) u_prim_buf_raddr_a ( + .in_i (raddr_onehot_a), + .out_o(raddr_onehot_a_buf) + ); + + prim_buf #( + .Width(NUM_WORDS) + ) u_prim_buf_raddr_b ( + .in_i (raddr_onehot_b), + .out_o(raddr_onehot_b_buf) + ); + + // SEC_CM: DATA_REG_SW.GLITCH_DETECT + // Check the one-hot encoded signals for glitches. + prim_onehot_check #( + .AddrWidth(ADDR_WIDTH), + .OneHotWidth(NUM_WORDS), + .AddrCheck(1), + // When AddrCheck=1 also EnableCheck needs to be 1. + .EnableCheck(1) + ) u_prim_onehot_check_raddr_a ( + .clk_i, + .rst_ni, + .oh_i (raddr_onehot_a_buf), + .addr_i (raddr_a_i), + // Set enable=1 as address is always valid. + .en_i (1'b1), + .err_o (oh_raddr_a_err) + ); + + prim_onehot_check #( + .AddrWidth(ADDR_WIDTH), + .OneHotWidth(NUM_WORDS), + .AddrCheck(1), + // When AddrCheck=1 also EnableCheck needs to be 1. + .EnableCheck(1) + ) u_prim_onehot_check_raddr_b ( + .clk_i, + .rst_ni, + .oh_i (raddr_onehot_b_buf), + .addr_i (raddr_b_i), + // Set enable=1 as address is always valid. + .en_i (1'b1), + .err_o (oh_raddr_b_err) + ); + + // MUX register to rdata_a/b_o according to raddr_a/b_onehot. + prim_onehot_mux #( + .Width(DataWidth), + .Inputs(NUM_WORDS) + ) u_rdata_a_mux ( + .clk_i, + .rst_ni, + .in_i (mem), + .sel_i (raddr_onehot_a), + .out_o (mem_o_a) + ); + + prim_onehot_mux #( + .Width(DataWidth), + .Inputs(NUM_WORDS) + ) u_rdata_b_mux ( + .clk_i, + .rst_ni, + .in_i (mem), + .sel_i (raddr_onehot_b), + .out_o (mem_o_b) + ); + + assign rdata_a_o = (raddr_a_i == '0) ? '0 : mem_o_a; + assign rdata_b_o = (raddr_b_i == '0) ? '0 : mem_o_b; + end else begin : gen_no_rdata_mux_check + // async_read a + assign rdata_a_o = (raddr_a_i == '0) ? '0 : mem[raddr_a_i]; + + // async_read b + assign rdata_b_o = (raddr_b_i == '0) ? '0 : mem[raddr_b_i]; + end // we select assign we = (waddr_a_i == '0) ? 1'b0 : we_a_i; @@ -60,9 +164,9 @@ module ibex_register_file_fpga #( // This checks for spurious WE strobes on the regfile. if (WrenCheck) begin : gen_wren_check // Since the FPGA uses a memory macro, there is only one write-enable strobe to check. - assign err_o = we && !we_a_i; + assign oh_we_err = we && !we_a_i; end else begin : gen_no_wren_check - assign err_o = 1'b0; + assign oh_we_err = 1'b0; end // Note that the SystemVerilog LRM requires variables on the LHS of assignments within diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_register_file_latch.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_register_file_latch.sv index 8b8a8bcc1acfb9..4c295e2ed136e3 100644 --- a/hw/vendor/lowrisc_ibex/rtl/ibex_register_file_latch.sv +++ b/hw/vendor/lowrisc_ibex/rtl/ibex_register_file_latch.sv @@ -16,6 +16,7 @@ module ibex_register_file_latch #( parameter int unsigned DataWidth = 32, parameter bit DummyInstructions = 0, parameter bit WrenCheck = 0, + parameter bit RdataMuxCheck = 0, parameter logic [DataWidth-1:0] WordZeroVal = '0 ) ( // Clock and Reset @@ -39,7 +40,7 @@ module ibex_register_file_latch #( input logic [DataWidth-1:0] wdata_a_i, input logic we_a_i, - // This indicates whether spurious WE are detected. + // This indicates whether spurious WE or non-one-hot encoded raddr are detected. output logic err_o ); @@ -50,6 +51,8 @@ module ibex_register_file_latch #( logic [NUM_WORDS-1:0] waddr_onehot_a; + logic oh_raddr_a_err, oh_raddr_b_err, oh_we_err; + logic [NUM_WORDS-1:1] mem_clocks; logic [DataWidth-1:0] wdata_a_q; @@ -62,11 +65,109 @@ module ibex_register_file_latch #( logic clk_int; + assign err_o = oh_raddr_a_err || oh_raddr_b_err || oh_we_err; + ////////// // READ // ////////// - assign rdata_a_o = mem[raddr_a_int]; - assign rdata_b_o = mem[raddr_b_int]; + if (RdataMuxCheck) begin : gen_rdata_mux_check + // Encode raddr_a/b into one-hot encoded signals. + logic [NUM_WORDS-1:0] raddr_onehot_a, raddr_onehot_b; + logic [NUM_WORDS-1:0] raddr_onehot_a_buf, raddr_onehot_b_buf; + prim_onehot_enc #( + .OneHotWidth(NUM_WORDS) + ) u_prim_onehot_enc_raddr_a ( + .in_i (raddr_a_int), + .en_i (1'b1), + .out_o (raddr_onehot_a) + ); + + prim_onehot_enc #( + .OneHotWidth(NUM_WORDS) + ) u_prim_onehot_enc_raddr_b ( + .in_i (raddr_b_int), + .en_i (1'b1), + .out_o (raddr_onehot_b) + ); + + // Buffer the one-hot encoded signals so that the checkers + // are not optimized. + prim_buf #( + .Width(NUM_WORDS) + ) u_prim_buf_raddr_a ( + .in_i(raddr_onehot_a), + .out_o(raddr_onehot_a_buf) + ); + + prim_buf #( + .Width(NUM_WORDS) + ) u_prim_buf_raddr_b ( + .in_i(raddr_onehot_b), + .out_o(raddr_onehot_b_buf) + ); + + // SEC_CM: DATA_REG_SW.GLITCH_DETECT + // Check the one-hot encoded signals for glitches. + prim_onehot_check #( + .AddrWidth(ADDR_WIDTH), + .OneHotWidth(NUM_WORDS), + .AddrCheck(1), + // When AddrCheck=1 also EnableCheck needs to be 1. + .EnableCheck(1) + ) u_prim_onehot_check_raddr_a ( + .clk_i, + .rst_ni, + .oh_i (raddr_onehot_a_buf), + .addr_i (raddr_b_int), + // Set enable=1 as address is always valid. + .en_i (1'b1), + .err_o (oh_raddr_a_err) + ); + + prim_onehot_check #( + .AddrWidth(ADDR_WIDTH), + .OneHotWidth(NUM_WORDS), + .AddrCheck(1), + // When AddrCheck=1 also EnableCheck needs to be 1. + .EnableCheck(1) + ) u_prim_onehot_check_raddr_b ( + .clk_i, + .rst_ni, + .oh_i (raddr_onehot_b_buf), + .addr_i (raddr_b_int), + // Set enable=1 as address is always valid. + .en_i (1'b1), + .err_o (oh_raddr_b_err) + ); + + // MUX register to rdata_a/b_o according to raddr_a/b_onehot. + prim_onehot_mux #( + .Width(DataWidth), + .Inputs(NUM_WORDS) + ) u_rdata_a_mux ( + .clk_i, + .rst_ni, + .in_i (mem), + .sel_i (raddr_onehot_a), + .out_o (rdata_a_o) + ); + + prim_onehot_mux #( + .Width(DataWidth), + .Inputs(NUM_WORDS) + ) u_rdata_b_mux ( + .clk_i, + .rst_ni, + .in_i (mem), + .sel_i (raddr_onehot_b), + .out_o (rdata_b_o) + ); + end else begin : gen_no_rdata_mux_check + assign rdata_a_o = mem[raddr_a_int]; + assign rdata_b_o = mem[raddr_b_int]; + assign oh_raddr_a_err = 1'b0; + assign oh_raddr_b_err = 1'b0; + end /////////// // WRITE // @@ -125,12 +226,12 @@ module ibex_register_file_latch #( .oh_i(waddr_onehot_a_buf), .addr_i(waddr_a_i), .en_i(we_a_i), - .err_o + .err_o(oh_we_err) ); end else begin : gen_no_wren_check logic unused_strobe; assign unused_strobe = waddr_onehot_a[0]; // this is never read from in this case - assign err_o = 1'b0; + assign oh_we_err = 1'b0; end // Individual clock gating (if integrated clock-gating cells are available) diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_top.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_top.sv index d1760630232830..dff77b0cde31f1 100644 --- a/hw/vendor/lowrisc_ibex/rtl/ibex_top.sv +++ b/hw/vendor/lowrisc_ibex/rtl/ibex_top.sv @@ -140,14 +140,15 @@ module ibex_top import ibex_pkg::*; #( input logic scan_rst_ni ); - localparam bit Lockstep = SecureIbex; - localparam bit ResetAll = Lockstep; - localparam bit DummyInstructions = SecureIbex; - localparam bit RegFileECC = SecureIbex; - localparam bit RegFileWrenCheck = SecureIbex; - localparam int unsigned RegFileDataWidth = RegFileECC ? 32 + 7 : 32; - localparam bit MemECC = SecureIbex; - localparam int unsigned MemDataWidth = MemECC ? 32 + 7 : 32; + localparam bit Lockstep = SecureIbex; + localparam bit ResetAll = Lockstep; + localparam bit DummyInstructions = SecureIbex; + localparam bit RegFileECC = SecureIbex; + localparam bit RegFileWrenCheck = SecureIbex; + localparam bit RegFileRdataMuxCheck = SecureIbex; + localparam int unsigned RegFileDataWidth = RegFileECC ? 32 + 7 : 32; + localparam bit MemECC = SecureIbex; + localparam int unsigned MemDataWidth = MemECC ? 32 + 7 : 32; // Icache parameters localparam int unsigned BusSizeECC = ICacheECC ? (BUS_SIZE + 7) : BUS_SIZE; localparam int unsigned LineSizeECC = BusSizeECC * IC_LINE_BEATS; @@ -421,6 +422,7 @@ module ibex_top import ibex_pkg::*; #( .DummyInstructions(DummyInstructions), // SEC_CM: DATA_REG_SW.GLITCH_DETECT .WrenCheck (RegFileWrenCheck), + .RdataMuxCheck (RegFileRdataMuxCheck), .WordZeroVal (RegFileDataWidth'(prim_secded_pkg::SecdedInv3932ZeroWord)) ) register_file_i ( .clk_i (clk), @@ -446,6 +448,7 @@ module ibex_top import ibex_pkg::*; #( .DummyInstructions(DummyInstructions), // SEC_CM: DATA_REG_SW.GLITCH_DETECT .WrenCheck (RegFileWrenCheck), + .RdataMuxCheck (RegFileRdataMuxCheck), .WordZeroVal (RegFileDataWidth'(prim_secded_pkg::SecdedInv3932ZeroWord)) ) register_file_i ( .clk_i (clk), @@ -471,6 +474,7 @@ module ibex_top import ibex_pkg::*; #( .DummyInstructions(DummyInstructions), // SEC_CM: DATA_REG_SW.GLITCH_DETECT .WrenCheck (RegFileWrenCheck), + .RdataMuxCheck (RegFileRdataMuxCheck), .WordZeroVal (RegFileDataWidth'(prim_secded_pkg::SecdedInv3932ZeroWord)) ) register_file_i ( .clk_i (clk), @@ -1301,4 +1305,33 @@ module ibex_top import ibex_pkg::*; #( crash_dump_o.exception_pc === u_ibex_core.cs_registers_i.mepc_q) `ASSERT(CrashDumpExceptionAddrConn, crash_dump_o.exception_addr === u_ibex_core.cs_registers_i.mtval_q) + + // Explicit INC_ASSERT due to instantiation of prim_secded_inv_39_32_dec below that is only used + // by assertions + `ifdef INC_ASSERT + if (MemECC) begin : g_mem_ecc_asserts + logic [1:0] data_ecc_err, instr_ecc_err; + + // Check alerts from memory integrity failures + + prim_secded_inv_39_32_dec u_data_intg_dec ( + .data_i (data_rdata_core), + .data_o (), + .syndrome_o (), + .err_o (data_ecc_err) + ); + `ASSERT(MajorAlertOnDMemIntegrityErr, + data_rvalid_i && (|data_ecc_err) |-> ##[0:5] alert_major_bus_o) + + prim_secded_inv_39_32_dec u_instr_intg_dec ( + .data_i (instr_rdata_core), + .data_o (), + .syndrome_o (), + .err_o (instr_ecc_err) + ); + // Check alerts from memory integrity failures + `ASSERT(MajorAlertOnIMemIntegrityErr, + instr_rvalid_i && (|instr_ecc_err) |-> ##[0:5] alert_major_bus_o) + end + `endif endmodule diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_tracer.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_tracer.sv index b07b742c506623..f361ddb35ce8b8 100644 --- a/hw/vendor/lowrisc_ibex/rtl/ibex_tracer.sv +++ b/hw/vendor/lowrisc_ibex/rtl/ibex_tracer.sv @@ -107,20 +107,9 @@ module ibex_tracer ( end end - function automatic void printbuffer_dumpline(); + function automatic void printbuffer_dumpline(int fh); string rvfi_insn_str; - if (file_handle == 32'h0) begin - string file_name_base = "trace_core"; - void'($value$plusargs("ibex_tracer_file_base=%s", file_name_base)); - $sformat(file_name, "%s_%h.log", file_name_base, hart_id_i); - - $display("%m: Writing execution trace to %s", file_name); - file_handle = $fopen(file_name, "w"); - $fwrite(file_handle, - "Time\tCycle\tPC\tInsn\tDecoded instruction\tRegister and memory contents\n"); - end - // Write compressed instructions as four hex digits (16 bit word), and // uncompressed ones as 8 hex digits (32 bit words). if (insn_is_compressed) begin @@ -129,33 +118,33 @@ module ibex_tracer ( rvfi_insn_str = $sformatf("%h", rvfi_insn); end - $fwrite(file_handle, "%15t\t%d\t%h\t%s\t%s\t", + $fwrite(fh, "%15t\t%d\t%h\t%s\t%s\t", $time, cycle, rvfi_pc_rdata, rvfi_insn_str, decoded_str); if ((data_accessed & RS1) != 0) begin - $fwrite(file_handle, " %s:0x%08x", reg_addr_to_str(rvfi_rs1_addr), rvfi_rs1_rdata); + $fwrite(fh, " %s:0x%08x", reg_addr_to_str(rvfi_rs1_addr), rvfi_rs1_rdata); end if ((data_accessed & RS2) != 0) begin - $fwrite(file_handle, " %s:0x%08x", reg_addr_to_str(rvfi_rs2_addr), rvfi_rs2_rdata); + $fwrite(fh, " %s:0x%08x", reg_addr_to_str(rvfi_rs2_addr), rvfi_rs2_rdata); end if ((data_accessed & RS3) != 0) begin - $fwrite(file_handle, " %s:0x%08x", reg_addr_to_str(rvfi_rs3_addr), rvfi_rs3_rdata); + $fwrite(fh, " %s:0x%08x", reg_addr_to_str(rvfi_rs3_addr), rvfi_rs3_rdata); end if ((data_accessed & RD) != 0) begin - $fwrite(file_handle, " %s=0x%08x", reg_addr_to_str(rvfi_rd_addr), rvfi_rd_wdata); + $fwrite(fh, " %s=0x%08x", reg_addr_to_str(rvfi_rd_addr), rvfi_rd_wdata); end if ((data_accessed & MEM) != 0) begin - $fwrite(file_handle, " PA:0x%08x", rvfi_mem_addr); + $fwrite(fh, " PA:0x%08x", rvfi_mem_addr); if (rvfi_mem_rmask != 4'b0000) begin - $fwrite(file_handle, " store:0x%08x", rvfi_mem_wdata); + $fwrite(fh, " store:0x%08x", rvfi_mem_wdata); end if (rvfi_mem_wmask != 4'b0000) begin - $fwrite(file_handle, " load:0x%08x", rvfi_mem_rdata); + $fwrite(fh, " load:0x%08x", rvfi_mem_rdata); end end - $fwrite(file_handle, "\n"); + $fwrite(fh, "\n"); endfunction @@ -747,14 +736,33 @@ module ibex_tracer ( // close output file for writing final begin if (file_handle != 32'h0) begin - $fclose(file_handle); + // This dance with "fh" is a bit silly. Some versions of Verilator treat a call of $fclose(xx) + // as a blocking assignment to xx. They then complain about the mixture with that an the + // non-blocking assignment we use when opening the file. The bug is fixed with recent versions + // of Verilator, but this hack is probably worth it for now. + int fh = file_handle; + $fclose(fh); end end // log execution - always_ff @(posedge clk_i) begin + always @(posedge clk_i) begin if (rvfi_valid && trace_log_enable) begin - printbuffer_dumpline(); + + int fh = file_handle; + + if (fh == 32'h0) begin + string file_name_base = "trace_core"; + void'($value$plusargs("ibex_tracer_file_base=%s", file_name_base)); + $sformat(file_name, "%s_%h.log", file_name_base, hart_id_i); + + $display("%m: Writing execution trace to %s", file_name); + fh = $fopen(file_name, "w"); + file_handle <= fh; + $fwrite(fh, "Time\tCycle\tPC\tInsn\tDecoded instruction\tRegister and memory contents\n"); + end + + printbuffer_dumpline(fh); end end diff --git a/hw/vendor/lowrisc_ibex/util/check_tool_requirements.py b/hw/vendor/lowrisc_ibex/util/check_tool_requirements.py index 08c5167210334b..bc9e32f6e123d5 100755 --- a/hw/vendor/lowrisc_ibex/util/check_tool_requirements.py +++ b/hw/vendor/lowrisc_ibex/util/check_tool_requirements.py @@ -4,9 +4,10 @@ # SPDX-License-Identifier: Apache-2.0 import argparse -from distutils.version import StrictVersion +from importlib.metadata import version import logging as log import os +from packaging.version import Version import re import shlex import subprocess @@ -156,7 +157,7 @@ def check(self): 'Failed to convert requirement to semantic version: {}' .format(err)) try: - min_sv = StrictVersion(min_semver) + min_sv = Version(min_semver) except ValueError as err: return (False, 'Bad semver inferred from required version ({}): {}' @@ -174,7 +175,7 @@ def check(self): 'Failed to convert installed to semantic version: {}' .format(err)) try: - actual_sv = StrictVersion(actual_semver) + actual_sv = Version(actual_semver) except ValueError as err: return (False, 'Bad semver inferred from installed version ({}): {}' @@ -212,7 +213,7 @@ class VeribleToolReq(ToolReq): def to_semver(self, version, from_req): # Drop the hash suffix and convert into version string that - # is compatible with StrictVersion in check_version below. + # is compatible with Version in check_version below. # Example: v0.0-808-g1e17daa -> 0.0.808 m = re.fullmatch(r'v([0-9]+)\.([0-9]+)-([0-9]+)-g[0-9a-f]+$', version) if m is None: @@ -237,7 +238,7 @@ def to_semver(self, version, from_req): # already. A version always has the "2020.03" (year and month) part, # and may also have an -SP and/or - suffix. # - # Since StrictVersion expects a 3 digit versioning scheme, we multiply + # Since Version expects a 3 digit versioning scheme, we multiply # any SP number by 100, which should work as long as the patch version # isn't greater than 99. # @@ -261,11 +262,11 @@ def to_semver(self, version, from_req): class PyModuleToolReq(ToolReq): '''A tool in a Python module (its version can be found by running pip)''' - version_regex = re.compile(r'Version: (.*)') - - def _get_tool_cmd(self): - return ['pip3', 'show', self.tool] + # For Python modules, use metadata directly instead of call into pip3, which + # may not always be available for some systems. + def get_version(self): + return version(self.tool) def dict_to_tool_req(path, tool, raw): '''Parse a dict (as read from Python) as a ToolReq diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/scripts/code_fixup.py b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/scripts/code_fixup.py new file mode 100644 index 00000000000000..cd982544dd97ae --- /dev/null +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/scripts/code_fixup.py @@ -0,0 +1,106 @@ +#!/usr/bin/env python3 +import argparse +import re + +# ============================================================================= + +class AssemblyLine: + """ + Simple assembly line representation + """ + + RE_INSTR = re.compile(r"(?P\S+)\s+(?P.*)") + + def __init__(self, text): + self.text = text + self.mnemonic = None + self.operands = None + + # Strip label if any + if ":" in text: + text = text.split(":", maxsplit=1)[1] + + # Strip comment if any + if "#" in text: + text = text.split("#", maxsplit=1)[0] + + # Get instruction and operands + m = self.RE_INSTR.match(text.strip()) + if m is not None: + + if m.group("mnemonic")[0] == ".": + return + + self.mnemonic = m.group("mnemonic").lower() + self.operands = [op.strip() for op in m.group("operands").split()] + + def __str__(self): + return self.text + +# ============================================================================= + + +def main(): + parser = argparse.ArgumentParser() + parser.add_argument( + "-i", + type=str, + required=True, + help="Input assembly file" + ) + parser.add_argument( + "-o", + type=str, + required=True, + help="Output assembly file" + ) + + args = parser.parse_args() + + max_nops = 10 + + # Read and parse + with open(args.i, "r") as fp: + inp_lines = [AssemblyLine(l) for l in fp.readlines()] + + # Identify a delayed write instruction followed by another one which writes + # to the same register + out_lines = [] + for i in range(len(inp_lines)): + line = inp_lines[i] + out_lines.append(line) + + # Bypass + if not line.mnemonic: + continue + + # Check if it is a delayed write. If not then bypass + is_delayed = line.mnemonic in ["div", "divu", "rem", "remu", "lw"] + if not is_delayed: + continue + + # Get next 2 instructions + following = [] + for j in range(i+1, len(inp_lines)): + if inp_lines[j].mnemonic is not None: + following.append(inp_lines[j]) + if len(following) >= 2: + break + + # If any of the instructions targets the same register insert NOPs + dst = line.operands[0] + for j, l in enumerate(following): + if l.operands and l.operands[0] == dst: + nops = max(0, max_nops - j) + for _ in range(nops): + out_lines.append(" " * 18 + "nop # FIXME: A fixup not to make VeeR cancel a delayed write\n") + break + + # Write + with open(args.o, "w") as fp: + for l in out_lines: + fp.write(str(l)) + + +if __name__ == "__main__": + main() diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/scripts/parse_testlist.py b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/scripts/parse_testlist.py new file mode 100644 index 00000000000000..9b36c5594eb945 --- /dev/null +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/scripts/parse_testlist.py @@ -0,0 +1,26 @@ +import sys +from json import dumps +from yaml import load, Loader +from typing import Generator + + +def parse_yaml(path: str) -> Generator[str, None, None]: + with open(path, 'rb') as fd: + tests = load(fd, Loader=Loader) + for test in tests: + if 'import' in test: + import_path = test['import'].split('/', 1)[1] + yield from parse_yaml(import_path) + elif 'test' in test: + yield test['test'] + + +if __name__ == "__main__": + if len(sys.argv) == 2: + testlist = parse_yaml(f'target/{sys.argv[1]}/testlist.yaml') + else: + testlist = parse_yaml('yaml/base_testlist.yaml') + testlist = list(testlist) + # remove, will cause incomplete sim, need customized RTL + testlist.remove("riscv_csr_test") + print(dumps(testlist)) diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/workflows/build-spike.yml b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/workflows/build-spike.yml new file mode 100644 index 00000000000000..442e825e827f51 --- /dev/null +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/workflows/build-spike.yml @@ -0,0 +1,63 @@ +# https://github.com/chipsalliance/Cores-VeeR-EL2/blob/774510e43f5408ec2b818db8f865027bc9be97b8/.github/workflows/build-spike.yml + +name: Spike Build + +on: + workflow_call: + +jobs: + verilator: + name: Build Spike + runs-on: ubuntu-latest + env: + TOOL_NAME: spike + TOOL_VERSION: d70ea67d + DEBIAN_FRONTEND: "noninteractive" + + steps: + - name: Setup Cache Metadata + id: cache_metadata + run: | + cache_date=$(date +"%Y_%m_%d") + cache_name=cache_${{ env.TOOL_NAME }}_${{ env.TOOL_VERSION }} + echo "Cache date: "$cache_date + echo "Cache name: "$cache_name + echo "cache_date=$cache_date" >> "$GITHUB_ENV" + echo "cache_name=$cache_name" >> "$GITHUB_ENV" + + - name: Setup cache + uses: actions/cache@v3 + id: cache + timeout-minutes: 60 + with: + path: | + /opt/spike + /opt/spike/.cache + key: ${{ env.cache_name }}_${{ env.cache_date }} + restore-keys: ${{ env.cache_name }}_ + + - name: Install prerequisities + if: ${{ steps.cache.outputs.cache-hit != 'true' }} + run: | + sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \ + git build-essential cmake ccache device-tree-compiler + + - name: Build Spike + if: ${{ steps.cache.outputs.cache-hit != 'true' }} + run: | + export CCACHE_DIR=/opt/spike/.cache + ccache --show-config | grep cache_dir + git clone https://github.com/riscv-software-src/riscv-isa-sim spike + export CC="ccache gcc" + export CXX="ccache g++" + pushd spike + git checkout ${{ env.TOOL_VERSION }} + mkdir build + cd build + ../configure --prefix=/opt/spike + make -j`nproc` + make install + popd + rm -rf /opt/spike/include # Remove include and lib to save space + rm -rf /opt/spike/lib + diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/workflows/metrics-regress.yml b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/workflows/metrics-regress.yml deleted file mode 100644 index de92648effd9ee..00000000000000 --- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/workflows/metrics-regress.yml +++ /dev/null @@ -1,27 +0,0 @@ -# This is a basic workflow to help you get started with Actions - -name: metrics-regress - -# Controls when the action will run. Triggers the workflow on push or pull request -# events but only for the master branch -on: - push: - branches: [ master ] -# pull_request_target: -# branches: [ master ] - -# If you fork this repository, you must create a new Metrics project for your fork -# and set the environment variable $METRICS_PROJECT_ID accordingly -jobs: - metrics-regression: - runs-on: ubuntu-latest - steps: - - uses: actions/checkout@v2 - - run: ./scripts/metrics-regress.py $METRICS_REGRESSION_NAME $METRICS_PROJECT_ID - env: - METRICS_CI_TOKEN: ${{ secrets.METRICS_CI_TOKEN }} - METRICS_REGRESSION_NAME: riscv-dv_regression - METRICS_PROJECT_ID: ${{ secrets.METRICS_PROJECT_ID }} - PR_NUMBER: ${{ github.event.pull_request.number }} - shell: bash - diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/workflows/run-tests.yml b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/workflows/run-tests.yml new file mode 100644 index 00000000000000..dd93d0cf63e760 --- /dev/null +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/.github/workflows/run-tests.yml @@ -0,0 +1,182 @@ +name: run-tests + +on: + push: + pull_request: + +env: + RISCV_TARGET: rv32imc + +jobs: + build-spike: + uses: ./.github/workflows/build-spike.yml + + generate-config: + runs-on: ubuntu-latest + outputs: + test-types: ${{ steps.test-types.outputs.tests }} + hash: ${{ steps.hash.outputs.files-hash }} + steps: + - uses: actions/checkout@v4 + - id: test-types + name: Prepare test types + run: | + python3 -m pip install pyyaml + echo "tests=$(python3 .github/scripts/parse_testlist.py $RISCV_TARGET)" | tee -a $GITHUB_OUTPUT + - id: hash + name: Prepare files' hash + run: | + echo "files-hash=$(sha256sum **/*.sv **/*.py **/*.yml **/*.yaml | cut -d\ -f1 | sha256sum | cut -d\ -f1)" | tee -a $GITHUB_OUTPUT + + + generate-code: + runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ] + container: centos:8 + needs: generate-config + strategy: + fail-fast: false + matrix: + test: ${{ fromJSON(needs.generate-config.outputs.test-types) }} + version: [ uvm ] + include: + - test: riscv_arithmetic_basic_test + version: pyflow + env: + GHA_EXTERNAL_DISK: additional-tools + CACHE_HASH: ${{ needs.generate-config.outputs.hash }} + steps: + - uses: actions/checkout@v3 + + - name: Setup Cache Metadata + id: cache_metadata + run: | + cache_code=cache_${{ matrix.test }}_${{ matrix.version }} + echo "cache_code=${cache_code}_${{ env.CACHE_HASH }}" | tee -a "$GITHUB_ENV" + + - name: Cache Code + uses: actions/cache@v3 + id: cache-code + timeout-minutes: 60 + with: + path: test/asm_test + key: ${{ env.cache_code }} + + - name: Prepare Environment + if: steps.cache-code.outputs.cache-hit != 'true' + run: _secret_environment + + - name: Setup Python 3.9 + if: steps.cache-code.outputs.cache-hit != 'true' + run: | + yum update -y + yum install -y python39 + python3.9 -m pip install -r requirements.txt + + - name: Generate UVM Tests + if: steps.cache-code.outputs.cache-hit != 'true' && matrix.version == 'uvm' + run: _secret_riscv + env: + RISCV_TEST: ${{ matrix.test }} + RISCV_TARGET: ${{ env.RISCV_TARGET }} + + - name: Generate PyFlow Tests + if: steps.cache-code.outputs.cache-hit != 'true' && matrix.version == 'pyflow' + run: | + set -eo pipefail + python3 run.py --simulator pyflow \ + --test ${{ matrix.test }} --iss spike \ + --start_seed 999 --iterations 1 --batch_size 1 \ + --isa $RISCV_TARGET --mabi ilp32 --steps gen -v -o test 2>&1 | tee test/generate.log + + - name: Upload Artifacts + uses: actions/upload-artifact@v3 + if: always() + with: + path: | + test/asm_test/*.S + + + run-tests: + runs-on: ubuntu-latest + needs: [ build-spike, generate-code, generate-config ] + strategy: + fail-fast: false + matrix: + test: ${{ fromJSON(needs.generate-config.outputs.test-types) }} + version: + - uvm + include: + - test: riscv_arithmetic_basic_test + version: pyflow + env: + TOOL_VERSION: d70ea67d + CACHE_HASH: ${{ needs.generate-config.outputs.hash }} + + steps: + - uses: actions/checkout@v4 + + - name: Install dependencies + run: sudo apt-get -qqy update && sudo apt-get -qqy install gcc-riscv64-unknown-elf device-tree-compiler + + - name: Setup python + # python dependencies cannot be properly downloaded with new versions of python + uses: actions/setup-python@v4 + with: + python-version: '3.9' + + - name: Install python dependencies + run: python3 -m pip install -r requirements.txt + + - name: Setup Cache Metadata + id: cache_metadata + run: | + date=$(date +"%Y_%m_%d") + time=$(date +"%Y%m%d_%H%M%S_%N") + cache_spike_restore_key=cache_spike_ + cache_spike_key=${cache_spike_restore_key}${{ env.TOOL_VERSION }}_${date} + cache_code=cache_${{ matrix.test }}_${{ matrix.version }} + + echo "cache_spike_restore_key=$cache_spike_restore_key" | tee -a "$GITHUB_ENV" + echo "cache_spike_key=$cache_spike_key" | tee -a "$GITHUB_ENV" + echo "cache_code=${cache_code}_${{ env.CACHE_HASH }}" | tee -a "$GITHUB_ENV" + + - name: Restore Spike cache + id: cache-spike-restore + uses: actions/cache/restore@v3 + with: + path: | + /opt/spike + /opt/spike/.cache + key: ${{ env.cache_spike_key }} + restore-keys: ${{ env.cache_spike_restore_key }} + + - name: Set variables + run: | + echo "RISCV_GCC=riscv64-unknown-elf-gcc" >> $GITHUB_ENV + echo "RISCV_OBJCOPY=riscv64-unknown-elf-objcopy" >> $GITHUB_ENV + echo "SPIKE_PATH=/opt/spike/bin" >> $GITHUB_ENV + echo "PYTHONPATH=pygen" >> $GITHUB_ENV + + - name: Cache Code Restore + uses: actions/cache/restore@v3 + id: cache-code-restore + timeout-minutes: 60 + with: + path: test/asm_test + key: ${{ env.cache_code }} + + - name: Run Tests + run: | + set -eo pipefail + python3 run.py --simulator pyflow \ + --test ${{ matrix.test }} --iss spike --iss_timeout 60 \ + --start_seed 999 --iterations 1 --batch_size 1 \ + --isa $RISCV_TARGET --mabi ilp32 --steps gcc_compile,iss_sim -v -o test 2>&1 | tee -a test/generate.log + + - name: Upload Artifacts + uses: actions/upload-artifact@v3 + if: always() + with: + path: | + test/asm_test/*.log + test/*.log diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/euvm/riscv/gen/riscv_asm_program_gen.d b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/euvm/riscv/gen/riscv_asm_program_gen.d index 98324ac4f7f841..abfb638dd44187 100644 --- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/euvm/riscv/gen/riscv_asm_program_gen.d +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/euvm/riscv/gen/riscv_asm_program_gen.d @@ -736,7 +736,7 @@ class riscv_asm_program_gen : uvm_object } // get a random double precision floating value - ubvec!XLEN get_rand_dpf_value() { + ubvec!64 get_rand_dpf_value() { ubvec!64 value; int randint = urandom(0,6); diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/euvm/riscv/gen/riscv_load_store_instr_lib.d b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/euvm/riscv/gen/riscv_load_store_instr_lib.d index 4694ce4d7ab9b3..a5308ed2865a24 100644 --- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/euvm/riscv/gen/riscv_load_store_instr_lib.d +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/euvm/riscv/gen/riscv_load_store_instr_lib.d @@ -670,11 +670,11 @@ class riscv_vector_load_store_instr_stream : riscv_mem_access_stream add_mixed_instr(num_mixed_instr); add_rs1_init_la_instr(rs1_reg, data_page_id, base); if (address_mode == address_mode_e.STRIDED) { - this.append_instr(get_init_gpr_instr(rs2_reg, toubvec!64(stride_byte_offset))); + this.append_instr(get_init_gpr_instr(rs2_reg, toubvec!XLEN(stride_byte_offset))); } else if (address_mode == address_mode_e.INDEXED) { // TODO: Support different index address for each element - add_init_vector_gpr_instr(vs2_reg, toubvec!64(index_addr)); + add_init_vector_gpr_instr(vs2_reg, toubvec!XLEN(index_addr)); } super.post_randomize(); } diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/euvm/riscv/gen/riscv_page_table_entry.d b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/euvm/riscv/gen/riscv_page_table_entry.d index cc1ae5de0c6a31..308526d73354b8 100644 --- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/euvm/riscv/gen/riscv_page_table_entry.d +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/euvm/riscv/gen/riscv_page_table_entry.d @@ -161,7 +161,7 @@ class riscv_page_table_entry(satp_mode_t MODE = satp_mode_t.SV39) : uvm_object void pack_entry() { switch (MODE) { case satp_mode_t.SV32: - bits = ppn1 ~ ppn0 ~ rsw ~ d ~ a ~ g ~ u ~ xwr ~ v; + bits = cast(ubvec!XLEN) (ppn1 ~ ppn0 ~ rsw ~ d ~ a ~ g ~ u ~ xwr ~ v); break; case satp_mode_t.SV39: bits = cast(ubvec!XLEN) (rsvd ~ ppn2 ~ ppn1 ~ ppn0 ~ rsw ~ d ~ a ~ g ~ u ~ xwr ~ v); diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/euvm/riscv/gen/riscv_privileged_common_seq.d b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/euvm/riscv/gen/riscv_privileged_common_seq.d index 8b41a9166edb0d..64e7a1987c5275 100644 --- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/euvm/riscv/gen/riscv_privileged_common_seq.d +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/euvm/riscv/gen/riscv_privileged_common_seq.d @@ -123,16 +123,18 @@ class riscv_privileged_common_seq : uvm_sequence!(uvm_sequence_item,uvm_sequence mstatus.set_field("TW", cfg.set_mstatus_tw); mstatus.set_field("FS", cfg.mstatus_fs); mstatus.set_field("VS", cfg.mstatus_vs); - if (!(canFind(supported_privileged_mode, privileged_mode_t.SUPERVISOR_MODE) && (XLEN != 32))) { - mstatus.set_field("SXL", toubvec!2(0b00)); - } - else if (XLEN == 64) { - mstatus.set_field("SXL", toubvec!2(0b10)); - } - if (!(canFind(supported_privileged_mode, privileged_mode_t.USER_MODE) && (XLEN != 32))) { - mstatus.set_field("UXL", toubvec!2(0b00)); - } else if (XLEN == 64) { - mstatus.set_field("UXL", toubvec!2(0b10)); + if (XLEN != 32) { + if (!(canFind(supported_privileged_mode, privileged_mode_t.SUPERVISOR_MODE))) { + mstatus.set_field("SXL", toubvec!2(0b00)); + } + else if (XLEN == 64) { + mstatus.set_field("SXL", toubvec!2(0b10)); + } + if (!(canFind(supported_privileged_mode, privileged_mode_t.USER_MODE))) { + mstatus.set_field("UXL", toubvec!2(0b00)); + } else if (XLEN == 64) { + mstatus.set_field("UXL", toubvec!2(0b10)); + } } mstatus.set_field("XS", 0); mstatus.set_field("SD", 0); diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/requirements.txt b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/requirements.txt index 49934ea5cf51c4..6fbc7060ce5e62 100644 --- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/requirements.txt +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/requirements.txt @@ -1,5 +1,5 @@ PyYAML -bitstring +bitstring==3.1.9 Sphinx Pallets-Sphinx-Themes sphinxcontrib-log-cabinet diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/run.py b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/run.py index 84c0eb6c1f4309..b6b8aa0a3b7e35 100644 --- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/run.py +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/run.py @@ -139,6 +139,11 @@ def parse_iss_yaml(iss, iss_yaml, isa, setting_dir, debug_cmd): """ logging.info("Processing ISS setup file : {}".format(iss_yaml)) yaml_data = read_yaml(iss_yaml) + + # Path to the "scripts" subdirectory + my_path = os.path.dirname(os.path.realpath(__file__)) + scripts_dir = os.path.join(my_path, "scripts") # Search for matched ISS + # Search for matched ISS for entry in yaml_data: if entry['iss'] == iss: @@ -161,6 +166,7 @@ def parse_iss_yaml(iss, iss_yaml, isa, setting_dir, debug_cmd): cmd = re.sub("\", variant, cmd) else: cmd = re.sub("\", isa, cmd) + cmd = re.sub("\", scripts_dir, cmd) return cmd logging.error("Cannot find ISS {}".format(iss)) sys.exit(RET_FAIL) @@ -662,7 +668,7 @@ def iss_sim(test_list, output_dir, iss_list, iss_yaml, iss_opts, prefix = ("{}/asm_test/{}_{}".format( output_dir, test['test'], i)) elf = prefix + ".o" - log = ("{}/{}.{}.log".format(log_dir, test['test'], i)) + log = ("{}/{}_{}.log".format(log_dir, test['test'], i)) cmd = get_iss_cmd(base_cmd, elf, log) if 'iss_opts' in test: cmd += ' ' diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/lib.py b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/lib.py index 9acf6dcfae3d1c..872752f0011cfa 100644 --- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/lib.py +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/lib.py @@ -109,6 +109,7 @@ def run_cmd(cmd, timeout_s=999, exit_on_error=1, check_return_code=True, executable='/bin/bash', universal_newlines=True, start_new_session=True, + env=os.environ, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) except subprocess.CalledProcessError: diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/renode_log_to_trace_csv.py b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/renode_log_to_trace_csv.py new file mode 100644 index 00000000000000..cee4a29ac04163 --- /dev/null +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/renode_log_to_trace_csv.py @@ -0,0 +1,156 @@ +#!/usr/bin/env python3 +""" +Converts Renode log to execution trace for RISC-V DV +""" + +import argparse +import os +import re +import sys +import logging + +sys.path.insert(0, os.path.dirname(os.path.realpath(__file__))) + +from riscv_trace_csv import * +from lib import * + +# ============================================================================= + +GPR_NAMES = [ + ("x0", "zero"), + ("x1", "ra"), + ("x2", "sp"), + ("x3", "gp"), + ("x4", "tp"), + ("x5", "t0"), + ("x6", "t1"), + ("x7", "t2"), + ("x8", "s0"), + ("x9", "s1"), + ("x10", "a0"), + ("x11", "a1"), + ("x12", "a2"), + ("x13", "a3"), + ("x14", "a4"), + ("x15", "a5"), + ("x16", "a6"), + ("x17", "a7"), + ("x18", "s2"), + ("x19", "s3"), + ("x20", "s4"), + ("x21", "s5"), + ("x22", "s6"), + ("x23", "s7"), + ("x24", "s8"), + ("x25", "s9"), + ("x26", "s10"), + ("x27", "s11"), + ("x28", "t3"), + ("x29", "t4"), + ("x30", "t5"), + ("x31", "t6"), +] + +# ============================================================================= + + +def process_renode_sim_log(log_name, csv_name): + """ + Converts a Renode trace log to CSV format + """ + + # Build lookups + gpr_to_name = {m[0]: m[1] for m in GPR_NAMES} + known_gpr = {m[0].upper() for m in GPR_NAMES} + + # FIXME: We need a previous PC each time. Assume its value for the first + # entry. + prev_pc = "80000000" + + # FIXME: Assume initial state of all GPR set to 0 + state = {m[0].upper(): "0" for m in GPR_NAMES} + trace = [] + + with open(log_name, "r") as fp: + for line in fp: + + line = line.strip() + if not line: + continue + + # Skip non-regdump + if not line.startswith("REGDUMP:"): + continue + + # Decode state + fields = line.replace("REGDUMP:", "").split(",") + regs = {fields[i]: fields[i+1] for i in range(0, len(fields), 2)} + + # Compute state difference + diff = {r: regs[r] for r in known_gpr \ + if r in state and r in regs and state[r] != regs[r]} + state = regs + + # Format the entry + entry = RiscvInstructionTraceEntry() + entry.pc = prev_pc + entry.binary = "0" + entry.operand = "" + entry.mode = "0" + + # GPRs + for x in range(32): + name = "X{}".format(x) + if name in diff: + lname = name.lower() + value = int(diff[name], 16) + entry.gpr.append("{}:{:08x}".format(gpr_to_name[lname], value)) + + # CSRs + # TODO: + + # Add only if there is a GPR/CSR change + if entry.gpr or entry.csr: + trace.append(entry) + + prev_pc = state["PC"] + + return trace + + +def write_csv(file_name, data): + """ + Writes the trace to CSV + """ + + with open(file_name, "w") as fp: + + writer = RiscvInstructionTraceCsv(fp) + writer.start_new_trace() + + for entry in data: + writer.write_trace_entry(entry) + +# ============================================================================ + + +def main(): + # Parse input arguments + parser = argparse.ArgumentParser() + parser.add_argument("--log", type=str, help="Input Renode simulation log") + parser.add_argument("--csv", type=str, help="Output trace CSV file") + parser.add_argument("-v", "--verbose", dest="verbose", action="store_true", + help="Verbose logging") + parser.set_defaults(verbose=False) + + args = parser.parse_args() + setup_logging(args.verbose) + + # Process Renode log + trace = process_renode_sim_log(args.log, args.csv) + # Write CSV + write_csv(args.csv, trace) + + +if __name__ == "__main__": + main() diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/renode_wrapper.py b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/renode_wrapper.py new file mode 100644 index 00000000000000..245de9278169f7 --- /dev/null +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/renode_wrapper.py @@ -0,0 +1,106 @@ +#!/usr/bin/env python3 +import argparse +import subprocess +import os +import tempfile + +# ============================================================================= + +REPL_TEMPLATE = """ +memory: Memory.MappedMemory @ sysbus 0x80000000 + size: 0x10000 + +cpu: CPU.RiscV32 @ sysbus + cpuType: "{isa}" + timeProvider: clint + hartId: 0 + +clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x02000000 + [0,1] -> cpu@[3,7] + frequency: 1000000 +""" + +RESC_TEMPLATE = """ +using sysbus +mach create "riscv" +machine LoadPlatformDescription @{repl} + +sysbus LoadELF @{elf} + +cpu MaximumBlockSize 1 +cpu SetHookAtBlockEnd "print('REGDUMP:' + ','.join(self.GetRegistersValues()))" + +emulation RunFor "0.000100" + +quit +""" + +# ============================================================================= + + +def main(): + """ + The entry point + """ + + parser = argparse.ArgumentParser() + + parser.add_argument( + "--renode", + type=str, + default="renode", + help="Path to Renode binary", + ) + parser.add_argument( + "--log", + type=str, + default=None, + help="Output log file", + ) + parser.add_argument( + "--isa", + type=str, + default="rv32i", + help="RISC-V ISA specification string", + ) + parser.add_argument( + "--elf", + type=str, + required=True, + help="ELF file to run", + ) + + args = parser.parse_args() + + with tempfile.TemporaryDirectory() as tmpdir: + + repl = os.path.join(tmpdir, "riscv.repl") + resc = os.path.join(tmpdir, "riscv.resc") + + params = { + "renode": args.renode, + "isa": args.isa, + "elf": args.elf, + "repl": repl, + "resc": resc, + "log": args.log, + } + + # Render REPL template + with open(repl, "w") as fp: + fp.write(REPL_TEMPLATE.format(**params)) + + # Render RESC template + with open(resc, "w") as fp: + fp.write(RESC_TEMPLATE.format(**params)) + + # Launch Renode, capture output + cmd = "{renode} --console -p {resc}".format(**params) + if args.log is not None: + cmd += " &>{log}".format(**params) + + subprocess.call(cmd, shell=True) + + +if __name__ == "__main__": + main() diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/spike_log_to_trace_csv.py b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/spike_log_to_trace_csv.py index 2272cc31dad940..b6970bcaf65dd9 100644 --- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/spike_log_to_trace_csv.py +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/spike_log_to_trace_csv.py @@ -27,10 +27,12 @@ from riscv_trace_csv import * from lib import * -RD_RE = re.compile(r"(core\s+\d+:\s+)?(?P\d) 0x(?P[a-f0-9]+?) " \ - "\((?P.*?)\) (?P[xf]\s*\d*?) 0x(?P[a-f0-9]+)") +RD_RE = re.compile( + r"(core\s+\d+:\s+)?(?P\d)\s+0x(?P[a-f0-9]+?)\s+" \ + r"\((?P.*?)\)\s+(?P[xf]\s*\d*?)\s+0x(?P[a-f0-9]+)" \ + r"(\s+(?P\S+)\s+0x(?P[a-f0-9]+))?") CORE_RE = re.compile( - r"core\s+\d+:\s+0x(?P[a-f0-9]+?) \(0x(?P.*?)\) (?P.*?)$") + r"core\s+\d+:\s+0x(?P[a-f0-9]+?)\s+\(0x(?P.*?)\)\s+(?P.*?)$") ADDR_RE = re.compile( r"(?P[a-z0-9]+?),(?P[\-0-9]+?)\((?P[a-z0-9]+)\)") ILLE_RE = re.compile(r"trap_illegal_instruction") @@ -173,9 +175,13 @@ def read_spike_trace(path, full_trace): # the --log-commits Spike option)? commit_match = RD_RE.match(line) if commit_match: - instr.gpr.append(gpr_to_abi(commit_match.group('reg') - .replace(' ', '')) + - ':' + commit_match.group('val')) + groups = commit_match.groupdict() + instr.gpr.append(gpr_to_abi(groups["reg"].replace(' ', '')) + + ":" + groups["val"]) + + if groups["csr"] and groups["csr_val"]: + instr.csr.append(groups["csr"] + ":" + groups["csr_val"]) + instr.mode = commit_match.group('pri') # At EOF, we might have an instruction in hand. Yield it if so. diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/whisper_log_trace_csv.py b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/whisper_log_trace_csv.py index cd509bee2e0445..c0ffb89eb61489 100644 --- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/whisper_log_trace_csv.py +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/whisper_log_trace_csv.py @@ -60,6 +60,7 @@ def process_whisper_sim_log(whisper_log, csv, full_trace=0): whisper_instr = m.group("instr").replace("\. + ", "") whisper_instr = whisper_instr.replace("\. - ", "-") rv_instr_trace = RiscvInstructionTraceEntry() + rv_instr_trace.pc = m.group("pc") rv_instr_trace.instr_str = whisper_instr rv_instr_trace.binary = m.group("bin") reg = "x" + str(int(m.group("reg"), 16)) diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_csr_instr.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_csr_instr.sv index 14a0b24726bf86..35d98fe4df8beb 100644 --- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_csr_instr.sv +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_csr_instr.sv @@ -114,7 +114,7 @@ class riscv_csr_instr extends riscv_instr; foreach (initial_csrs[r]) begin if (!(initial_csrs[r] inside {remove_csr})) begin - include_write_reg.push_back(initial_csrs[r]); + include_write_reg.push_back(privileged_reg_t'(initial_csrs[r])); end end diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_page_table_list.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_page_table_list.sv index 0bf6a61798ee54..a6935e0fb47d56 100644 --- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_page_table_list.sv +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_page_table_list.sv @@ -186,6 +186,9 @@ class riscv_page_table_list#(satp_mode_t MODE = SV39) extends uvm_object; $cast(valid_data_leaf_pte, valid_leaf_pte.clone()); illegal_pte.turn_off_default_constraint(); valid_link_pte.xwr = NEXT_LEVEL_PAGE; + valid_link_pte.a = 1'b0; + valid_link_pte.d = 1'b0; + valid_link_pte.u = 1'b0; valid_link_pte.pack_entry(); // Set data page to read/write, but not executable valid_data_leaf_pte.xwr = READ_WRITE_PAGE; diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_pmp_cfg.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_pmp_cfg.sv index 147f13ed3eb4b6..e25617838894f1 100644 --- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_pmp_cfg.sv +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_pmp_cfg.sv @@ -764,15 +764,26 @@ class riscv_pmp_cfg extends uvm_object; // if counter < pmp_num_regions => branch to beginning of loop, // otherwise jump to the end of the loop $sformatf("ble x%0d, x%0d, 19f", scratch_reg[1], scratch_reg[0]), - $sformatf("j 0b"), - // If we reach here, it means that no PMP entry has matched the request. - // We must immediately jump to since the CPU is taking a PMP exception, - // but this routine is unable to find a matching PMP region for the faulting access - - // there is a bug somewhere. - // In case of MMWP mode this is expected behavior, we should try to continue. - $sformatf("19: csrr x%0d, 0x%0x", scratch_reg[0], MSECCFG), - $sformatf("andi x%0d, x%0d, 2", scratch_reg[0], scratch_reg[0]), - $sformatf("bnez x%0d, 27f", scratch_reg[0]), + $sformatf("j 0b") + }; + + // If we reach here, it means that no PMP entry has matched the request. + // We must immediately jump to since the CPU is taking a PMP exception, + // but this routine is unable to find a matching PMP region for the faulting access - + // there is a bug somewhere. + // In case of MMWP mode this is expected behavior, we should try to continue. + if (riscv_instr_pkg::support_epmp) begin + instr = {instr, + $sformatf("19: csrr x%0d, 0x%0x", scratch_reg[0], MSECCFG), + $sformatf("andi x%0d, x%0d, 2", scratch_reg[0], scratch_reg[0]), + $sformatf("bnez x%0d, 27f", scratch_reg[0]) + }; + end else begin + instr = {instr, + $sformatf("19: nop") + }; + end + instr = {instr, $sformatf("la x%0d, test_done", scratch_reg[0]), $sformatf("jalr x0, x%0d, 0", scratch_reg[0]) }; @@ -839,16 +850,24 @@ class riscv_pmp_cfg extends uvm_object; // If masked_fault_addr != masked_pmpaddr[i] : mismatch, so continue looping $sformatf("bne x%0d, x%0d, 18b", scratch_reg[0], scratch_reg[4]), $sformatf("j 26f") - }; + }; // Sub-section that is common to the address modes deciding what to do what to do when hitting // a locked region + if (riscv_instr_pkg::support_epmp) begin + instr = {instr, + // If we get here there is an address match. + // First check whether we are in MML mode. + $sformatf("26: csrr x%0d, 0x%0x", scratch_reg[4], MSECCFG), + $sformatf("andi x%0d, x%0d, 1", scratch_reg[4], scratch_reg[4]), + $sformatf("bnez x%0d, 27f", scratch_reg[4]) + }; + end else begin + instr = {instr, + $sformatf("26: nop") + }; + end instr = {instr, - // If we get here there is an address match. - // First check whether we are in MML mode. - $sformatf("26: csrr x%0d, 0x%0x", scratch_reg[4], MSECCFG), - $sformatf("andi x%0d, x%0d, 1", scratch_reg[4], scratch_reg[4]), - $sformatf("bnez x%0d, 27f", scratch_reg[4]), // Then check whether the lock bit is set. $sformatf("andi x%0d, x%0d, 128", scratch_reg[4], scratch_reg[3]), $sformatf("bnez x%0d, 27f", scratch_reg[4]), diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/iss.yaml b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/iss.yaml index 63cbb2a1000a82..8a8b662307b4b3 100644 --- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/iss.yaml +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/iss.yaml @@ -36,3 +36,8 @@ path_var: WHISPER_ISS cmd: > --log --xlen --isa + +- iss: renode + path_var: RENODE_PATH + cmd: > + python3 /renode_wrapper.py --renode "" --elf --isa diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/simulator.yaml b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/simulator.yaml index 730f494ce0f151..76dd6f1e64e5b0 100644 --- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/simulator.yaml +++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/simulator.yaml @@ -22,6 +22,7 @@ - "vcs -file /vcs.compile.option.f +incdir+ +incdir+ + +vcs+lic+wait -f /files.f -full64 -l /compile.log -LDFLAGS '-Wl,--no-as-needed' @@ -53,7 +54,7 @@ - tool: questa compile: cmd: - - "vmap mtiUvm $QUESTA_HOME/questasim/uvm-1.2" + - "vmap mtiUvm $QUESTA_HOME/uvm-1.2" - "vlog -64 +incdir+ +incdir+