diff --git a/sw/host/opentitanlib/BUILD b/sw/host/opentitanlib/BUILD index 2897d8f3a967ba..c3be68abd25913 100644 --- a/sw/host/opentitanlib/BUILD +++ b/sw/host/opentitanlib/BUILD @@ -71,9 +71,9 @@ rust_library( "src/bootstrap/primitive.rs", "src/bootstrap/rescue.rs", "src/chip/alert.rs", + "src/chip/autogen/mod.rs", "src/chip/boolean.rs", "src/chip/mod.rs", - "src/chip/autogen/mod.rs", "src/console/mod.rs", "src/console/spi.rs", "src/crypto/mod.rs", @@ -83,10 +83,10 @@ rust_library( "src/dif/aon_timer.rs", "src/dif/clkmgr.rs", "src/dif/lc_ctrl.rs", + "src/dif/mod.rs", "src/dif/otp_ctrl.rs", "src/dif/rstmgr.rs", "src/dif/uart.rs", - "src/dif/mod.rs", "src/image/image.rs", "src/image/manifest.rs", "src/image/manifest_def.rs", @@ -109,10 +109,10 @@ rust_library( "src/otp/lc_state.rs", "src/otp/mod.rs", "src/otp/otp_img.rs", - "src/proxy/nonblocking_uart.rs", "src/proxy/errors.rs", "src/proxy/handler.rs", "src/proxy/mod.rs", + "src/proxy/nonblocking_uart.rs", "src/proxy/protocol.rs", "src/proxy/socket_server.rs", "src/spiflash/flash.rs", @@ -126,6 +126,7 @@ rust_library( "src/test_utils/gpio.rs", "src/test_utils/i2c_target.rs", "src/test_utils/init.rs", + "src/test_utils/lc.rs", "src/test_utils/lc_transition.rs", "src/test_utils/load_bitstream.rs", "src/test_utils/load_sram_program.rs", @@ -142,14 +143,14 @@ rust_library( "src/tpm/driver.rs", "src/tpm/mod.rs", "src/tpm/status.rs", - "src/transport/common/mod.rs", - "src/transport/common/fpga.rs", - "src/transport/common/uart.rs", "src/transport/chip_whisperer/board.rs", "src/transport/chip_whisperer/gpio.rs", "src/transport/chip_whisperer/mod.rs", "src/transport/chip_whisperer/spi.rs", "src/transport/chip_whisperer/usb.rs", + "src/transport/common/fpga.rs", + "src/transport/common/mod.rs", + "src/transport/common/uart.rs", "src/transport/dediprog/gpio.rs", "src/transport/dediprog/mod.rs", "src/transport/dediprog/spi.rs", @@ -182,8 +183,8 @@ rust_library( "src/transport/ultradebug/mpsse.rs", "src/transport/ultradebug/spi.rs", "src/transport/ultradebug/uart.rs", - "src/transport/verilator/mod.rs", "src/transport/verilator/gpio.rs", + "src/transport/verilator/mod.rs", "src/transport/verilator/subprocess.rs", "src/transport/verilator/transport.rs", "src/transport/verilator/uart.rs", diff --git a/sw/host/opentitanlib/src/test_utils/lc.rs b/sw/host/opentitanlib/src/test_utils/lc.rs new file mode 100644 index 00000000000000..935d5681dedfcf --- /dev/null +++ b/sw/host/opentitanlib/src/test_utils/lc.rs @@ -0,0 +1,24 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +use std::time::Duration; + +use anyhow::Result; + +use crate::app::TransportWrapper; +use crate::dif::lc_ctrl::{DifLcCtrlState, LcCtrlReg}; +use crate::io::jtag::{JtagParams, JtagTap}; + +pub fn read_lc_state( + transport: &TransportWrapper, + jtag_params: &JtagParams, + reset_delay: Duration, +) -> Result { + transport.pin_strapping("PINMUX_TAP_LC")?.apply()?; + transport.reset_target(reset_delay, true)?; + let mut jtag = jtag_params.create(&transport)?.connect(JtagTap::LcTap)?; + let raw_lc_state = jtag.read_lc_ctrl_reg(&LcCtrlReg::LcState)?; + jtag.disconnect()?; + DifLcCtrlState::from_redundant_encoding(raw_lc_state) +} diff --git a/sw/host/opentitanlib/src/test_utils/mod.rs b/sw/host/opentitanlib/src/test_utils/mod.rs index 84823ce20e3828..44fefc14bc4c28 100644 --- a/sw/host/opentitanlib/src/test_utils/mod.rs +++ b/sw/host/opentitanlib/src/test_utils/mod.rs @@ -10,6 +10,7 @@ pub mod extclk; pub mod gpio; pub mod i2c_target; pub mod init; +pub mod lc; pub mod lc_transition; pub mod load_bitstream; pub mod load_sram_program; diff --git a/sw/host/tests/manuf/provisioning/cp/src/main.rs b/sw/host/tests/manuf/provisioning/cp/src/main.rs index 474108e5795d2f..f390dcf0d34ed2 100644 --- a/sw/host/tests/manuf/provisioning/cp/src/main.rs +++ b/sw/host/tests/manuf/provisioning/cp/src/main.rs @@ -8,9 +8,9 @@ use anyhow::Result; use clap::Parser; use cp_lib::{reset_and_lock, run_sram_cp_provision, ManufCpProvisioningDataInput}; -use opentitanlib::dif::lc_ctrl::{DifLcCtrlState, LcCtrlReg}; -use opentitanlib::io::jtag::JtagTap; +use opentitanlib::dif::lc_ctrl::DifLcCtrlState; use opentitanlib::test_utils::init::InitializeTest; +use opentitanlib::test_utils::lc::read_lc_state; use opentitanlib::test_utils::load_sram_program::SramProgramParams; use ujson_lib::provisioning_data::ManufCpProvisioningData; use util_lib::hex_string_to_u32_arrayvec; @@ -50,21 +50,14 @@ fn main() -> Result<()> { )?, }; - // Read the LC state. - transport.pin_strapping("PINMUX_TAP_LC")?.apply()?; - transport.reset_target(opts.init.bootstrap.options.reset_delay, true)?; - let mut jtag = opts - .init - .jtag_params - .create(&transport)? - .connect(JtagTap::LcTap)?; - let lc_state = - DifLcCtrlState::from_redundant_encoding(jtag.read_lc_ctrl_reg(&LcCtrlReg::LcState)?)?; - jtag.disconnect()?; - // Only run CP provisioning if requested in any of the TestUnlocked states, except the last // state (TestUnlocked7), as this state requires special handling of the wafer authentication // secret, which is not yet implemented. + let lc_state = read_lc_state( + &transport, + &opts.init.jtag_params, + opts.init.bootstrap.options.reset_delay, + )?; match lc_state { DifLcCtrlState::TestUnlocked0 | DifLcCtrlState::TestUnlocked1 @@ -81,23 +74,22 @@ fn main() -> Result<()> { &provisioning_data, opts.timeout, )?; + // Only perform lock if we are in TEST_UNLOCKED0, otherwise we are running from a later + // stage and want to run FT stage directly after. + if lc_state == DifLcCtrlState::TestUnlocked0 { + reset_and_lock( + &transport, + &opts.init.jtag_params, + opts.init.bootstrap.options.reset_delay, + )?; + } else { + log::info!("Skipping resetting and locking the device."); + } } _ => { log::info!("Skipping executing the SRAM CP provisioning binary."); } }; - // Only perform lock if we are in TEST_UNLOCKED0, otherwise we are running from a later - // stage and want to run FT stage directly after. - if lc_state == DifLcCtrlState::TestUnlocked0 { - reset_and_lock( - &transport, - &opts.init.jtag_params, - opts.init.bootstrap.options.reset_delay, - )?; - } else { - log::info!("Skipping resetting and locking the device."); - } - Ok(()) } diff --git a/sw/host/tests/manuf/provisioning/ft/src/main.rs b/sw/host/tests/manuf/provisioning/ft/src/main.rs index 74bd7ae9a72caf..50047e49f35db8 100644 --- a/sw/host/tests/manuf/provisioning/ft/src/main.rs +++ b/sw/host/tests/manuf/provisioning/ft/src/main.rs @@ -10,9 +10,9 @@ use clap::{Args, Parser}; use ft_lib::{run_ft_personalize, run_sram_ft_individualize, test_exit, test_unlock}; use opentitanlib::backend; -use opentitanlib::dif::lc_ctrl::{DifLcCtrlState, LcCtrlReg}; -use opentitanlib::io::jtag::JtagTap; +use opentitanlib::dif::lc_ctrl::DifLcCtrlState; use opentitanlib::test_utils::init::InitializeTest; +use opentitanlib::test_utils::lc::read_lc_state; use opentitanlib::test_utils::load_sram_program::SramProgramParams; use ujson_lib::provisioning_data::{ManufCertPersoDataIn, ManufFtIndividualizeData}; use util_lib::hex_string_to_u32_arrayvec; @@ -112,20 +112,12 @@ fn main() -> Result<()> { owner_measurement: owner_measurement.clone(), }; - // Read the LC state. - transport.pin_strapping("PINMUX_TAP_LC")?.apply()?; - transport.reset_target(opts.init.bootstrap.options.reset_delay, true)?; - let mut jtag = opts - .init - .jtag_params - .create(&transport)? - .connect(JtagTap::LcTap)?; - let lc_state = - DifLcCtrlState::from_redundant_encoding(jtag.read_lc_ctrl_reg(&LcCtrlReg::LcState)?)?; - jtag.disconnect()?; - // Only run test unlock operation if we are in a locked LC state. - match lc_state { + match read_lc_state( + &transport, + &opts.init.jtag_params, + opts.init.bootstrap.options.reset_delay, + )? { DifLcCtrlState::TestLocked0 | DifLcCtrlState::TestLocked1 | DifLcCtrlState::TestLocked2 @@ -147,7 +139,11 @@ fn main() -> Result<()> { // Only run the SRAM individualize program in a test unlocked state. If we have transitioned to // a mission state already, then we can skip this step. - match lc_state { + match read_lc_state( + &transport, + &opts.init.jtag_params, + opts.init.bootstrap.options.reset_delay, + )? { DifLcCtrlState::TestUnlocked0 => { bail!("FT stage cannot be run from test unlocked 0. Run CP stage first."); }