From 1e1e0619c91229bed1eb64f5584a1bdd5cdae1e9 Mon Sep 17 00:00:00 2001 From: Robert Schilling Date: Fri, 6 Dec 2024 13:05:26 -0800 Subject: [PATCH] [soc_dbg_ctrl,rtl] Add status registers that IBEX writes and JTAG reads Signed-off-by: Robert Schilling --- hw/ip/soc_dbg_ctrl/data/soc_dbg_ctrl.hjson | 107 +++++++++++ hw/ip/soc_dbg_ctrl/doc/registers.md | 144 +++++++++++--- hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl.sv | 4 + .../rtl/soc_dbg_ctrl_core_reg_top.sv | 178 +++++++++++++++++- .../rtl/soc_dbg_ctrl_jtag_reg_top.sv | 113 ++++++++++- .../soc_dbg_ctrl/rtl/soc_dbg_ctrl_reg_pkg.sv | 78 ++++++-- .../data/autogen/top_darjeeling.gen.hjson | 2 +- .../dv/autogen/xbar_env_pkg__params.sv | 2 +- .../dv/autogen/xbar_tgl_excl.cfg | 2 +- .../xbar_dbg/data/autogen/xbar_dbg.gen.hjson | 2 +- .../ip/xbar_dbg/dv/autogen/xbar_cover.cfg | 2 +- .../dv/autogen/xbar_env_pkg__params.sv | 2 +- .../ip/xbar_dbg/rtl/autogen/tl_dbg_pkg.sv | 2 +- 13 files changed, 579 insertions(+), 59 deletions(-) diff --git a/hw/ip/soc_dbg_ctrl/data/soc_dbg_ctrl.hjson b/hw/ip/soc_dbg_ctrl/data/soc_dbg_ctrl.hjson index b7cdbd793dc360..494714633bc0be 100644 --- a/hw/ip/soc_dbg_ctrl/data/soc_dbg_ctrl.hjson +++ b/hw/ip/soc_dbg_ctrl/data/soc_dbg_ctrl.hjson @@ -225,6 +225,59 @@ } ] } + { name: "STATUS" + desc: "Debug Status Register" + swaccess: "rw" + hwaccess: "hro" + fields: [ + { bits: "0" + name: "auth_debug_intent_set" + desc: ''' + Status bit indicating whether the debug intent hardware strap + was set. If set, SoC will be treated as under debug and + authorized debug can be enabled to unlock the SoC at desired + debug unlock level + ''' + resval: "0" + } + { bits: "4" + name: "auth_window_open" + desc: ''' + Status bit that tells whether debug authorization exchange + can take place + This bit is set when auth_debug_intent_set is 1 and SoC reset + sequence is paused to enable debug authorization exchange + ''' + resval: "0" + } + { bits: "5" + name: "auth_window_closed" + desc: ''' + Status bit that indicates that SoC reset sequence is + unpaused SoC shall continue to boot and the debug authorization + exchange cannot take place anymore until next reset. Note that + the rest of the SoC reset sequence is triggered by the OT RoT + ''' + resval: "0" + } + { bits: "6" + name: "auth_unlock_success" + desc: ''' + Status bit indicating whether the unlock protocol + resulted in a successful unlock at requested level" + ''' + resval: "0" + } + { bits: "7" + name: "auth_unlock_failed" + desc: ''' + Status bit indicating whether the unlock protocol was + ulted in unlock failure at requested level" + ''' + resval: "0" + } + ] + } ] jtag: [ { name: "JTAG_TRACE_DEBUG_POLICY_CATEGORY" @@ -278,6 +331,60 @@ } ] } + { name: "JTAG_STATUS" + desc: "Debug Status Register" + swaccess: "ro" + hwaccess: "hwo" + hwext: "true" + fields: [ + { bits: "0" + name: "auth_debug_intent_set" + desc: ''' + Status bit indicating whether the debug intent hardware strap + was set. If set, SoC will be treated as under debug and + authorized debug can be enabled to unlock the SoC at desired + debug unlock level" + ''' + resval: "0" + } + { bits: "4" + name: "auth_window_open" + desc: ''' + Status bit that tells whether debug authorization exchange + can take place + This bit is set when auth_debug_intent_set is 1 and SoC reset + sequence is paused to enable debug authorization exchange" + ''' + resval: "0" + } + { bits: "5" + name: "auth_window_closed" + desc: ''' + Status bit that indicates that SoC reset sequence is + unpaused, SoC shall continue to boot and the debug authorization + exchange cannot take place anymore until next reset. Note that + the rest of the SoC reset sequence is triggered by the OT RoT" + ''' + resval: "0" + } + { bits: "6" + name: "auth_unlock_success" + desc: ''' + Status bit indicating whether the unlock protocol + resulted in a successful unlock at requested level" + ''' + resval: "0" + } + { bits: "7" + name: "auth_unlock_failed" + desc: ''' + Status bit indicating whether the unlock protocol was + ulted in unlock failure at requested level" + ''' + resval: "0" + } + ] + } { name: "JTAG_BOOT_STATUS" desc: ''' Debug boot status register that tells important boot state information. diff --git a/hw/ip/soc_dbg_ctrl/doc/registers.md b/hw/ip/soc_dbg_ctrl/doc/registers.md index 1379c60c35a253..fe3c577fa12640 100644 --- a/hw/ip/soc_dbg_ctrl/doc/registers.md +++ b/hw/ip/soc_dbg_ctrl/doc/registers.md @@ -15,6 +15,7 @@ Depending on the configured debug category, a consumer might accept the debug co | soc_dbg_ctrl.[`DEBUG_POLICY_RELOCKED`](#debug_policy_relocked) | 0xc | 4 | Debug Policy relocked | | soc_dbg_ctrl.[`TRACE_DEBUG_POLICY_CATEGORY`](#trace_debug_policy_category) | 0x10 | 4 | Trace register to observe the debug category that is either determined by hardware or software. | | soc_dbg_ctrl.[`TRACE_DEBUG_POLICY_VALID_RELOCKED`](#trace_debug_policy_valid_relocked) | 0x14 | 4 | Trace register to observe the valid or relocked state that is either determined by hardware or software. | +| soc_dbg_ctrl.[`STATUS`](#status) | 0x18 | 4 | Debug Status Register | ## ALERT_TEST Alert Test Register @@ -121,6 +122,28 @@ Trace register to observe the valid or relocked state that is either determined | 7:4 | ro | 0x9 | relocked | The relocked state determined by hardware or software. | | 3:0 | ro | 0x9 | valid | The valid state determined by hardware or software. | +## STATUS +Debug Status Register +- Offset: `0x18` +- Reset default: `0x0` +- Reset mask: `0xf1` + +### Fields + +```wavejson +{"reg": [{"name": "auth_debug_intent_set", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "auth_window_open", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "auth_window_closed", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "auth_unlock_success", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "auth_unlock_failed", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:8 | | | | Reserved | +| 7 | rw | 0x0 | auth_unlock_failed | Status bit indicating whether the unlock protocol was ulted in unlock failure at requested level" | +| 6 | rw | 0x0 | auth_unlock_success | Status bit indicating whether the unlock protocol resulted in a successful unlock at requested level" | +| 5 | rw | 0x0 | auth_window_closed | Status bit that indicates that SoC reset sequence is unpaused SoC shall continue to boot and the debug authorization exchange cannot take place anymore until next reset. Note that the rest of the SoC reset sequence is triggered by the OT RoT | +| 4 | rw | 0x0 | auth_window_open | Status bit that tells whether debug authorization exchange can take place This bit is set when auth_debug_intent_set is 1 and SoC reset sequence is paused to enable debug authorization exchange | +| 3:1 | | | | Reserved | +| 0 | rw | 0x0 | auth_debug_intent_set | Status bit indicating whether the debug intent hardware strap was set. If set, SoC will be treated as under debug and authorized debug can be enabled to unlock the SoC at desired debug unlock level | + ## Summary of the **`jtag`** interface's registers | Name | Offset | Length | Description | @@ -128,7 +151,9 @@ Trace register to observe the valid or relocked state that is either determined | soc_dbg_ctrl.[`JTAG_TRACE_DEBUG_POLICY_CATEGORY`](#jtag_trace_debug_policy_category) | 0x0 | 4 | Trace register to observe the debug category that is either determined by hardware or software. | | soc_dbg_ctrl.[`JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED`](#jtag_trace_debug_policy_valid_relocked) | 0x4 | 4 | Trace register to observe the valid or relocked state that is either determined by hardware or software. | | soc_dbg_ctrl.[`JTAG_CONTROL`](#jtag_control) | 0x8 | 4 | JTAG control register to interact with the boot flow. | -| soc_dbg_ctrl.[`JTAG_BOOT_STATUS`](#jtag_boot_status) | 0xc | 4 | Debug Status Register that tells important boot state information. | +| soc_dbg_ctrl.[`JTAG_STATUS`](#jtag_status) | 0xc | 4 | Debug Status Register | +| soc_dbg_ctrl.[`JTAG_BOOT_STATUS`](#jtag_boot_status) | 0x10 | 4 | Debug boot status register that tells important boot state information. | +| soc_dbg_ctrl.[`JTAG_TRACE_SOC_DBG_STATE`](#jtag_trace_soc_dbg_state) | 0x14 | 4 | Tells the current debug state coming from OTP. | ## JTAG_TRACE_DEBUG_POLICY_CATEGORY Trace register to observe the debug category that is either determined by hardware or software. @@ -182,58 +207,127 @@ JTAG control register to interact with the boot flow. | 31:1 | | | | Reserved | | 0 | rw | 0x0 | boot_continue | JTAG bit to stop or continue the boot flow if Ibex. | -## JTAG_BOOT_STATUS - Debug Status Register that tells important boot state information. - Note that this information is reflected only if the hw_dft_en signal is true +## JTAG_STATUS +Debug Status Register - Offset: `0xc` - Reset default: `0x0` -- Reset mask: `0x7ff` +- Reset mask: `0xf1` ### Fields ```wavejson -{"reg": [{"name": "main_clk_status", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "io_clk_status", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "otp_done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "lc_done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rom_ctrl_done", "bits": 3, "attr": ["ro"], "rotate": -90}, {"name": "rom_ctrl_good", "bits": 3, "attr": ["ro"], "rotate": -90}, {"name": "cpu_fetch_en", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}} +{"reg": [{"name": "auth_debug_intent_set", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 3}, {"name": "auth_window_open", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "auth_window_closed", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "auth_unlock_success", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "auth_unlock_failed", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:-------------------------------------------------------------| +| 31:8 | | | Reserved | +| 7 | ro | 0x0 | [auth_unlock_failed](#jtag_status--auth_unlock_failed) | +| 6 | ro | 0x0 | [auth_unlock_success](#jtag_status--auth_unlock_success) | +| 5 | ro | 0x0 | [auth_window_closed](#jtag_status--auth_window_closed) | +| 4 | ro | 0x0 | [auth_window_open](#jtag_status--auth_window_open) | +| 3:1 | | | Reserved | +| 0 | ro | 0x0 | [auth_debug_intent_set](#jtag_status--auth_debug_intent_set) | + +### JTAG_STATUS . auth_unlock_failed + Status bit indicating whether the unlock protocol was + ulted in unlock failure at requested level" + +### JTAG_STATUS . auth_unlock_success + Status bit indicating whether the unlock protocol + resulted in a successful unlock at requested level" + +### JTAG_STATUS . auth_window_closed + Status bit that indicates that SoC reset sequence is + unpaused, SoC shall continue to boot and the debug authorization + exchange cannot take place anymore until next reset. Note that + the rest of the SoC reset sequence is triggered by the OT RoT" + +### JTAG_STATUS . auth_window_open + Status bit that tells whether debug authorization exchange + can take place + This bit is set when auth_debug_intent_set is 1 and SoC reset + sequence is paused to enable debug authorization exchange" + +### JTAG_STATUS . auth_debug_intent_set + Status bit indicating whether the debug intent hardware strap + was set. If set, SoC will be treated as under debug and + authorized debug can be enabled to unlock the SoC at desired + debug unlock level" + +## JTAG_BOOT_STATUS +Debug boot status register that tells important boot state information. +Note that this information is reflected only if the hw_dft_en signal is true. +- Offset: `0x10` +- Reset default: `0x0` +- Reset mask: `0x3ffff` + +### Fields + +```wavejson +{"reg": [{"name": "main_clk_status", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "io_clk_status", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "otp_done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "lc_done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "cpu_fetch_en", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "halt_fsm_state", "bits": 7, "attr": ["ro"], "rotate": -90}, {"name": "rom_ctrl_done", "bits": 3, "attr": ["ro"], "rotate": -90}, {"name": "rom_ctrl_good", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 14}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}} ``` | Bits | Type | Reset | Name | |:------:|:------:|:-------:|:------------------------------------------------------| -| 31:11 | | | Reserved | -| 10 | ro | 0x0 | [cpu_fetch_en](#jtag_boot_status--cpu_fetch_en) | -| 9:7 | ro | 0x0 | [rom_ctrl_good](#jtag_boot_status--rom_ctrl_good) | -| 6:4 | ro | 0x0 | [rom_ctrl_done](#jtag_boot_status--rom_ctrl_done) | +| 31:18 | | | Reserved | +| 17:15 | ro | 0x0 | [rom_ctrl_good](#jtag_boot_status--rom_ctrl_good) | +| 14:12 | ro | 0x0 | [rom_ctrl_done](#jtag_boot_status--rom_ctrl_done) | +| 11:5 | ro | 0x0 | [halt_fsm_state](#jtag_boot_status--halt_fsm_state) | +| 4 | ro | 0x0 | [cpu_fetch_en](#jtag_boot_status--cpu_fetch_en) | | 3 | ro | 0x0 | [lc_done](#jtag_boot_status--lc_done) | | 2 | ro | 0x0 | [otp_done](#jtag_boot_status--otp_done) | | 1 | ro | 0x0 | [io_clk_status](#jtag_boot_status--io_clk_status) | | 0 | ro | 0x0 | [main_clk_status](#jtag_boot_status--main_clk_status) | -### JTAG_BOOT_STATUS . cpu_fetch_en - Indication from powermanger to IBEX to state code execution - ### JTAG_BOOT_STATUS . rom_ctrl_good - Rom control integrity check status; One bit corresponding to each ROM - ROM0 = base ROM - ROM1 = second ROM partition - ROM2 = the continue boot inidcaiton form IBEX halt FSM socdbg_ctrl module - + Rom control integrity check status; One bit corresponding to each ROM + ROM0 = base ROM + ROM1 = second ROM partition + ROM2 = the continue boot inidcaiton form IBEX halt FSM socdbg_ctrl module - leverages pwrmgr ROM controler inputs to halt boot sequence ### JTAG_BOOT_STATUS . rom_ctrl_done - Rom control initialization done; One bit corresponding to each ROM - ROM0 = base ROM - ROM1 = second ROM partition - ROM2 = the continue boot inidcaiton form IBEX halt FSM socdbg_ctrl module - + Rom control initialization done; One bit corresponding to each ROM + ROM0 = base ROM + ROM1 = second ROM partition + ROM2 = the continue boot inidcaiton form IBEX halt FSM socdbg_ctrl module - leverages pwrmgr ROM controler inputs to halt boot sequence +### JTAG_BOOT_STATUS . halt_fsm_state +The state of the halt state FSM. + +### JTAG_BOOT_STATUS . cpu_fetch_en + Indication from powermanger to IBEX to state code execution + ### JTAG_BOOT_STATUS . lc_done - Lifecycle controller initialization done; LC policy is decoded and set + Lifecycle controller initialization done; LC policy is decoded and set ### JTAG_BOOT_STATUS . otp_done - OTP controller initialization complete + OTP controller initialization complete ### JTAG_BOOT_STATUS . io_clk_status - Status of the IO Clock activation + Status of the IO Clock activation ### JTAG_BOOT_STATUS . main_clk_status - Status of the main clock activation + Status of the main clock activation + +## JTAG_TRACE_SOC_DBG_STATE +Tells the current debug state coming from OTP. +Note that this information is reflected only if the hw_dft_en signal is true. +- Offset: `0x14` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "soc_dbg_state", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------|:-------------------------| +| 31:0 | ro | 0x0 | soc_dbg_state | The current debug state. | diff --git a/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl.sv b/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl.sv index b72e86ebe4e5d1..e129c9652e50de 100644 --- a/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl.sv +++ b/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl.sv @@ -244,6 +244,10 @@ module soc_dbg_ctrl assign jtag_hw2reg.jtag_trace_debug_policy_valid_relocked.relocked.de = 1'b1; assign jtag_hw2reg.jtag_trace_debug_policy_valid_relocked.relocked.d = soc_dbg_policy_q.relocked; + // The status register is written by IBEX firmware and is reflected into the JTAG status register. + // The JTAG user shall query this status register. + assign jtag_hw2reg.jtag_status = socdbg_ctrl_hw2reg_jtag_status_reg_t'(core_reg2hw.status); + always_comb begin jtag_hw2reg.jtag_boot_status = '0; jtag_hw2reg.jtag_trace_soc_dbg_state = '0; diff --git a/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl_core_reg_top.sv b/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl_core_reg_top.sv index 2d0ad6158ce713..910e6624ee6903 100644 --- a/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl_core_reg_top.sv +++ b/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl_core_reg_top.sv @@ -56,9 +56,9 @@ module soc_dbg_ctrl_core_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [5:0] reg_we_check; + logic [6:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(6) + .OneHotWidth(7) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -144,6 +144,17 @@ module soc_dbg_ctrl_core_reg_top ( logic [6:0] trace_debug_policy_category_qs; logic [3:0] trace_debug_policy_valid_relocked_valid_qs; logic [3:0] trace_debug_policy_valid_relocked_relocked_qs; + logic status_we; + logic status_auth_debug_intent_set_qs; + logic status_auth_debug_intent_set_wd; + logic status_auth_window_open_qs; + logic status_auth_window_open_wd; + logic status_auth_window_closed_qs; + logic status_auth_window_closed_wd; + logic status_auth_unlock_success_qs; + logic status_auth_unlock_success_wd; + logic status_auth_unlock_failed_qs; + logic status_auth_unlock_failed_wd; // Register instances // R[alert_test]: V(True) @@ -352,8 +363,145 @@ module soc_dbg_ctrl_core_reg_top ( ); + // R[status]: V(False) + // F[auth_debug_intent_set]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_status_auth_debug_intent_set ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (status_we), + .wd (status_auth_debug_intent_set_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.status.auth_debug_intent_set.q), + .ds (), + + // to register interface (read) + .qs (status_auth_debug_intent_set_qs) + ); + + // F[auth_window_open]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_status_auth_window_open ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (status_we), + .wd (status_auth_window_open_wd), - logic [5:0] addr_hit; + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.status.auth_window_open.q), + .ds (), + + // to register interface (read) + .qs (status_auth_window_open_qs) + ); + + // F[auth_window_closed]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_status_auth_window_closed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (status_we), + .wd (status_auth_window_closed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.status.auth_window_closed.q), + .ds (), + + // to register interface (read) + .qs (status_auth_window_closed_qs) + ); + + // F[auth_unlock_success]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_status_auth_unlock_success ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (status_we), + .wd (status_auth_unlock_success_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.status.auth_unlock_success.q), + .ds (), + + // to register interface (read) + .qs (status_auth_unlock_success_qs) + ); + + // F[auth_unlock_failed]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_status_auth_unlock_failed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (status_we), + .wd (status_auth_unlock_failed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.status.auth_unlock_failed.q), + .ds (), + + // to register interface (read) + .qs (status_auth_unlock_failed_qs) + ); + + + + logic [6:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[0] = (reg_addr == SOC_DBG_CTRL_ALERT_TEST_OFFSET); @@ -362,6 +510,7 @@ module soc_dbg_ctrl_core_reg_top ( addr_hit[3] = (reg_addr == SOC_DBG_CTRL_DEBUG_POLICY_RELOCKED_OFFSET); addr_hit[4] = (reg_addr == SOC_DBG_CTRL_TRACE_DEBUG_POLICY_CATEGORY_OFFSET); addr_hit[5] = (reg_addr == SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED_OFFSET); + addr_hit[6] = (reg_addr == SOC_DBG_CTRL_STATUS_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -374,7 +523,8 @@ module soc_dbg_ctrl_core_reg_top ( (addr_hit[2] & (|(SOC_DBG_CTRL_CORE_PERMIT[2] & ~reg_be))) | (addr_hit[3] & (|(SOC_DBG_CTRL_CORE_PERMIT[3] & ~reg_be))) | (addr_hit[4] & (|(SOC_DBG_CTRL_CORE_PERMIT[4] & ~reg_be))) | - (addr_hit[5] & (|(SOC_DBG_CTRL_CORE_PERMIT[5] & ~reg_be))))); + (addr_hit[5] & (|(SOC_DBG_CTRL_CORE_PERMIT[5] & ~reg_be))) | + (addr_hit[6] & (|(SOC_DBG_CTRL_CORE_PERMIT[6] & ~reg_be))))); end // Generate write-enables @@ -394,6 +544,17 @@ module soc_dbg_ctrl_core_reg_top ( assign debug_policy_relocked_we = addr_hit[3] & reg_we & !reg_error; assign debug_policy_relocked_wd = reg_wdata[3:0]; + assign status_we = addr_hit[6] & reg_we & !reg_error; + + assign status_auth_debug_intent_set_wd = reg_wdata[0]; + + assign status_auth_window_open_wd = reg_wdata[4]; + + assign status_auth_window_closed_wd = reg_wdata[5]; + + assign status_auth_unlock_success_wd = reg_wdata[6]; + + assign status_auth_unlock_failed_wd = reg_wdata[7]; // Assign write-enables to checker logic vector. always_comb begin @@ -404,6 +565,7 @@ module soc_dbg_ctrl_core_reg_top ( reg_we_check[3] = debug_policy_relocked_we; reg_we_check[4] = 1'b0; reg_we_check[5] = 1'b0; + reg_we_check[6] = status_we; end // Read data return @@ -436,6 +598,14 @@ module soc_dbg_ctrl_core_reg_top ( reg_rdata_next[7:4] = trace_debug_policy_valid_relocked_relocked_qs; end + addr_hit[6]: begin + reg_rdata_next[0] = status_auth_debug_intent_set_qs; + reg_rdata_next[4] = status_auth_window_open_qs; + reg_rdata_next[5] = status_auth_window_closed_qs; + reg_rdata_next[6] = status_auth_unlock_success_qs; + reg_rdata_next[7] = status_auth_unlock_failed_qs; + end + default: begin reg_rdata_next = '1; end diff --git a/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl_jtag_reg_top.sv b/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl_jtag_reg_top.sv index 1969e3c418123c..440ddf94bb98d1 100644 --- a/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl_jtag_reg_top.sv +++ b/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl_jtag_reg_top.sv @@ -52,9 +52,9 @@ module soc_dbg_ctrl_jtag_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [4:0] reg_we_check; + logic [5:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(5) + .OneHotWidth(6) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -127,6 +127,12 @@ module soc_dbg_ctrl_jtag_reg_top ( logic jtag_control_we; logic jtag_control_qs; logic jtag_control_wd; + logic jtag_status_re; + logic jtag_status_auth_debug_intent_set_qs; + logic jtag_status_auth_window_open_qs; + logic jtag_status_auth_window_closed_qs; + logic jtag_status_auth_unlock_success_qs; + logic jtag_status_auth_unlock_failed_qs; logic jtag_boot_status_re; logic jtag_boot_status_main_clk_status_qs; logic jtag_boot_status_io_clk_status_qs; @@ -252,6 +258,83 @@ module soc_dbg_ctrl_jtag_reg_top ( ); + // R[jtag_status]: V(True) + // F[auth_debug_intent_set]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_jtag_status_auth_debug_intent_set ( + .re (jtag_status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.jtag_status.auth_debug_intent_set.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (jtag_status_auth_debug_intent_set_qs) + ); + + // F[auth_window_open]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_jtag_status_auth_window_open ( + .re (jtag_status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.jtag_status.auth_window_open.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (jtag_status_auth_window_open_qs) + ); + + // F[auth_window_closed]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_jtag_status_auth_window_closed ( + .re (jtag_status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.jtag_status.auth_window_closed.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (jtag_status_auth_window_closed_qs) + ); + + // F[auth_unlock_success]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_jtag_status_auth_unlock_success ( + .re (jtag_status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.jtag_status.auth_unlock_success.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (jtag_status_auth_unlock_success_qs) + ); + + // F[auth_unlock_failed]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_jtag_status_auth_unlock_failed ( + .re (jtag_status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.jtag_status.auth_unlock_failed.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (jtag_status_auth_unlock_failed_qs) + ); + + // R[jtag_boot_status]: V(True) // F[main_clk_status]: 0:0 prim_subreg_ext #( @@ -391,14 +474,15 @@ module soc_dbg_ctrl_jtag_reg_top ( - logic [4:0] addr_hit; + logic [5:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[0] = (reg_addr == SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_CATEGORY_OFFSET); addr_hit[1] = (reg_addr == SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED_OFFSET); addr_hit[2] = (reg_addr == SOC_DBG_CTRL_JTAG_CONTROL_OFFSET); - addr_hit[3] = (reg_addr == SOC_DBG_CTRL_JTAG_BOOT_STATUS_OFFSET); - addr_hit[4] = (reg_addr == SOC_DBG_CTRL_JTAG_TRACE_SOC_DBG_STATE_OFFSET); + addr_hit[3] = (reg_addr == SOC_DBG_CTRL_JTAG_STATUS_OFFSET); + addr_hit[4] = (reg_addr == SOC_DBG_CTRL_JTAG_BOOT_STATUS_OFFSET); + addr_hit[5] = (reg_addr == SOC_DBG_CTRL_JTAG_TRACE_SOC_DBG_STATE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -410,15 +494,17 @@ module soc_dbg_ctrl_jtag_reg_top ( (addr_hit[1] & (|(SOC_DBG_CTRL_JTAG_PERMIT[1] & ~reg_be))) | (addr_hit[2] & (|(SOC_DBG_CTRL_JTAG_PERMIT[2] & ~reg_be))) | (addr_hit[3] & (|(SOC_DBG_CTRL_JTAG_PERMIT[3] & ~reg_be))) | - (addr_hit[4] & (|(SOC_DBG_CTRL_JTAG_PERMIT[4] & ~reg_be))))); + (addr_hit[4] & (|(SOC_DBG_CTRL_JTAG_PERMIT[4] & ~reg_be))) | + (addr_hit[5] & (|(SOC_DBG_CTRL_JTAG_PERMIT[5] & ~reg_be))))); end // Generate write-enables assign jtag_control_we = addr_hit[2] & reg_we & !reg_error; assign jtag_control_wd = reg_wdata[0]; - assign jtag_boot_status_re = addr_hit[3] & reg_re & !reg_error; - assign jtag_trace_soc_dbg_state_re = addr_hit[4] & reg_re & !reg_error; + assign jtag_status_re = addr_hit[3] & reg_re & !reg_error; + assign jtag_boot_status_re = addr_hit[4] & reg_re & !reg_error; + assign jtag_trace_soc_dbg_state_re = addr_hit[5] & reg_re & !reg_error; // Assign write-enables to checker logic vector. always_comb begin @@ -428,6 +514,7 @@ module soc_dbg_ctrl_jtag_reg_top ( reg_we_check[2] = jtag_control_we; reg_we_check[3] = 1'b0; reg_we_check[4] = 1'b0; + reg_we_check[5] = 1'b0; end // Read data return @@ -448,6 +535,14 @@ module soc_dbg_ctrl_jtag_reg_top ( end addr_hit[3]: begin + reg_rdata_next[0] = jtag_status_auth_debug_intent_set_qs; + reg_rdata_next[4] = jtag_status_auth_window_open_qs; + reg_rdata_next[5] = jtag_status_auth_window_closed_qs; + reg_rdata_next[6] = jtag_status_auth_unlock_success_qs; + reg_rdata_next[7] = jtag_status_auth_unlock_failed_qs; + end + + addr_hit[4]: begin reg_rdata_next[0] = jtag_boot_status_main_clk_status_qs; reg_rdata_next[1] = jtag_boot_status_io_clk_status_qs; reg_rdata_next[2] = jtag_boot_status_otp_done_qs; @@ -458,7 +553,7 @@ module soc_dbg_ctrl_jtag_reg_top ( reg_rdata_next[17:15] = jtag_boot_status_rom_ctrl_good_qs; end - addr_hit[4]: begin + addr_hit[5]: begin reg_rdata_next[31:0] = jtag_trace_soc_dbg_state_qs; end diff --git a/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl_reg_pkg.sv b/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl_reg_pkg.sv index 7123eba46120a4..c24810c43d6f7a 100644 --- a/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl_reg_pkg.sv +++ b/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl_reg_pkg.sv @@ -42,6 +42,24 @@ package soc_dbg_ctrl_reg_pkg; logic [3:0] q; } soc_dbg_ctrl_reg2hw_debug_policy_relocked_reg_t; + typedef struct packed { + struct packed { + logic q; + } auth_unlock_failed; + struct packed { + logic q; + } auth_unlock_success; + struct packed { + logic q; + } auth_window_closed; + struct packed { + logic q; + } auth_window_open; + struct packed { + logic q; + } auth_debug_intent_set; + } soc_dbg_ctrl_reg2hw_status_reg_t; + typedef struct packed { logic [6:0] d; } soc_dbg_ctrl_hw2reg_debug_policy_category_shadowed_reg_t; @@ -64,11 +82,12 @@ package soc_dbg_ctrl_reg_pkg; // Register -> HW type for core interface typedef struct packed { - soc_dbg_ctrl_reg2hw_alert_test_reg_t alert_test; // [20:17] - soc_dbg_ctrl_reg2hw_debug_policy_valid_shadowed_reg_t debug_policy_valid_shadowed; // [16:13] + soc_dbg_ctrl_reg2hw_alert_test_reg_t alert_test; // [25:22] + soc_dbg_ctrl_reg2hw_debug_policy_valid_shadowed_reg_t debug_policy_valid_shadowed; // [21:18] soc_dbg_ctrl_reg2hw_debug_policy_category_shadowed_reg_t - debug_policy_category_shadowed; // [12:4] - soc_dbg_ctrl_reg2hw_debug_policy_relocked_reg_t debug_policy_relocked; // [3:0] + debug_policy_category_shadowed; // [17:9] + soc_dbg_ctrl_reg2hw_debug_policy_relocked_reg_t debug_policy_relocked; // [8:5] + soc_dbg_ctrl_reg2hw_status_reg_t status; // [4:0] } soc_dbg_ctrl_core_reg2hw_t; // HW -> register type for core interface @@ -87,6 +106,7 @@ package soc_dbg_ctrl_reg_pkg; parameter logic [CoreAw-1:0] SOC_DBG_CTRL_DEBUG_POLICY_RELOCKED_OFFSET = 5'h c; parameter logic [CoreAw-1:0] SOC_DBG_CTRL_TRACE_DEBUG_POLICY_CATEGORY_OFFSET = 5'h 10; parameter logic [CoreAw-1:0] SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED_OFFSET = 5'h 14; + parameter logic [CoreAw-1:0] SOC_DBG_CTRL_STATUS_OFFSET = 5'h 18; // Reset values for hwext registers and their fields for core interface parameter logic [1:0] SOC_DBG_CTRL_ALERT_TEST_RESVAL = 2'h 0; @@ -104,17 +124,19 @@ package soc_dbg_ctrl_reg_pkg; SOC_DBG_CTRL_DEBUG_POLICY_CATEGORY_SHADOWED, SOC_DBG_CTRL_DEBUG_POLICY_RELOCKED, SOC_DBG_CTRL_TRACE_DEBUG_POLICY_CATEGORY, - SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED + SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED, + SOC_DBG_CTRL_STATUS } soc_dbg_ctrl_core_id_e; // Register width information to check illegal writes for core interface - parameter logic [3:0] SOC_DBG_CTRL_CORE_PERMIT [6] = '{ + parameter logic [3:0] SOC_DBG_CTRL_CORE_PERMIT [7] = '{ 4'b 0001, // index[0] SOC_DBG_CTRL_ALERT_TEST 4'b 0001, // index[1] SOC_DBG_CTRL_DEBUG_POLICY_VALID_SHADOWED 4'b 0001, // index[2] SOC_DBG_CTRL_DEBUG_POLICY_CATEGORY_SHADOWED 4'b 0001, // index[3] SOC_DBG_CTRL_DEBUG_POLICY_RELOCKED 4'b 0001, // index[4] SOC_DBG_CTRL_TRACE_DEBUG_POLICY_CATEGORY - 4'b 0001 // index[5] SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED + 4'b 0001, // index[5] SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED + 4'b 0001 // index[6] SOC_DBG_CTRL_STATUS }; /////////////////////////////////////////////// @@ -141,6 +163,24 @@ package soc_dbg_ctrl_reg_pkg; } relocked; } soc_dbg_ctrl_hw2reg_jtag_trace_debug_policy_valid_relocked_reg_t; + typedef struct packed { + struct packed { + logic d; + } auth_debug_intent_set; + struct packed { + logic d; + } auth_window_open; + struct packed { + logic d; + } auth_window_closed; + struct packed { + logic d; + } auth_unlock_success; + struct packed { + logic d; + } auth_unlock_failed; + } soc_dbg_ctrl_hw2reg_jtag_status_reg_t; + typedef struct packed { struct packed { logic d; @@ -180,9 +220,10 @@ package soc_dbg_ctrl_reg_pkg; // HW -> register type for jtag interface typedef struct packed { soc_dbg_ctrl_hw2reg_jtag_trace_debug_policy_category_reg_t - jtag_trace_debug_policy_category; // [67:60] + jtag_trace_debug_policy_category; // [72:65] soc_dbg_ctrl_hw2reg_jtag_trace_debug_policy_valid_relocked_reg_t - jtag_trace_debug_policy_valid_relocked; // [59:50] + jtag_trace_debug_policy_valid_relocked; // [64:55] + soc_dbg_ctrl_hw2reg_jtag_status_reg_t jtag_status; // [54:50] soc_dbg_ctrl_hw2reg_jtag_boot_status_reg_t jtag_boot_status; // [49:32] soc_dbg_ctrl_hw2reg_jtag_trace_soc_dbg_state_reg_t jtag_trace_soc_dbg_state; // [31:0] } soc_dbg_ctrl_jtag_hw2reg_t; @@ -191,10 +232,17 @@ package soc_dbg_ctrl_reg_pkg; parameter logic [JtagAw-1:0] SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_CATEGORY_OFFSET = 5'h 0; parameter logic [JtagAw-1:0] SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED_OFFSET = 5'h 4; parameter logic [JtagAw-1:0] SOC_DBG_CTRL_JTAG_CONTROL_OFFSET = 5'h 8; - parameter logic [JtagAw-1:0] SOC_DBG_CTRL_JTAG_BOOT_STATUS_OFFSET = 5'h c; - parameter logic [JtagAw-1:0] SOC_DBG_CTRL_JTAG_TRACE_SOC_DBG_STATE_OFFSET = 5'h 10; + parameter logic [JtagAw-1:0] SOC_DBG_CTRL_JTAG_STATUS_OFFSET = 5'h c; + parameter logic [JtagAw-1:0] SOC_DBG_CTRL_JTAG_BOOT_STATUS_OFFSET = 5'h 10; + parameter logic [JtagAw-1:0] SOC_DBG_CTRL_JTAG_TRACE_SOC_DBG_STATE_OFFSET = 5'h 14; // Reset values for hwext registers and their fields for jtag interface + parameter logic [7:0] SOC_DBG_CTRL_JTAG_STATUS_RESVAL = 8'h 0; + parameter logic [0:0] SOC_DBG_CTRL_JTAG_STATUS_AUTH_DEBUG_INTENT_SET_RESVAL = 1'h 0; + parameter logic [0:0] SOC_DBG_CTRL_JTAG_STATUS_AUTH_WINDOW_OPEN_RESVAL = 1'h 0; + parameter logic [0:0] SOC_DBG_CTRL_JTAG_STATUS_AUTH_WINDOW_CLOSED_RESVAL = 1'h 0; + parameter logic [0:0] SOC_DBG_CTRL_JTAG_STATUS_AUTH_UNLOCK_SUCCESS_RESVAL = 1'h 0; + parameter logic [0:0] SOC_DBG_CTRL_JTAG_STATUS_AUTH_UNLOCK_FAILED_RESVAL = 1'h 0; parameter logic [17:0] SOC_DBG_CTRL_JTAG_BOOT_STATUS_RESVAL = 18'h 0; parameter logic [0:0] SOC_DBG_CTRL_JTAG_BOOT_STATUS_MAIN_CLK_STATUS_RESVAL = 1'h 0; parameter logic [0:0] SOC_DBG_CTRL_JTAG_BOOT_STATUS_IO_CLK_STATUS_RESVAL = 1'h 0; @@ -212,17 +260,19 @@ package soc_dbg_ctrl_reg_pkg; SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_CATEGORY, SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED, SOC_DBG_CTRL_JTAG_CONTROL, + SOC_DBG_CTRL_JTAG_STATUS, SOC_DBG_CTRL_JTAG_BOOT_STATUS, SOC_DBG_CTRL_JTAG_TRACE_SOC_DBG_STATE } soc_dbg_ctrl_jtag_id_e; // Register width information to check illegal writes for jtag interface - parameter logic [3:0] SOC_DBG_CTRL_JTAG_PERMIT [5] = '{ + parameter logic [3:0] SOC_DBG_CTRL_JTAG_PERMIT [6] = '{ 4'b 0001, // index[0] SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_CATEGORY 4'b 0001, // index[1] SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED 4'b 0001, // index[2] SOC_DBG_CTRL_JTAG_CONTROL - 4'b 0111, // index[3] SOC_DBG_CTRL_JTAG_BOOT_STATUS - 4'b 1111 // index[4] SOC_DBG_CTRL_JTAG_TRACE_SOC_DBG_STATE + 4'b 0001, // index[3] SOC_DBG_CTRL_JTAG_STATUS + 4'b 0111, // index[4] SOC_DBG_CTRL_JTAG_BOOT_STATUS + 4'b 1111 // index[5] SOC_DBG_CTRL_JTAG_TRACE_SOC_DBG_STATE }; endpackage diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson index 5accfa44662f05..4d42fb9ced8264 100644 --- a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson @@ -13016,7 +13016,7 @@ { soc_dbg: 0x2300 } - size_byte: 0x10 + size_byte: 0x20 } ] xbar: false diff --git a/hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv index 9078fb599d7e02..3a9c2ca599a6d2 100644 --- a/hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv @@ -203,7 +203,7 @@ tl_device_t xbar_devices[$] = '{ '{32'h00020000, 32'h00020fff} }}, '{"soc_dbg_ctrl__jtag", '{ - '{32'h00002300, 32'h0000230f} + '{32'h00002300, 32'h0000231f} }}}; // List of Xbar hosts diff --git a/hw/top_darjeeling/dv/autogen/xbar_tgl_excl.cfg b/hw/top_darjeeling/dv/autogen/xbar_tgl_excl.cfg index c6e6cb0df4240a..b2763b01cb5eb8 100644 --- a/hw/top_darjeeling/dv/autogen/xbar_tgl_excl.cfg +++ b/hw/top_darjeeling/dv/autogen/xbar_tgl_excl.cfg @@ -287,6 +287,6 @@ -node tb.dut*.u_mbx_jtag soc_tl_*i.a_address[31:13] -node tb.dut*.u_lc_ctrl dmi_tl_*i.a_address[16:12] -node tb.dut*.u_lc_ctrl dmi_tl_*i.a_address[31:18] --node tb.dut*.u_soc_dbg_ctrl jtag_tl_*i.a_address[7:4] +-node tb.dut*.u_soc_dbg_ctrl jtag_tl_*i.a_address[7:5] -node tb.dut*.u_soc_dbg_ctrl jtag_tl_*i.a_address[12:10] -node tb.dut*.u_soc_dbg_ctrl jtag_tl_*i.a_address[31:14] diff --git a/hw/top_darjeeling/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson b/hw/top_darjeeling/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson index a7c2afa34d8819..5117c7f0b5f9c9 100644 --- a/hw/top_darjeeling/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson +++ b/hw/top_darjeeling/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson @@ -139,7 +139,7 @@ { soc_dbg: 0x2300 } - size_byte: 0x10 + size_byte: 0x20 } ] xbar: false diff --git a/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_cover.cfg b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_cover.cfg index 5a9d9a19a18335..67f75b9686cbff 100644 --- a/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_cover.cfg +++ b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_cover.cfg @@ -26,7 +26,7 @@ -node tb.dut tl_mbx_jtag__soc_o.a_address[31:13] -node tb.dut tl_lc_ctrl__dmi_o.a_address[16:12] -node tb.dut tl_lc_ctrl__dmi_o.a_address[31:18] --node tb.dut tl_soc_dbg_ctrl__jtag_o.a_address[7:4] +-node tb.dut tl_soc_dbg_ctrl__jtag_o.a_address[7:5] -node tb.dut tl_soc_dbg_ctrl__jtag_o.a_address[12:10] -node tb.dut tl_soc_dbg_ctrl__jtag_o.a_address[31:14] diff --git a/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_env_pkg__params.sv index 93532a2d173cd7..1d89f28dc5484d 100644 --- a/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_env_pkg__params.sv @@ -17,7 +17,7 @@ tl_device_t xbar_devices[$] = '{ '{32'h00020000, 32'h00020fff} }}, '{"soc_dbg_ctrl__jtag", '{ - '{32'h00002300, 32'h0000230f} + '{32'h00002300, 32'h0000231f} }}}; // List of Xbar hosts diff --git a/hw/top_darjeeling/ip/xbar_dbg/rtl/autogen/tl_dbg_pkg.sv b/hw/top_darjeeling/ip/xbar_dbg/rtl/autogen/tl_dbg_pkg.sv index ef7b8234bd7e0f..ebcf9415105c13 100644 --- a/hw/top_darjeeling/ip/xbar_dbg/rtl/autogen/tl_dbg_pkg.sv +++ b/hw/top_darjeeling/ip/xbar_dbg/rtl/autogen/tl_dbg_pkg.sv @@ -14,7 +14,7 @@ package tl_dbg_pkg; localparam logic [31:0] ADDR_MASK_RV_DM__DBG = 32'h 000001ff; localparam logic [31:0] ADDR_MASK_MBX_JTAG__SOC = 32'h 0000001f; localparam logic [31:0] ADDR_MASK_LC_CTRL__DMI = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_SOC_DBG_CTRL__JTAG = 32'h 0000000f; + localparam logic [31:0] ADDR_MASK_SOC_DBG_CTRL__JTAG = 32'h 0000001f; localparam int N_HOST = 1; localparam int N_DEVICE = 4;