From 1a8515441091115a4d089332dbfc698e84033dc4 Mon Sep 17 00:00:00 2001 From: Robert Schilling Date: Sun, 1 Dec 2024 12:59:11 -0800 Subject: [PATCH] [hw,pwrmgr,rv_core,rtl] Move pwrmgr interface to rv_core_ibex Signed-off-by: Robert Schilling --- hw/ip/rv_core_ibex/data/rv_core_ibex.hjson | 4 +- hw/ip/rv_core_ibex/doc/interfaces.md | 4 +- hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv | 2 +- hw/ip/rv_core_ibex/rtl/rv_core_ibex_pkg.sv | 10 ++++ hw/ip/rv_core_ibex/rv_core_ibex.core | 1 - hw/ip_templates/pwrmgr/data/pwrmgr.hjson.tpl | 4 +- hw/ip_templates/pwrmgr/dv/env/pwrmgr_if.sv | 4 +- hw/ip_templates/pwrmgr/pwrmgr.core.tpl | 1 + hw/ip_templates/pwrmgr/rtl/pwrmgr.sv.tpl | 2 +- hw/ip_templates/pwrmgr/rtl/pwrmgr_pkg.sv.tpl | 10 ---- .../data/autogen/top_darjeeling.gen.hjson | 26 ++++++----- .../ip_autogen/pwrmgr/data/pwrmgr.hjson | 4 +- .../ip_autogen/pwrmgr/doc/interfaces.md | 46 +++++++++---------- .../ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv | 4 +- .../ip_autogen/pwrmgr/pwrmgr.core | 1 + .../ip_autogen/pwrmgr/rtl/pwrmgr.sv | 2 +- .../ip_autogen/pwrmgr/rtl/pwrmgr_pkg.sv | 10 ---- .../rtl/autogen/top_darjeeling.sv | 3 +- .../data/autogen/top_earlgrey.gen.hjson | 22 ++++----- .../ip_autogen/pwrmgr/data/pwrmgr.hjson | 4 +- .../ip_autogen/pwrmgr/doc/interfaces.md | 44 +++++++++--------- .../ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv | 4 +- hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core | 1 + .../ip_autogen/pwrmgr/rtl/pwrmgr.sv | 2 +- .../ip_autogen/pwrmgr/rtl/pwrmgr_pkg.sv | 10 ---- hw/top_earlgrey/rtl/autogen/top_earlgrey.sv | 2 +- 26 files changed, 107 insertions(+), 120 deletions(-) diff --git a/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson b/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson index 1ae9059d94c5c..d1fc2ee084d2e 100644 --- a/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson +++ b/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson @@ -153,11 +153,11 @@ package: "lc_ctrl_pkg", }, - { struct: "pwr_cpu", + { struct: "cpu_pwrmgr", type: "uni", name: "pwrmgr", act: "req", - package: "pwrmgr_pkg", + package: "rv_core_ibex_pkg", }, { struct: "logic", diff --git a/hw/ip/rv_core_ibex/doc/interfaces.md b/hw/ip/rv_core_ibex/doc/interfaces.md index b93592c7e1531..1b648cf9c993d 100644 --- a/hw/ip/rv_core_ibex/doc/interfaces.md +++ b/hw/ip/rv_core_ibex/doc/interfaces.md @@ -28,7 +28,7 @@ Referring to the [Comportable guideline for peripheral device functionality](htt | crash_dump | rv_core_ibex_pkg::cpu_crash_dump | uni | req | 1 | | | lc_cpu_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | | pwrmgr_cpu_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| pwrmgr | pwrmgr_pkg::pwr_cpu | uni | req | 1 | | +| pwrmgr | rv_core_ibex_pkg::cpu_pwrmgr | uni | req | 1 | | | nmi_wdog | logic | uni | rcv | 1 | | | edn | edn_pkg::edn | req_rsp | req | 1 | | | icache_otp_key | otp_ctrl_pkg::sram_otp_key | req_rsp | req | 1 | | @@ -100,7 +100,7 @@ Signal | Direction | Type `cfg_tl_d_o ` | `output` | `tlul_pkg::tl_d2h_t` | Outgoing configuration bus response. `lc_cpu_en_i` | `input` | `lc_ctrl_pkg::lc_tx_t` | CPU enable signal from life cycle controller. `pwrmgr_cpu_en_i` | `input` | `lc_ctrl_pkg::lc_tx_t` | CPU enable signal from power manager. -`pwrmgr_o` | `output` | `pwrmgr_pkg::pwr_cpu_t` | Low-power CPU status to power manager. +`pwrmgr_o` | `output` | `pwrmgr_pkg::cpu_pwrmgr_t` | Low-power CPU status to power manager. `edn_i` | `input` | `edn_pkg::edn_rsp_t` | Incoming entropy response from entropy distribution network. `edn_o` | `output` | `edn_pkg::edn_req_t` | Outgoing entropy request to entropy distribution network. `icache_otp_key_i` | `input` | `otp_ctrl_pkg::sram_otp_key_rsp_t` | Incoming scrambling key response from OTP to icache. diff --git a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv index d98c74c2979ca..af00f370358a9 100644 --- a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv +++ b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv @@ -92,7 +92,7 @@ module rv_core_ibex // CPU Control Signals input lc_ctrl_pkg::lc_tx_t lc_cpu_en_i, input lc_ctrl_pkg::lc_tx_t pwrmgr_cpu_en_i, - output pwrmgr_pkg::pwr_cpu_t pwrmgr_o, + output cpu_pwrmgr_t pwrmgr_o, // dft bypass input scan_rst_ni, diff --git a/hw/ip/rv_core_ibex/rtl/rv_core_ibex_pkg.sv b/hw/ip/rv_core_ibex/rtl/rv_core_ibex_pkg.sv index 5ea7d41c168f1..bcf013163a783 100644 --- a/hw/ip/rv_core_ibex/rtl/rv_core_ibex_pkg.sv +++ b/hw/ip/rv_core_ibex/rtl/rv_core_ibex_pkg.sv @@ -21,4 +21,14 @@ package rv_core_ibex_pkg; ibex_pkg::crash_dump_t current; } cpu_crash_dump_t; + // processor to pwrmgr + typedef struct packed { + logic core_sleeping; + } cpu_pwrmgr_t; + + // default value (for dangling ports) + parameter cpu_pwrmgr_t CPU_PWRMGR_DEFAULT = '{ + core_sleeping: 1'b0 + }; + endpackage // rv_core_ibex_pkg diff --git a/hw/ip/rv_core_ibex/rv_core_ibex.core b/hw/ip/rv_core_ibex/rv_core_ibex.core index b3400ed68c2ad..a67b0ba628079 100644 --- a/hw/ip/rv_core_ibex/rv_core_ibex.core +++ b/hw/ip/rv_core_ibex/rv_core_ibex.core @@ -10,7 +10,6 @@ filesets: - lowrisc:ibex:ibex_top - lowrisc:ip:lc_ctrl_pkg - lowrisc:ip:otp_ctrl_pkg - - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:rv_core_ibex_pkg - lowrisc:ip:tlul - lowrisc:prim:all diff --git a/hw/ip_templates/pwrmgr/data/pwrmgr.hjson.tpl b/hw/ip_templates/pwrmgr/data/pwrmgr.hjson.tpl index 585f641ec074f..c968284b86459 100644 --- a/hw/ip_templates/pwrmgr/data/pwrmgr.hjson.tpl +++ b/hw/ip_templates/pwrmgr/data/pwrmgr.hjson.tpl @@ -206,11 +206,11 @@ package: "prim_esc_pkg", }, - { struct: "pwr_cpu", + { struct: "cpu_pwrmgr", type: "uni", name: "pwr_cpu", act: "rcv", - package: "pwrmgr_pkg", + package: "rv_core_ibex_pkg", }, { struct: "logic", diff --git a/hw/ip_templates/pwrmgr/dv/env/pwrmgr_if.sv b/hw/ip_templates/pwrmgr/dv/env/pwrmgr_if.sv index 101e78e81f5a1..ed590d1345df9 100644 --- a/hw/ip_templates/pwrmgr/dv/env/pwrmgr_if.sv +++ b/hw/ip_templates/pwrmgr/dv/env/pwrmgr_if.sv @@ -36,7 +36,7 @@ interface pwrmgr_if ( pwrmgr_pkg::pwr_flash_t pwr_flash; pwrmgr_pkg::pwrmgr_cpu_t cpu_i; - pwrmgr_pkg::pwr_cpu_t pwr_cpu; + rv_core_ibex_pkg::cpu_pwrmgr_t pwr_cpu; lc_ctrl_pkg::lc_tx_t fetch_en; lc_ctrl_pkg::lc_tx_t lc_hw_debug_en; @@ -192,7 +192,7 @@ interface pwrmgr_if ( pwr_otp_rsp = '{default: '0}; pwr_lc_rsp = '{default: '0}; pwr_flash = '{default: '0}; - pwr_cpu = pwrmgr_pkg::PWR_CPU_DEFAULT; + pwr_cpu = rv_core_ibex_pkg::CPU_PWRMGR_DEFAULT; wakeups_i = pwrmgr_pkg::WAKEUPS_DEFAULT; rstreqs_i = pwrmgr_pkg::RSTREQS_DEFAULT; sw_rst_req_i = prim_mubi_pkg::MuBi4False; diff --git a/hw/ip_templates/pwrmgr/pwrmgr.core.tpl b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl index be5aa3740b7c2..ff456a51e7e09 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr.core.tpl +++ b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl @@ -12,6 +12,7 @@ filesets: depend: - ${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1")} - ${instance_vlnv("lowrisc:ip:pwrmgr_reg:0.1")} + - lowrisc:ip:rv_core_ibex_pkg - lowrisc:ip:pwrmgr_component file_type: systemVerilogSource diff --git a/hw/ip_templates/pwrmgr/rtl/pwrmgr.sv.tpl b/hw/ip_templates/pwrmgr/rtl/pwrmgr.sv.tpl index c6693109288c4..8ac6dc9743c83 100644 --- a/hw/ip_templates/pwrmgr/rtl/pwrmgr.sv.tpl +++ b/hw/ip_templates/pwrmgr/rtl/pwrmgr.sv.tpl @@ -56,7 +56,7 @@ module pwrmgr input pwr_flash_t pwr_flash_i, // processor interface - input pwr_cpu_t pwr_cpu_i, + input rv_core_ibex_pkg::cpu_pwrmgr_t pwr_cpu_i, // SEC_CM: LC_CTRL.INTERSIG.MUBI output lc_ctrl_pkg::lc_tx_t fetch_en_o, input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, diff --git a/hw/ip_templates/pwrmgr/rtl/pwrmgr_pkg.sv.tpl b/hw/ip_templates/pwrmgr/rtl/pwrmgr_pkg.sv.tpl index 366fd911d57fb..700a4ad073fcd 100644 --- a/hw/ip_templates/pwrmgr/rtl/pwrmgr_pkg.sv.tpl +++ b/hw/ip_templates/pwrmgr/rtl/pwrmgr_pkg.sv.tpl @@ -145,11 +145,6 @@ package pwrmgr_pkg; flash_idle: 1'b1 }; - // processor to pwrmgr - typedef struct packed { - logic core_sleeping; - } pwr_cpu_t; - // cpu reset requests and status typedef struct packed { logic ndmreset_req; @@ -174,11 +169,6 @@ package pwrmgr_pkg; ndmreset_req: '0 }; - // default value (for dangling ports) - parameter pwr_cpu_t PWR_CPU_DEFAULT = '{ - core_sleeping: 1'b0 - }; - // default value (for dangling ports) parameter int WAKEUPS_DEFAULT = '0; parameter int RSTREQS_DEFAULT = '0; diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson index 7a7e6950ec066..70ab193d59b27 100644 --- a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson @@ -2403,8 +2403,8 @@ } { name: pwr_cpu - struct: pwr_cpu - package: pwrmgr_pkg + struct: cpu_pwrmgr + package: rv_core_ibex_pkg type: uni act: rcv width: 1 @@ -8849,8 +8849,8 @@ } { name: pwrmgr - struct: pwr_cpu - package: pwrmgr_pkg + struct: cpu_pwrmgr + package: rv_core_ibex_pkg type: uni act: req width: 1 @@ -15386,6 +15386,7 @@ } } ] + incoming_alert: {} exported_clks: {} wakeups: [ @@ -16311,6 +16312,7 @@ mbx_pcie1 rv_core_ibex ] + outgoing_alert_module: {} alert: [ { @@ -17205,6 +17207,7 @@ lpg_idx: 11 } ] + outgoing_alert: {} unmanaged_resets: {} exported_rsts: {} alert_lpgs: @@ -17682,6 +17685,7 @@ } } ] + outgoing_alert_lpgs: {} inter_signal: { signals: @@ -18879,8 +18883,8 @@ } { name: pwr_cpu - struct: pwr_cpu - package: pwrmgr_pkg + struct: cpu_pwrmgr + package: rv_core_ibex_pkg type: uni act: rcv width: 1 @@ -22356,8 +22360,8 @@ } { name: pwrmgr - struct: pwr_cpu - package: pwrmgr_pkg + struct: cpu_pwrmgr + package: rv_core_ibex_pkg type: uni act: req width: 1 @@ -25470,15 +25474,15 @@ default: rv_core_ibex_pkg::CPU_CRASH_DUMP_DEFAULT } { - package: pwrmgr_pkg - struct: pwr_cpu + package: rv_core_ibex_pkg + struct: cpu_pwrmgr signame: rv_core_ibex_pwrmgr width: 1 type: uni end_idx: -1 act: req suffix: "" - default: pwrmgr_pkg::PWR_CPU_DEFAULT + default: rv_core_ibex_pkg::CPU_PWRMGR_DEFAULT } { package: spi_device_pkg diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/data/pwrmgr.hjson b/hw/top_darjeeling/ip_autogen/pwrmgr/data/pwrmgr.hjson index 42b40b8c4edf4..70ef52bd947f3 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/data/pwrmgr.hjson +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/data/pwrmgr.hjson @@ -217,11 +217,11 @@ package: "prim_esc_pkg", }, - { struct: "pwr_cpu", + { struct: "cpu_pwrmgr", type: "uni", name: "pwr_cpu", act: "rcv", - package: "pwrmgr_pkg", + package: "rv_core_ibex_pkg", }, { struct: "logic", diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/doc/interfaces.md b/hw/top_darjeeling/ip_autogen/pwrmgr/doc/interfaces.md index 533338e1dad4e..1eb627f2e7359 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/doc/interfaces.md +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/doc/interfaces.md @@ -10,29 +10,29 @@ Referring to the [Comportable guideline for peripheral device functionality](htt ## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) -| Port Name | Package::Struct | Type | Act | Width | Description | -|:---------------|:----------------------------|:--------|:------|--------:|:--------------| -| boot_status | pwrmgr_pkg::pwr_boot_status | uni | req | 1 | | -| pwr_ast | pwrmgr_pkg::pwr_ast | req_rsp | req | 1 | | -| pwr_rst | pwrmgr_pkg::pwr_rst | req_rsp | req | 1 | | -| pwr_clk | pwrmgr_pkg::pwr_clk | req_rsp | req | 1 | | -| pwr_otp | pwrmgr_pkg::pwr_otp | req_rsp | req | 1 | | -| pwr_lc | pwrmgr_pkg::pwr_lc | req_rsp | req | 1 | | -| pwr_flash | pwrmgr_pkg::pwr_flash | uni | rcv | 1 | | -| esc_rst_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | | -| esc_rst_rx | prim_esc_pkg::esc_rx | uni | req | 1 | | -| pwr_cpu | pwrmgr_pkg::pwr_cpu | uni | rcv | 1 | | -| wakeups | logic | uni | rcv | 5 | | -| rstreqs | logic | uni | rcv | 2 | | -| ndmreset_req | logic | uni | rcv | 1 | | -| strap | logic | uni | req | 1 | | -| low_power | logic | uni | req | 1 | | -| rom_ctrl | rom_ctrl_pkg::pwrmgr_data | uni | rcv | 2 | | -| fetch_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | | -| lc_dft_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| sw_rst_req | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | -| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | +| Port Name | Package::Struct | Type | Act | Width | Description | +|:---------------|:-----------------------------|:--------|:------|--------:|:--------------| +| boot_status | pwrmgr_pkg::pwr_boot_status | uni | req | 1 | | +| pwr_ast | pwrmgr_pkg::pwr_ast | req_rsp | req | 1 | | +| pwr_rst | pwrmgr_pkg::pwr_rst | req_rsp | req | 1 | | +| pwr_clk | pwrmgr_pkg::pwr_clk | req_rsp | req | 1 | | +| pwr_otp | pwrmgr_pkg::pwr_otp | req_rsp | req | 1 | | +| pwr_lc | pwrmgr_pkg::pwr_lc | req_rsp | req | 1 | | +| pwr_flash | pwrmgr_pkg::pwr_flash | uni | rcv | 1 | | +| esc_rst_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | | +| esc_rst_rx | prim_esc_pkg::esc_rx | uni | req | 1 | | +| pwr_cpu | rv_core_ibex_pkg::cpu_pwrmgr | uni | rcv | 1 | | +| wakeups | logic | uni | rcv | 5 | | +| rstreqs | logic | uni | rcv | 2 | | +| ndmreset_req | logic | uni | rcv | 1 | | +| strap | logic | uni | req | 1 | | +| low_power | logic | uni | req | 1 | | +| rom_ctrl | rom_ctrl_pkg::pwrmgr_data | uni | rcv | 2 | | +| fetch_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | | +| lc_dft_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| sw_rst_req | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | +| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | ## Interrupts diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv index 101e78e81f5a1..ed590d1345df9 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv @@ -36,7 +36,7 @@ interface pwrmgr_if ( pwrmgr_pkg::pwr_flash_t pwr_flash; pwrmgr_pkg::pwrmgr_cpu_t cpu_i; - pwrmgr_pkg::pwr_cpu_t pwr_cpu; + rv_core_ibex_pkg::cpu_pwrmgr_t pwr_cpu; lc_ctrl_pkg::lc_tx_t fetch_en; lc_ctrl_pkg::lc_tx_t lc_hw_debug_en; @@ -192,7 +192,7 @@ interface pwrmgr_if ( pwr_otp_rsp = '{default: '0}; pwr_lc_rsp = '{default: '0}; pwr_flash = '{default: '0}; - pwr_cpu = pwrmgr_pkg::PWR_CPU_DEFAULT; + pwr_cpu = rv_core_ibex_pkg::CPU_PWRMGR_DEFAULT; wakeups_i = pwrmgr_pkg::WAKEUPS_DEFAULT; rstreqs_i = pwrmgr_pkg::RSTREQS_DEFAULT; sw_rst_req_i = prim_mubi_pkg::MuBi4False; diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core index 4534fd5287a52..bd571df415d59 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core @@ -12,6 +12,7 @@ filesets: depend: - lowrisc:opentitan:top_darjeeling_pwrmgr_pkg:0.1 - lowrisc:opentitan:top_darjeeling_pwrmgr_reg:0.1 + - lowrisc:ip:rv_core_ibex_pkg - lowrisc:ip:pwrmgr_component file_type: systemVerilogSource diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr.sv index 72a68f6fb3977..a2629dfbb4885 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr.sv +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr.sv @@ -56,7 +56,7 @@ module pwrmgr input pwr_flash_t pwr_flash_i, // processor interface - input pwr_cpu_t pwr_cpu_i, + input rv_core_ibex_pkg::cpu_pwrmgr_t pwr_cpu_i, // SEC_CM: LC_CTRL.INTERSIG.MUBI output lc_ctrl_pkg::lc_tx_t fetch_en_o, input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_pkg.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_pkg.sv index d3b3d6ac115d6..3838bb921a470 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_pkg.sv +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_pkg.sv @@ -145,11 +145,6 @@ package pwrmgr_pkg; flash_idle: 1'b1 }; - // processor to pwrmgr - typedef struct packed { - logic core_sleeping; - } pwr_cpu_t; - // cpu reset requests and status typedef struct packed { logic ndmreset_req; @@ -172,11 +167,6 @@ package pwrmgr_pkg; ndmreset_req: '0 }; - // default value (for dangling ports) - parameter pwr_cpu_t PWR_CPU_DEFAULT = '{ - core_sleeping: 1'b0 - }; - // default value (for dangling ports) parameter int WAKEUPS_DEFAULT = '0; parameter int RSTREQS_DEFAULT = '0; diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv index 27a428a8eafc7..404f42a0f7b61 100644 --- a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv @@ -530,7 +530,7 @@ module top_darjeeling #( logic rv_plic_irq; logic rv_dm_debug_req; rv_core_ibex_pkg::cpu_crash_dump_t rv_core_ibex_crash_dump; - pwrmgr_pkg::pwr_cpu_t rv_core_ibex_pwrmgr; + rv_core_ibex_pkg::cpu_pwrmgr_t rv_core_ibex_pwrmgr; spi_device_pkg::passthrough_req_t spi_device_passthrough_req; spi_device_pkg::passthrough_rsp_t spi_device_passthrough_rsp; logic rv_dm_ndmreset_req; @@ -838,6 +838,7 @@ module top_darjeeling #( assign lpg_cg_en[18] = clkmgr_aon_cg_en.main_otbn; assign lpg_rst_en[18] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; + // tie-off unused connections //VCS coverage off // pragma coverage off diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 3214a1554308d..d8b9824cc9689 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -3276,8 +3276,8 @@ } { name: pwr_cpu - struct: pwr_cpu - package: pwrmgr_pkg + struct: cpu_pwrmgr + package: rv_core_ibex_pkg type: uni act: rcv width: 1 @@ -8769,8 +8769,8 @@ } { name: pwrmgr - struct: pwr_cpu - package: pwrmgr_pkg + struct: cpu_pwrmgr + package: rv_core_ibex_pkg type: uni act: req width: 1 @@ -18532,8 +18532,8 @@ } { name: pwr_cpu - struct: pwr_cpu - package: pwrmgr_pkg + struct: cpu_pwrmgr + package: rv_core_ibex_pkg type: uni act: rcv width: 1 @@ -21421,8 +21421,8 @@ } { name: pwrmgr - struct: pwr_cpu - package: pwrmgr_pkg + struct: cpu_pwrmgr + package: rv_core_ibex_pkg type: uni act: req width: 1 @@ -23960,15 +23960,15 @@ default: rv_core_ibex_pkg::CPU_CRASH_DUMP_DEFAULT } { - package: pwrmgr_pkg - struct: pwr_cpu + package: rv_core_ibex_pkg + struct: cpu_pwrmgr signame: rv_core_ibex_pwrmgr width: 1 type: uni end_idx: -1 act: req suffix: "" - default: pwrmgr_pkg::PWR_CPU_DEFAULT + default: rv_core_ibex_pkg::CPU_PWRMGR_DEFAULT } { package: spi_device_pkg diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/data/pwrmgr.hjson b/hw/top_earlgrey/ip_autogen/pwrmgr/data/pwrmgr.hjson index 36ff6a791196a..75547969f21e4 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/data/pwrmgr.hjson +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/data/pwrmgr.hjson @@ -217,11 +217,11 @@ package: "prim_esc_pkg", }, - { struct: "pwr_cpu", + { struct: "cpu_pwrmgr", type: "uni", name: "pwr_cpu", act: "rcv", - package: "pwrmgr_pkg", + package: "rv_core_ibex_pkg", }, { struct: "logic", diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/doc/interfaces.md b/hw/top_earlgrey/ip_autogen/pwrmgr/doc/interfaces.md index e4b8fae8150a0..e833d6f10f46a 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/doc/interfaces.md +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/doc/interfaces.md @@ -10,28 +10,28 @@ Referring to the [Comportable guideline for peripheral device functionality](htt ## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) -| Port Name | Package::Struct | Type | Act | Width | Description | -|:---------------|:--------------------------|:--------|:------|--------:|:--------------| -| pwr_ast | pwrmgr_pkg::pwr_ast | req_rsp | req | 1 | | -| pwr_rst | pwrmgr_pkg::pwr_rst | req_rsp | req | 1 | | -| pwr_clk | pwrmgr_pkg::pwr_clk | req_rsp | req | 1 | | -| pwr_otp | pwrmgr_pkg::pwr_otp | req_rsp | req | 1 | | -| pwr_lc | pwrmgr_pkg::pwr_lc | req_rsp | req | 1 | | -| pwr_flash | pwrmgr_pkg::pwr_flash | uni | rcv | 1 | | -| esc_rst_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | | -| esc_rst_rx | prim_esc_pkg::esc_rx | uni | req | 1 | | -| pwr_cpu | pwrmgr_pkg::pwr_cpu | uni | rcv | 1 | | -| wakeups | logic | uni | rcv | 6 | | -| rstreqs | logic | uni | rcv | 2 | | -| ndmreset_req | logic | uni | rcv | 1 | | -| strap | logic | uni | req | 1 | | -| low_power | logic | uni | req | 1 | | -| rom_ctrl | rom_ctrl_pkg::pwrmgr_data | uni | rcv | 1 | | -| fetch_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | | -| lc_dft_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| sw_rst_req | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | -| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | +| Port Name | Package::Struct | Type | Act | Width | Description | +|:---------------|:-----------------------------|:--------|:------|--------:|:--------------| +| pwr_ast | pwrmgr_pkg::pwr_ast | req_rsp | req | 1 | | +| pwr_rst | pwrmgr_pkg::pwr_rst | req_rsp | req | 1 | | +| pwr_clk | pwrmgr_pkg::pwr_clk | req_rsp | req | 1 | | +| pwr_otp | pwrmgr_pkg::pwr_otp | req_rsp | req | 1 | | +| pwr_lc | pwrmgr_pkg::pwr_lc | req_rsp | req | 1 | | +| pwr_flash | pwrmgr_pkg::pwr_flash | uni | rcv | 1 | | +| esc_rst_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | | +| esc_rst_rx | prim_esc_pkg::esc_rx | uni | req | 1 | | +| pwr_cpu | rv_core_ibex_pkg::cpu_pwrmgr | uni | rcv | 1 | | +| wakeups | logic | uni | rcv | 6 | | +| rstreqs | logic | uni | rcv | 2 | | +| ndmreset_req | logic | uni | rcv | 1 | | +| strap | logic | uni | req | 1 | | +| low_power | logic | uni | req | 1 | | +| rom_ctrl | rom_ctrl_pkg::pwrmgr_data | uni | rcv | 1 | | +| fetch_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | | +| lc_dft_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| sw_rst_req | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | +| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | ## Interrupts diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv index 101e78e81f5a1..ed590d1345df9 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv @@ -36,7 +36,7 @@ interface pwrmgr_if ( pwrmgr_pkg::pwr_flash_t pwr_flash; pwrmgr_pkg::pwrmgr_cpu_t cpu_i; - pwrmgr_pkg::pwr_cpu_t pwr_cpu; + rv_core_ibex_pkg::cpu_pwrmgr_t pwr_cpu; lc_ctrl_pkg::lc_tx_t fetch_en; lc_ctrl_pkg::lc_tx_t lc_hw_debug_en; @@ -192,7 +192,7 @@ interface pwrmgr_if ( pwr_otp_rsp = '{default: '0}; pwr_lc_rsp = '{default: '0}; pwr_flash = '{default: '0}; - pwr_cpu = pwrmgr_pkg::PWR_CPU_DEFAULT; + pwr_cpu = rv_core_ibex_pkg::CPU_PWRMGR_DEFAULT; wakeups_i = pwrmgr_pkg::WAKEUPS_DEFAULT; rstreqs_i = pwrmgr_pkg::RSTREQS_DEFAULT; sw_rst_req_i = prim_mubi_pkg::MuBi4False; diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core index cc29a53d783e6..e02527dbc422d 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core @@ -12,6 +12,7 @@ filesets: depend: - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1 - lowrisc:opentitan:top_earlgrey_pwrmgr_reg:0.1 + - lowrisc:ip:rv_core_ibex_pkg - lowrisc:ip:pwrmgr_component file_type: systemVerilogSource diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/rtl/pwrmgr.sv b/hw/top_earlgrey/ip_autogen/pwrmgr/rtl/pwrmgr.sv index 907c732feccc0..5adc250a037d1 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/rtl/pwrmgr.sv +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/rtl/pwrmgr.sv @@ -56,7 +56,7 @@ module pwrmgr input pwr_flash_t pwr_flash_i, // processor interface - input pwr_cpu_t pwr_cpu_i, + input rv_core_ibex_pkg::cpu_pwrmgr_t pwr_cpu_i, // SEC_CM: LC_CTRL.INTERSIG.MUBI output lc_ctrl_pkg::lc_tx_t fetch_en_o, input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/rtl/pwrmgr_pkg.sv b/hw/top_earlgrey/ip_autogen/pwrmgr/rtl/pwrmgr_pkg.sv index e52f79aee3de9..795060b1a5394 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/rtl/pwrmgr_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/rtl/pwrmgr_pkg.sv @@ -145,11 +145,6 @@ package pwrmgr_pkg; flash_idle: 1'b1 }; - // processor to pwrmgr - typedef struct packed { - logic core_sleeping; - } pwr_cpu_t; - // cpu reset requests and status typedef struct packed { logic ndmreset_req; @@ -162,11 +157,6 @@ package pwrmgr_pkg; ndmreset_req: '0 }; - // default value (for dangling ports) - parameter pwr_cpu_t PWR_CPU_DEFAULT = '{ - core_sleeping: 1'b0 - }; - // default value (for dangling ports) parameter int WAKEUPS_DEFAULT = '0; parameter int RSTREQS_DEFAULT = '0; diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 352a180c34b8e..265dd999a92e6 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -641,7 +641,7 @@ module top_earlgrey #( logic rv_plic_irq; logic rv_dm_debug_req; rv_core_ibex_pkg::cpu_crash_dump_t rv_core_ibex_crash_dump; - pwrmgr_pkg::pwr_cpu_t rv_core_ibex_pwrmgr; + rv_core_ibex_pkg::cpu_pwrmgr_t rv_core_ibex_pwrmgr; spi_device_pkg::passthrough_req_t spi_device_passthrough_req; spi_device_pkg::passthrough_rsp_t spi_device_passthrough_rsp; logic rv_dm_ndmreset_req;