From 0bbd2f4f66b909acd7ff313fec913af32b942a29 Mon Sep 17 00:00:00 2001 From: Amaury Pouly Date: Wed, 4 Dec 2024 15:35:46 +0100 Subject: [PATCH] [topgen] Add class to load a complete topcfg properly At the moment, topgen simplies serialized the complete topcfg using hjson.dumps() but this poses a few problems. The biggest one is that it is a mix of manual conversion to dict (when calling as_dict() in the various topgen functions) and automatic (when calling _asdict() from hjson.dumps). Furthermore, it turns out that we are missing some fields that probably were never added to _asdict(). This commit introduces a new class (CompleteTopCfg) whose sole purpose is to take the produced Hjson and reconstruct an in-memory topcfg that is *exactly* equivalent (in Pythonic types) to the ones that was dumped. This requires to sometimes reconstruct some classes, sometimes not. Classes that need to be reconstruct get a new method (fromdict) and the CompleteTopCfg does as much automatic deserializing as possible, then some manual fixing. There is also a small tweak to how clock groups are handled: in alert_lpgs, the clock groups are all elements of the clocks.groups but because of the naive serializing, a full copy is made. This commit introduces GroupProxy that behaves like a Group for all purposes but serializes only to the group name. This makes the resulting hjson clearer and the deserialization easier. Since this process is quite fragile, when topgen is running it will actually check that this works by dumping the Hjson, reloading it with the CompleteTopCfg and then checking that the two are equivalent. Signed-off-by: Amaury Pouly --- .../data/autogen/top_earlgrey.gen.hjson | 1170 +++++++++++++---- util/reggen/inter_signal.py | 13 + util/reggen/params.py | 37 + util/topgen.py | 24 +- util/topgen/clocks.py | 84 +- util/topgen/merge.py | 9 +- util/topgen/resets.py | 30 +- util/topgen/topcfg.py | 145 ++ util/topgen/validate.py | 16 + 9 files changed, 1241 insertions(+), 287 deletions(-) create mode 100644 util/topgen/topcfg.py diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index c4bb2ff3287714..166b1ae86065a0 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -196,6 +196,9 @@ shadowed: false sw: false path: rstmgr_aon_resets.rst_por_aon_n + shadow_path: rstmgr_aon_resets.rst_por_aon_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.por_aon_shadowed + lpg_path: rstmgr_aon_rst_en.por_aon clock: aon } { @@ -206,6 +209,7 @@ shadowed: false sw: false path: "" + shadow_path: "" clock: io_div4 } { @@ -216,6 +220,7 @@ shadowed: false sw: false path: "" + shadow_path: "" clock: io_div4 } { @@ -229,6 +234,9 @@ shadowed: false sw: false path: rstmgr_aon_resets.rst_por_n + shadow_path: rstmgr_aon_resets.rst_por_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.por_shadowed + lpg_path: rstmgr_aon_rst_en.por parent: por_aon clock: main } @@ -243,6 +251,9 @@ shadowed: false sw: false path: rstmgr_aon_resets.rst_por_io_n + shadow_path: rstmgr_aon_resets.rst_por_io_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.por_io_shadowed + lpg_path: rstmgr_aon_rst_en.por_io parent: por_aon clock: io } @@ -257,6 +268,9 @@ shadowed: false sw: false path: rstmgr_aon_resets.rst_por_io_div2_n + shadow_path: rstmgr_aon_resets.rst_por_io_div2_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.por_io_div2_shadowed + lpg_path: rstmgr_aon_rst_en.por_io_div2 parent: por_aon clock: io_div2 } @@ -271,6 +285,9 @@ shadowed: false sw: false path: rstmgr_aon_resets.rst_por_io_div4_n + shadow_path: rstmgr_aon_resets.rst_por_io_div4_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.por_io_div4_shadowed + lpg_path: rstmgr_aon_rst_en.por_io_div4 parent: por_aon clock: io_div4 } @@ -285,6 +302,9 @@ shadowed: false sw: false path: rstmgr_aon_resets.rst_por_usb_n + shadow_path: rstmgr_aon_resets.rst_por_usb_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.por_usb_shadowed + lpg_path: rstmgr_aon_rst_en.por_usb parent: por_aon clock: usb } @@ -300,6 +320,9 @@ shadowed: true sw: false path: rstmgr_aon_resets.rst_lc_n + shadow_path: rstmgr_aon_resets.rst_lc_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.lc_shadowed + lpg_path: rstmgr_aon_rst_en.lc parent: lc_src clock: main } @@ -314,6 +337,9 @@ shadowed: false sw: false path: rstmgr_aon_resets.rst_lc_aon_n + shadow_path: rstmgr_aon_resets.rst_lc_aon_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.lc_aon_shadowed + lpg_path: rstmgr_aon_rst_en.lc_aon parent: lc_src clock: aon } @@ -329,6 +355,9 @@ shadowed: false sw: false path: rstmgr_aon_resets.rst_lc_io_n + shadow_path: rstmgr_aon_resets.rst_lc_io_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.lc_io_shadowed + lpg_path: rstmgr_aon_rst_en.lc_io parent: lc_src clock: io } @@ -344,6 +373,9 @@ shadowed: false sw: false path: rstmgr_aon_resets.rst_lc_io_div2_n + shadow_path: rstmgr_aon_resets.rst_lc_io_div2_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.lc_io_div2_shadowed + lpg_path: rstmgr_aon_rst_en.lc_io_div2 parent: lc_src clock: io_div2 } @@ -359,6 +391,9 @@ shadowed: true sw: false path: rstmgr_aon_resets.rst_lc_io_div4_n + shadow_path: rstmgr_aon_resets.rst_lc_io_div4_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.lc_io_div4_shadowed + lpg_path: rstmgr_aon_rst_en.lc_io_div4 parent: lc_src clock: io_div4 } @@ -374,6 +409,9 @@ shadowed: false sw: false path: rstmgr_aon_resets.rst_lc_usb_n + shadow_path: rstmgr_aon_resets.rst_lc_usb_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.lc_usb_shadowed + lpg_path: rstmgr_aon_rst_en.lc_usb parent: lc_src clock: usb } @@ -388,6 +426,9 @@ shadowed: false sw: false path: rstmgr_aon_resets.rst_sys_n + shadow_path: rstmgr_aon_resets.rst_sys_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.sys_shadowed + lpg_path: rstmgr_aon_rst_en.sys parent: sys_src clock: main } @@ -402,6 +443,9 @@ shadowed: false sw: false path: rstmgr_aon_resets.rst_sys_io_div4_n + shadow_path: rstmgr_aon_resets.rst_sys_io_div4_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.sys_io_div4_shadowed + lpg_path: rstmgr_aon_rst_en.sys_io_div4 parent: sys_src clock: io_div4 } @@ -416,6 +460,9 @@ shadowed: false sw: true path: rstmgr_aon_resets.rst_spi_device_n + shadow_path: rstmgr_aon_resets.rst_spi_device_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.spi_device_shadowed + lpg_path: rstmgr_aon_rst_en.spi_device parent: lc_src clock: io_div4 } @@ -430,6 +477,9 @@ shadowed: false sw: true path: rstmgr_aon_resets.rst_spi_host0_n + shadow_path: rstmgr_aon_resets.rst_spi_host0_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.spi_host0_shadowed + lpg_path: rstmgr_aon_rst_en.spi_host0 parent: lc_src clock: io } @@ -444,6 +494,9 @@ shadowed: false sw: true path: rstmgr_aon_resets.rst_spi_host1_n + shadow_path: rstmgr_aon_resets.rst_spi_host1_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.spi_host1_shadowed + lpg_path: rstmgr_aon_rst_en.spi_host1 parent: lc_src clock: io_div2 } @@ -458,6 +511,9 @@ shadowed: false sw: true path: rstmgr_aon_resets.rst_usb_n + shadow_path: rstmgr_aon_resets.rst_usb_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.usb_shadowed + lpg_path: rstmgr_aon_rst_en.usb parent: lc_src clock: usb } @@ -472,6 +528,9 @@ shadowed: false sw: true path: rstmgr_aon_resets.rst_usb_aon_n + shadow_path: rstmgr_aon_resets.rst_usb_aon_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.usb_aon_shadowed + lpg_path: rstmgr_aon_rst_en.usb_aon parent: lc_src clock: aon } @@ -486,6 +545,9 @@ shadowed: false sw: true path: rstmgr_aon_resets.rst_i2c0_n + shadow_path: rstmgr_aon_resets.rst_i2c0_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.i2c0_shadowed + lpg_path: rstmgr_aon_rst_en.i2c0 parent: lc_src clock: io_div4 } @@ -500,6 +562,9 @@ shadowed: false sw: true path: rstmgr_aon_resets.rst_i2c1_n + shadow_path: rstmgr_aon_resets.rst_i2c1_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.i2c1_shadowed + lpg_path: rstmgr_aon_rst_en.i2c1 parent: lc_src clock: io_div4 } @@ -514,6 +579,9 @@ shadowed: false sw: true path: rstmgr_aon_resets.rst_i2c2_n + shadow_path: rstmgr_aon_resets.rst_i2c2_shadowed_n + shadow_lpg_path: rstmgr_aon_rst_en.i2c2_shadowed + lpg_path: rstmgr_aon_rst_en.i2c2 parent: lc_src clock: io_div4 } @@ -626,6 +694,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: uart0 index: -1 } @@ -636,6 +705,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: uart0 default: "" end_idx: -1 @@ -691,6 +761,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: uart1 index: -1 } @@ -701,6 +772,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: uart1 default: "" end_idx: -1 @@ -756,6 +828,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: uart2 index: -1 } @@ -766,6 +839,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: uart2 default: "" end_idx: -1 @@ -821,6 +895,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: uart3 index: -1 } @@ -831,6 +906,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: uart3 default: "" end_idx: -1 @@ -908,6 +984,7 @@ act: rcv width: 1 default: 1'b0 + class: InterSignal inst_name: gpio index: -1 } @@ -920,6 +997,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: gpio index: -1 } @@ -930,6 +1008,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: gpio default: "" end_idx: -1 @@ -995,6 +1074,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: spi_device default: "" top_signame: ast_spi_ram_2p_cfg @@ -1007,6 +1087,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: spi_device default: "" end_idx: -1 @@ -1019,6 +1100,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: spi_device index: -1 } @@ -1028,6 +1110,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: spi_device default: "" package: "" @@ -1043,6 +1126,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: spi_device default: "" end_idx: -1 @@ -1110,6 +1194,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: i2c0 default: "" top_signame: ast_ram_1p_cfg @@ -1126,6 +1211,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: i2c0 index: -1 } @@ -1136,6 +1222,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: i2c0 default: "" end_idx: -1 @@ -1203,6 +1290,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: i2c1 default: "" top_signame: ast_ram_1p_cfg @@ -1219,6 +1307,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: i2c1 index: -1 } @@ -1229,6 +1318,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: i2c1 default: "" end_idx: -1 @@ -1296,6 +1386,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: i2c2 default: "" top_signame: ast_ram_1p_cfg @@ -1312,6 +1403,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: i2c2 index: -1 } @@ -1322,6 +1414,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: i2c2 default: "" end_idx: -1 @@ -1373,6 +1466,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: pattgen default: "" end_idx: -1 @@ -1424,6 +1518,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rv_timer default: "" end_idx: -1 @@ -1535,6 +1630,7 @@ act: none width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl package: "" external: true @@ -1551,6 +1647,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl external: true top_signame: otp_ctrl_otp_ast_pwr_seq @@ -1566,6 +1663,7 @@ act: rcv width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl external: true top_signame: otp_ctrl_otp_ast_pwr_seq_h @@ -1580,6 +1678,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: otp_ctrl default: "" top_signame: edn0_edn @@ -1594,6 +1693,7 @@ act: rsp width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl top_signame: pwrmgr_aon_pwr_otp index: -1 @@ -1607,6 +1707,7 @@ act: rsp width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl top_signame: lc_ctrl_lc_otp_vendor_test index: -1 @@ -1620,6 +1721,7 @@ act: rsp width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl top_signame: lc_ctrl_lc_otp_program index: -1 @@ -1637,6 +1739,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl end_idx: -1 top_type: broadcast @@ -1656,6 +1759,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otp_ctrl top_signame: lc_ctrl_lc_escalate_en index: -1 @@ -1673,6 +1777,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otp_ctrl top_signame: lc_ctrl_lc_creator_seed_sw_rw_en index: -1 @@ -1690,6 +1795,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otp_ctrl index: -1 } @@ -1706,6 +1812,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otp_ctrl top_signame: lc_ctrl_lc_seed_hw_rd_en index: -1 @@ -1723,6 +1830,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otp_ctrl top_signame: lc_ctrl_lc_dft_en index: -1 @@ -1740,6 +1848,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otp_ctrl top_signame: lc_ctrl_lc_check_byp_en index: -1 @@ -1753,6 +1862,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl end_idx: -1 top_type: broadcast @@ -1768,6 +1878,7 @@ act: rsp width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl top_signame: flash_ctrl_otp index: -1 @@ -1781,6 +1892,7 @@ act: rsp width: 4 default: "'0" + class: InterSignal inst_name: otp_ctrl end_idx: 3 top_type: partial-one-to-N @@ -1796,6 +1908,7 @@ act: rsp width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl end_idx: -1 top_signame: otp_ctrl_otbn_otp_key @@ -1810,6 +1923,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl top_signame: otp_ctrl_otp_broadcast index: -1 @@ -1822,6 +1936,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: otp_ctrl default: "" top_signame: ast_obs_ctrl @@ -1834,6 +1949,7 @@ type: uni act: req width: 8 + class: InterSignal inst_name: otp_ctrl default: "" package: "" @@ -1849,6 +1965,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: otp_ctrl default: "" end_idx: -1 @@ -1862,6 +1979,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: otp_ctrl default: "" end_idx: -1 @@ -2058,6 +2176,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: lc_ctrl default: "" top_signame: pinmux_aon_lc_jtag @@ -2070,6 +2189,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: lc_ctrl default: "" top_signame: alert_handler_esc_tx @@ -2082,6 +2202,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: lc_ctrl default: "" top_signame: alert_handler_esc_rx @@ -2094,6 +2215,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: lc_ctrl default: "" top_signame: alert_handler_esc_tx @@ -2106,6 +2228,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: lc_ctrl default: "" top_signame: alert_handler_esc_rx @@ -2118,6 +2241,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: lc_ctrl default: "" top_signame: pwrmgr_aon_pwr_lc @@ -2131,6 +2255,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_signame: lc_ctrl_lc_otp_vendor_test @@ -2144,6 +2269,7 @@ act: rcv width: 1 default: otp_ctrl_pkg::OTP_LC_DATA_DEFAULT + class: InterSignal inst_name: lc_ctrl top_signame: otp_ctrl_otp_lc_data index: -1 @@ -2156,6 +2282,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_signame: lc_ctrl_lc_otp_program @@ -2169,6 +2296,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: lc_ctrl top_signame: kmac_app index: 1 @@ -2181,6 +2309,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -2195,6 +2324,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -2209,6 +2339,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -2223,6 +2354,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -2237,6 +2369,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -2251,6 +2384,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -2265,6 +2399,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -2279,6 +2414,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -2293,6 +2429,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -2307,6 +2444,7 @@ act: rcv width: 2 default: lc_ctrl_pkg::On + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: one-to-N @@ -2321,6 +2459,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: lc_ctrl top_signame: flash_ctrl_rma_seed index: -1 @@ -2333,6 +2472,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -2347,6 +2487,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -2361,6 +2502,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -2375,6 +2517,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -2389,6 +2532,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -2403,6 +2547,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -2417,6 +2562,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -2431,6 +2577,7 @@ act: rcv width: 1 default: "'0" + class: InterSignal inst_name: lc_ctrl top_signame: lc_ctrl_otp_device_id index: -1 @@ -2443,6 +2590,7 @@ act: rcv width: 1 default: "'0" + class: InterSignal inst_name: lc_ctrl top_signame: lc_ctrl_otp_manuf_state index: -1 @@ -2455,6 +2603,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: lc_ctrl index: -1 } @@ -2472,6 +2621,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: lc_ctrl package: "" end_idx: -1 @@ -2486,6 +2636,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: lc_ctrl default: "" end_idx: -1 @@ -2499,6 +2650,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: lc_ctrl index: -1 } @@ -2571,6 +2723,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: alert_handler default: "" end_idx: -1 @@ -2585,6 +2738,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: alert_handler default: "" top_signame: edn0_edn @@ -2597,6 +2751,7 @@ type: uni act: rcv width: 4 + class: InterSignal inst_name: alert_handler default: "" end_idx: -1 @@ -2611,6 +2766,7 @@ type: uni act: req width: 4 + class: InterSignal inst_name: alert_handler default: "" end_idx: -1 @@ -2625,6 +2781,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: alert_handler default: "" end_idx: -1 @@ -2676,6 +2833,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: spi_host0 default: "" top_signame: spi_device_passthrough @@ -2692,6 +2850,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: spi_host0 index: -1 } @@ -2702,6 +2861,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: spi_host0 default: "" end_idx: -1 @@ -2753,6 +2913,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: spi_host1 index: -1 } @@ -2767,6 +2928,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: spi_host1 index: -1 } @@ -2777,6 +2939,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: spi_host1 default: "" end_idx: -1 @@ -2859,6 +3022,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -2874,6 +3038,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -2889,6 +3054,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -2904,6 +3070,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -2919,6 +3086,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -2934,6 +3102,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -2949,6 +3118,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -2964,6 +3134,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -2979,6 +3150,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -2994,6 +3166,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -3009,6 +3182,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -3024,6 +3198,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -3039,6 +3214,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -3054,6 +3230,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -3069,6 +3246,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -3082,6 +3260,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: usbdev default: "" top_signame: ast_usb_ram_1p_cfg @@ -3094,6 +3273,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: usbdev default: "" end_idx: -1 @@ -3177,6 +3357,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" external: true @@ -3191,6 +3372,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" end_idx: -1 @@ -3204,6 +3386,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" end_idx: -1 @@ -3217,6 +3400,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" end_idx: -1 @@ -3230,6 +3414,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" end_idx: -1 @@ -3243,6 +3428,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" end_idx: -1 @@ -3257,6 +3443,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" top_signame: alert_handler_esc_tx @@ -3269,6 +3456,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" top_signame: alert_handler_esc_rx @@ -3281,6 +3469,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" top_signame: rv_core_ibex_pwrmgr @@ -3292,6 +3481,7 @@ type: uni act: rcv width: 6 + class: InterSignal inst_name: pwrmgr_aon default: "" package: "" @@ -3306,6 +3496,7 @@ type: uni act: rcv width: 2 + class: InterSignal inst_name: pwrmgr_aon default: "" package: "" @@ -3320,6 +3511,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" package: "" @@ -3332,6 +3524,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" package: "" @@ -3346,6 +3539,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" package: "" @@ -3362,6 +3556,7 @@ act: rcv width: 1 default: rom_ctrl_pkg::PWRMGR_DATA_DEFAULT + class: InterSignal inst_name: pwrmgr_aon top_signame: rom_ctrl_pwrmgr_data index: -1 @@ -3373,6 +3568,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" end_idx: -1 @@ -3387,6 +3583,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" top_signame: lc_ctrl_lc_dft_en @@ -3399,6 +3596,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" top_signame: lc_ctrl_lc_hw_debug_en @@ -3411,6 +3609,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" top_signame: rstmgr_aon_sw_rst_req @@ -3423,6 +3622,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" end_idx: -1 @@ -3528,6 +3728,7 @@ type: uni act: rcv width: 2 + class: InterSignal inst_name: rstmgr_aon default: "" package: "" @@ -3547,6 +3748,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rstmgr_aon default: "" package: pwrmgr_pkg @@ -3561,6 +3763,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rstmgr_aon default: "" top_signame: rstmgr_aon_resets @@ -3574,6 +3777,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rstmgr_aon default: "" top_signame: rstmgr_aon_rst_en @@ -3587,6 +3791,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rstmgr_aon default: "" top_signame: alert_handler_crashdump @@ -3600,6 +3805,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rstmgr_aon default: "" top_signame: rv_core_ibex_crash_dump @@ -3613,6 +3819,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rstmgr_aon default: "" end_idx: -1 @@ -3627,6 +3834,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rstmgr_aon default: "" end_idx: -1 @@ -3763,6 +3971,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" top_signame: clkmgr_aon_clocks @@ -3775,6 +3984,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" top_signame: clkmgr_aon_cg_en @@ -3787,6 +3997,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" top_signame: lc_ctrl_lc_hw_debug_en @@ -3799,6 +4010,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" external: true @@ -3813,6 +4025,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" external: true @@ -3827,6 +4040,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" external: true @@ -3841,6 +4055,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" external: true @@ -3855,6 +4070,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" external: true @@ -3869,6 +4085,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" external: true @@ -3883,6 +4100,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" top_signame: lc_ctrl_lc_clk_byp_req @@ -3895,6 +4113,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" top_signame: lc_ctrl_lc_clk_byp_ack @@ -3907,6 +4126,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" external: true @@ -3920,6 +4140,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" package: pwrmgr_pkg @@ -3933,6 +4154,7 @@ type: uni act: rcv width: 4 + class: InterSignal inst_name: clkmgr_aon default: "" end_idx: -1 @@ -3949,6 +4171,7 @@ act: rcv width: 1 default: prim_mubi_pkg::MuBi4True + class: InterSignal inst_name: clkmgr_aon external: true top_signame: calib_rdy @@ -3962,6 +4185,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" end_idx: -1 @@ -4019,6 +4243,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: sysrst_ctrl_aon default: "" package: "" @@ -4031,6 +4256,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: sysrst_ctrl_aon default: "" package: "" @@ -4044,6 +4270,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: sysrst_ctrl_aon default: "" end_idx: -1 @@ -4102,6 +4329,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: adc_ctrl_aon default: "" external: true @@ -4115,6 +4343,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: adc_ctrl_aon default: "" package: "" @@ -4128,6 +4357,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: adc_ctrl_aon default: "" end_idx: -1 @@ -4186,6 +4416,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: pwm_aon default: "" end_idx: -1 @@ -4284,6 +4515,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: pinmux_aon top_signame: lc_ctrl_lc_hw_debug_en index: -1 @@ -4297,6 +4529,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: pinmux_aon top_signame: lc_ctrl_lc_dft_en index: -1 @@ -4314,6 +4547,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: pinmux_aon top_signame: lc_ctrl_lc_escalate_en index: -1 @@ -4334,6 +4568,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: pinmux_aon top_signame: lc_ctrl_lc_check_byp_en index: -1 @@ -4351,6 +4586,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: pinmux_aon end_idx: -1 top_type: broadcast @@ -4365,6 +4601,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: pinmux_aon default: "" end_idx: -1 @@ -4379,6 +4616,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: pinmux_aon default: "" end_idx: -1 @@ -4393,6 +4631,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: pinmux_aon default: "" top_signame: pinmux_aon_dft_jtag @@ -4407,6 +4646,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: pinmux_aon external: true top_signame: dft_strap_test @@ -4421,6 +4661,7 @@ act: rcv width: 1 default: "'0" + class: InterSignal inst_name: pinmux_aon package: "" external: true @@ -4436,6 +4677,7 @@ act: rcv width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" top_signame: pwrmgr_aon_low_power @@ -4449,6 +4691,7 @@ act: rcv width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" top_signame: pwrmgr_aon_strap @@ -4468,6 +4711,7 @@ act: rcv width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" top_signame: lc_ctrl_strap_en_override @@ -4481,6 +4725,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" top_signame: pwrmgr_aon_wakeups @@ -4493,6 +4738,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pinmux_aon default: "" package: "" @@ -4506,6 +4752,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pinmux_aon default: "" package: "" @@ -4520,6 +4767,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" external: true @@ -4535,6 +4783,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" external: true @@ -4550,6 +4799,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" top_signame: pwrmgr_aon_wakeups @@ -4562,6 +4812,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pinmux_aon default: "" package: "" @@ -4575,6 +4826,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pinmux_aon default: "" package: "" @@ -4589,6 +4841,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" top_signame: usbdev_usb_aon_bus_not_idle @@ -4602,6 +4855,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" top_signame: usbdev_usb_aon_bus_reset @@ -4615,6 +4869,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" top_signame: usbdev_usb_aon_sense_lost @@ -4628,6 +4883,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" end_idx: -1 @@ -4642,6 +4898,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: pinmux_aon default: "" end_idx: -1 @@ -4700,6 +4957,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: aon_timer_aon package: "" end_idx: -1 @@ -4714,6 +4972,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: aon_timer_aon package: "" top_signame: pwrmgr_aon_wakeups @@ -4726,6 +4985,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: aon_timer_aon package: "" top_signame: pwrmgr_aon_rstreqs @@ -4739,6 +4999,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: aon_timer_aon top_signame: lc_ctrl_lc_escalate_en index: -1 @@ -4749,6 +5010,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: aon_timer_aon default: "" package: "" @@ -4762,6 +5024,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: aon_timer_aon default: "" end_idx: -1 @@ -4874,6 +5137,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: ast index: -1 } @@ -4930,6 +5194,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: sensor_ctrl_aon default: "" external: true @@ -4944,6 +5209,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: sensor_ctrl_aon default: "" external: true @@ -4959,6 +5225,7 @@ act: rcv width: 1 default: prim_mubi_pkg::MuBi4True + class: InterSignal inst_name: sensor_ctrl_aon external: true top_signame: ast_init_done @@ -4971,6 +5238,7 @@ type: uni act: rcv width: 9 + class: InterSignal inst_name: sensor_ctrl_aon default: "" package: "" @@ -4985,6 +5253,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: sensor_ctrl_aon default: "" package: "" @@ -4999,6 +5268,7 @@ act: req width: 4 default: "'0" + class: InterSignal inst_name: sensor_ctrl_aon external: true top_signame: sensor_ctrl_manual_pad_attr @@ -5012,6 +5282,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: sensor_ctrl_aon default: "" end_idx: -1 @@ -5163,6 +5434,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: sram_ctrl_ret_aon default: "" top_signame: otp_ctrl_sram_otp_key @@ -5176,6 +5448,7 @@ act: rcv width: 1 default: "'0" + class: InterSignal inst_name: sram_ctrl_ret_aon top_signame: ast_ram_1p_cfg index: -1 @@ -5188,6 +5461,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: sram_ctrl_ret_aon top_signame: lc_ctrl_lc_escalate_en index: -1 @@ -5200,6 +5474,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: sram_ctrl_ret_aon index: -1 } @@ -5211,6 +5486,7 @@ act: rcv width: 1 default: prim_mubi_pkg::MuBi8False + class: InterSignal inst_name: sram_ctrl_ret_aon index: -1 } @@ -5221,6 +5497,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: sram_ctrl_ret_aon default: "" end_idx: -1 @@ -5234,6 +5511,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: sram_ctrl_ret_aon default: "" end_idx: -1 @@ -5295,12 +5573,22 @@ byte_write: False config: { + class: Flash banks: 2 pages_per_bank: 256 program_resolution: 8 pgm_resolution_bytes: 64 bytes_per_page: 2048 bytes_per_bank: 524288 + data_width: 64 + metadata_width: 12 + info_types: 3 + infos_per_bank: + [ + 10 + 1 + 2 + ] size: 0x100000 } size: 0x100000 @@ -5405,6 +5693,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: flash_ctrl default: "" end_idx: -1 @@ -5418,6 +5707,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_nvm_debug_en @@ -5430,6 +5720,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" external: true @@ -5443,6 +5734,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" package: "" @@ -5457,6 +5749,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" package: "" @@ -5471,6 +5764,7 @@ type: io act: none width: 2 + class: InterSignal inst_name: flash_ctrl default: "" package: "" @@ -5485,6 +5779,7 @@ type: io act: none width: 1 + class: InterSignal inst_name: flash_ctrl default: "" package: "" @@ -5500,6 +5795,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_creator_seed_sw_rw_en @@ -5512,6 +5808,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_owner_seed_sw_rw_en @@ -5524,6 +5821,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_iso_part_sw_rd_en @@ -5536,6 +5834,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_iso_part_sw_wr_en @@ -5548,6 +5847,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_seed_hw_rd_en @@ -5560,6 +5860,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_escalate_en @@ -5572,6 +5873,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_flash_rma_req @@ -5584,6 +5886,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_flash_rma_ack @@ -5596,6 +5899,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" end_idx: -1 @@ -5610,6 +5914,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: pwrmgr_aon_pwr_flash @@ -5622,6 +5927,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: flash_ctrl default: "" end_idx: -1 @@ -5636,6 +5942,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: ast_obs_ctrl @@ -5647,6 +5954,7 @@ type: uni act: req width: 8 + class: InterSignal inst_name: flash_ctrl default: "" package: "" @@ -5662,6 +5970,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: flash_ctrl default: "" end_idx: -1 @@ -5675,6 +5984,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: flash_ctrl default: "" end_idx: -1 @@ -5688,6 +5998,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: flash_ctrl default: "" end_idx: -1 @@ -5801,6 +6112,7 @@ act: rcv width: 1 default: "'0" + class: InterSignal inst_name: rv_dm index: -1 } @@ -5812,6 +6124,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rv_dm default: "" top_signame: pinmux_aon_rv_jtag @@ -5830,6 +6143,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: rv_dm top_signame: lc_ctrl_lc_hw_debug_en index: -1 @@ -5847,6 +6161,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: rv_dm top_signame: lc_ctrl_lc_dft_en index: -1 @@ -5866,6 +6181,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: rv_dm top_signame: pinmux_aon_pinmux_hw_debug_en index: -1 @@ -5878,6 +6194,7 @@ act: rcv width: 1 default: prim_mubi_pkg::MuBi8False + class: InterSignal inst_name: rv_dm top_signame: rv_dm_otp_dis_rv_dm_late_debug index: -1 @@ -5894,6 +6211,7 @@ act: rcv width: 1 default: 1'b0 + class: InterSignal inst_name: rv_dm index: -1 } @@ -5904,6 +6222,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_dm default: "" package: "" @@ -5923,6 +6242,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_dm index: -1 } @@ -5933,6 +6253,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_dm default: "" package: "" @@ -5954,6 +6275,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: rv_dm index: -1 } @@ -5973,6 +6295,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: rv_dm index: -1 } @@ -5984,6 +6307,7 @@ act: rcv width: 1 default: 1'b0 + class: InterSignal inst_name: rv_dm index: -1 } @@ -6001,6 +6325,7 @@ act: rcv width: 1 default: 1'b0 + class: InterSignal inst_name: rv_dm index: -1 } @@ -6011,6 +6336,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: rv_dm default: "" top_signame: main_tl_rv_dm__sba @@ -6023,6 +6349,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rv_dm default: "" end_idx: -1 @@ -6036,6 +6363,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rv_dm default: "" end_idx: -1 @@ -6049,6 +6377,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rv_dm index: -1 } @@ -6089,6 +6418,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_plic default: "" package: "" @@ -6103,6 +6433,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_plic index: -1 } @@ -6112,6 +6443,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_plic default: "" package: "" @@ -6127,6 +6459,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rv_plic default: "" end_idx: -1 @@ -6314,6 +6647,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: aes default: "" top_signame: clkmgr_aon_idle @@ -6327,6 +6661,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: aes top_signame: lc_ctrl_lc_escalate_en index: -1 @@ -6338,6 +6673,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: aes default: "" top_signame: edn0_edn @@ -6350,6 +6686,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: aes default: "" top_signame: keymgr_aes_key @@ -6362,6 +6699,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: aes default: "" end_idx: -1 @@ -6413,6 +6751,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: hmac default: "" top_signame: clkmgr_aon_idle @@ -6425,6 +6764,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: hmac default: "" end_idx: -1 @@ -6605,6 +6945,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: kmac default: "" top_signame: keymgr_kmac_key @@ -6620,13 +6961,14 @@ { name: NumAppIntf desc: Number of application interfaces - param_type: int - unpacked_dimensions: null - default: 3 - local: false - expose: true + type: int name_top: KmacNumAppIntf + default: 3 + local: "false" + expose: "true" + class: Parameter } + class: InterSignal inst_name: kmac default: "" end_idx: -1 @@ -6641,6 +6983,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: kmac default: "" top_signame: edn0_edn @@ -6653,6 +6996,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: kmac default: "" top_signame: clkmgr_aon_idle @@ -6664,6 +7008,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: kmac default: "" package: "" @@ -6680,6 +7025,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: kmac top_signame: lc_ctrl_lc_escalate_en index: -1 @@ -6691,6 +7037,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: kmac default: "" end_idx: -1 @@ -6848,6 +7195,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: otbn top_signame: otp_ctrl_otbn_otp_key index: -1 @@ -6859,6 +7207,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: otbn default: "" top_signame: edn1_edn @@ -6871,6 +7220,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: otbn default: "" top_signame: edn0_edn @@ -6883,6 +7233,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: otbn default: "" top_signame: clkmgr_aon_idle @@ -6895,6 +7246,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: otbn default: "" top_signame: ast_ram_1p_cfg @@ -6908,6 +7260,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otbn top_signame: lc_ctrl_lc_escalate_en index: -1 @@ -6920,6 +7273,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otbn top_signame: lc_ctrl_lc_flash_rma_req index: -1 @@ -6932,6 +7286,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otbn top_signame: lc_ctrl_lc_flash_rma_ack index: 1 @@ -6943,6 +7298,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: otbn default: "" top_signame: keymgr_otbn_key @@ -6955,6 +7311,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: otbn default: "" end_idx: -1 @@ -7180,6 +7537,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: keymgr default: "" top_signame: edn0_edn @@ -7192,6 +7550,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: keymgr default: "" end_idx: -1 @@ -7206,6 +7565,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: keymgr default: "" end_idx: -1 @@ -7220,6 +7580,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: keymgr default: "" end_idx: -1 @@ -7234,6 +7595,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: keymgr default: "" top_signame: kmac_app @@ -7246,6 +7608,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: keymgr default: "" top_signame: otp_ctrl_otp_keymgr_key @@ -7258,6 +7621,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: keymgr default: "" top_signame: keymgr_otp_device_id @@ -7270,6 +7634,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: keymgr default: "" top_signame: flash_ctrl_keymgr @@ -7283,6 +7648,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::On + class: InterSignal inst_name: keymgr top_signame: lc_ctrl_lc_keymgr_en index: -1 @@ -7294,6 +7660,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: keymgr default: "" top_signame: lc_ctrl_lc_keymgr_div @@ -7306,6 +7673,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: keymgr default: "" top_signame: rom_ctrl_keymgr_data @@ -7317,6 +7685,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: keymgr default: "" package: "" @@ -7330,6 +7699,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: keymgr default: "" end_idx: -1 @@ -7413,6 +7783,7 @@ type: req_rsp act: rsp width: 2 + class: InterSignal inst_name: csrng default: "" end_idx: -1 @@ -7427,6 +7798,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: csrng default: "" end_idx: -1 @@ -7445,6 +7817,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: csrng default: "" end_idx: -1 @@ -7459,6 +7832,7 @@ act: rcv width: 1 default: prim_mubi_pkg::MuBi8True + class: InterSignal inst_name: csrng top_signame: csrng_otp_en_csrng_sw_app_read index: -1 @@ -7471,6 +7845,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: csrng top_signame: lc_ctrl_lc_hw_debug_en index: -1 @@ -7482,6 +7857,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: csrng default: "" end_idx: -1 @@ -7563,6 +7939,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: entropy_src default: "" top_signame: csrng_entropy_src_hw_if @@ -7582,6 +7959,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: entropy_src default: "" top_signame: csrng_cs_aes_halt @@ -7594,6 +7972,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: entropy_src default: "" external: true @@ -7608,6 +7987,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: entropy_src index: -1 } @@ -7619,6 +7999,7 @@ act: rcv width: 1 default: prim_mubi_pkg::MuBi8True + class: InterSignal inst_name: entropy_src index: -1 } @@ -7630,6 +8011,7 @@ act: rcv width: 1 default: prim_mubi_pkg::MuBi8True + class: InterSignal inst_name: entropy_src index: -1 } @@ -7639,6 +8021,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: entropy_src default: "" package: "" @@ -7654,6 +8037,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: entropy_src default: "" end_idx: -1 @@ -7706,6 +8090,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: edn0 default: "" top_signame: csrng_csrng_cmd @@ -7727,6 +8112,7 @@ act: rsp width: 8 default: "'0" + class: InterSignal inst_name: edn0 end_idx: -1 top_type: one-to-N @@ -7740,6 +8126,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: edn0 default: "" end_idx: -1 @@ -7792,6 +8179,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: edn1 default: "" top_signame: csrng_csrng_cmd @@ -7813,6 +8201,7 @@ act: rsp width: 8 default: "'0" + class: InterSignal inst_name: edn1 end_idx: 1 top_type: partial-one-to-N @@ -7826,6 +8215,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: edn1 default: "" end_idx: -1 @@ -7978,6 +8368,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: sram_ctrl_main default: "" top_signame: otp_ctrl_sram_otp_key @@ -7991,6 +8382,7 @@ act: rcv width: 1 default: "'0" + class: InterSignal inst_name: sram_ctrl_main top_signame: ast_ram_1p_cfg index: -1 @@ -8003,6 +8395,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: sram_ctrl_main top_signame: lc_ctrl_lc_escalate_en index: -1 @@ -8015,6 +8408,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: sram_ctrl_main top_signame: lc_ctrl_lc_hw_debug_en index: -1 @@ -8027,6 +8421,7 @@ act: rcv width: 1 default: prim_mubi_pkg::MuBi8False + class: InterSignal inst_name: sram_ctrl_main top_signame: sram_ctrl_main_otp_en_sram_ifetch index: -1 @@ -8038,6 +8433,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: sram_ctrl_main default: "" end_idx: -1 @@ -8051,6 +8447,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: sram_ctrl_main default: "" end_idx: -1 @@ -8174,6 +8571,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rom_ctrl default: "" top_signame: ast_rom_cfg @@ -8186,6 +8584,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rom_ctrl default: "" end_idx: -1 @@ -8200,6 +8599,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rom_ctrl default: "" end_idx: -1 @@ -8214,6 +8614,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: rom_ctrl default: "" top_signame: kmac_app @@ -8226,6 +8627,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rom_ctrl default: "" end_idx: -1 @@ -8239,6 +8641,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rom_ctrl default: "" end_idx: -1 @@ -8598,6 +9001,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_core_ibex index: -1 } @@ -8608,6 +9012,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: ast_ram_1p_cfg @@ -8619,6 +9024,7 @@ type: uni act: rcv width: 32 + class: InterSignal inst_name: rv_core_ibex default: "" package: "" @@ -8631,6 +9037,7 @@ type: uni act: rcv width: 32 + class: InterSignal inst_name: rv_core_ibex default: "" package: "" @@ -8643,6 +9050,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" package: "" @@ -8655,6 +9063,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" package: "" @@ -8667,6 +9076,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" package: "" @@ -8680,6 +9090,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: alert_handler_esc_tx @@ -8692,6 +9103,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: alert_handler_esc_rx @@ -8703,6 +9115,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" package: "" @@ -8716,6 +9129,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" end_idx: -1 @@ -8730,6 +9144,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: lc_ctrl_lc_cpu_en @@ -8742,6 +9157,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: pwrmgr_aon_fetch_en @@ -8754,6 +9170,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" end_idx: -1 @@ -8767,6 +9184,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" package: "" @@ -8780,6 +9198,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: edn0_edn @@ -8792,6 +9211,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: otp_ctrl_sram_otp_key @@ -8803,6 +9223,7 @@ type: uni act: rcv width: 32 + class: InterSignal inst_name: rv_core_ibex default: "" package: "" @@ -8818,6 +9239,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: main_tl_rv_core_ibex__corei @@ -8830,6 +9252,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: main_tl_rv_core_ibex__cored @@ -8842,6 +9265,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" end_idx: -1 @@ -10343,6 +10767,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: main default: "" end_idx: -1 @@ -10356,6 +10781,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: main default: "" end_idx: -1 @@ -10369,6 +10795,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: main default: "" end_idx: -1 @@ -10382,6 +10809,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: rv_dm_regs_tl_d @@ -10394,6 +10822,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: rv_dm_mem_tl_d @@ -10406,6 +10835,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: rom_ctrl_rom_tl @@ -10418,6 +10848,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: rom_ctrl_regs_tl @@ -10430,6 +10861,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" end_idx: -1 @@ -10443,6 +10875,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: spi_host0_tl @@ -10455,6 +10888,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: spi_host1_tl @@ -10467,6 +10901,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: usbdev_tl @@ -10479,6 +10914,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: flash_ctrl_core_tl @@ -10491,6 +10927,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: flash_ctrl_prim_tl @@ -10503,6 +10940,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: flash_ctrl_mem_tl @@ -10515,6 +10953,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: hmac_tl @@ -10527,6 +10966,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: kmac_tl @@ -10539,6 +10979,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: aes_tl @@ -10551,6 +10992,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: entropy_src_tl @@ -10563,6 +11005,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: csrng_tl @@ -10575,6 +11018,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: edn0_tl @@ -10587,6 +11031,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: edn1_tl @@ -10599,6 +11044,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: rv_plic_tl @@ -10611,6 +11057,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: otbn_tl @@ -10623,6 +11070,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: keymgr_tl @@ -10635,6 +11083,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: rv_core_ibex_cfg_tl_d @@ -10647,6 +11096,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: sram_ctrl_main_regs_tl @@ -10659,6 +11109,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: sram_ctrl_main_ram_tl @@ -11321,6 +11772,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: peri default: "" top_signame: main_tl_peri @@ -11333,6 +11785,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: uart0_tl @@ -11345,6 +11798,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: uart1_tl @@ -11357,6 +11811,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: uart2_tl @@ -11369,6 +11824,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: uart3_tl @@ -11381,6 +11837,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: i2c0_tl @@ -11393,6 +11850,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: i2c1_tl @@ -11405,6 +11863,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: i2c2_tl @@ -11417,6 +11876,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: pattgen_tl @@ -11429,6 +11889,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: pwm_aon_tl @@ -11441,6 +11902,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: gpio_tl @@ -11453,6 +11915,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: spi_device_tl @@ -11465,6 +11928,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: rv_timer_tl @@ -11477,6 +11941,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: pwrmgr_aon_tl @@ -11489,6 +11954,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: rstmgr_aon_tl @@ -11501,6 +11967,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: clkmgr_aon_tl @@ -11513,6 +11980,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: pinmux_aon_tl @@ -11525,6 +11993,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: otp_ctrl_core_tl @@ -11537,6 +12006,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: otp_ctrl_prim_tl @@ -11549,6 +12019,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: lc_ctrl_regs_tl @@ -11561,6 +12032,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: sensor_ctrl_aon_tl @@ -11573,6 +12045,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: alert_handler_tl @@ -11585,6 +12058,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: sram_ctrl_ret_aon_regs_tl @@ -11597,6 +12071,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: sram_ctrl_ret_aon_ram_tl @@ -11609,6 +12084,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: aon_timer_aon_tl @@ -11621,6 +12097,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: sysrst_ctrl_aon_tl @@ -11633,6 +12110,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: adc_ctrl_aon_tl @@ -11645,6 +12123,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" external: true @@ -16261,17 +16740,6 @@ clock_group: { name: peri - src: top - sw_cg: yes - unique: no - clocks: - { - clk_io_div4_peri: io_div4 - clk_io_div2_peri: io_div2 - clk_io_peri: io - clk_usb_peri: usb - clk_aon_peri: aon - } } clock_connection: clkmgr_aon_clocks.clk_io_div4_peri unmanaged_clock: false @@ -16286,17 +16754,6 @@ clock_group: { name: peri - src: top - sw_cg: yes - unique: no - clocks: - { - clk_io_div4_peri: io_div4 - clk_io_div2_peri: io_div2 - clk_io_peri: io - clk_usb_peri: usb - clk_aon_peri: aon - } } clock_connection: clkmgr_aon_clocks.clk_io_div4_peri unmanaged_clock: false @@ -16311,17 +16768,6 @@ clock_group: { name: peri - src: top - sw_cg: yes - unique: no - clocks: - { - clk_io_div4_peri: io_div4 - clk_io_div2_peri: io_div2 - clk_io_peri: io - clk_usb_peri: usb - clk_aon_peri: aon - } } clock_connection: clkmgr_aon_clocks.clk_io_div4_peri unmanaged_clock: false @@ -16336,17 +16782,6 @@ clock_group: { name: peri - src: top - sw_cg: yes - unique: no - clocks: - { - clk_io_div4_peri: io_div4 - clk_io_div2_peri: io_div2 - clk_io_peri: io - clk_usb_peri: usb - clk_aon_peri: aon - } } clock_connection: clkmgr_aon_clocks.clk_io_div4_peri unmanaged_clock: false @@ -16361,17 +16796,6 @@ clock_group: { name: peri - src: top - sw_cg: yes - unique: no - clocks: - { - clk_io_div4_peri: io_div4 - clk_io_div2_peri: io_div2 - clk_io_peri: io - clk_usb_peri: usb - clk_aon_peri: aon - } } clock_connection: clkmgr_aon_clocks.clk_io_div4_peri unmanaged_clock: false @@ -16386,14 +16810,6 @@ clock_group: { name: timers - src: top - sw_cg: no - unique: no - clocks: - { - clk_io_div4_timers: io_div4 - clk_aon_timers: aon - } } clock_connection: clkmgr_aon_clocks.clk_io_div4_timers unmanaged_clock: false @@ -16408,15 +16824,6 @@ clock_group: { name: secure - src: top - sw_cg: no - unique: no - clocks: - { - clk_io_div4_secure: io_div4 - clk_main_secure: main - clk_aon_secure: aon - } } clock_connection: clkmgr_aon_clocks.clk_io_div4_secure unmanaged_clock: false @@ -16431,17 +16838,6 @@ clock_group: { name: peri - src: top - sw_cg: yes - unique: no - clocks: - { - clk_io_div4_peri: io_div4 - clk_io_div2_peri: io_div2 - clk_io_peri: io - clk_usb_peri: usb - clk_aon_peri: aon - } } clock_connection: clkmgr_aon_clocks.clk_io_peri unmanaged_clock: false @@ -16456,17 +16852,6 @@ clock_group: { name: peri - src: top - sw_cg: yes - unique: no - clocks: - { - clk_io_div4_peri: io_div4 - clk_io_div2_peri: io_div2 - clk_io_peri: io - clk_usb_peri: usb - clk_aon_peri: aon - } } clock_connection: clkmgr_aon_clocks.clk_io_div2_peri unmanaged_clock: false @@ -16481,17 +16866,6 @@ clock_group: { name: peri - src: top - sw_cg: yes - unique: no - clocks: - { - clk_io_div4_peri: io_div4 - clk_io_div2_peri: io_div2 - clk_io_peri: io - clk_usb_peri: usb - clk_aon_peri: aon - } } clock_connection: clkmgr_aon_clocks.clk_usb_peri unmanaged_clock: false @@ -16506,18 +16880,6 @@ clock_group: { name: powerup - src: top - sw_cg: no - unique: no - clocks: - { - clk_io_div4_powerup: io_div4 - clk_aon_powerup: aon - clk_main_powerup: main - clk_io_powerup: io - clk_usb_powerup: usb - clk_io_div2_powerup: io_div2 - } } clock_connection: clkmgr_aon_clocks.clk_io_div4_powerup unmanaged_clock: false @@ -16532,18 +16894,6 @@ clock_group: { name: powerup - src: top - sw_cg: no - unique: no - clocks: - { - clk_io_div4_powerup: io_div4 - clk_aon_powerup: aon - clk_main_powerup: main - clk_io_powerup: io - clk_usb_powerup: usb - clk_io_div2_powerup: io_div2 - } } clock_connection: clkmgr_aon_clocks.clk_io_div4_powerup unmanaged_clock: false @@ -16558,15 +16908,6 @@ clock_group: { name: secure - src: top - sw_cg: no - unique: no - clocks: - { - clk_io_div4_secure: io_div4 - clk_main_secure: main - clk_aon_secure: aon - } } clock_connection: clkmgr_aon_clocks.clk_io_div4_secure unmanaged_clock: false @@ -16581,17 +16922,6 @@ clock_group: { name: peri - src: top - sw_cg: yes - unique: no - clocks: - { - clk_io_div4_peri: io_div4 - clk_io_div2_peri: io_div2 - clk_io_peri: io - clk_usb_peri: usb - clk_aon_peri: aon - } } clock_connection: clkmgr_aon_clocks.clk_io_div4_peri unmanaged_clock: false @@ -16606,14 +16936,6 @@ clock_group: { name: timers - src: top - sw_cg: no - unique: no - clocks: - { - clk_io_div4_timers: io_div4 - clk_aon_timers: aon - } } clock_connection: clkmgr_aon_clocks.clk_io_div4_timers unmanaged_clock: false @@ -16628,17 +16950,6 @@ clock_group: { name: infra - src: top - sw_cg: no - unique: no - clocks: - { - clk_io_div4_infra: io_div4 - clk_main_infra: main - clk_usb_infra: usb - clk_io_infra: io - clk_io_div2_infra: io_div2 - } } clock_connection: clkmgr_aon_clocks.clk_io_div4_infra unmanaged_clock: false @@ -16653,17 +16964,6 @@ clock_group: { name: infra - src: top - sw_cg: no - unique: no - clocks: - { - clk_io_div4_infra: io_div4 - clk_main_infra: main - clk_usb_infra: usb - clk_io_infra: io - clk_io_div2_infra: io_div2 - } } clock_connection: clkmgr_aon_clocks.clk_io_div4_infra unmanaged_clock: false @@ -16678,17 +16978,6 @@ clock_group: { name: infra - src: top - sw_cg: no - unique: no - clocks: - { - clk_io_div4_infra: io_div4 - clk_main_infra: main - clk_usb_infra: usb - clk_io_infra: io - clk_io_div2_infra: io_div2 - } } clock_connection: clkmgr_aon_clocks.clk_main_infra unmanaged_clock: false @@ -16703,17 +16992,6 @@ clock_group: { name: infra - src: top - sw_cg: no - unique: no - clocks: - { - clk_io_div4_infra: io_div4 - clk_main_infra: main - clk_usb_infra: usb - clk_io_infra: io - clk_io_div2_infra: io_div2 - } } clock_connection: clkmgr_aon_clocks.clk_main_infra unmanaged_clock: false @@ -16728,15 +17006,6 @@ clock_group: { name: secure - src: top - sw_cg: no - unique: no - clocks: - { - clk_io_div4_secure: io_div4 - clk_main_secure: main - clk_aon_secure: aon - } } clock_connection: clkmgr_aon_clocks.clk_main_secure unmanaged_clock: false @@ -16751,16 +17020,6 @@ clock_group: { name: trans - src: top - sw_cg: hint - unique: yes - clocks: - { - clk_main_aes: main - clk_main_hmac: main - clk_main_kmac: main - clk_main_otbn: main - } } clock_connection: clkmgr_aon_clocks.clk_main_aes unmanaged_clock: false @@ -16775,16 +17034,6 @@ clock_group: { name: trans - src: top - sw_cg: hint - unique: yes - clocks: - { - clk_main_aes: main - clk_main_hmac: main - clk_main_kmac: main - clk_main_otbn: main - } } clock_connection: clkmgr_aon_clocks.clk_main_hmac unmanaged_clock: false @@ -16799,16 +17048,6 @@ clock_group: { name: trans - src: top - sw_cg: hint - unique: yes - clocks: - { - clk_main_aes: main - clk_main_hmac: main - clk_main_kmac: main - clk_main_otbn: main - } } clock_connection: clkmgr_aon_clocks.clk_main_kmac unmanaged_clock: false @@ -16823,16 +17062,6 @@ clock_group: { name: trans - src: top - sw_cg: hint - unique: yes - clocks: - { - clk_main_aes: main - clk_main_hmac: main - clk_main_kmac: main - clk_main_otbn: main - } } clock_connection: clkmgr_aon_clocks.clk_main_otbn unmanaged_clock: false @@ -16858,6 +17087,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: uart0 index: -1 } @@ -16868,6 +17098,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: uart0 default: "" end_idx: -1 @@ -16885,6 +17116,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: uart1 index: -1 } @@ -16895,6 +17127,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: uart1 default: "" end_idx: -1 @@ -16912,6 +17145,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: uart2 index: -1 } @@ -16922,6 +17156,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: uart2 default: "" end_idx: -1 @@ -16939,6 +17174,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: uart3 index: -1 } @@ -16949,6 +17185,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: uart3 default: "" end_idx: -1 @@ -16963,6 +17200,7 @@ act: rcv width: 1 default: 1'b0 + class: InterSignal inst_name: gpio index: -1 } @@ -16975,6 +17213,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: gpio index: -1 } @@ -16985,6 +17224,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: gpio default: "" end_idx: -1 @@ -16998,6 +17238,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: spi_device default: "" top_signame: ast_spi_ram_2p_cfg @@ -17010,6 +17251,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: spi_device default: "" end_idx: -1 @@ -17022,6 +17264,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: spi_device index: -1 } @@ -17031,6 +17274,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: spi_device default: "" package: "" @@ -17046,6 +17290,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: spi_device default: "" end_idx: -1 @@ -17059,6 +17304,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: i2c0 default: "" top_signame: ast_ram_1p_cfg @@ -17075,6 +17321,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: i2c0 index: -1 } @@ -17085,6 +17332,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: i2c0 default: "" end_idx: -1 @@ -17098,6 +17346,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: i2c1 default: "" top_signame: ast_ram_1p_cfg @@ -17114,6 +17363,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: i2c1 index: -1 } @@ -17124,6 +17374,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: i2c1 default: "" end_idx: -1 @@ -17137,6 +17388,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: i2c2 default: "" top_signame: ast_ram_1p_cfg @@ -17153,6 +17405,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: i2c2 index: -1 } @@ -17163,6 +17416,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: i2c2 default: "" end_idx: -1 @@ -17176,6 +17430,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: pattgen default: "" end_idx: -1 @@ -17189,6 +17444,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rv_timer default: "" end_idx: -1 @@ -17202,6 +17458,7 @@ act: none width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl package: "" external: true @@ -17218,6 +17475,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl external: true top_signame: otp_ctrl_otp_ast_pwr_seq @@ -17233,6 +17491,7 @@ act: rcv width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl external: true top_signame: otp_ctrl_otp_ast_pwr_seq_h @@ -17247,6 +17506,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: otp_ctrl default: "" top_signame: edn0_edn @@ -17261,6 +17521,7 @@ act: rsp width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl top_signame: pwrmgr_aon_pwr_otp index: -1 @@ -17274,6 +17535,7 @@ act: rsp width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl top_signame: lc_ctrl_lc_otp_vendor_test index: -1 @@ -17287,6 +17549,7 @@ act: rsp width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl top_signame: lc_ctrl_lc_otp_program index: -1 @@ -17304,6 +17567,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl end_idx: -1 top_type: broadcast @@ -17323,6 +17587,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otp_ctrl top_signame: lc_ctrl_lc_escalate_en index: -1 @@ -17340,6 +17605,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otp_ctrl top_signame: lc_ctrl_lc_creator_seed_sw_rw_en index: -1 @@ -17357,6 +17623,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otp_ctrl index: -1 } @@ -17373,6 +17640,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otp_ctrl top_signame: lc_ctrl_lc_seed_hw_rd_en index: -1 @@ -17390,6 +17658,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otp_ctrl top_signame: lc_ctrl_lc_dft_en index: -1 @@ -17407,6 +17676,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otp_ctrl top_signame: lc_ctrl_lc_check_byp_en index: -1 @@ -17420,6 +17690,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl end_idx: -1 top_type: broadcast @@ -17435,6 +17706,7 @@ act: rsp width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl top_signame: flash_ctrl_otp index: -1 @@ -17448,6 +17720,7 @@ act: rsp width: 4 default: "'0" + class: InterSignal inst_name: otp_ctrl end_idx: 3 top_type: partial-one-to-N @@ -17463,6 +17736,7 @@ act: rsp width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl end_idx: -1 top_signame: otp_ctrl_otbn_otp_key @@ -17477,6 +17751,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: otp_ctrl top_signame: otp_ctrl_otp_broadcast index: -1 @@ -17489,6 +17764,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: otp_ctrl default: "" top_signame: ast_obs_ctrl @@ -17501,6 +17777,7 @@ type: uni act: req width: 8 + class: InterSignal inst_name: otp_ctrl default: "" package: "" @@ -17516,6 +17793,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: otp_ctrl default: "" end_idx: -1 @@ -17529,6 +17807,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: otp_ctrl default: "" end_idx: -1 @@ -17542,6 +17821,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: lc_ctrl default: "" top_signame: pinmux_aon_lc_jtag @@ -17554,6 +17834,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: lc_ctrl default: "" top_signame: alert_handler_esc_tx @@ -17566,6 +17847,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: lc_ctrl default: "" top_signame: alert_handler_esc_rx @@ -17578,6 +17860,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: lc_ctrl default: "" top_signame: alert_handler_esc_tx @@ -17590,6 +17873,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: lc_ctrl default: "" top_signame: alert_handler_esc_rx @@ -17602,6 +17886,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: lc_ctrl default: "" top_signame: pwrmgr_aon_pwr_lc @@ -17615,6 +17900,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_signame: lc_ctrl_lc_otp_vendor_test @@ -17628,6 +17914,7 @@ act: rcv width: 1 default: otp_ctrl_pkg::OTP_LC_DATA_DEFAULT + class: InterSignal inst_name: lc_ctrl top_signame: otp_ctrl_otp_lc_data index: -1 @@ -17640,6 +17927,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_signame: lc_ctrl_lc_otp_program @@ -17653,6 +17941,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: lc_ctrl top_signame: kmac_app index: 1 @@ -17665,6 +17954,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -17679,6 +17969,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -17693,6 +17984,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -17707,6 +17999,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -17721,6 +18014,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -17735,6 +18029,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -17749,6 +18044,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -17763,6 +18059,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -17777,6 +18074,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -17791,6 +18089,7 @@ act: rcv width: 2 default: lc_ctrl_pkg::On + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: one-to-N @@ -17805,6 +18104,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: lc_ctrl top_signame: flash_ctrl_rma_seed index: -1 @@ -17817,6 +18117,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -17831,6 +18132,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -17845,6 +18147,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -17859,6 +18162,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -17873,6 +18177,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -17887,6 +18192,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -17901,6 +18207,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: lc_ctrl end_idx: -1 top_type: broadcast @@ -17915,6 +18222,7 @@ act: rcv width: 1 default: "'0" + class: InterSignal inst_name: lc_ctrl top_signame: lc_ctrl_otp_device_id index: -1 @@ -17927,6 +18235,7 @@ act: rcv width: 1 default: "'0" + class: InterSignal inst_name: lc_ctrl top_signame: lc_ctrl_otp_manuf_state index: -1 @@ -17939,6 +18248,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: lc_ctrl index: -1 } @@ -17956,6 +18266,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: lc_ctrl package: "" end_idx: -1 @@ -17970,6 +18281,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: lc_ctrl default: "" end_idx: -1 @@ -17983,6 +18295,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: lc_ctrl index: -1 } @@ -17993,6 +18306,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: alert_handler default: "" end_idx: -1 @@ -18007,6 +18321,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: alert_handler default: "" top_signame: edn0_edn @@ -18019,6 +18334,7 @@ type: uni act: rcv width: 4 + class: InterSignal inst_name: alert_handler default: "" end_idx: -1 @@ -18033,6 +18349,7 @@ type: uni act: req width: 4 + class: InterSignal inst_name: alert_handler default: "" end_idx: -1 @@ -18047,6 +18364,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: alert_handler default: "" end_idx: -1 @@ -18060,6 +18378,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: spi_host0 default: "" top_signame: spi_device_passthrough @@ -18076,6 +18395,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: spi_host0 index: -1 } @@ -18086,6 +18406,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: spi_host0 default: "" end_idx: -1 @@ -18099,6 +18420,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: spi_host1 index: -1 } @@ -18113,6 +18435,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: spi_host1 index: -1 } @@ -18123,6 +18446,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: spi_host1 default: "" end_idx: -1 @@ -18136,6 +18460,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -18151,6 +18476,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -18166,6 +18492,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -18181,6 +18508,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -18196,6 +18524,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -18211,6 +18540,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -18226,6 +18556,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -18241,6 +18572,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -18256,6 +18588,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -18271,6 +18604,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -18286,6 +18620,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -18301,6 +18636,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -18316,6 +18652,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -18331,6 +18668,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -18346,6 +18684,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: usbdev default: "" package: "" @@ -18359,6 +18698,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: usbdev default: "" top_signame: ast_usb_ram_1p_cfg @@ -18371,6 +18711,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: usbdev default: "" end_idx: -1 @@ -18384,6 +18725,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" external: true @@ -18398,6 +18740,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" end_idx: -1 @@ -18411,6 +18754,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" end_idx: -1 @@ -18424,6 +18768,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" end_idx: -1 @@ -18437,6 +18782,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" end_idx: -1 @@ -18450,6 +18796,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" end_idx: -1 @@ -18464,6 +18811,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" top_signame: alert_handler_esc_tx @@ -18476,6 +18824,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" top_signame: alert_handler_esc_rx @@ -18488,6 +18837,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" top_signame: rv_core_ibex_pwrmgr @@ -18499,6 +18849,7 @@ type: uni act: rcv width: 6 + class: InterSignal inst_name: pwrmgr_aon default: "" package: "" @@ -18513,6 +18864,7 @@ type: uni act: rcv width: 2 + class: InterSignal inst_name: pwrmgr_aon default: "" package: "" @@ -18527,6 +18879,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" package: "" @@ -18539,6 +18892,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" package: "" @@ -18553,6 +18907,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" package: "" @@ -18569,6 +18924,7 @@ act: rcv width: 1 default: rom_ctrl_pkg::PWRMGR_DATA_DEFAULT + class: InterSignal inst_name: pwrmgr_aon top_signame: rom_ctrl_pwrmgr_data index: -1 @@ -18580,6 +18936,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" end_idx: -1 @@ -18594,6 +18951,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" top_signame: lc_ctrl_lc_dft_en @@ -18606,6 +18964,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" top_signame: lc_ctrl_lc_hw_debug_en @@ -18618,6 +18977,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" top_signame: rstmgr_aon_sw_rst_req @@ -18630,6 +18990,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: pwrmgr_aon default: "" end_idx: -1 @@ -18647,6 +19008,7 @@ type: uni act: rcv width: 2 + class: InterSignal inst_name: rstmgr_aon default: "" package: "" @@ -18666,6 +19028,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rstmgr_aon default: "" package: pwrmgr_pkg @@ -18680,6 +19043,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rstmgr_aon default: "" top_signame: rstmgr_aon_resets @@ -18693,6 +19057,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rstmgr_aon default: "" top_signame: rstmgr_aon_rst_en @@ -18706,6 +19071,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rstmgr_aon default: "" top_signame: alert_handler_crashdump @@ -18719,6 +19085,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rstmgr_aon default: "" top_signame: rv_core_ibex_crash_dump @@ -18732,6 +19099,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rstmgr_aon default: "" end_idx: -1 @@ -18746,6 +19114,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rstmgr_aon default: "" end_idx: -1 @@ -18759,6 +19128,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" top_signame: clkmgr_aon_clocks @@ -18771,6 +19141,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" top_signame: clkmgr_aon_cg_en @@ -18783,6 +19154,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" top_signame: lc_ctrl_lc_hw_debug_en @@ -18795,6 +19167,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" external: true @@ -18809,6 +19182,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" external: true @@ -18823,6 +19197,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" external: true @@ -18837,6 +19212,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" external: true @@ -18851,6 +19227,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" external: true @@ -18865,6 +19242,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" external: true @@ -18879,6 +19257,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" top_signame: lc_ctrl_lc_clk_byp_req @@ -18891,6 +19270,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" top_signame: lc_ctrl_lc_clk_byp_ack @@ -18903,6 +19283,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" external: true @@ -18916,6 +19297,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" package: pwrmgr_pkg @@ -18929,6 +19311,7 @@ type: uni act: rcv width: 4 + class: InterSignal inst_name: clkmgr_aon default: "" end_idx: -1 @@ -18945,6 +19328,7 @@ act: rcv width: 1 default: prim_mubi_pkg::MuBi4True + class: InterSignal inst_name: clkmgr_aon external: true top_signame: calib_rdy @@ -18958,6 +19342,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: clkmgr_aon default: "" end_idx: -1 @@ -18970,6 +19355,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: sysrst_ctrl_aon default: "" package: "" @@ -18982,6 +19368,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: sysrst_ctrl_aon default: "" package: "" @@ -18995,6 +19382,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: sysrst_ctrl_aon default: "" end_idx: -1 @@ -19008,6 +19396,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: adc_ctrl_aon default: "" external: true @@ -19021,6 +19410,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: adc_ctrl_aon default: "" package: "" @@ -19034,6 +19424,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: adc_ctrl_aon default: "" end_idx: -1 @@ -19047,6 +19438,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: pwm_aon default: "" end_idx: -1 @@ -19062,6 +19454,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: pinmux_aon top_signame: lc_ctrl_lc_hw_debug_en index: -1 @@ -19075,6 +19468,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: pinmux_aon top_signame: lc_ctrl_lc_dft_en index: -1 @@ -19092,6 +19486,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: pinmux_aon top_signame: lc_ctrl_lc_escalate_en index: -1 @@ -19112,6 +19507,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: pinmux_aon top_signame: lc_ctrl_lc_check_byp_en index: -1 @@ -19129,6 +19525,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: pinmux_aon end_idx: -1 top_type: broadcast @@ -19143,6 +19540,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: pinmux_aon default: "" end_idx: -1 @@ -19157,6 +19555,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: pinmux_aon default: "" end_idx: -1 @@ -19171,6 +19570,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: pinmux_aon default: "" top_signame: pinmux_aon_dft_jtag @@ -19185,6 +19585,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: pinmux_aon external: true top_signame: dft_strap_test @@ -19199,6 +19600,7 @@ act: rcv width: 1 default: "'0" + class: InterSignal inst_name: pinmux_aon package: "" external: true @@ -19214,6 +19616,7 @@ act: rcv width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" top_signame: pwrmgr_aon_low_power @@ -19227,6 +19630,7 @@ act: rcv width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" top_signame: pwrmgr_aon_strap @@ -19246,6 +19650,7 @@ act: rcv width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" top_signame: lc_ctrl_strap_en_override @@ -19259,6 +19664,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" top_signame: pwrmgr_aon_wakeups @@ -19271,6 +19677,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pinmux_aon default: "" package: "" @@ -19284,6 +19691,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pinmux_aon default: "" package: "" @@ -19298,6 +19706,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" external: true @@ -19313,6 +19722,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" external: true @@ -19328,6 +19738,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" top_signame: pwrmgr_aon_wakeups @@ -19340,6 +19751,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pinmux_aon default: "" package: "" @@ -19353,6 +19765,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: pinmux_aon default: "" package: "" @@ -19367,6 +19780,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" top_signame: usbdev_usb_aon_bus_not_idle @@ -19380,6 +19794,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" top_signame: usbdev_usb_aon_bus_reset @@ -19393,6 +19808,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" top_signame: usbdev_usb_aon_sense_lost @@ -19406,6 +19822,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: pinmux_aon package: "" end_idx: -1 @@ -19420,6 +19837,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: pinmux_aon default: "" end_idx: -1 @@ -19433,6 +19851,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: aon_timer_aon package: "" end_idx: -1 @@ -19447,6 +19866,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: aon_timer_aon package: "" top_signame: pwrmgr_aon_wakeups @@ -19459,6 +19879,7 @@ act: req width: 1 default: 1'b0 + class: InterSignal inst_name: aon_timer_aon package: "" top_signame: pwrmgr_aon_rstreqs @@ -19472,6 +19893,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: aon_timer_aon top_signame: lc_ctrl_lc_escalate_en index: -1 @@ -19482,6 +19904,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: aon_timer_aon default: "" package: "" @@ -19495,6 +19918,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: aon_timer_aon default: "" end_idx: -1 @@ -19508,6 +19932,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: ast index: -1 } @@ -19518,6 +19943,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: sensor_ctrl_aon default: "" external: true @@ -19532,6 +19958,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: sensor_ctrl_aon default: "" external: true @@ -19547,6 +19974,7 @@ act: rcv width: 1 default: prim_mubi_pkg::MuBi4True + class: InterSignal inst_name: sensor_ctrl_aon external: true top_signame: ast_init_done @@ -19559,6 +19987,7 @@ type: uni act: rcv width: 9 + class: InterSignal inst_name: sensor_ctrl_aon default: "" package: "" @@ -19573,6 +20002,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: sensor_ctrl_aon default: "" package: "" @@ -19587,6 +20017,7 @@ act: req width: 4 default: "'0" + class: InterSignal inst_name: sensor_ctrl_aon external: true top_signame: sensor_ctrl_manual_pad_attr @@ -19600,6 +20031,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: sensor_ctrl_aon default: "" end_idx: -1 @@ -19613,6 +20045,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: sram_ctrl_ret_aon default: "" top_signame: otp_ctrl_sram_otp_key @@ -19626,6 +20059,7 @@ act: rcv width: 1 default: "'0" + class: InterSignal inst_name: sram_ctrl_ret_aon top_signame: ast_ram_1p_cfg index: -1 @@ -19638,6 +20072,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: sram_ctrl_ret_aon top_signame: lc_ctrl_lc_escalate_en index: -1 @@ -19650,6 +20085,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: sram_ctrl_ret_aon index: -1 } @@ -19661,6 +20097,7 @@ act: rcv width: 1 default: prim_mubi_pkg::MuBi8False + class: InterSignal inst_name: sram_ctrl_ret_aon index: -1 } @@ -19671,6 +20108,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: sram_ctrl_ret_aon default: "" end_idx: -1 @@ -19684,6 +20122,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: sram_ctrl_ret_aon default: "" end_idx: -1 @@ -19697,6 +20136,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: flash_ctrl default: "" end_idx: -1 @@ -19710,6 +20150,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_nvm_debug_en @@ -19722,6 +20163,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" external: true @@ -19735,6 +20177,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" package: "" @@ -19749,6 +20192,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" package: "" @@ -19763,6 +20207,7 @@ type: io act: none width: 2 + class: InterSignal inst_name: flash_ctrl default: "" package: "" @@ -19777,6 +20222,7 @@ type: io act: none width: 1 + class: InterSignal inst_name: flash_ctrl default: "" package: "" @@ -19792,6 +20238,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_creator_seed_sw_rw_en @@ -19804,6 +20251,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_owner_seed_sw_rw_en @@ -19816,6 +20264,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_iso_part_sw_rd_en @@ -19828,6 +20277,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_iso_part_sw_wr_en @@ -19840,6 +20290,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_seed_hw_rd_en @@ -19852,6 +20303,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_escalate_en @@ -19864,6 +20316,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_flash_rma_req @@ -19876,6 +20329,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: lc_ctrl_lc_flash_rma_ack @@ -19888,6 +20342,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" end_idx: -1 @@ -19902,6 +20357,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: pwrmgr_aon_pwr_flash @@ -19914,6 +20370,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: flash_ctrl default: "" end_idx: -1 @@ -19928,6 +20385,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: flash_ctrl default: "" top_signame: ast_obs_ctrl @@ -19939,6 +20397,7 @@ type: uni act: req width: 8 + class: InterSignal inst_name: flash_ctrl default: "" package: "" @@ -19954,6 +20413,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: flash_ctrl default: "" end_idx: -1 @@ -19967,6 +20427,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: flash_ctrl default: "" end_idx: -1 @@ -19980,6 +20441,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: flash_ctrl default: "" end_idx: -1 @@ -19999,6 +20461,7 @@ act: rcv width: 1 default: "'0" + class: InterSignal inst_name: rv_dm index: -1 } @@ -20010,6 +20473,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rv_dm default: "" top_signame: pinmux_aon_rv_jtag @@ -20028,6 +20492,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: rv_dm top_signame: lc_ctrl_lc_hw_debug_en index: -1 @@ -20045,6 +20510,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: rv_dm top_signame: lc_ctrl_lc_dft_en index: -1 @@ -20064,6 +20530,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: rv_dm top_signame: pinmux_aon_pinmux_hw_debug_en index: -1 @@ -20076,6 +20543,7 @@ act: rcv width: 1 default: prim_mubi_pkg::MuBi8False + class: InterSignal inst_name: rv_dm top_signame: rv_dm_otp_dis_rv_dm_late_debug index: -1 @@ -20092,6 +20560,7 @@ act: rcv width: 1 default: 1'b0 + class: InterSignal inst_name: rv_dm index: -1 } @@ -20102,6 +20571,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_dm default: "" package: "" @@ -20121,6 +20591,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_dm index: -1 } @@ -20131,6 +20602,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_dm default: "" package: "" @@ -20152,6 +20624,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: rv_dm index: -1 } @@ -20171,6 +20644,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: rv_dm index: -1 } @@ -20182,6 +20656,7 @@ act: rcv width: 1 default: 1'b0 + class: InterSignal inst_name: rv_dm index: -1 } @@ -20199,6 +20674,7 @@ act: rcv width: 1 default: 1'b0 + class: InterSignal inst_name: rv_dm index: -1 } @@ -20209,6 +20685,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: rv_dm default: "" top_signame: main_tl_rv_dm__sba @@ -20221,6 +20698,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rv_dm default: "" end_idx: -1 @@ -20234,6 +20712,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rv_dm default: "" end_idx: -1 @@ -20247,6 +20726,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rv_dm index: -1 } @@ -20256,6 +20736,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_plic default: "" package: "" @@ -20270,6 +20751,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_plic index: -1 } @@ -20279,6 +20761,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_plic default: "" package: "" @@ -20294,6 +20777,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rv_plic default: "" end_idx: -1 @@ -20307,6 +20791,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: aes default: "" top_signame: clkmgr_aon_idle @@ -20320,6 +20805,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: aes top_signame: lc_ctrl_lc_escalate_en index: -1 @@ -20331,6 +20817,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: aes default: "" top_signame: edn0_edn @@ -20343,6 +20830,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: aes default: "" top_signame: keymgr_aes_key @@ -20355,6 +20843,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: aes default: "" end_idx: -1 @@ -20368,6 +20857,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: hmac default: "" top_signame: clkmgr_aon_idle @@ -20380,6 +20870,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: hmac default: "" end_idx: -1 @@ -20393,6 +20884,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: kmac default: "" top_signame: keymgr_kmac_key @@ -20408,13 +20900,14 @@ { name: NumAppIntf desc: Number of application interfaces - param_type: int - unpacked_dimensions: null - default: 3 - local: false - expose: true + type: int name_top: KmacNumAppIntf + default: 3 + local: "false" + expose: "true" + class: Parameter } + class: InterSignal inst_name: kmac default: "" end_idx: -1 @@ -20429,6 +20922,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: kmac default: "" top_signame: edn0_edn @@ -20441,6 +20935,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: kmac default: "" top_signame: clkmgr_aon_idle @@ -20452,6 +20947,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: kmac default: "" package: "" @@ -20468,6 +20964,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: kmac top_signame: lc_ctrl_lc_escalate_en index: -1 @@ -20479,6 +20976,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: kmac default: "" end_idx: -1 @@ -20493,6 +20991,7 @@ act: req width: 1 default: "'0" + class: InterSignal inst_name: otbn top_signame: otp_ctrl_otbn_otp_key index: -1 @@ -20504,6 +21003,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: otbn default: "" top_signame: edn1_edn @@ -20516,6 +21016,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: otbn default: "" top_signame: edn0_edn @@ -20528,6 +21029,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: otbn default: "" top_signame: clkmgr_aon_idle @@ -20540,6 +21042,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: otbn default: "" top_signame: ast_ram_1p_cfg @@ -20553,6 +21056,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otbn top_signame: lc_ctrl_lc_escalate_en index: -1 @@ -20565,6 +21069,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otbn top_signame: lc_ctrl_lc_flash_rma_req index: -1 @@ -20577,6 +21082,7 @@ act: req width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: otbn top_signame: lc_ctrl_lc_flash_rma_ack index: 1 @@ -20588,6 +21094,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: otbn default: "" top_signame: keymgr_otbn_key @@ -20600,6 +21107,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: otbn default: "" end_idx: -1 @@ -20613,6 +21121,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: keymgr default: "" top_signame: edn0_edn @@ -20625,6 +21134,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: keymgr default: "" end_idx: -1 @@ -20639,6 +21149,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: keymgr default: "" end_idx: -1 @@ -20653,6 +21164,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: keymgr default: "" end_idx: -1 @@ -20667,6 +21179,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: keymgr default: "" top_signame: kmac_app @@ -20679,6 +21192,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: keymgr default: "" top_signame: otp_ctrl_otp_keymgr_key @@ -20691,6 +21205,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: keymgr default: "" top_signame: keymgr_otp_device_id @@ -20703,6 +21218,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: keymgr default: "" top_signame: flash_ctrl_keymgr @@ -20716,6 +21232,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::On + class: InterSignal inst_name: keymgr top_signame: lc_ctrl_lc_keymgr_en index: -1 @@ -20727,6 +21244,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: keymgr default: "" top_signame: lc_ctrl_lc_keymgr_div @@ -20739,6 +21257,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: keymgr default: "" top_signame: rom_ctrl_keymgr_data @@ -20750,6 +21269,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: keymgr default: "" package: "" @@ -20763,6 +21283,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: keymgr default: "" end_idx: -1 @@ -20776,6 +21297,7 @@ type: req_rsp act: rsp width: 2 + class: InterSignal inst_name: csrng default: "" end_idx: -1 @@ -20790,6 +21312,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: csrng default: "" end_idx: -1 @@ -20808,6 +21331,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: csrng default: "" end_idx: -1 @@ -20822,6 +21346,7 @@ act: rcv width: 1 default: prim_mubi_pkg::MuBi8True + class: InterSignal inst_name: csrng top_signame: csrng_otp_en_csrng_sw_app_read index: -1 @@ -20834,6 +21359,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: csrng top_signame: lc_ctrl_lc_hw_debug_en index: -1 @@ -20845,6 +21371,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: csrng default: "" end_idx: -1 @@ -20858,6 +21385,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: entropy_src default: "" top_signame: csrng_entropy_src_hw_if @@ -20877,6 +21405,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: entropy_src default: "" top_signame: csrng_cs_aes_halt @@ -20889,6 +21418,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: entropy_src default: "" external: true @@ -20903,6 +21433,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: entropy_src index: -1 } @@ -20914,6 +21445,7 @@ act: rcv width: 1 default: prim_mubi_pkg::MuBi8True + class: InterSignal inst_name: entropy_src index: -1 } @@ -20925,6 +21457,7 @@ act: rcv width: 1 default: prim_mubi_pkg::MuBi8True + class: InterSignal inst_name: entropy_src index: -1 } @@ -20934,6 +21467,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: entropy_src default: "" package: "" @@ -20949,6 +21483,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: entropy_src default: "" end_idx: -1 @@ -20963,6 +21498,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: edn0 default: "" top_signame: csrng_csrng_cmd @@ -20984,6 +21520,7 @@ act: rsp width: 8 default: "'0" + class: InterSignal inst_name: edn0 end_idx: -1 top_type: one-to-N @@ -20997,6 +21534,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: edn0 default: "" end_idx: -1 @@ -21011,6 +21549,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: edn1 default: "" top_signame: csrng_csrng_cmd @@ -21032,6 +21571,7 @@ act: rsp width: 8 default: "'0" + class: InterSignal inst_name: edn1 end_idx: 1 top_type: partial-one-to-N @@ -21045,6 +21585,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: edn1 default: "" end_idx: -1 @@ -21058,6 +21599,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: sram_ctrl_main default: "" top_signame: otp_ctrl_sram_otp_key @@ -21071,6 +21613,7 @@ act: rcv width: 1 default: "'0" + class: InterSignal inst_name: sram_ctrl_main top_signame: ast_ram_1p_cfg index: -1 @@ -21083,6 +21626,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: sram_ctrl_main top_signame: lc_ctrl_lc_escalate_en index: -1 @@ -21095,6 +21639,7 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off + class: InterSignal inst_name: sram_ctrl_main top_signame: lc_ctrl_lc_hw_debug_en index: -1 @@ -21107,6 +21652,7 @@ act: rcv width: 1 default: prim_mubi_pkg::MuBi8False + class: InterSignal inst_name: sram_ctrl_main top_signame: sram_ctrl_main_otp_en_sram_ifetch index: -1 @@ -21118,6 +21664,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: sram_ctrl_main default: "" end_idx: -1 @@ -21131,6 +21678,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: sram_ctrl_main default: "" end_idx: -1 @@ -21144,6 +21692,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rom_ctrl default: "" top_signame: ast_rom_cfg @@ -21156,6 +21705,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rom_ctrl default: "" end_idx: -1 @@ -21170,6 +21720,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rom_ctrl default: "" end_idx: -1 @@ -21184,6 +21735,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: rom_ctrl default: "" top_signame: kmac_app @@ -21196,6 +21748,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rom_ctrl default: "" end_idx: -1 @@ -21209,6 +21762,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rom_ctrl default: "" end_idx: -1 @@ -21221,6 +21775,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_core_ibex index: -1 } @@ -21231,6 +21786,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: ast_ram_1p_cfg @@ -21242,6 +21798,7 @@ type: uni act: rcv width: 32 + class: InterSignal inst_name: rv_core_ibex default: "" package: "" @@ -21254,6 +21811,7 @@ type: uni act: rcv width: 32 + class: InterSignal inst_name: rv_core_ibex default: "" package: "" @@ -21266,6 +21824,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" package: "" @@ -21278,6 +21837,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" package: "" @@ -21290,6 +21850,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" package: "" @@ -21303,6 +21864,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: alert_handler_esc_tx @@ -21315,6 +21877,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: alert_handler_esc_rx @@ -21326,6 +21889,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" package: "" @@ -21339,6 +21903,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" end_idx: -1 @@ -21353,6 +21918,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: lc_ctrl_lc_cpu_en @@ -21365,6 +21931,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: pwrmgr_aon_fetch_en @@ -21377,6 +21944,7 @@ type: uni act: req width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" end_idx: -1 @@ -21390,6 +21958,7 @@ type: uni act: rcv width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" package: "" @@ -21403,6 +21972,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: edn0_edn @@ -21415,6 +21985,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: otp_ctrl_sram_otp_key @@ -21426,6 +21997,7 @@ type: uni act: rcv width: 32 + class: InterSignal inst_name: rv_core_ibex default: "" package: "" @@ -21441,6 +22013,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: main_tl_rv_core_ibex__corei @@ -21453,6 +22026,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" top_signame: main_tl_rv_core_ibex__cored @@ -21465,6 +22039,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: rv_core_ibex default: "" end_idx: -1 @@ -21478,6 +22053,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: main default: "" end_idx: -1 @@ -21491,6 +22067,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: main default: "" end_idx: -1 @@ -21504,6 +22081,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: main default: "" end_idx: -1 @@ -21517,6 +22095,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: rv_dm_regs_tl_d @@ -21529,6 +22108,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: rv_dm_mem_tl_d @@ -21541,6 +22121,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: rom_ctrl_rom_tl @@ -21553,6 +22134,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: rom_ctrl_regs_tl @@ -21565,6 +22147,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" end_idx: -1 @@ -21578,6 +22161,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: spi_host0_tl @@ -21590,6 +22174,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: spi_host1_tl @@ -21602,6 +22187,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: usbdev_tl @@ -21614,6 +22200,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: flash_ctrl_core_tl @@ -21626,6 +22213,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: flash_ctrl_prim_tl @@ -21638,6 +22226,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: flash_ctrl_mem_tl @@ -21650,6 +22239,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: hmac_tl @@ -21662,6 +22252,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: kmac_tl @@ -21674,6 +22265,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: aes_tl @@ -21686,6 +22278,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: entropy_src_tl @@ -21698,6 +22291,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: csrng_tl @@ -21710,6 +22304,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: edn0_tl @@ -21722,6 +22317,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: edn1_tl @@ -21734,6 +22330,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: rv_plic_tl @@ -21746,6 +22343,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: otbn_tl @@ -21758,6 +22356,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: keymgr_tl @@ -21770,6 +22369,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: rv_core_ibex_cfg_tl_d @@ -21782,6 +22382,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: sram_ctrl_main_regs_tl @@ -21794,6 +22395,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: main default: "" top_signame: sram_ctrl_main_ram_tl @@ -21806,6 +22408,7 @@ type: req_rsp act: rsp width: 1 + class: InterSignal inst_name: peri default: "" top_signame: main_tl_peri @@ -21818,6 +22421,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: uart0_tl @@ -21830,6 +22434,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: uart1_tl @@ -21842,6 +22447,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: uart2_tl @@ -21854,6 +22460,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: uart3_tl @@ -21866,6 +22473,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: i2c0_tl @@ -21878,6 +22486,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: i2c1_tl @@ -21890,6 +22499,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: i2c2_tl @@ -21902,6 +22512,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: pattgen_tl @@ -21914,6 +22525,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: pwm_aon_tl @@ -21926,6 +22538,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: gpio_tl @@ -21938,6 +22551,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: spi_device_tl @@ -21950,6 +22564,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: rv_timer_tl @@ -21962,6 +22577,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: pwrmgr_aon_tl @@ -21974,6 +22590,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: rstmgr_aon_tl @@ -21986,6 +22603,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: clkmgr_aon_tl @@ -21998,6 +22616,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: pinmux_aon_tl @@ -22010,6 +22629,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: otp_ctrl_core_tl @@ -22022,6 +22642,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: otp_ctrl_prim_tl @@ -22034,6 +22655,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: lc_ctrl_regs_tl @@ -22046,6 +22668,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: sensor_ctrl_aon_tl @@ -22058,6 +22681,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: alert_handler_tl @@ -22070,6 +22694,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: sram_ctrl_ret_aon_regs_tl @@ -22082,6 +22707,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: sram_ctrl_ret_aon_ram_tl @@ -22094,6 +22720,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: aon_timer_aon_tl @@ -22106,6 +22733,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: sysrst_ctrl_aon_tl @@ -22118,6 +22746,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" top_signame: adc_ctrl_aon_tl @@ -22130,6 +22759,7 @@ type: req_rsp act: req width: 1 + class: InterSignal inst_name: peri default: "" external: true @@ -23524,12 +24154,12 @@ { name: NumAppIntf desc: Number of application interfaces - param_type: int - unpacked_dimensions: null - default: 3 - local: false - expose: true + type: int name_top: KmacNumAppIntf + default: 3 + local: "false" + expose: "true" + class: Parameter } type: req_rsp end_idx: -1 @@ -23545,12 +24175,12 @@ { name: NumAppIntf desc: Number of application interfaces - param_type: int - unpacked_dimensions: null - default: 3 - local: false - expose: true + type: int name_top: KmacNumAppIntf + default: 3 + local: "false" + expose: "true" + class: Parameter } type: req_rsp end_idx: -1 diff --git a/util/reggen/inter_signal.py b/util/reggen/inter_signal.py index d9d98a12a48905..a686de8fb069e5 100644 --- a/util/reggen/inter_signal.py +++ b/util/reggen/inter_signal.py @@ -90,8 +90,21 @@ def _asdict(self) -> Dict[str, object]: ret['width'] = self.width if self.default is not None: ret['default'] = self.default + ret['class'] = 'InterSignal' # This will let fromdict() know it has to create the class return ret + @classmethod + def fromdict(cls, item: Dict[str, object]) -> object: + if 'class' not in item or item['class'] == 'InterSignal': + return item + item["package"] = item.get("package", None) + item["default"] = item.get("default", None) + item["signal_type"] = item["type"] + del item["type"] + c = cls.__new__(cls) + c.__dict__.update(**item) + return c + def as_dict(self) -> Dict[str, object]: return self._asdict() diff --git a/util/reggen/params.py b/util/reggen/params.py index a790370fc05660..b1c84d2f642d9b 100644 --- a/util/reggen/params.py +++ b/util/reggen/params.py @@ -55,8 +55,29 @@ def as_dict(self) -> Dict[str, object]: rd['type'] = self.param_type if self.unpacked_dimensions is not None: rd['unpacked_dimensions'] = self.unpacked_dimensions + # topgen sometimes manually adds a 'name_top' field after creation. + if getattr(self, "name_top", None): + rd['name_top'] = self.name_top return rd + def _asdict(self) -> Dict[str, object]: + # Add an attribute to distinguished between manual serialization (as_dict()) + # or automatic by hjson. + d = self.as_dict() + d['class'] = self.__class__.__name__ + return d + + @classmethod + def fromdict(cls, param: Dict[str, object]) -> object: + param['desc'] = param.get('desc', None) + param['unpacked_dimensions'] = param.get('unpacked_dimensions', None) + del param['class'] + param['param_type'] = param['type'] + del param['type'] + c = cls.__new__(cls) + c.__dict__.update(**param) + return c + class LocalParam(BaseParam): def __init__(self, @@ -82,6 +103,12 @@ def as_dict(self) -> Dict[str, object]: rd['default'] = self.value return rd + @classmethod + def fromdict(cls, param: Dict[str, object]) -> object: + assert param['local'] + del param['local'] + return super().fromdict.__func__(cls, param) + class Parameter(BaseParam): def __init__(self, @@ -104,6 +131,12 @@ def as_dict(self) -> Dict[str, object]: rd['expose'] = 'true' if self.expose else 'false' return rd + @classmethod + def fromdict(cls, param: Dict[str, object]) -> object: + param['local'] = param['local'] == 'true' + param['expose'] = param['expose'] == 'true' + return super().fromdict.__func__(cls, param) + class RandParameter(BaseParam): def __init__(self, @@ -129,6 +162,10 @@ def as_dict(self) -> Dict[str, object]: rd['randtype'] = self.randtype return rd + @classmethod + def fromdict(cls, param: Dict[str, object]) -> object: + return super().fromdict.__func__(cls, param) + class MemSizeParameter(BaseParam): def __init__(self, diff --git a/util/topgen.py b/util/topgen.py index 82ff3c8ef21554..820164cbedadc5 100755 --- a/util/topgen.py +++ b/util/topgen.py @@ -39,6 +39,7 @@ from topgen.resets import Resets from topgen.rust import TopGenRust from topgen.top import Top +from topgen.topcfg import CompleteTopCfg # Common header for generated files warnhdr = """// @@ -90,6 +91,9 @@ def ipgen_render(template_name: str, topname: str, params: Dict[str, object], log.error(e.verbose_str()) sys.exit(1) + # Remote extra topname + params.pop("topname") + def generate_top(top: Dict[str, object], name_to_block: Dict[str, IpBlock], tpl_filename: str, **kwargs: Dict[str, object]) -> None: @@ -460,12 +464,6 @@ def generate_flash(topcfg: Dict[str, object], out_path: Path) -> None: return params = vars(flash_mems[0]["memory"]["mem"]["config"]) - # Additional parameters not provided in the top config. - params.update({ - "metadata_width": 12, - "info_types": 3, - "infos_per_bank": [10, 1, 2] - }) params.pop('base_addrs', None) ipgen_render("flash_ctrl", topname, params, out_path) @@ -822,6 +820,12 @@ def _process_top( return completecfg, name_to_block, name_to_hjson +def test_topcfg_loader(genhjson_path: Path, completecfg: Dict[str, object]): + loaded_cfg = CompleteTopCfg.from_path(genhjson_path) + + CompleteTopCfg.check_equivalent(completecfg, loaded_cfg) + + def _check_countermeasures(completecfg: Dict[str, object], name_to_block: Dict[str, IpBlock], name_to_hjson: Dict[str, Path]) -> bool: @@ -1106,6 +1110,10 @@ def main(): genhjson_path.write_text(genhdr + gencmd + hjson.dumps(completecfg, for_json=True, default=vars) + '\n') + # We also run a sanity check on the topcfg loader to make sure that it roundtrips + # correctly when loading. + test_topcfg_loader(genhjson_path, completecfg) + # Generate Rust toplevel definitions if not args.no_rust: generate_rust(topname, completecfg, name_to_block, out_path.resolve(), @@ -1287,9 +1295,9 @@ def render_template(template_path: str, rendered_path: Path, # Auto-generate tests in "sw/device/tests/autogen" area. gencmd = warnhdr + GENCMD.format(top_name=top_name) - for fname in ["plic_all_irqs_test.c", "alert_test.c", "BUILD"]: + for fname in ["plic_all_irqs_test.c", "alert_test.c"]: outfile = SRCTREE_TOP / "sw/device/tests/autogen" / fname - render_template(TOPGEN_TEMPLATE_PATH / f"{fname}.tpl", + render_template(TOPGEN_TEMPLATE_PATH / ".." / ".." / "autogen_tests" / "templates" / f"{fname}.tpl", outfile, helper=c_helper, gencmd=gencmd) diff --git a/util/topgen/clocks.py b/util/topgen/clocks.py index 73d736b9f921e9..15de5fd5ae854d 100644 --- a/util/topgen/clocks.py +++ b/util/topgen/clocks.py @@ -20,13 +20,17 @@ def _bool_to_yn(val: bool) -> str: return 'yes' if val else 'no' +def _bool_from_yn(val: str) -> bool: + return val == 'yes' + + def _to_int(val: object) -> int: if isinstance(val, int): return val return int(str(val)) -def _check_choices(val: str, what: str, choices: List[str]) -> str: +def _check_choices(val: str, what: str, choices: list[str]) -> str: if val in choices: return val raise ValueError( @@ -64,6 +68,14 @@ def _asdict(self) -> Dict[str, object]: 'ref': self.ref } + @classmethod + def fromdict(cls, src: Dict[str, object]) -> object: + src['aon'] = _bool_from_yn(src['aon']) + src['freq'] = int(src['freq']) + c = cls.__new__(cls) + c.__dict__.update(**src) + return c + class DerivedSourceClock(SourceClock): '''A derived source clock (divided down from some other clock).''' @@ -80,6 +92,12 @@ def _asdict(self) -> Dict[str, object]: ret['src'] = self.src.name return ret + @classmethod + def fromdict(cls, src: Dict[str, object], clocks: Dict[str, SourceClock]) -> object: + src['div'] = int(src['div']) + src['src'] = clocks[src['src']] + return super().fromdict.__func__(cls, src) + class ClockSignal: '''A clock signal in the design.''' @@ -139,6 +157,42 @@ def _asdict(self) -> Dict[str, object]: for name, sig in self.clocks.items()} } + @classmethod + def fromdict(cls, src: Dict[str, object], clocks: Dict[str, SourceClock]) -> object: + src['unique'] = _bool_from_yn(src['unique']) + src['clocks'] = { + name: ClockSignal(name, clocks[sig_src_name]) + for (name, sig_src_name) in src['clocks'].items() + } + c = cls.__new__(cls) + c.__dict__.update(**src) + return c + + +class GroupProxy: + """ + The sole purpose of this class is to use an object as if it's an object + but when serializing, we only print the group name instead of the definition. + """ + def __init__(self, grp): + self._grp = grp + + def __getattr__(self, name): + return getattr(self._grp, name) + + def _asdict(self): + return { + "name": self._grp.name + } + + @classmethod + def fromdict(cls, proxy: Dict[str, object], clocks: object) -> object: + proxy['_grp'] = clocks.groups[proxy["name"]] + del proxy["name"] + c = cls.__new__(cls) + c.__dict__.update(**proxy) + return c + class TypedClocks(NamedTuple): # External clocks that are consumed only inside the clkmgr and are fed from @@ -170,7 +224,7 @@ class TypedClocks(NamedTuple): # division, sorted by name. This doesn't include clock sources that are # only used to derive divided clocks (we might gate the divided clocks, but # don't bother gating the upstream source). - rg_srcs: List[str] + rg_srcs: list[str] # A diction of the clock families. # The key for each is root clock, while the list contains all the clocks @@ -225,6 +279,9 @@ def __init__(self, raw: List[object]): def _asdict(self) -> Dict[str, object]: return self.clks + def _check_field(self) -> list[str]: + return ["clkc"] + class Clocks: '''Clock connections for the chip.''' @@ -265,6 +322,25 @@ def _asdict(self) -> Dict[str, object]: 'groups': list(self.groups.values()) } + @classmethod + def fromdict(cls, clocks: Dict[str, object]) -> object: + clocks['srcs'] = { + src["name"]: SourceClock.fromdict(src) for src in clocks['srcs'] + } + clocks['derived_srcs'] = { + src["name"]: DerivedSourceClock.fromdict(src, clocks['srcs']) + for src in clocks['derived_srcs'] + } + clocks['all_srcs'] = clocks['srcs'].copy() + clocks['all_srcs'].update(clocks['derived_srcs']) + all_clocks = clocks['all_srcs'] + clocks['groups'] = { + src["name"]: Group.fromdict(src, all_clocks) for src in clocks['groups'] + } + c = cls.__new__(cls) + c.__dict__.update(clocks) + return c + def add_clock_to_group(self, grp: Group, clk_name: str, src_name: str) -> ClockSignal: src = self.all_srcs.get(src_name) @@ -280,7 +356,7 @@ def get_clock_by_name(self, name: str) -> object: raise ValueError(f'{name} is not a valid clock') return ret - def reset_signals(self) -> List[str]: + def reset_signals(self) -> list[str]: '''Return the list of clock reset signal names. These signals are inputs to the clock manager (from the reset @@ -364,7 +440,7 @@ def make_clock_to_group(self) -> Dict[str, Group]: c2g[clk_name] = grp return c2g - def all_derived_srcs(self) -> List[str]: + def all_derived_srcs(self) -> list[str]: '''Return a list of all the clocks used as the source for derived clocks''' srcs = [] diff --git a/util/topgen/merge.py b/util/topgen/merge.py index 89992dc16f07ee..ef8a557ed42d5f 100644 --- a/util/topgen/merge.py +++ b/util/topgen/merge.py @@ -10,7 +10,7 @@ from typing import Dict, List, Union, Tuple from topgen import lib, secure_prng -from .clocks import Clocks +from .clocks import Clocks, GroupProxy from .resets import Resets from reggen.ip_block import IpBlock from reggen.params import LocalParam, Parameter, RandParameter, MemSizeParameter @@ -875,8 +875,9 @@ def create_alert_lpgs(top, name_to_block: Dict[str, IpBlock]): else: clk = clk.split(".")[-1] - # Discover what clock group we are related to - clock_group = clock_groups[clk] + # Discover what clock group we are related to. + # We create a proxy so that it is only serialized by name. + clock_group = GroupProxy(clock_groups[clk]) # using this info, we can create an LPG identifier # and uniquify it via a dict. @@ -896,7 +897,7 @@ def create_alert_lpgs(top, name_to_block: Dict[str, IpBlock]): 'clock_group': None if unmanaged_clock else clock_group, 'clock_connection': clock, 'unmanaged_clock': unmanaged_clock, - 'reset_connection': primary_reset + 'reset_connection': primary_reset, }) num_lpg += 1 diff --git a/util/topgen/resets.py b/util/topgen/resets.py index ddcb5e8c3ac975..94294d1add3a7b 100644 --- a/util/topgen/resets.py +++ b/util/topgen/resets.py @@ -50,9 +50,16 @@ def _asdict(self) -> Dict[str, object]: 'domains': self.domains, 'shadowed': self.shadowed, 'sw': self.sw, - 'path': self.path + 'path': self.path, + 'shadow_path': self.shadow_path, } + if getattr(self, "shadow_lpg_path", None): + ret['shadow_lpg_path'] = self.shadow_lpg_path + + if getattr(self, "lpg_path", None): + ret['lpg_path'] = self.lpg_path + if self.parent: ret['parent'] = self.parent @@ -61,6 +68,17 @@ def _asdict(self) -> Dict[str, object]: return ret + @classmethod + def fromdict(cls, item: Dict[str, object], clocks: Clocks) -> object: + # rst_type can be None which is serialized as "null", also the name is different + item["rst_type"] = None if item["type"] == "null" else item["type"] + del item["type"] + item["clock"] = clocks.get_clock_by_name(item["clock"]) + item["parent"] = item.get("parent", "") + c = cls.__new__(cls) + c.__dict__.update(**item) + return c + class Resets: '''Resets for the chip''' @@ -86,6 +104,16 @@ def _asdict(self) -> Dict[str, object]: return ret + @classmethod + def fromdict(cls, resets: Dict[str, object], clocks: Clocks) -> object: + # Reconstruct dict. + resets['nodes'] = { + node["name"]: ResetItem.fromdict(node, clocks) for node in resets['nodes'] + } + c = cls.__new__(cls) + c.__dict__.update(**resets) + return c + def get_reset_by_name(self, name: str) -> ResetItem: ret = self.nodes.get(name, None) diff --git a/util/topgen/topcfg.py b/util/topgen/topcfg.py new file mode 100644 index 00000000000000..72287b93159388 --- /dev/null +++ b/util/topgen/topcfg.py @@ -0,0 +1,145 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +'''Code to load a top complete configuration from a Hjson file''' + +import hjson + +from collections import OrderedDict +from collections.abc import KeysView +from pathlib import Path +from typing import Dict + +from reggen.inter_signal import InterSignal +from reggen.params import BaseParam, Parameter, LocalParam, RandParameter +from reggen.interrupt import IntrType + +from .merge import _get_clock_group_name +from .clocks import Clocks, GroupProxy, UnmanagedClocks +from .resets import Resets +from .validate import Flash + + +def _check_equivalent(actual: object, loaded: object, path: str) -> (bool, str): + # The loaded object can be an OrderedDict when the actual is just a dict. + type_ok = (isinstance(actual, dict) and isinstance(loaded, OrderedDict)) or \ + (isinstance(actual, KeysView) and isinstance(loaded, KeysView)) + assert type(actual) == type(loaded) or type_ok, \ + "objects at {} do not have the same type: {} vs {}".format(path, type(actual), type(loaded)) + + if isinstance(actual, list): + assert len(actual) == len(loaded), f"lists at {path} do not have the same length: " + \ + "{} vs {}".format(len(actual), len(loaded)) + for i in range(len(actual)): + _check_equivalent(actual[i], loaded[i], f"{path}[{i}]") + + elif isinstance(actual, dict) or isinstance(actual, OrderedDict): + _check_equivalent(actual.keys(), loaded.keys(), f"{path}.keys()") + for x in actual.keys(): + _check_equivalent(actual[x], loaded[x], f"{path}.{x}") + + elif getattr(actual, "__dict__", None): + _check_equivalent(actual.__dict__, loaded.__dict__, path) + + else: + assert actual == loaded, f"objects at {path} are not equal: " + \ + "{} vs {}".format(actual, loaded) + + +_CLASSES = { + 'InterSignal': InterSignal, + 'BaseParam': BaseParam, + 'Parameter': Parameter, + 'LocalParam': LocalParam, + 'RandParameter': RandParameter, + 'Flash': Flash, +} + + +def _topcfg_hook(obj): + """ + The main purpose of this hook is to handle classes that were serialized + with a 'class' attribute. Those will be deserialize at this point. + """ + obj = OrderedDict(obj) + if 'class' in obj and obj['class'] in _CLASSES: + return _CLASSES[obj['class']].fromdict(obj) + return obj + + +class CompleteTopCfg: + """ + An object representing a complete top configuration. This is + the configuration produced by topgen.py and exported to Hjson. + """ + + @staticmethod + def from_path(path: Path) -> object: + """ + Load a configuration from the Hjson produced by topgen. + """ + return CompleteTopCfg.from_hjson( + hjson.loads( + path.read_text(), + object_pairs_hook=_topcfg_hook, + use_decimal=True + ) + ) + + @staticmethod + def from_hjson(topcfg: Dict[str, object]) -> object: + """ + Load a configuration from an already parsed Hjson. + """ + + topcfg["clocks"] = Clocks.fromdict(topcfg["clocks"]) + topcfg['unmanaged_clocks'] = UnmanagedClocks(topcfg['unmanaged_clocks']) + topcfg['resets'] = Resets.fromdict(topcfg['resets'], topcfg["clocks"]) + # The modules need some fixing. + for mod in topcfg['module']: + base_addrs = mod['base_addrs'] + if 'null' in base_addrs: + base_addrs[None] = base_addrs['null'] + del base_addrs['null'] + # The interrupts as well. + for intr in topcfg['interrupt']: + if intr["intr_type"] == "IntrType.Status": + intr["intr_type"] = IntrType.Status + elif intr["intr_type"] == "IntrType.Event": + intr["intr_type"] = IntrType.Event + else: + assert False, "unknown interrupt type {}".format(intr["intr_type"]) + # Alert handlers. + for alert in topcfg['alert_lpgs']: + alert['clock_group'] = GroupProxy.fromdict(alert['clock_group'], topcfg['clocks']) + # The clocks need some fixing. This reimplements part of extract_clocks. + for ep in topcfg['module'] + topcfg['memory'] + topcfg['xbar']: + for port, clk in ep['clock_srcs'].items(): + group_name, src_name = _get_clock_group_name(clk, ep['clock_group']) + group = topcfg["clocks"].groups[group_name] + if group.src == 'ext': + name = "{}_i".format(src_name) + elif group.unique: + name = "{}_{}".format(src_name, ep["name"]) + else: + name = "{}_{}".format(src_name, group_name) + clk_name = "clk_" + name + group.clocks[clk_name].add_endpoint(ep["name"], port) + + return topcfg + + @staticmethod + def check_equivalent(actual: Dict[str, object], loaded: Dict[str, object]): + """ + Check if the two configurations are equivalent, ie they have exactly + the same types and same content. Throws an exception in case of error. + """ + try: + return _check_equivalent(actual, loaded, "") + except AssertionError as exc: + raise RuntimeError( + "Serialized Hjson file is not equivalent to the in-memory one.\n" + + "You can find the problematic section by running:\n" + + "cat /path/to/file | hjson -c | jq " + ) from exc diff --git a/util/topgen/validate.py b/util/topgen/validate.py index d24cb4de096016..1952a22e3ba9c6 100644 --- a/util/topgen/validate.py +++ b/util/topgen/validate.py @@ -328,16 +328,32 @@ def check_values(self): raise ValueError('flash number of banks and pages per bank too large') def _asdict(self): + # Do not include base_addrs as it will get removed later. return { + 'class': 'Flash', 'banks': self.banks, 'pages_per_bank': self.pages_per_bank, 'program_resolution': self.program_resolution, 'pgm_resolution_bytes': self.pgm_resolution_bytes, 'bytes_per_page': self.bytes_per_page, 'bytes_per_bank': self.bytes_per_bank, + 'data_width': self.data_width, + 'metadata_width': self.metadata_width, + 'info_types': self.info_types, + 'infos_per_bank': self.infos_per_bank, 'size': self.size } + @classmethod + def fromdict(cls, item: Dict[str, object]) -> object: + del item["class"] + item["word_bytes"] = int(item["data_width"] / 8) + item["words_per_page"] = int(item["bytes_per_page"] / item["word_bytes"]) + item["pages_per_bank"] = int(item["bytes_per_bank"] / item["bytes_per_page"]) + c = cls.__new__(cls) + c.__dict__.update(**item) + return c + # Check to see if each module/xbar defined in top.hjson exists as ip/xbar.hjson # Also check to make sure there are not multiple definitions of ip/xbar.hjson for each