diff --git a/hw/ip/clkmgr/dv/env/clkmgr_env.core b/hw/ip/clkmgr/dv/env/clkmgr_env.core index 446d07e8ac1c38..f4b76088b71fca 100644 --- a/hw/ip/clkmgr/dv/env/clkmgr_env.core +++ b/hw/ip/clkmgr/dv/env/clkmgr_env.core @@ -9,7 +9,7 @@ filesets: depend: - lowrisc:dv:ralgen - lowrisc:dv:cip_lib - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:systems:clkmgr_pkg files: - clkmgr_csrs_if.sv diff --git a/hw/ip/flash_ctrl/flash_ctrl_pkg.core b/hw/ip/flash_ctrl/flash_ctrl_pkg.core index 05ec6743f249fd..461ba7f7112473 100644 --- a/hw/ip/flash_ctrl/flash_ctrl_pkg.core +++ b/hw/ip/flash_ctrl/flash_ctrl_pkg.core @@ -11,7 +11,7 @@ filesets: - lowrisc:constants:top_pkg - lowrisc:prim:util - lowrisc:ip:lc_ctrl_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:jtag_pkg - lowrisc:ip:edn_pkg - "fileset_partner ? (partner:systems:ast_pkg)" diff --git a/hw/ip/lc_ctrl/lc_ctrl.core b/hw/ip/lc_ctrl/lc_ctrl.core index 4dd46ccd9b4879..c1efa3b8984df2 100644 --- a/hw/ip/lc_ctrl/lc_ctrl.core +++ b/hw/ip/lc_ctrl/lc_ctrl.core @@ -17,7 +17,7 @@ filesets: - lowrisc:prim:sparse_fsm - lowrisc:ip:lc_ctrl_pkg - lowrisc:ip:tlul - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:otp_ctrl_pkg - lowrisc:ip:kmac_pkg - lowrisc:ip:rv_dm diff --git a/hw/ip/otp_ctrl/otp_ctrl.core b/hw/ip/otp_ctrl/otp_ctrl.core index 9f18a1a1a4414b..10971dd549c4c8 100644 --- a/hw/ip/otp_ctrl/otp_ctrl.core +++ b/hw/ip/otp_ctrl/otp_ctrl.core @@ -22,7 +22,7 @@ filesets: - lowrisc:prim:secded - lowrisc:ip:edn_requester - lowrisc:prim:sec_anchor - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:edn_pkg - lowrisc:prim:sparse_fsm - "fileset_partner ? (partner:systems:ast_pkg)" diff --git a/hw/ip/rstmgr/dv/sva/rstmgr_sva_ifs.core b/hw/ip/rstmgr/dv/sva/rstmgr_sva_ifs.core index bdedf685562ffe..eff742449cc7cd 100644 --- a/hw/ip/rstmgr/dv/sva/rstmgr_sva_ifs.core +++ b/hw/ip/rstmgr/dv/sva/rstmgr_sva_ifs.core @@ -8,7 +8,7 @@ filesets: files_dv: depend: - lowrisc:ip:lc_ctrl_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:rstmgr files: diff --git a/hw/ip/rstmgr/rstmgr_pkg.core b/hw/ip/rstmgr/rstmgr_pkg.core index 97511dfb561aea..6aa6f66e784e2d 100644 --- a/hw/ip/rstmgr/rstmgr_pkg.core +++ b/hw/ip/rstmgr/rstmgr_pkg.core @@ -9,7 +9,7 @@ filesets: files_rtl: depend: - lowrisc:ip:alert_handler_component - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:rstmgr_reg - lowrisc:ip_interfaces:alert_handler_reg - "fileset_top ? (lowrisc:systems:rstmgr_pkg)" diff --git a/hw/ip/rv_core_ibex/rv_core_ibex.core b/hw/ip/rv_core_ibex/rv_core_ibex.core index bd14e14a936b80..4b0c539c83a003 100644 --- a/hw/ip/rv_core_ibex/rv_core_ibex.core +++ b/hw/ip/rv_core_ibex/rv_core_ibex.core @@ -11,7 +11,7 @@ filesets: - lowrisc:ip:edn_requester - lowrisc:ip:lc_ctrl_pkg - lowrisc:ip:otp_ctrl_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:rv_core_ibex_pkg - lowrisc:ip:tlul - lowrisc:ip_interfaces:alert_handler_reg diff --git a/hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core b/hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core index d71a35180c2772..b19f07c3623908 100644 --- a/hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core +++ b/hw/ip_templates/pwrmgr/dv/env/pwrmgr_env.core @@ -9,7 +9,7 @@ filesets: depend: - lowrisc:dv:ralgen - lowrisc:dv:cip_lib - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg files: - pwrmgr_env_pkg.sv - pwrmgr_env_cfg.sv: {is_include_file: true} diff --git a/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core b/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core index 9eaa8fd0db4d5a..d35cbce65b7b7a 100644 --- a/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core +++ b/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core @@ -7,7 +7,7 @@ description: "PWRMGR DV sim target" filesets: files_rtl: depend: - - lowrisc:ip:pwrmgr + - lowrisc:ip_interfaces:pwrmgr files_dv: depend: - lowrisc:dv:pwrmgr_test diff --git a/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core b/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core index 79631950495e26..8adac26d23551f 100644 --- a/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core +++ b/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core @@ -7,7 +7,7 @@ description: "PWRMGR to RSTMGR assertion interface." filesets: files_dv: depend: - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:prim:assert files: - pwrmgr_rstmgr_sva_if.sv diff --git a/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_sva.core b/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_sva.core index b71c2dede28a47..4d606bf4e35228 100644 --- a/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_sva.core +++ b/hw/ip_templates/pwrmgr/dv/sva/pwrmgr_sva.core @@ -9,7 +9,7 @@ filesets: depend: - lowrisc:tlul:headers - lowrisc:fpv:csr_assert_gen - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:dv:clkmgr_pwrmgr_sva_if - lowrisc:dv:pwrmgr_rstmgr_sva_if files: @@ -21,7 +21,7 @@ filesets: files_formal: depend: - - lowrisc:ip:pwrmgr + - lowrisc:ip_interfaces:pwrmgr generate: csr_assert_gen: diff --git a/hw/ip_templates/pwrmgr/pwrmgr.core.tpl b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl new file mode 100644 index 00000000000000..3b83fcde96d924 --- /dev/null +++ b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl @@ -0,0 +1,66 @@ +CAPI=2: +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: ${instance_vlnv("lowrisc:ip:pwrmgr:0.1")} +description: "Power manager RTL" +virtual: + - lowrisc:ip_interfaces:pwrmgr + +filesets: + files_rtl: + depend: + - ${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1")} + - ${instance_vlnv("lowrisc:ip:pwrmgr_reg:0.1")} + - lowrisc:ip:pwrmgr_component + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: pwrmgr + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/ip_templates/pwrmgr/pwrmgr.core b/hw/ip_templates/pwrmgr/pwrmgr_components.core similarity index 95% rename from hw/ip_templates/pwrmgr/pwrmgr.core rename to hw/ip_templates/pwrmgr/pwrmgr_components.core index c384dae955aaba..2069107cadb6b0 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr.core +++ b/hw/ip_templates/pwrmgr/pwrmgr_components.core @@ -2,7 +2,7 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr:0.1" +name: "lowrisc:ip:pwrmgr_component:0.1" description: "Power manager RTL" filesets: @@ -20,8 +20,7 @@ filesets: - lowrisc:prim:clock_buf - lowrisc:prim:measure - lowrisc:ip_interfaces:alert_handler_reg - - lowrisc:ip:pwrmgr_pkg - - lowrisc:ip:pwrmgr_reg + - lowrisc:ip_interfaces:pwrmgr_pkg files: - rtl/pwrmgr_cdc.sv - rtl/pwrmgr_slow_fsm.sv diff --git a/hw/ip_templates/pwrmgr/pwrmgr_pkg.core b/hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl similarity index 79% rename from hw/ip_templates/pwrmgr/pwrmgr_pkg.core rename to hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl index 3e83cde44fd128..f2d8b0995aaf57 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr_pkg.core +++ b/hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl @@ -2,13 +2,15 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr_pkg:0.1" +name: ${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1")} description: "Power manager package" +virtual: + - lowrisc:ip_interfaces:pwrmgr_pkg filesets: files_rtl: depend: - - lowrisc:ip:pwrmgr_reg + - ${instance_vlnv("lowrisc:ip:pwrmgr_reg")} files: - rtl/pwrmgr_pkg.sv file_type: systemVerilogSource diff --git a/hw/ip_templates/pwrmgr/pwrmgr_reg.core b/hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl similarity index 82% rename from hw/ip_templates/pwrmgr/pwrmgr_reg.core rename to hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl index c20cd917273d83..b2b8124fd5d04f 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr_reg.core +++ b/hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl @@ -2,8 +2,10 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr_reg:0.1" +name: ${instance_vlnv("lowrisc:ip:pwrmgr_reg:0.1")} description: "Power manager registers" +virtual: + - lowrisc:ip_interfaces:pwrmgr_reg filesets: files_rtl: diff --git a/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_pkg.sv b/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_pkg.sv deleted file mode 100644 index f55eaaf7a32b44..00000000000000 --- a/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_pkg.sv +++ /dev/null @@ -1,215 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Package auto-generated by `reggen` containing data structure - -package pwrmgr_reg_pkg; - - // Param list - parameter int NumWkups = 1; - parameter int NumRstReqs = 1; - - // Address widths within the block - parameter int BlockAw = 6; - - //////////////////////////// - // Typedefs for registers // - //////////////////////////// - - typedef struct packed { - logic q; - } pwrmgr_reg2hw_intr_state_reg_t; - - typedef struct packed { - logic q; - } pwrmgr_reg2hw_intr_enable_reg_t; - - typedef struct packed { - logic q; - logic qe; - } pwrmgr_reg2hw_intr_test_reg_t; - - typedef struct packed { - struct packed { - logic q; - } low_power_hint; - struct packed { - logic q; - } core_clk_en; - struct packed { - logic q; - } io_clk_en; - struct packed { - logic q; - } usb_clk_en_lp; - struct packed { - logic q; - } usb_clk_en_active; - struct packed { - logic q; - } main_pd_n; - } pwrmgr_reg2hw_control_reg_t; - - typedef struct packed { - logic q; - logic qe; - } pwrmgr_reg2hw_cfg_cdc_sync_reg_t; - - typedef struct packed { - logic q; - } pwrmgr_reg2hw_wakeup_en_mreg_t; - - typedef struct packed { - logic q; - } pwrmgr_reg2hw_reset_en_mreg_t; - - typedef struct packed { - logic q; - } pwrmgr_reg2hw_wake_info_capture_dis_reg_t; - - typedef struct packed { - struct packed { - logic q; - logic qe; - } reasons; - struct packed { - logic q; - logic qe; - } fall_through; - struct packed { - logic q; - logic qe; - } abort; - } pwrmgr_reg2hw_wake_info_reg_t; - - typedef struct packed { - logic d; - logic de; - } pwrmgr_hw2reg_intr_state_reg_t; - - typedef struct packed { - logic d; - } pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t; - - typedef struct packed { - struct packed { - logic d; - logic de; - } low_power_hint; - } pwrmgr_hw2reg_control_reg_t; - - typedef struct packed { - logic d; - logic de; - } pwrmgr_hw2reg_cfg_cdc_sync_reg_t; - - typedef struct packed { - logic d; - logic de; - } pwrmgr_hw2reg_wake_status_mreg_t; - - typedef struct packed { - logic d; - logic de; - } pwrmgr_hw2reg_reset_status_mreg_t; - - typedef struct packed { - struct packed { - logic d; - } reasons; - struct packed { - logic d; - } fall_through; - struct packed { - logic d; - } abort; - } pwrmgr_hw2reg_wake_info_reg_t; - - // Register -> HW type - typedef struct packed { - pwrmgr_reg2hw_intr_state_reg_t intr_state; // [20:20] - pwrmgr_reg2hw_intr_enable_reg_t intr_enable; // [19:19] - pwrmgr_reg2hw_intr_test_reg_t intr_test; // [18:17] - pwrmgr_reg2hw_control_reg_t control; // [16:11] - pwrmgr_reg2hw_cfg_cdc_sync_reg_t cfg_cdc_sync; // [10:9] - pwrmgr_reg2hw_wakeup_en_mreg_t [0:0] wakeup_en; // [8:8] - pwrmgr_reg2hw_reset_en_mreg_t [0:0] reset_en; // [7:7] - pwrmgr_reg2hw_wake_info_capture_dis_reg_t wake_info_capture_dis; // [6:6] - pwrmgr_reg2hw_wake_info_reg_t wake_info; // [5:0] - } pwrmgr_reg2hw_t; - - // HW -> register type - typedef struct packed { - pwrmgr_hw2reg_intr_state_reg_t intr_state; // [13:12] - pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t ctrl_cfg_regwen; // [11:11] - pwrmgr_hw2reg_control_reg_t control; // [10:9] - pwrmgr_hw2reg_cfg_cdc_sync_reg_t cfg_cdc_sync; // [8:7] - pwrmgr_hw2reg_wake_status_mreg_t [0:0] wake_status; // [6:5] - pwrmgr_hw2reg_reset_status_mreg_t [0:0] reset_status; // [4:3] - pwrmgr_hw2reg_wake_info_reg_t wake_info; // [2:0] - } pwrmgr_hw2reg_t; - - // Register offsets - parameter logic [BlockAw-1:0] PWRMGR_INTR_STATE_OFFSET = 6'h 0; - parameter logic [BlockAw-1:0] PWRMGR_INTR_ENABLE_OFFSET = 6'h 4; - parameter logic [BlockAw-1:0] PWRMGR_INTR_TEST_OFFSET = 6'h 8; - parameter logic [BlockAw-1:0] PWRMGR_CTRL_CFG_REGWEN_OFFSET = 6'h c; - parameter logic [BlockAw-1:0] PWRMGR_CONTROL_OFFSET = 6'h 10; - parameter logic [BlockAw-1:0] PWRMGR_CFG_CDC_SYNC_OFFSET = 6'h 14; - parameter logic [BlockAw-1:0] PWRMGR_WAKEUP_EN_REGWEN_OFFSET = 6'h 18; - parameter logic [BlockAw-1:0] PWRMGR_WAKEUP_EN_OFFSET = 6'h 1c; - parameter logic [BlockAw-1:0] PWRMGR_WAKE_STATUS_OFFSET = 6'h 20; - parameter logic [BlockAw-1:0] PWRMGR_RESET_EN_REGWEN_OFFSET = 6'h 24; - parameter logic [BlockAw-1:0] PWRMGR_RESET_EN_OFFSET = 6'h 28; - parameter logic [BlockAw-1:0] PWRMGR_RESET_STATUS_OFFSET = 6'h 2c; - parameter logic [BlockAw-1:0] PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET = 6'h 30; - parameter logic [BlockAw-1:0] PWRMGR_WAKE_INFO_OFFSET = 6'h 34; - - // Reset values for hwext registers and their fields - parameter logic [0:0] PWRMGR_INTR_TEST_RESVAL = 1'h 0; - parameter logic [0:0] PWRMGR_INTR_TEST_WAKEUP_RESVAL = 1'h 0; - parameter logic [0:0] PWRMGR_CTRL_CFG_REGWEN_RESVAL = 1'h 1; - parameter logic [0:0] PWRMGR_CTRL_CFG_REGWEN_EN_RESVAL = 1'h 1; - parameter logic [2:0] PWRMGR_WAKE_INFO_RESVAL = 3'h 0; - parameter logic [0:0] PWRMGR_WAKE_INFO_REASONS_RESVAL = 1'h 0; - parameter logic [0:0] PWRMGR_WAKE_INFO_FALL_THROUGH_RESVAL = 1'h 0; - parameter logic [0:0] PWRMGR_WAKE_INFO_ABORT_RESVAL = 1'h 0; - - // Register index - typedef enum int { - PWRMGR_INTR_STATE, - PWRMGR_INTR_ENABLE, - PWRMGR_INTR_TEST, - PWRMGR_CTRL_CFG_REGWEN, - PWRMGR_CONTROL, - PWRMGR_CFG_CDC_SYNC, - PWRMGR_WAKEUP_EN_REGWEN, - PWRMGR_WAKEUP_EN, - PWRMGR_WAKE_STATUS, - PWRMGR_RESET_EN_REGWEN, - PWRMGR_RESET_EN, - PWRMGR_RESET_STATUS, - PWRMGR_WAKE_INFO_CAPTURE_DIS, - PWRMGR_WAKE_INFO - } pwrmgr_id_e; - - // Register width information to check illegal writes - parameter logic [3:0] PWRMGR_PERMIT [14] = '{ - 4'b 0001, // index[ 0] PWRMGR_INTR_STATE - 4'b 0001, // index[ 1] PWRMGR_INTR_ENABLE - 4'b 0001, // index[ 2] PWRMGR_INTR_TEST - 4'b 0001, // index[ 3] PWRMGR_CTRL_CFG_REGWEN - 4'b 0011, // index[ 4] PWRMGR_CONTROL - 4'b 0001, // index[ 5] PWRMGR_CFG_CDC_SYNC - 4'b 0001, // index[ 6] PWRMGR_WAKEUP_EN_REGWEN - 4'b 0001, // index[ 7] PWRMGR_WAKEUP_EN - 4'b 0001, // index[ 8] PWRMGR_WAKE_STATUS - 4'b 0001, // index[ 9] PWRMGR_RESET_EN_REGWEN - 4'b 0001, // index[10] PWRMGR_RESET_EN - 4'b 0001, // index[11] PWRMGR_RESET_STATUS - 4'b 0001, // index[12] PWRMGR_WAKE_INFO_CAPTURE_DIS - 4'b 0001 // index[13] PWRMGR_WAKE_INFO - }; - -endpackage diff --git a/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_top.sv b/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_top.sv deleted file mode 100644 index 3c9198dc73624e..00000000000000 --- a/hw/ip_templates/pwrmgr/rtl/pwrmgr_reg_top.sv +++ /dev/null @@ -1,947 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Top module auto-generated by `reggen` - -`include "prim_assert.sv" - -module pwrmgr_reg_top ( - input clk_i, - input rst_ni, - input tlul_pkg::tl_h2d_t tl_i, - output tlul_pkg::tl_d2h_t tl_o, - // To HW - output pwrmgr_reg_pkg::pwrmgr_reg2hw_t reg2hw, // Write - input pwrmgr_reg_pkg::pwrmgr_hw2reg_t hw2reg, // Read - - // Integrity check errors - output logic intg_err_o -); - - import pwrmgr_reg_pkg::* ; - - localparam int AW = 6; - localparam int DW = 32; - localparam int DBW = DW/8; // Byte Width - - // register signals - logic reg_we; - logic reg_re; - logic [AW-1:0] reg_addr; - logic [DW-1:0] reg_wdata; - logic [DBW-1:0] reg_be; - logic [DW-1:0] reg_rdata; - logic reg_error; - - logic addrmiss, wr_err; - - logic [DW-1:0] reg_rdata_next; - logic reg_busy; - - tlul_pkg::tl_h2d_t tl_reg_h2d; - tlul_pkg::tl_d2h_t tl_reg_d2h; - - - // incoming payload check - logic intg_err; - tlul_cmd_intg_chk u_chk ( - .tl_i(tl_i), - .err_o(intg_err) - ); - - // also check for spurious write enables - logic reg_we_err; - logic [13:0] reg_we_check; - prim_reg_we_check #( - .OneHotWidth(14) - ) u_prim_reg_we_check ( - .clk_i(clk_i), - .rst_ni(rst_ni), - .oh_i (reg_we_check), - .en_i (reg_we && !addrmiss), - .err_o (reg_we_err) - ); - - logic err_q; - always_ff @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - err_q <= '0; - end else if (intg_err || reg_we_err) begin - err_q <= 1'b1; - end - end - - // integrity error output is permanent and should be used for alert generation - // register errors are transactional - assign intg_err_o = err_q | intg_err | reg_we_err; - - // outgoing integrity generation - tlul_pkg::tl_d2h_t tl_o_pre; - tlul_rsp_intg_gen #( - .EnableRspIntgGen(1), - .EnableDataIntgGen(1) - ) u_rsp_intg_gen ( - .tl_i(tl_o_pre), - .tl_o(tl_o) - ); - - assign tl_reg_h2d = tl_i; - assign tl_o_pre = tl_reg_d2h; - - tlul_adapter_reg #( - .RegAw(AW), - .RegDw(DW), - .EnableDataIntgGen(0) - ) u_reg_if ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - .tl_i (tl_reg_h2d), - .tl_o (tl_reg_d2h), - - .en_ifetch_i(prim_mubi_pkg::MuBi4False), - .intg_error_o(), - - .we_o (reg_we), - .re_o (reg_re), - .addr_o (reg_addr), - .wdata_o (reg_wdata), - .be_o (reg_be), - .busy_i (reg_busy), - .rdata_i (reg_rdata), - .error_i (reg_error) - ); - - // cdc oversampling signals - - assign reg_rdata = reg_rdata_next ; - assign reg_error = addrmiss | wr_err | intg_err; - - // Define SW related signals - // Format: __{wd|we|qs} - // or _{wd|we|qs} if field == 1 or 0 - logic intr_state_we; - logic intr_state_qs; - logic intr_state_wd; - logic intr_enable_we; - logic intr_enable_qs; - logic intr_enable_wd; - logic intr_test_we; - logic intr_test_wd; - logic ctrl_cfg_regwen_re; - logic ctrl_cfg_regwen_qs; - logic control_we; - logic control_low_power_hint_qs; - logic control_low_power_hint_wd; - logic control_core_clk_en_qs; - logic control_core_clk_en_wd; - logic control_io_clk_en_qs; - logic control_io_clk_en_wd; - logic control_usb_clk_en_lp_qs; - logic control_usb_clk_en_lp_wd; - logic control_usb_clk_en_active_qs; - logic control_usb_clk_en_active_wd; - logic control_main_pd_n_qs; - logic control_main_pd_n_wd; - logic cfg_cdc_sync_we; - logic cfg_cdc_sync_qs; - logic cfg_cdc_sync_wd; - logic wakeup_en_regwen_we; - logic wakeup_en_regwen_qs; - logic wakeup_en_regwen_wd; - logic wakeup_en_we; - logic wakeup_en_qs; - logic wakeup_en_wd; - logic wake_status_qs; - logic reset_en_regwen_we; - logic reset_en_regwen_qs; - logic reset_en_regwen_wd; - logic reset_en_we; - logic reset_en_qs; - logic reset_en_wd; - logic reset_status_qs; - logic wake_info_capture_dis_we; - logic wake_info_capture_dis_qs; - logic wake_info_capture_dis_wd; - logic wake_info_re; - logic wake_info_we; - logic wake_info_reasons_qs; - logic wake_info_reasons_wd; - logic wake_info_fall_through_qs; - logic wake_info_fall_through_wd; - logic wake_info_abort_qs; - logic wake_info_abort_wd; - - // Register instances - // R[intr_state]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW1C), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_intr_state ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (intr_state_we), - .wd (intr_state_wd), - - // from internal hardware - .de (hw2reg.intr_state.de), - .d (hw2reg.intr_state.d), - - // to internal hardware - .qe (), - .q (reg2hw.intr_state.q), - .ds (), - - // to register interface (read) - .qs (intr_state_qs) - ); - - - // R[intr_enable]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_intr_enable ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (intr_enable_we), - .wd (intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.intr_enable.q), - .ds (), - - // to register interface (read) - .qs (intr_enable_qs) - ); - - - // R[intr_test]: V(True) - logic intr_test_qe; - logic [0:0] intr_test_flds_we; - assign intr_test_qe = &intr_test_flds_we; - prim_subreg_ext #( - .DW (1) - ) u_intr_test ( - .re (1'b0), - .we (intr_test_we), - .wd (intr_test_wd), - .d ('0), - .qre (), - .qe (intr_test_flds_we[0]), - .q (reg2hw.intr_test.q), - .ds (), - .qs () - ); - assign reg2hw.intr_test.qe = intr_test_qe; - - - // R[ctrl_cfg_regwen]: V(True) - prim_subreg_ext #( - .DW (1) - ) u_ctrl_cfg_regwen ( - .re (ctrl_cfg_regwen_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.ctrl_cfg_regwen.d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (ctrl_cfg_regwen_qs) - ); - - - // R[control]: V(False) - // Create REGWEN-gated WE signal - logic control_gated_we; - assign control_gated_we = control_we & ctrl_cfg_regwen_qs; - // F[low_power_hint]: 0:0 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_control_low_power_hint ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_low_power_hint_wd), - - // from internal hardware - .de (hw2reg.control.low_power_hint.de), - .d (hw2reg.control.low_power_hint.d), - - // to internal hardware - .qe (), - .q (reg2hw.control.low_power_hint.q), - .ds (), - - // to register interface (read) - .qs (control_low_power_hint_qs) - ); - - // F[core_clk_en]: 4:4 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_control_core_clk_en ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_core_clk_en_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.control.core_clk_en.q), - .ds (), - - // to register interface (read) - .qs (control_core_clk_en_qs) - ); - - // F[io_clk_en]: 5:5 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_control_io_clk_en ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_io_clk_en_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.control.io_clk_en.q), - .ds (), - - // to register interface (read) - .qs (control_io_clk_en_qs) - ); - - // F[usb_clk_en_lp]: 6:6 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_control_usb_clk_en_lp ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_usb_clk_en_lp_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.control.usb_clk_en_lp.q), - .ds (), - - // to register interface (read) - .qs (control_usb_clk_en_lp_qs) - ); - - // F[usb_clk_en_active]: 7:7 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_control_usb_clk_en_active ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_usb_clk_en_active_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.control.usb_clk_en_active.q), - .ds (), - - // to register interface (read) - .qs (control_usb_clk_en_active_qs) - ); - - // F[main_pd_n]: 8:8 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_control_main_pd_n ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (control_gated_we), - .wd (control_main_pd_n_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.control.main_pd_n.q), - .ds (), - - // to register interface (read) - .qs (control_main_pd_n_qs) - ); - - - // R[cfg_cdc_sync]: V(False) - logic cfg_cdc_sync_qe; - logic [0:0] cfg_cdc_sync_flds_we; - prim_flop #( - .Width(1), - .ResetValue(0) - ) u_cfg_cdc_sync0_qe ( - .clk_i(clk_i), - .rst_ni(rst_ni), - .d_i(&cfg_cdc_sync_flds_we), - .q_o(cfg_cdc_sync_qe) - ); - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_cfg_cdc_sync ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (cfg_cdc_sync_we), - .wd (cfg_cdc_sync_wd), - - // from internal hardware - .de (hw2reg.cfg_cdc_sync.de), - .d (hw2reg.cfg_cdc_sync.d), - - // to internal hardware - .qe (cfg_cdc_sync_flds_we[0]), - .q (reg2hw.cfg_cdc_sync.q), - .ds (), - - // to register interface (read) - .qs (cfg_cdc_sync_qs) - ); - assign reg2hw.cfg_cdc_sync.qe = cfg_cdc_sync_qe; - - - // R[wakeup_en_regwen]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_wakeup_en_regwen ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (wakeup_en_regwen_we), - .wd (wakeup_en_regwen_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (wakeup_en_regwen_qs) - ); - - - // Subregister 0 of Multireg wakeup_en - // R[wakeup_en]: V(False) - // Create REGWEN-gated WE signal - logic wakeup_en_gated_we; - assign wakeup_en_gated_we = wakeup_en_we & wakeup_en_regwen_qs; - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_wakeup_en ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (wakeup_en_gated_we), - .wd (wakeup_en_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.wakeup_en[0].q), - .ds (), - - // to register interface (read) - .qs (wakeup_en_qs) - ); - - - // Subregister 0 of Multireg wake_status - // R[wake_status]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_wake_status ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.wake_status[0].de), - .d (hw2reg.wake_status[0].d), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (wake_status_qs) - ); - - - // R[reset_en_regwen]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_reset_en_regwen ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (reset_en_regwen_we), - .wd (reset_en_regwen_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (reset_en_regwen_qs) - ); - - - // Subregister 0 of Multireg reset_en - // R[reset_en]: V(False) - // Create REGWEN-gated WE signal - logic reset_en_gated_we; - assign reset_en_gated_we = reset_en_we & reset_en_regwen_qs; - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_reset_en ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (reset_en_gated_we), - .wd (reset_en_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.reset_en[0].q), - .ds (), - - // to register interface (read) - .qs (reset_en_qs) - ); - - - // Subregister 0 of Multireg reset_status - // R[reset_status]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_reset_status ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.reset_status[0].de), - .d (hw2reg.reset_status[0].d), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (reset_status_qs) - ); - - - // R[wake_info_capture_dis]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_wake_info_capture_dis ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (wake_info_capture_dis_we), - .wd (wake_info_capture_dis_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.wake_info_capture_dis.q), - .ds (), - - // to register interface (read) - .qs (wake_info_capture_dis_qs) - ); - - - // R[wake_info]: V(True) - logic wake_info_qe; - logic [2:0] wake_info_flds_we; - assign wake_info_qe = &wake_info_flds_we; - // F[reasons]: 0:0 - prim_subreg_ext #( - .DW (1) - ) u_wake_info_reasons ( - .re (wake_info_re), - .we (wake_info_we), - .wd (wake_info_reasons_wd), - .d (hw2reg.wake_info.reasons.d), - .qre (), - .qe (wake_info_flds_we[0]), - .q (reg2hw.wake_info.reasons.q), - .ds (), - .qs (wake_info_reasons_qs) - ); - assign reg2hw.wake_info.reasons.qe = wake_info_qe; - - // F[fall_through]: 1:1 - prim_subreg_ext #( - .DW (1) - ) u_wake_info_fall_through ( - .re (wake_info_re), - .we (wake_info_we), - .wd (wake_info_fall_through_wd), - .d (hw2reg.wake_info.fall_through.d), - .qre (), - .qe (wake_info_flds_we[1]), - .q (reg2hw.wake_info.fall_through.q), - .ds (), - .qs (wake_info_fall_through_qs) - ); - assign reg2hw.wake_info.fall_through.qe = wake_info_qe; - - // F[abort]: 2:2 - prim_subreg_ext #( - .DW (1) - ) u_wake_info_abort ( - .re (wake_info_re), - .we (wake_info_we), - .wd (wake_info_abort_wd), - .d (hw2reg.wake_info.abort.d), - .qre (), - .qe (wake_info_flds_we[2]), - .q (reg2hw.wake_info.abort.q), - .ds (), - .qs (wake_info_abort_qs) - ); - assign reg2hw.wake_info.abort.qe = wake_info_qe; - - - - logic [13:0] addr_hit; - always_comb begin - addr_hit = '0; - addr_hit[ 0] = (reg_addr == PWRMGR_INTR_STATE_OFFSET); - addr_hit[ 1] = (reg_addr == PWRMGR_INTR_ENABLE_OFFSET); - addr_hit[ 2] = (reg_addr == PWRMGR_INTR_TEST_OFFSET); - addr_hit[ 3] = (reg_addr == PWRMGR_CTRL_CFG_REGWEN_OFFSET); - addr_hit[ 4] = (reg_addr == PWRMGR_CONTROL_OFFSET); - addr_hit[ 5] = (reg_addr == PWRMGR_CFG_CDC_SYNC_OFFSET); - addr_hit[ 6] = (reg_addr == PWRMGR_WAKEUP_EN_REGWEN_OFFSET); - addr_hit[ 7] = (reg_addr == PWRMGR_WAKEUP_EN_OFFSET); - addr_hit[ 8] = (reg_addr == PWRMGR_WAKE_STATUS_OFFSET); - addr_hit[ 9] = (reg_addr == PWRMGR_RESET_EN_REGWEN_OFFSET); - addr_hit[10] = (reg_addr == PWRMGR_RESET_EN_OFFSET); - addr_hit[11] = (reg_addr == PWRMGR_RESET_STATUS_OFFSET); - addr_hit[12] = (reg_addr == PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET); - addr_hit[13] = (reg_addr == PWRMGR_WAKE_INFO_OFFSET); - end - - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; - - // Check sub-word write is permitted - always_comb begin - wr_err = (reg_we & - ((addr_hit[ 0] & (|(PWRMGR_PERMIT[ 0] & ~reg_be))) | - (addr_hit[ 1] & (|(PWRMGR_PERMIT[ 1] & ~reg_be))) | - (addr_hit[ 2] & (|(PWRMGR_PERMIT[ 2] & ~reg_be))) | - (addr_hit[ 3] & (|(PWRMGR_PERMIT[ 3] & ~reg_be))) | - (addr_hit[ 4] & (|(PWRMGR_PERMIT[ 4] & ~reg_be))) | - (addr_hit[ 5] & (|(PWRMGR_PERMIT[ 5] & ~reg_be))) | - (addr_hit[ 6] & (|(PWRMGR_PERMIT[ 6] & ~reg_be))) | - (addr_hit[ 7] & (|(PWRMGR_PERMIT[ 7] & ~reg_be))) | - (addr_hit[ 8] & (|(PWRMGR_PERMIT[ 8] & ~reg_be))) | - (addr_hit[ 9] & (|(PWRMGR_PERMIT[ 9] & ~reg_be))) | - (addr_hit[10] & (|(PWRMGR_PERMIT[10] & ~reg_be))) | - (addr_hit[11] & (|(PWRMGR_PERMIT[11] & ~reg_be))) | - (addr_hit[12] & (|(PWRMGR_PERMIT[12] & ~reg_be))) | - (addr_hit[13] & (|(PWRMGR_PERMIT[13] & ~reg_be))))); - end - - // Generate write-enables - assign intr_state_we = addr_hit[0] & reg_we & !reg_error; - - assign intr_state_wd = reg_wdata[0]; - assign intr_enable_we = addr_hit[1] & reg_we & !reg_error; - - assign intr_enable_wd = reg_wdata[0]; - assign intr_test_we = addr_hit[2] & reg_we & !reg_error; - - assign intr_test_wd = reg_wdata[0]; - assign ctrl_cfg_regwen_re = addr_hit[3] & reg_re & !reg_error; - assign control_we = addr_hit[4] & reg_we & !reg_error; - - assign control_low_power_hint_wd = reg_wdata[0]; - - assign control_core_clk_en_wd = reg_wdata[4]; - - assign control_io_clk_en_wd = reg_wdata[5]; - - assign control_usb_clk_en_lp_wd = reg_wdata[6]; - - assign control_usb_clk_en_active_wd = reg_wdata[7]; - - assign control_main_pd_n_wd = reg_wdata[8]; - assign cfg_cdc_sync_we = addr_hit[5] & reg_we & !reg_error; - - assign cfg_cdc_sync_wd = reg_wdata[0]; - assign wakeup_en_regwen_we = addr_hit[6] & reg_we & !reg_error; - - assign wakeup_en_regwen_wd = reg_wdata[0]; - assign wakeup_en_we = addr_hit[7] & reg_we & !reg_error; - - assign wakeup_en_wd = reg_wdata[0]; - assign reset_en_regwen_we = addr_hit[9] & reg_we & !reg_error; - - assign reset_en_regwen_wd = reg_wdata[0]; - assign reset_en_we = addr_hit[10] & reg_we & !reg_error; - - assign reset_en_wd = reg_wdata[0]; - assign wake_info_capture_dis_we = addr_hit[12] & reg_we & !reg_error; - - assign wake_info_capture_dis_wd = reg_wdata[0]; - assign wake_info_re = addr_hit[13] & reg_re & !reg_error; - assign wake_info_we = addr_hit[13] & reg_we & !reg_error; - - assign wake_info_reasons_wd = reg_wdata[0]; - - assign wake_info_fall_through_wd = reg_wdata[1]; - - assign wake_info_abort_wd = reg_wdata[2]; - - // Assign write-enables to checker logic vector. - always_comb begin - reg_we_check = '0; - reg_we_check[0] = intr_state_we; - reg_we_check[1] = intr_enable_we; - reg_we_check[2] = intr_test_we; - reg_we_check[3] = 1'b0; - reg_we_check[4] = control_gated_we; - reg_we_check[5] = cfg_cdc_sync_we; - reg_we_check[6] = wakeup_en_regwen_we; - reg_we_check[7] = wakeup_en_gated_we; - reg_we_check[8] = 1'b0; - reg_we_check[9] = reset_en_regwen_we; - reg_we_check[10] = reset_en_gated_we; - reg_we_check[11] = 1'b0; - reg_we_check[12] = wake_info_capture_dis_we; - reg_we_check[13] = wake_info_we; - end - - // Read data return - always_comb begin - reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin - reg_rdata_next[0] = intr_state_qs; - end - - addr_hit[1]: begin - reg_rdata_next[0] = intr_enable_qs; - end - - addr_hit[2]: begin - reg_rdata_next[0] = '0; - end - - addr_hit[3]: begin - reg_rdata_next[0] = ctrl_cfg_regwen_qs; - end - - addr_hit[4]: begin - reg_rdata_next[0] = control_low_power_hint_qs; - reg_rdata_next[4] = control_core_clk_en_qs; - reg_rdata_next[5] = control_io_clk_en_qs; - reg_rdata_next[6] = control_usb_clk_en_lp_qs; - reg_rdata_next[7] = control_usb_clk_en_active_qs; - reg_rdata_next[8] = control_main_pd_n_qs; - end - - addr_hit[5]: begin - reg_rdata_next[0] = cfg_cdc_sync_qs; - end - - addr_hit[6]: begin - reg_rdata_next[0] = wakeup_en_regwen_qs; - end - - addr_hit[7]: begin - reg_rdata_next[0] = wakeup_en_qs; - end - - addr_hit[8]: begin - reg_rdata_next[0] = wake_status_qs; - end - - addr_hit[9]: begin - reg_rdata_next[0] = reset_en_regwen_qs; - end - - addr_hit[10]: begin - reg_rdata_next[0] = reset_en_qs; - end - - addr_hit[11]: begin - reg_rdata_next[0] = reset_status_qs; - end - - addr_hit[12]: begin - reg_rdata_next[0] = wake_info_capture_dis_qs; - end - - addr_hit[13]: begin - reg_rdata_next[0] = wake_info_reasons_qs; - reg_rdata_next[1] = wake_info_fall_through_qs; - reg_rdata_next[2] = wake_info_abort_qs; - end - - default: begin - reg_rdata_next = '1; - end - endcase - end - - // shadow busy - logic shadow_busy; - assign shadow_busy = 1'b0; - - // register busy - assign reg_busy = shadow_busy; - - // Unused signal tieoff - - // wdata / byte enable are not always fully used - // add a blanket unused statement to handle lint waivers - logic unused_wdata; - logic unused_be; - assign unused_wdata = ^reg_wdata; - assign unused_be = ^reg_be; - - // Assertions for Register Interface - `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) - `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) - - `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) - - `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) - - // this is formulated as an assumption such that the FPV testbenches do disprove this - // property by mistake - //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) - -endmodule diff --git a/hw/top_earlgrey/dv/chip_sim.core b/hw/top_earlgrey/dv/chip_sim.core index c79fe5592d1a63..c8732a52a3b1c8 100644 --- a/hw/top_earlgrey/dv/chip_sim.core +++ b/hw/top_earlgrey/dv/chip_sim.core @@ -16,6 +16,9 @@ filesets: files_dv: depend: + # Place the autogen packages first to avoid conflicts + - lowrisc:opentitan:top_earlgrey_alert_handler_reg + - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg - lowrisc:ip:tlul - lowrisc:dv:chip_test - lowrisc:dv:clkmgr_sva diff --git a/hw/top_earlgrey/dv/env/chip_env.core b/hw/top_earlgrey/dv/env/chip_env.core index b7cf1059cbd300..a35712a9091a33 100644 --- a/hw/top_earlgrey/dv/env/chip_env.core +++ b/hw/top_earlgrey/dv/env/chip_env.core @@ -31,7 +31,7 @@ filesets: - lowrisc:dv:i2c_agent - lowrisc:dv:pattgen_agent - lowrisc:ip:otp_ctrl_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:dv:lc_ctrl_dv_utils - "!fileset_partner ? (lowrisc:systems:ast_pkg)" - "fileset_partner ? (partner:systems:ast_pkg)" diff --git a/hw/top_earlgrey/dv/sva/top_earlgrey_sva.core b/hw/top_earlgrey/dv/sva/top_earlgrey_sva.core index d429f609e9db8f..e86c330f155ea1 100644 --- a/hw/top_earlgrey/dv/sva/top_earlgrey_sva.core +++ b/hw/top_earlgrey/dv/sva/top_earlgrey_sva.core @@ -7,7 +7,7 @@ description: "TOP_EARLGREY assertion modules and bind file." filesets: files_dv: depend: - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:prim:assert - lowrisc:systems:top_earlgrey files: diff --git a/hw/top_earlgrey/ip/clkmgr/clkmgr.core b/hw/top_earlgrey/ip/clkmgr/clkmgr.core index b146e9cd3305b3..06422de232a83c 100644 --- a/hw/top_earlgrey/ip/clkmgr/clkmgr.core +++ b/hw/top_earlgrey/ip/clkmgr/clkmgr.core @@ -9,7 +9,7 @@ filesets: files_rtl: depend: - lowrisc:ip:lc_ctrl_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:tlul - lowrisc:prim:all - lowrisc:prim:buf diff --git a/hw/top_earlgrey/ip/clkmgr/clkmgr_pkg.core b/hw/top_earlgrey/ip/clkmgr/clkmgr_pkg.core index c8c3b25229ae08..c47cf27c055fd5 100644 --- a/hw/top_earlgrey/ip/clkmgr/clkmgr_pkg.core +++ b/hw/top_earlgrey/ip/clkmgr/clkmgr_pkg.core @@ -9,7 +9,7 @@ filesets: files_rtl: depend: - lowrisc:constants:top_pkg - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg files: - rtl/autogen/clkmgr_pkg.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/ip/rstmgr/system_rstmgr_pkg.core b/hw/top_earlgrey/ip/rstmgr/system_rstmgr_pkg.core index aaf4e9d5e052dc..ec08c5d8b2714c 100644 --- a/hw/top_earlgrey/ip/rstmgr/system_rstmgr_pkg.core +++ b/hw/top_earlgrey/ip/rstmgr/system_rstmgr_pkg.core @@ -8,7 +8,7 @@ description: "Auto-generated reset manager package for top_earlgrey" filesets: files_rtl: depend: - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:ip:rstmgr_reg - lowrisc:ip_interfaces:alert_handler_reg - lowrisc:ip:alert_handler_component diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core index d71a35180c2772..b19f07c3623908 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core @@ -9,7 +9,7 @@ filesets: depend: - lowrisc:dv:ralgen - lowrisc:dv:cip_lib - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg files: - pwrmgr_env_pkg.sv - pwrmgr_env_cfg.sv: {is_include_file: true} diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core index 9eaa8fd0db4d5a..d35cbce65b7b7a 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core @@ -7,7 +7,7 @@ description: "PWRMGR DV sim target" filesets: files_rtl: depend: - - lowrisc:ip:pwrmgr + - lowrisc:ip_interfaces:pwrmgr files_dv: depend: - lowrisc:dv:pwrmgr_test diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core index 79631950495e26..8adac26d23551f 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core @@ -7,7 +7,7 @@ description: "PWRMGR to RSTMGR assertion interface." filesets: files_dv: depend: - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:prim:assert files: - pwrmgr_rstmgr_sva_if.sv diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core index b71c2dede28a47..4d606bf4e35228 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core @@ -9,7 +9,7 @@ filesets: depend: - lowrisc:tlul:headers - lowrisc:fpv:csr_assert_gen - - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:dv:clkmgr_pwrmgr_sva_if - lowrisc:dv:pwrmgr_rstmgr_sva_if files: @@ -21,7 +21,7 @@ filesets: files_formal: depend: - - lowrisc:ip:pwrmgr + - lowrisc:ip_interfaces:pwrmgr generate: csr_assert_gen: diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core index c384dae955aaba..a12e1d70b13931 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core @@ -2,32 +2,17 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr:0.1" +name: lowrisc:opentitan:top_earlgrey_pwrmgr:0.1 description: "Power manager RTL" +virtual: + - lowrisc:ip_interfaces:pwrmgr filesets: files_rtl: depend: - - lowrisc:ip:tlul - - lowrisc:prim:esc - - lowrisc:prim:lc_sync - - lowrisc:prim:lc_sender - - lowrisc:prim:all - - lowrisc:ip:rom_ctrl_pkg - - lowrisc:ip:lc_ctrl_pkg - - lowrisc:prim:sparse_fsm - - lowrisc:prim:mubi - - lowrisc:prim:clock_buf - - lowrisc:prim:measure - - lowrisc:ip_interfaces:alert_handler_reg - - lowrisc:ip:pwrmgr_pkg - - lowrisc:ip:pwrmgr_reg - files: - - rtl/pwrmgr_cdc.sv - - rtl/pwrmgr_slow_fsm.sv - - rtl/pwrmgr_fsm.sv - - rtl/pwrmgr_wake_info.sv - - rtl/pwrmgr.sv + - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1 + - lowrisc:opentitan:top_earlgrey_pwrmgr_reg:0.1 + - lowrisc:ip:pwrmgr_component file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core new file mode 100644 index 00000000000000..2069107cadb6b0 --- /dev/null +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core @@ -0,0 +1,80 @@ +CAPI=2: +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:ip:pwrmgr_component:0.1" +description: "Power manager RTL" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:esc + - lowrisc:prim:lc_sync + - lowrisc:prim:lc_sender + - lowrisc:prim:all + - lowrisc:ip:rom_ctrl_pkg + - lowrisc:ip:lc_ctrl_pkg + - lowrisc:prim:sparse_fsm + - lowrisc:prim:mubi + - lowrisc:prim:clock_buf + - lowrisc:prim:measure + - lowrisc:ip_interfaces:alert_handler_reg + - lowrisc:ip_interfaces:pwrmgr_pkg + files: + - rtl/pwrmgr_cdc.sv + - rtl/pwrmgr_slow_fsm.sv + - rtl/pwrmgr_fsm.sv + - rtl/pwrmgr_wake_info.sv + - rtl/pwrmgr.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: pwrmgr + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core index 3e83cde44fd128..71d3abdcafc86f 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core @@ -2,13 +2,15 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr_pkg:0.1" +name: lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1 description: "Power manager package" +virtual: + - lowrisc:ip_interfaces:pwrmgr_pkg filesets: files_rtl: depend: - - lowrisc:ip:pwrmgr_reg + - lowrisc:opentitan:top_earlgrey_pwrmgr_reg files: - rtl/pwrmgr_pkg.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core index c20cd917273d83..75361f737b0b80 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core @@ -2,8 +2,10 @@ CAPI=2: # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:pwrmgr_reg:0.1" +name: lowrisc:opentitan:top_earlgrey_pwrmgr_reg:0.1 description: "Power manager registers" +virtual: + - lowrisc:ip_interfaces:pwrmgr_reg filesets: files_rtl: diff --git a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson index 1bb7e093dbd686..be8ef48fe87e2c 100644 --- a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson +++ b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson @@ -175,7 +175,7 @@ ] }, { name: pwrmgr - fusesoc_core: lowrisc:ip:pwrmgr + fusesoc_core: lowrisc:ip_interfaces:pwrmgr import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], rel_path: "hw/top_earlgrey/ip_autogen/pwrmgr/lint/{tool}", overrides: [ diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core index e2e3536fcfaac4..4dd99a51b247c3 100644 --- a/hw/top_earlgrey/top_earlgrey.core +++ b/hw/top_earlgrey/top_earlgrey.core @@ -7,6 +7,9 @@ description: "Technology-independent Earl Grey toplevel" filesets: files_rtl_generic: depend: + # Place the autogen packages first to avoid conflicts + - lowrisc:opentitan:top_earlgrey_alert_handler_reg + - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg - lowrisc:ip:uart:0.1 - lowrisc:opentitan:top_earlgrey_alert_handler - lowrisc:ip:gpio @@ -41,7 +44,7 @@ filesets: - lowrisc:top_earlgrey:xbar_main - lowrisc:top_earlgrey:xbar_peri - lowrisc:ip:rstmgr - - lowrisc:ip:pwrmgr + - lowrisc:opentitan:top_earlgrey_pwrmgr - lowrisc:ip:aon_timer - lowrisc:ip:adc_ctrl - lowrisc:ip:sysrst_ctrl diff --git a/hw/top_englishbreakfast/lint/top_englishbreakfast_lint_cfgs.hjson b/hw/top_englishbreakfast/lint/top_englishbreakfast_lint_cfgs.hjson index 76975e3855fbab..7e5090d6f52a33 100644 --- a/hw/top_englishbreakfast/lint/top_englishbreakfast_lint_cfgs.hjson +++ b/hw/top_englishbreakfast/lint/top_englishbreakfast_lint_cfgs.hjson @@ -41,7 +41,7 @@ ] }, { name: pwrmgr - fusesoc_core: lowrisc:ip:pwrmgr + fusesoc_core: lowrisc:ip_interfaces:pwrmgr import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], rel_path: "hw/ip/pwrmgr/lint/{tool}", overrides: [ diff --git a/hw/top_englishbreakfast/top_englishbreakfast.core b/hw/top_englishbreakfast/top_englishbreakfast.core index 981cc42037b68d..6d7dfc1fb1233f 100644 --- a/hw/top_englishbreakfast/top_englishbreakfast.core +++ b/hw/top_englishbreakfast/top_englishbreakfast.core @@ -39,7 +39,7 @@ filesets: - lowrisc:top_englishbreakfast:xbar_main - lowrisc:top_englishbreakfast:xbar_peri - lowrisc:ip:rstmgr - - lowrisc:ip:pwrmgr + - lowrisc:ip_interfaces:pwrmgr - lowrisc:ip:rom_ctrl - lowrisc:ip:aon_timer diff --git a/util/topgen-fusesoc.py b/util/topgen-fusesoc.py index 61114341d8104e..a74482c973ec3d 100755 --- a/util/topgen-fusesoc.py +++ b/util/topgen-fusesoc.py @@ -125,7 +125,7 @@ def main(): 'lowrisc:constants:top_pkg', 'lowrisc:prim:util', 'lowrisc:ip:lc_ctrl_pkg', - 'lowrisc:ip:pwrmgr_pkg', + 'lowrisc:ip_interfaces:pwrmgr_pkg', # rstmgr 'lowrisc:prim:clock_mux2', # clkmgr