From 96a1c02ba03400a8b0d69f08b97004adc436dfb7 Mon Sep 17 00:00:00 2001
From: Greg Chadwick <gac@lowrisc.org>
Date: Mon, 15 Jul 2024 21:14:43 +0100
Subject: [PATCH] [dv] Increase iterations and instructions in
 riscv_rf_intg_test

This enables more scenarios begin stimulated per regression run around
RF ECC errors.
---
 dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
index 1869a6f7f..5f8b3a33c 100644
--- a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
+++ b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
@@ -683,8 +683,14 @@
 - test: riscv_rf_intg_test
   description: >
     Randomly corrupt the register file read port once in the middle of program execution
-  iterations: 15
+  iterations: 100
   gen_test: riscv_rand_instr_test
+  gen_opts: >
+    +instr_cnt=10000
+    +num_of_sub_program=5
+    +gen_all_csrs_by_default=1
+    +add_csr_write=MSTATUS,MEPC,MCAUSE,MTVAL,0x7c0,0x7c1
+    +no_csr_instr=0
   rtl_test: core_ibex_rf_intg_test
   rtl_params:
     SecureIbex: 1