From 53888bcdf4ca3c07e5e715fb6386cb4cc643a61b Mon Sep 17 00:00:00 2001
From: lingscale <lingscale@163.com>
Date: Tue, 27 Aug 2024 22:43:10 +0800
Subject: [PATCH] [rtl] fix a typo.

---
 rtl/ibex_core.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rtl/ibex_core.sv b/rtl/ibex_core.sv
index 5df9ae1b7..fd5e7868b 100644
--- a/rtl/ibex_core.sv
+++ b/rtl/ibex_core.sv
@@ -1678,7 +1678,7 @@ module ibex_core import ibex_pkg::*; #(
   end
 
 
-  // Memory adddress/write data available first cycle of ld/st instruction from register read
+  // Memory address/write data available first cycle of ld/st instruction from register read
   always_comb begin
     if (instr_first_cycle_id) begin
       rvfi_mem_addr_d  = alu_adder_result_ex;