From 40cfa8269d39dd57624321553c4605a40ffc0483 Mon Sep 17 00:00:00 2001 From: Pascal Nasahl Date: Fri, 29 Nov 2024 18:58:35 +0100 Subject: [PATCH] [rtl] Move counter_q definition The counter_q definition should be outside of the if else such that we have the correct scope. Moreover, Xilinx Vivado reports an error if the DspPragma is a string instead of an int. Signed-off-by: Pascal Nasahl --- rtl/ibex_counter.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/rtl/ibex_counter.sv b/rtl/ibex_counter.sv index d3ca14ca0..4d3007227 100644 --- a/rtl/ibex_counter.sv +++ b/rtl/ibex_counter.sv @@ -53,13 +53,13 @@ module ibex_counter #( `ifdef FPGA_XILINX // On Xilinx FPGAs, 48-bit DSPs are available that can be used for the // counter. - if (CounterWidth < 49) begin : g_dsp_counter - // Set DSP pragma for supported xilinx FPGAs - (* use_dsp = "yes" *) logic [CounterWidth-1:0] counter_q; + localparam int DspPragma = CounterWidth < 49 ? "yes" : "no"; + (* use_dsp = DspPragma *) logic [CounterWidth-1:0] counter_q; + + if (CounterWidth < 49) begin : g_dsp_sync_reset // DSP output register requires synchronous reset. `define COUNTER_FLOP_RST posedge clk_i - end else begin : g_no_dsp_counter - (* use_dsp = "no" *) logic [CounterWidth-1:0] counter_q; + end else begin : g_dsp_async_reset `define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni end `else